1 /* $NetBSD: if_jme.c,v 1.56 2023/12/20 05:08:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.56 2023/12/20 05:08:34 thorpej Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 73 #include <sys/device.h> 74 #include <sys/syslog.h> 75 #include <sys/sysctl.h> 76 77 #include <net/if.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_dl.h> 81 #include <net/route.h> 82 #include <net/bpf.h> 83 84 #include <sys/rndsource.h> 85 86 #include <netinet/in.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/ip.h> 89 #include <netinet/ip_var.h> 90 91 #include <netinet6/ip6_var.h> 92 93 #ifdef INET 94 #include <netinet/in_var.h> 95 #endif 96 97 #include <netinet/tcp.h> 98 #include <netinet/tcp_timer.h> 99 #include <netinet/tcp_var.h> 100 101 #include <net/if_ether.h> 102 #if defined(INET) 103 #include <netinet/if_inarp.h> 104 #endif 105 106 #include <sys/bus.h> 107 #include <sys/intr.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 #include <dev/pci/if_jmereg.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 117 /* number of entries in transmit and receive rings */ 118 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 119 120 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 121 122 /* Water mark to kick reclaiming Tx buffers. */ 123 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 124 125 126 struct jme_softc { 127 device_t jme_dev; /* base device */ 128 bus_space_tag_t jme_bt_mac; 129 bus_space_handle_t jme_bh_mac; /* Mac registers */ 130 bus_space_tag_t jme_bt_phy; 131 bus_space_handle_t jme_bh_phy; /* PHY registers */ 132 bus_space_tag_t jme_bt_misc; 133 bus_space_handle_t jme_bh_misc; /* Misc registers */ 134 bus_dma_tag_t jme_dmatag; 135 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 136 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 137 struct jme_desc* jme_txring; /* transmit ring */ 138 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 139 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 140 int jme_tx_cons; /* transmit ring consumer */ 141 int jme_tx_prod; /* transmit ring producer */ 142 int jme_tx_cnt; /* transmit ring active count */ 143 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 144 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 145 struct jme_desc* jme_rxring; /* receive ring */ 146 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 147 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 148 int jme_rx_cons; /* receive ring consumer */ 149 int jme_rx_prod; /* receive ring producer */ 150 void* jme_ih; /* our interrupt */ 151 struct ethercom jme_ec; 152 struct callout jme_tick_ch; /* tick callout */ 153 uint8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 154 uint8_t jme_phyaddr; /* address of integrated phy */ 155 uint8_t jme_chip_rev; /* chip revision */ 156 uint8_t jme_rev; /* PCI revision */ 157 mii_data_t jme_mii; /* mii bus */ 158 uint32_t jme_flags; /* device features, see below */ 159 uint32_t jme_txcsr; /* TX config register */ 160 uint32_t jme_rxcsr; /* RX config register */ 161 krndsource_t rnd_source; 162 /* interrupt coalition parameters */ 163 struct sysctllog *jme_clog; 164 int jme_intrxto; /* interrupt RX timeout */ 165 int jme_intrxct; /* interrupt RX packets counter */ 166 int jme_inttxto; /* interrupt TX timeout */ 167 int jme_inttxct; /* interrupt TX packets counter */ 168 }; 169 170 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 171 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 172 173 174 #define jme_if jme_ec.ec_if 175 #define jme_bpf jme_if.if_bpf 176 177 typedef struct jme_softc jme_softc_t; 178 typedef u_long ioctl_cmd_t; 179 180 static int jme_pci_match(device_t, cfdata_t, void *); 181 static void jme_pci_attach(device_t, device_t, void *); 182 static void jme_intr_rx(jme_softc_t *); 183 static int jme_intr(void *); 184 185 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 186 static int jme_mediachange(struct ifnet *); 187 static void jme_ifwatchdog(struct ifnet *); 188 static bool jme_shutdown(device_t, int); 189 190 static void jme_txeof(struct jme_softc *); 191 static void jme_ifstart(struct ifnet *); 192 static void jme_reset(jme_softc_t *); 193 static int jme_ifinit(struct ifnet *); 194 static int jme_init(struct ifnet *, int); 195 static void jme_stop(struct ifnet *, int); 196 // static void jme_restart(void *); 197 static void jme_ticks(void *); 198 static void jme_mac_config(jme_softc_t *); 199 static void jme_set_filter(jme_softc_t *); 200 201 static int jme_mii_read(device_t, int, int, uint16_t *); 202 static int jme_mii_write(device_t, int, int, uint16_t); 203 static void jme_statchg(struct ifnet *); 204 205 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 206 static int jme_eeprom_macaddr(struct jme_softc *); 207 static int jme_reg_macaddr(struct jme_softc *); 208 209 #define JME_TIMEOUT 1000 210 #define JME_PHY_TIMEOUT 1000 211 #define JME_EEPROM_TIMEOUT 1000 212 213 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 214 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 215 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 216 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 217 static int jme_root_num; 218 219 220 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 221 jme_pci_match, jme_pci_attach, NULL, NULL); 222 223 static const struct device_compatible_entry compat_data[] = { 224 { .id = PCI_ID_CODE(PCI_VENDOR_JMICRON, 225 PCI_PRODUCT_JMICRON_JMC250), 226 .data = "JMicron JMC250 Gigabit Ethernet Controller" }, 227 228 { .id = PCI_ID_CODE(PCI_VENDOR_JMICRON, 229 PCI_PRODUCT_JMICRON_JMC260), 230 .data = "JMicron JMC260 Gigabit Ethernet Controller" }, 231 232 PCI_COMPAT_EOL 233 }; 234 235 static int 236 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 237 { 238 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 239 240 return pci_compatible_match(pa, compat_data); 241 } 242 243 static void 244 jme_pci_attach(device_t parent, device_t self, void *aux) 245 { 246 jme_softc_t *sc = device_private(self); 247 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 248 const struct device_compatible_entry *dce; 249 struct ifnet * const ifp = &sc->jme_if; 250 struct mii_data * const mii = &sc->jme_mii; 251 bus_space_tag_t iot1, iot2, memt; 252 bus_space_handle_t ioh1, ioh2, memh; 253 bus_size_t size, size2; 254 pci_intr_handle_t intrhandle; 255 const char *intrstr; 256 pcireg_t csr; 257 int nsegs, i; 258 const struct sysctlnode *node; 259 int jme_nodenum; 260 char intrbuf[PCI_INTRSTR_LEN]; 261 262 sc->jme_dev = self; 263 aprint_normal("\n"); 264 callout_init(&sc->jme_tick_ch, 0); 265 callout_setfunc(&sc->jme_tick_ch, jme_ticks, sc); 266 267 dce = pci_compatible_lookup(pa, compat_data); 268 KASSERT(dce != NULL); 269 270 if (PCI_PRODUCT(dce->id) == PCI_PRODUCT_JMICRON_JMC250) 271 sc->jme_flags = JME_FLAG_GIGA; 272 273 /* 274 * Map the card space. Try Mem first. 275 */ 276 if (pci_mapreg_map(pa, JME_PCI_BAR0, 277 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 278 0, &memt, &memh, NULL, &size) == 0) { 279 sc->jme_bt_mac = memt; 280 sc->jme_bh_mac = memh; 281 sc->jme_bt_phy = memt; 282 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 283 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 284 aprint_error_dev(self, "can't subregion PHY space\n"); 285 bus_space_unmap(memt, memh, size); 286 return; 287 } 288 sc->jme_bt_misc = memt; 289 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 290 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 291 aprint_error_dev(self, "can't subregion misc space\n"); 292 bus_space_unmap(memt, memh, size); 293 return; 294 } 295 } else { 296 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 297 0, &iot1, &ioh1, NULL, &size) != 0) { 298 aprint_error_dev(self, "can't map I/O space 1\n"); 299 return; 300 } 301 sc->jme_bt_mac = iot1; 302 sc->jme_bh_mac = ioh1; 303 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 304 0, &iot2, &ioh2, NULL, &size2) != 0) { 305 aprint_error_dev(self, "can't map I/O space 2\n"); 306 bus_space_unmap(iot1, ioh1, size); 307 return; 308 } 309 sc->jme_bt_phy = iot2; 310 sc->jme_bh_phy = ioh2; 311 sc->jme_bt_misc = iot2; 312 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 313 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 314 aprint_error_dev(self, "can't subregion misc space\n"); 315 bus_space_unmap(iot1, ioh1, size); 316 bus_space_unmap(iot2, ioh2, size2); 317 return; 318 } 319 } 320 321 if (pci_dma64_available(pa)) 322 sc->jme_dmatag = pa->pa_dmat64; 323 else 324 sc->jme_dmatag = pa->pa_dmat; 325 326 /* Enable the device. */ 327 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 328 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 329 csr | PCI_COMMAND_MASTER_ENABLE); 330 331 aprint_normal_dev(self, "%s\n", (const char *)dce->data); 332 333 sc->jme_rev = PCI_REVISION(pa->pa_class); 334 335 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 336 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 337 CHIPMODE_NOT_FPGA) 338 sc->jme_flags |= JME_FLAG_FPGA; 339 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 340 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 341 "0x%x", sc->jme_rev, sc->jme_chip_rev); 342 if (sc->jme_flags & JME_FLAG_FPGA) 343 aprint_verbose(" FPGA revision: 0x%x", 344 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 345 aprint_verbose("\n"); 346 347 /* 348 * Save PHY address. 349 * Integrated JR0211 has fixed PHY address whereas FPGA version 350 * requires PHY probing to get correct PHY address. 351 */ 352 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 353 sc->jme_phyaddr = 354 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 355 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 356 } else 357 sc->jme_phyaddr = 0; 358 359 360 jme_reset(sc); 361 362 /* read mac addr */ 363 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 364 aprint_error_dev(self, "error reading Ethernet address\n"); 365 /* return; */ 366 } 367 aprint_normal_dev(self, "Ethernet address %s\n", 368 ether_sprintf(sc->jme_enaddr)); 369 370 /* Map and establish interrupts */ 371 if (pci_intr_map(pa, &intrhandle)) { 372 aprint_error_dev(self, "couldn't map interrupt\n"); 373 return; 374 } 375 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 376 sc->jme_if.if_softc = sc; 377 sc->jme_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 378 jme_intr, sc, device_xname(self)); 379 if (sc->jme_ih == NULL) { 380 aprint_error_dev(self, "couldn't establish interrupt"); 381 if (intrstr != NULL) 382 aprint_error(" at %s", intrstr); 383 aprint_error("\n"); 384 return; 385 } 386 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 387 388 /* allocate and map DMA-safe memory for transmit ring */ 389 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 390 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 391 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 392 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 393 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 394 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 395 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 396 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 397 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 398 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 399 return; 400 } 401 /* allocate and map DMA-safe memory for receive ring */ 402 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 403 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 404 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 405 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 406 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 407 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 408 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 409 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 410 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 411 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 412 return; 413 } 414 for (i = 0; i < JME_NBUFS; i++) { 415 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 416 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 417 JME_NBUFS, JME_MAX_TX_LEN, 0, 418 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 419 &sc->jme_txmbufm[i]) != 0) { 420 aprint_error_dev(self, "can't allocate DMA TX map\n"); 421 return; 422 } 423 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 424 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 425 &sc->jme_rxmbufm[i]) != 0) { 426 aprint_error_dev(self, "can't allocate DMA RX map\n"); 427 return; 428 } 429 } 430 /* 431 * Initialize our media structures and probe the MII. 432 * 433 * Note that we don't care about the media instance. We 434 * are expecting to have multiple PHYs on the 10/100 cards, 435 * and on those cards we exclude the internal PHY from providing 436 * 10baseT. By ignoring the instance, it allows us to not have 437 * to specify it on the command line when switching media. 438 */ 439 mii->mii_ifp = ifp; 440 mii->mii_readreg = jme_mii_read; 441 mii->mii_writereg = jme_mii_write; 442 mii->mii_statchg = jme_statchg; 443 sc->jme_ec.ec_mii = mii; 444 ifmedia_init(&mii->mii_media, IFM_IMASK, jme_mediachange, 445 ether_mediastatus); 446 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 447 if (LIST_FIRST(&mii->mii_phys) == NULL) { 448 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 449 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 450 } else 451 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 452 453 /* 454 * We can support 802.1Q VLAN-sized frames. 455 */ 456 sc->jme_ec.ec_capabilities |= 457 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 458 sc->jme_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 459 460 if (sc->jme_flags & JME_FLAG_GIGA) 461 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 462 463 464 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 465 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 466 ifp->if_ioctl = jme_ifioctl; 467 ifp->if_start = jme_ifstart; 468 ifp->if_watchdog = jme_ifwatchdog; 469 ifp->if_init = jme_ifinit; 470 ifp->if_stop = jme_stop; 471 ifp->if_timer = 0; 472 ifp->if_capabilities |= 473 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 474 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 475 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 476 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 477 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 478 IFCAP_TSOv4 | IFCAP_TSOv6; 479 IFQ_SET_READY(&ifp->if_snd); 480 if_attach(ifp); 481 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 482 483 /* 484 * Add shutdown hook so that DMA is disabled prior to reboot. 485 */ 486 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 487 pmf_class_network_register(self, ifp); 488 else 489 aprint_error_dev(self, "couldn't establish power handler\n"); 490 491 rnd_attach_source(&sc->rnd_source, device_xname(self), 492 RND_TYPE_NET, RND_FLAG_DEFAULT); 493 494 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 495 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 496 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 497 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 498 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 499 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 500 SYSCTL_DESCR("jme per-controller controls"), 501 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 502 CTL_EOL) != 0) { 503 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 504 return; 505 } 506 jme_nodenum = node->sysctl_num; 507 508 /* interrupt moderation sysctls */ 509 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 510 CTLFLAG_READWRITE, 511 CTLTYPE_INT, "int_rxto", 512 SYSCTL_DESCR("jme RX interrupt moderation timer"), 513 jme_sysctl_intrxto, 0, (void *)sc, 514 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 515 CTL_EOL) != 0) { 516 aprint_normal_dev(sc->jme_dev, 517 "couldn't create int_rxto sysctl node\n"); 518 } 519 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 520 CTLFLAG_READWRITE, 521 CTLTYPE_INT, "int_rxct", 522 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 523 jme_sysctl_intrxct, 0, (void *)sc, 524 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 525 CTL_EOL) != 0) { 526 aprint_normal_dev(sc->jme_dev, 527 "couldn't create int_rxct sysctl node\n"); 528 } 529 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 530 CTLFLAG_READWRITE, 531 CTLTYPE_INT, "int_txto", 532 SYSCTL_DESCR("jme TX interrupt moderation timer"), 533 jme_sysctl_inttxto, 0, (void *)sc, 534 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 535 CTL_EOL) != 0) { 536 aprint_normal_dev(sc->jme_dev, 537 "couldn't create int_txto sysctl node\n"); 538 } 539 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 540 CTLFLAG_READWRITE, 541 CTLTYPE_INT, "int_txct", 542 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 543 jme_sysctl_inttxct, 0, (void *)sc, 544 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 545 CTL_EOL) != 0) { 546 aprint_normal_dev(sc->jme_dev, 547 "couldn't create int_txct sysctl node\n"); 548 } 549 } 550 551 static void 552 jme_stop_rx(jme_softc_t *sc) 553 { 554 uint32_t reg; 555 int i; 556 557 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 558 if ((reg & RXCSR_RX_ENB) == 0) 559 return; 560 reg &= ~RXCSR_RX_ENB; 561 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 562 for (i = JME_TIMEOUT / 10; i > 0; i--) { 563 DELAY(10); 564 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 565 JME_RXCSR) & RXCSR_RX_ENB) == 0) 566 break; 567 } 568 if (i == 0) 569 aprint_error_dev(sc->jme_dev, "stopping receiver timeout!\n"); 570 571 } 572 573 static void 574 jme_stop_tx(jme_softc_t *sc) 575 { 576 uint32_t reg; 577 int i; 578 579 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 580 if ((reg & TXCSR_TX_ENB) == 0) 581 return; 582 reg &= ~TXCSR_TX_ENB; 583 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 584 for (i = JME_TIMEOUT / 10; i > 0; i--) { 585 DELAY(10); 586 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 587 JME_TXCSR) & TXCSR_TX_ENB) == 0) 588 break; 589 } 590 if (i == 0) 591 aprint_error_dev(sc->jme_dev, 592 "stopping transmitter timeout!\n"); 593 } 594 595 static void 596 jme_reset(jme_softc_t *sc) 597 { 598 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 599 DELAY(10); 600 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 601 } 602 603 static bool 604 jme_shutdown(device_t self, int howto) 605 { 606 jme_softc_t *sc; 607 struct ifnet *ifp; 608 609 sc = device_private(self); 610 ifp = &sc->jme_if; 611 jme_stop(ifp, 1); 612 613 return true; 614 } 615 616 static void 617 jme_stop(struct ifnet *ifp, int disable) 618 { 619 jme_softc_t *sc = ifp->if_softc; 620 int i; 621 /* Stop receiver, transmitter. */ 622 jme_stop_rx(sc); 623 jme_stop_tx(sc); 624 /* free receive mbufs */ 625 for (i = 0; i < JME_NBUFS; i++) { 626 if (sc->jme_rxmbuf[i]) { 627 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 628 m_freem(sc->jme_rxmbuf[i]); 629 } 630 sc->jme_rxmbuf[i] = NULL; 631 } 632 /* process completed transmits */ 633 jme_txeof(sc); 634 /* free abort pending transmits */ 635 for (i = 0; i < JME_NBUFS; i++) { 636 if (sc->jme_txmbuf[i]) { 637 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 638 m_freem(sc->jme_txmbuf[i]); 639 sc->jme_txmbuf[i] = NULL; 640 } 641 } 642 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 643 ifp->if_timer = 0; 644 } 645 646 #if 0 647 static void 648 jme_restart(void *v) 649 { 650 651 jme_init(v); 652 } 653 #endif 654 655 static int 656 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 657 { 658 int error; 659 bus_dmamap_t map; 660 int i = sc->jme_rx_prod; 661 662 if (sc->jme_rxmbuf[i] != NULL) { 663 aprint_error_dev(sc->jme_dev, 664 "mbuf already here: rxprod %d rxcons %d\n", 665 sc->jme_rx_prod, sc->jme_rx_cons); 666 if (m) 667 m_freem(m); 668 return EINVAL; 669 } 670 671 if (m == NULL) { 672 sc->jme_rxmbuf[i] = NULL; 673 MGETHDR(m, M_DONTWAIT, MT_DATA); 674 if (m == NULL) 675 return (ENOBUFS); 676 MCLGET(m, M_DONTWAIT); 677 if ((m->m_flags & M_EXT) == 0) { 678 m_freem(m); 679 return (ENOBUFS); 680 } 681 } 682 map = sc->jme_rxmbufm[i]; 683 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 684 KASSERT(m->m_len == MCLBYTES); 685 686 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 687 BUS_DMA_READ | BUS_DMA_NOWAIT); 688 if (error) { 689 sc->jme_rxmbuf[i] = NULL; 690 aprint_error_dev(sc->jme_dev, 691 "unable to load rx DMA map %d, error = %d\n", 692 i, error); 693 m_freem(m); 694 return (error); 695 } 696 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 697 BUS_DMASYNC_PREREAD); 698 699 sc->jme_rxmbuf[i] = m; 700 701 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 702 sc->jme_rxring[i].addr_lo = 703 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 704 sc->jme_rxring[i].addr_hi = 705 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 706 sc->jme_rxring[i].flags = 707 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 708 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 709 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 711 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 712 return (0); 713 } 714 715 static int 716 jme_ifinit(struct ifnet *ifp) 717 { 718 return jme_init(ifp, 1); 719 } 720 721 static int 722 jme_init(struct ifnet *ifp, int do_ifinit) 723 { 724 jme_softc_t *sc = ifp->if_softc; 725 int i, s; 726 uint8_t eaddr[ETHER_ADDR_LEN]; 727 uint32_t reg; 728 729 s = splnet(); 730 /* cancel any pending IO */ 731 jme_stop(ifp, 1); 732 jme_reset(sc); 733 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 734 splx(s); 735 return 0; 736 } 737 /* allocate receive ring */ 738 sc->jme_rx_prod = 0; 739 for (i = 0; i < JME_NBUFS; i++) { 740 if (jme_add_rxbuf(sc, NULL) < 0) { 741 aprint_error_dev(sc->jme_dev, 742 "can't allocate rx mbuf\n"); 743 for (i--; i >= 0; i--) { 744 bus_dmamap_unload(sc->jme_dmatag, 745 sc->jme_rxmbufm[i]); 746 m_freem(sc->jme_rxmbuf[i]); 747 sc->jme_rxmbuf[i] = NULL; 748 } 749 splx(s); 750 return ENOMEM; 751 } 752 } 753 /* init TX ring */ 754 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 755 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 756 0, JME_NBUFS * sizeof(struct jme_desc), 757 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 758 for (i = 0; i < JME_NBUFS; i++) 759 sc->jme_txmbuf[i] = NULL; 760 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 761 762 /* Reprogram the station address. */ 763 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 764 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 765 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 766 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 767 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 768 769 /* 770 * Configure Tx queue. 771 * Tx priority queue weight value : 0 772 * Tx FIFO threshold for processing next packet : 16QW 773 * Maximum Tx DMA length : 512 774 * Allow Tx DMA burst. 775 */ 776 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 777 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 778 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 779 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 780 sc->jme_txcsr |= TXCSR_DMA_BURST; 781 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 782 JME_TXCSR, sc->jme_txcsr); 783 784 /* Set Tx descriptor counter. */ 785 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 786 JME_TXQDC, JME_NBUFS); 787 788 /* Set Tx ring address to the hardware. */ 789 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 790 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 791 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 792 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 793 794 /* Configure TxMAC parameters. */ 795 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 796 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 797 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 798 799 /* 800 * Configure Rx queue. 801 * FIFO full threshold for transmitting Tx pause packet : 128T 802 * FIFO threshold for processing next packet : 128QW 803 * Rx queue 0 select 804 * Max Rx DMA length : 128 805 * Rx descriptor retry : 32 806 * Rx descriptor retry time gap : 256ns 807 * Don't receive runt/bad frame. 808 */ 809 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 810 /* 811 * Since Rx FIFO size is 4K bytes, receiving frames larger 812 * than 4K bytes will suffer from Rx FIFO overruns. So 813 * decrease FIFO threshold to reduce the FIFO overruns for 814 * frames larger than 4000 bytes. 815 * For best performance of standard MTU sized frames use 816 * maximum allowable FIFO threshold, 128QW. 817 */ 818 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 819 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 820 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 821 else 822 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 823 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 824 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 825 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 826 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 827 JME_RXCSR, sc->jme_rxcsr); 828 829 /* Set Rx descriptor counter. */ 830 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 831 JME_RXQDC, JME_NBUFS); 832 833 /* Set Rx ring address to the hardware. */ 834 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 835 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 836 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 837 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 838 839 /* Clear receive filter. */ 840 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 841 /* Set up the receive filter. */ 842 jme_set_filter(sc); 843 844 /* 845 * Disable all WOL bits as WOL can interfere normal Rx 846 * operation. Also clear WOL detection status bits. 847 */ 848 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 849 reg &= ~PMCS_WOL_ENB_MASK; 850 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 851 852 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 853 /* 854 * Pad 10bytes right before received frame. This will greatly 855 * help Rx performance on strict-alignment architectures as 856 * it does not need to copy the frame to align the payload. 857 */ 858 reg |= RXMAC_PAD_10BYTES; 859 if ((ifp->if_capenable & 860 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 861 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) != 0) 862 reg |= RXMAC_CSUM_ENB; 863 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 864 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 865 866 /* Configure general purpose reg0 */ 867 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 868 reg &= ~GPREG0_PCC_UNIT_MASK; 869 /* Set PCC timer resolution to micro-seconds unit. */ 870 reg |= GPREG0_PCC_UNIT_US; 871 /* 872 * Disable all shadow register posting as we have to read 873 * JME_INTR_STATUS register in jme_int_task. Also it seems 874 * that it's hard to synchronize interrupt status between 875 * hardware and software with shadow posting due to 876 * requirements of bus_dmamap_sync(9). 877 */ 878 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 879 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 880 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 881 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 882 /* Disable posting of DW0. */ 883 reg &= ~GPREG0_POST_DW0_ENB; 884 /* Clear PME message. */ 885 reg &= ~GPREG0_PME_ENB; 886 /* Set PHY address. */ 887 reg &= ~GPREG0_PHY_ADDR_MASK; 888 reg |= sc->jme_phyaddr; 889 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 890 891 /* Configure Tx queue 0 packet completion coalescing. */ 892 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 893 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 894 reg |= PCCTX_COAL_TXQ0; 895 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 896 897 /* Configure Rx queue 0 packet completion coalescing. */ 898 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 899 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 900 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 901 902 /* Disable Timers */ 903 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 904 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 905 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 906 907 /* Configure retry transmit period, retry limit value. */ 908 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 909 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 910 TXTRHD_RT_PERIOD_MASK) | 911 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 912 TXTRHD_RT_LIMIT_SHIFT)); 913 914 /* Disable RSS. */ 915 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 916 JME_RSSC, RSSC_DIS_RSS); 917 918 /* Initialize the interrupt mask. */ 919 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 920 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 921 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 922 JME_INTR_STATUS, 0xFFFFFFFF); 923 924 /* set media, if not already handling a media change */ 925 if (do_ifinit) { 926 int error; 927 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 928 error = 0; 929 else if (error != 0) { 930 aprint_error_dev(sc->jme_dev, "could not set media\n"); 931 splx(s); 932 return error; 933 } 934 } 935 936 /* Program MAC with resolved speed/duplex/flow-control. */ 937 jme_mac_config(sc); 938 939 /* Start receiver/transmitter. */ 940 sc->jme_rx_cons = 0; 941 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 942 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 943 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 944 sc->jme_txcsr | TXCSR_TX_ENB); 945 946 /* start ticks calls */ 947 callout_schedule(&sc->jme_tick_ch, hz); 948 sc->jme_if.if_flags |= IFF_RUNNING; 949 sc->jme_if.if_flags &= ~IFF_OACTIVE; 950 splx(s); 951 return 0; 952 } 953 954 static int 955 jme_mii_read(device_t self, int phy, int reg, uint16_t *val) 956 { 957 struct jme_softc *sc = device_private(self); 958 int data, i; 959 960 /* For FPGA version, PHY address 0 should be ignored. */ 961 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 962 if (phy == 0) 963 return -1; 964 } else { 965 if (sc->jme_phyaddr != phy) 966 return -1; 967 } 968 969 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 970 SMI_OP_READ | SMI_OP_EXECUTE | 971 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 972 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 973 delay(10); 974 if (((data = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 975 JME_SMI)) & SMI_OP_EXECUTE) == 0) 976 break; 977 } 978 979 if (i == 0) { 980 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 981 return ETIMEDOUT; 982 } 983 984 *val = (data & SMI_DATA_MASK) >> SMI_DATA_SHIFT; 985 return 0; 986 } 987 988 static int 989 jme_mii_write(device_t self, int phy, int reg, uint16_t val) 990 { 991 struct jme_softc *sc = device_private(self); 992 int i; 993 994 /* For FPGA version, PHY address 0 should be ignored. */ 995 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 996 if (phy == 0) 997 return -1; 998 } else { 999 if (sc->jme_phyaddr != phy) 1000 return -1; 1001 } 1002 1003 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1004 SMI_OP_WRITE | SMI_OP_EXECUTE | 1005 (((uint32_t)val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1006 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1007 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1008 delay(10); 1009 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1010 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1011 break; 1012 } 1013 1014 if (i == 0) { 1015 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1016 return ETIMEDOUT; 1017 } 1018 1019 return 0; 1020 } 1021 1022 static void 1023 jme_statchg(struct ifnet *ifp) 1024 { 1025 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1026 jme_init(ifp, 0); 1027 } 1028 1029 static void 1030 jme_intr_rx(jme_softc_t *sc) { 1031 struct mbuf *m, *mhead; 1032 bus_dmamap_t mmap; 1033 struct ifnet *ifp = &sc->jme_if; 1034 uint32_t flags, buflen; 1035 int i, ipackets, nsegs, seg, error; 1036 struct jme_desc *desc; 1037 1038 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1039 sizeof(struct jme_desc) * JME_NBUFS, 1040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1041 #ifdef JMEDEBUG_RX 1042 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1043 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1044 #endif 1045 ipackets = 0; 1046 while ((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) 1047 == 0) { 1048 i = sc->jme_rx_cons; 1049 desc = &sc->jme_rxring[i]; 1050 #ifdef JMEDEBUG_RX 1051 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1052 i, le32toh(desc->flags), le32toh(desc->buflen)); 1053 #endif 1054 if (sc->jme_rxmbuf[i] == NULL) { 1055 if ((error = jme_add_rxbuf(sc, NULL)) != 0) { 1056 aprint_error_dev(sc->jme_dev, 1057 "can't add new mbuf to empty slot: %d\n", 1058 error); 1059 break; 1060 } 1061 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1062 i = sc->jme_rx_cons; 1063 continue; 1064 } 1065 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1066 break; 1067 1068 buflen = le32toh(desc->buflen); 1069 nsegs = JME_RX_NSEGS(buflen); 1070 flags = le32toh(desc->flags); 1071 if ((buflen & JME_RX_ERR_STAT) != 0 || 1072 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1073 JME_RX_BYTES(buflen) > 1074 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1075 #ifdef JMEDEBUG_RX 1076 printf("rx error flags 0x%x buflen 0x%x\n", 1077 flags, buflen); 1078 #endif 1079 if_statinc(ifp, if_ierrors); 1080 /* reuse the mbufs */ 1081 for (seg = 0; seg < nsegs; seg++) { 1082 m = sc->jme_rxmbuf[i]; 1083 sc->jme_rxmbuf[i] = NULL; 1084 mmap = sc->jme_rxmbufm[i]; 1085 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1086 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1087 bus_dmamap_unload(sc->jme_dmatag, mmap); 1088 if ((error = jme_add_rxbuf(sc, m)) != 0) 1089 aprint_error_dev(sc->jme_dev, 1090 "can't reuse mbuf: %d\n", error); 1091 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1092 i = sc->jme_rx_cons; 1093 } 1094 continue; 1095 } 1096 /* receive this packet */ 1097 mhead = m = sc->jme_rxmbuf[i]; 1098 sc->jme_rxmbuf[i] = NULL; 1099 mmap = sc->jme_rxmbufm[i]; 1100 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1101 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1102 bus_dmamap_unload(sc->jme_dmatag, mmap); 1103 /* add a new buffer to chain */ 1104 if (jme_add_rxbuf(sc, NULL) != 0) { 1105 if ((error = jme_add_rxbuf(sc, m)) != 0) 1106 aprint_error_dev(sc->jme_dev, 1107 "can't reuse mbuf: %d\n", error); 1108 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1109 i = sc->jme_rx_cons; 1110 for (seg = 1; seg < nsegs; seg++) { 1111 m = sc->jme_rxmbuf[i]; 1112 sc->jme_rxmbuf[i] = NULL; 1113 mmap = sc->jme_rxmbufm[i]; 1114 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1115 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1116 bus_dmamap_unload(sc->jme_dmatag, mmap); 1117 if ((error = jme_add_rxbuf(sc, m)) != 0) 1118 aprint_error_dev(sc->jme_dev, 1119 "can't reuse mbuf: %d\n", error); 1120 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1121 i = sc->jme_rx_cons; 1122 } 1123 if_statinc(ifp, if_ierrors); 1124 continue; 1125 } 1126 1127 /* build mbuf chain: head, then remaining segments */ 1128 m_set_rcvif(m, ifp); 1129 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1130 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1131 m->m_pkthdr.len; 1132 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1133 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1134 for (seg = 1; seg < nsegs; seg++) { 1135 i = sc->jme_rx_cons; 1136 m = sc->jme_rxmbuf[i]; 1137 sc->jme_rxmbuf[i] = NULL; 1138 mmap = sc->jme_rxmbufm[i]; 1139 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1140 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1141 bus_dmamap_unload(sc->jme_dmatag, mmap); 1142 if ((error = jme_add_rxbuf(sc, NULL)) != 0) 1143 aprint_error_dev(sc->jme_dev, 1144 "can't add new mbuf: %d\n", error); 1145 m->m_flags &= ~M_PKTHDR; 1146 m_cat(mhead, m); 1147 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1148 } 1149 /* and adjust last mbuf's size */ 1150 if (nsegs > 1) { 1151 m->m_len = 1152 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1153 } 1154 ipackets++; 1155 1156 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1157 (flags & JME_RD_IPV4)) { 1158 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1159 if (!(flags & JME_RD_IPCSUM)) 1160 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1161 } 1162 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1163 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1164 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1165 if (!(flags & JME_RD_TCPCSUM)) 1166 mhead->m_pkthdr.csum_flags |= 1167 M_CSUM_TCP_UDP_BAD; 1168 } 1169 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1170 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1171 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1172 if (!(flags & JME_RD_UDPCSUM)) 1173 mhead->m_pkthdr.csum_flags |= 1174 M_CSUM_TCP_UDP_BAD; 1175 } 1176 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1177 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1178 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1179 if (!(flags & JME_RD_TCPCSUM)) 1180 mhead->m_pkthdr.csum_flags |= 1181 M_CSUM_TCP_UDP_BAD; 1182 } 1183 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1184 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1185 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1186 if (!(flags & JME_RD_UDPCSUM)) 1187 mhead->m_pkthdr.csum_flags |= 1188 M_CSUM_TCP_UDP_BAD; 1189 } 1190 if (flags & JME_RD_VLAN_TAG) { 1191 /* pass to vlan_input() */ 1192 vlan_set_tag(mhead, (flags & JME_RD_VLAN_MASK)); 1193 } 1194 if_percpuq_enqueue(ifp->if_percpuq, mhead); 1195 } 1196 if (ipackets) 1197 rnd_add_uint32(&sc->rnd_source, ipackets); 1198 } 1199 1200 static int 1201 jme_intr(void *v) 1202 { 1203 jme_softc_t *sc = v; 1204 uint32_t istatus; 1205 1206 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1207 JME_INTR_STATUS); 1208 if (istatus == 0 || istatus == 0xFFFFFFFF) 1209 return 0; 1210 /* Disable interrupts. */ 1211 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1212 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1213 again: 1214 /* and update istatus */ 1215 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1216 JME_INTR_STATUS); 1217 if ((istatus & JME_INTRS_CHECK) == 0) 1218 goto done; 1219 /* Reset PCC counter/timer and Ack interrupts. */ 1220 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1221 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1222 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1223 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1224 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1225 JME_INTR_STATUS, istatus); 1226 1227 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1228 goto done; 1229 #ifdef JMEDEBUG_RX 1230 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1231 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1232 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1233 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1234 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1235 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1236 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1237 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1238 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1239 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1240 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1241 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1242 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1243 #endif 1244 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1245 jme_intr_rx(sc); 1246 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1247 /* 1248 * Notify hardware availability of new Rx 1249 * buffers. 1250 * Reading RXCSR takes very long time under 1251 * heavy load so cache RXCSR value and writes 1252 * the ORed value with the kick command to 1253 * the RXCSR. This saves one register access 1254 * cycle. 1255 */ 1256 sc->jme_rx_cons = 0; 1257 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1258 JME_RXCSR, 1259 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1260 } 1261 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1262 jme_ifstart(&sc->jme_if); 1263 1264 goto again; 1265 1266 done: 1267 /* enable interrupts. */ 1268 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1269 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1270 return 1; 1271 } 1272 1273 1274 static int 1275 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1276 { 1277 struct jme_softc *sc = ifp->if_softc; 1278 int s, error; 1279 struct ifreq *ifr; 1280 struct ifcapreq *ifcr; 1281 1282 s = splnet(); 1283 /* 1284 * we can't support at the same time jumbo frames and 1285 * TX checksums offload/TSO 1286 */ 1287 switch (cmd) { 1288 case SIOCSIFMTU: 1289 ifr = data; 1290 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1291 (ifp->if_capenable & ( 1292 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1293 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1294 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1295 splx(s); 1296 return EINVAL; 1297 } 1298 break; 1299 case SIOCSIFCAP: 1300 ifcr = data; 1301 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1302 (ifcr->ifcr_capenable & ( 1303 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1304 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1305 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1306 splx(s); 1307 return EINVAL; 1308 } 1309 break; 1310 } 1311 1312 error = ether_ioctl(ifp, cmd, data); 1313 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1314 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1315 jme_set_filter(sc); 1316 error = 0; 1317 } else { 1318 error = jme_init(ifp, 0); 1319 } 1320 } 1321 splx(s); 1322 return error; 1323 } 1324 1325 static int 1326 jme_encap(struct jme_softc *sc, struct mbuf * const m) 1327 { 1328 struct jme_desc *desc; 1329 int error, i, prod, headdsc, nsegs; 1330 uint32_t cflags, tso_segsz; 1331 1332 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1333 /* 1334 * Due to the adherence to NDIS specification JMC250 1335 * assumes upper stack computed TCP pseudo checksum 1336 * without including payload length. This breaks 1337 * checksum offload for TSO case so recompute TCP 1338 * pseudo checksum for JMC250. Hopefully this wouldn't 1339 * be much burden on modern CPUs. 1340 */ 1341 bool v4 = (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1342 int iphl = v4 ? 1343 M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data) : 1344 M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 1345 /* 1346 * note: we support vlan offloading, so we should never have 1347 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1348 * right. 1349 */ 1350 int hlen = ETHER_HDR_LEN + iphl; 1351 1352 if (__predict_false(m->m_len < 1353 (hlen + sizeof(struct tcphdr)))) { 1354 /* 1355 * 1356 * TCP/IP headers are not in the first mbuf; we need 1357 * to do this the slow and painful way. Let's just 1358 * hope this doesn't happen very often. 1359 */ 1360 struct tcphdr th; 1361 1362 m_copydata(m, hlen, sizeof(th), &th); 1363 if (v4) { 1364 struct ip ip; 1365 1366 m_copydata(m, ETHER_HDR_LEN, sizeof(ip), &ip); 1367 ip.ip_len = 0; 1368 m_copyback(m, 1369 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1370 sizeof(ip.ip_len), &ip.ip_len); 1371 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1372 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1373 } else { 1374 #if INET6 1375 struct ip6_hdr ip6; 1376 1377 m_copydata(m, ETHER_HDR_LEN, 1378 sizeof(ip6), &ip6); 1379 ip6.ip6_plen = 0; 1380 m_copyback(m, ETHER_HDR_LEN + 1381 offsetof(struct ip6_hdr, ip6_plen), 1382 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1383 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1384 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1385 #endif /* INET6 */ 1386 } 1387 m_copyback(m, hlen + offsetof(struct tcphdr, th_sum), 1388 sizeof(th.th_sum), &th.th_sum); 1389 1390 hlen += th.th_off << 2; 1391 } else { 1392 /* 1393 * TCP/IP headers are in the first mbuf; we can do 1394 * this the easy way. 1395 */ 1396 struct tcphdr *th; 1397 1398 if (v4) { 1399 struct ip *ip = 1400 (void *)(mtod(m, char *) + 1401 ETHER_HDR_LEN); 1402 th = (void *)(mtod(m, char *) + hlen); 1403 1404 ip->ip_len = 0; 1405 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1406 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1407 } else { 1408 #if INET6 1409 struct ip6_hdr *ip6 = 1410 (void *)(mtod(m, char *) + 1411 ETHER_HDR_LEN); 1412 th = (void *)(mtod(m, char *) + hlen); 1413 1414 ip6->ip6_plen = 0; 1415 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1416 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1417 #endif /* INET6 */ 1418 } 1419 hlen += th->th_off << 2; 1420 } 1421 } 1422 1423 prod = sc->jme_tx_prod; 1424 1425 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1426 m, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1427 if (error) { 1428 if (error == EFBIG) { 1429 log(LOG_ERR, "%s: Tx packet consumes too many " 1430 "DMA segments, dropping...\n", 1431 device_xname(sc->jme_dev)); 1432 /* Caller will free the packet. */ 1433 } 1434 return (error); 1435 } 1436 /* 1437 * Check descriptor overrun. Leave one free descriptor. 1438 * Since we always use 64bit address mode for transmitting, 1439 * each Tx request requires one more dummy descriptor. 1440 */ 1441 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1442 #ifdef JMEDEBUG_TX 1443 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1444 #endif 1445 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1446 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1447 return (ENOBUFS); 1448 } 1449 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1450 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1451 1452 cflags = 0; 1453 tso_segsz = 0; 1454 /* Configure checksum offload and TSO. */ 1455 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1456 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1457 cflags |= JME_TD_TSO; 1458 } else { 1459 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1460 cflags |= JME_TD_IPCSUM; 1461 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) 1462 != 0) 1463 cflags |= JME_TD_TCPCSUM; 1464 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) 1465 != 0) 1466 cflags |= JME_TD_UDPCSUM; 1467 } 1468 /* Configure VLAN. */ 1469 if (vlan_has_tag(m)) { 1470 cflags |= (vlan_get_tag(m) & JME_TD_VLAN_MASK); 1471 cflags |= JME_TD_VLAN_TAG; 1472 } 1473 1474 desc = &sc->jme_txring[prod]; 1475 desc->flags = htole32(cflags); 1476 desc->buflen = htole32(tso_segsz); 1477 desc->addr_hi = htole32(m->m_pkthdr.len); 1478 desc->addr_lo = 0; 1479 headdsc = prod; 1480 sc->jme_tx_cnt++; 1481 JME_DESC_INC(prod, JME_NBUFS); 1482 for (i = 0; i < nsegs; i++) { 1483 desc = &sc->jme_txring[prod]; 1484 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1485 desc->buflen = 1486 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1487 desc->addr_hi = htole32( 1488 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1489 desc->addr_lo = htole32( 1490 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1491 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1492 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1494 sc->jme_txmbuf[prod] = NULL; 1495 sc->jme_tx_cnt++; 1496 JME_DESC_INC(prod, JME_NBUFS); 1497 } 1498 1499 /* Update producer index. */ 1500 sc->jme_tx_prod = prod; 1501 #ifdef JMEDEBUG_TX 1502 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1503 #endif 1504 /* 1505 * Finally request interrupt and give the first descriptor 1506 * ownership to hardware. 1507 */ 1508 desc = &sc->jme_txring[headdsc]; 1509 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1510 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1511 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1512 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1513 1514 sc->jme_txmbuf[headdsc] = m; 1515 return (0); 1516 } 1517 1518 static void 1519 jme_txeof(struct jme_softc *sc) 1520 { 1521 struct ifnet *ifp; 1522 struct jme_desc *desc; 1523 uint32_t status; 1524 int cons, cons0, nsegs, seg; 1525 1526 ifp = &sc->jme_if; 1527 1528 #ifdef JMEDEBUG_TX 1529 printf("jme_txeof cons %d prod %d\n", 1530 sc->jme_tx_cons, sc->jme_tx_prod); 1531 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1532 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1533 "JME_TXTRHD 0x%x\n", 1534 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1535 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1536 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1537 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1538 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1539 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1540 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1541 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1542 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1543 desc = &sc->jme_txring[cons]; 1544 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1545 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1546 JME_DESC_INC(cons, JME_NBUFS); 1547 } 1548 #endif 1549 1550 cons = sc->jme_tx_cons; 1551 if (cons == sc->jme_tx_prod) 1552 return; 1553 1554 /* 1555 * Go through our Tx list and free mbufs for those 1556 * frames which have been transmitted. 1557 */ 1558 for (; cons != sc->jme_tx_prod;) { 1559 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1560 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1561 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1562 1563 desc = &sc->jme_txring[cons]; 1564 status = le32toh(desc->flags); 1565 #ifdef JMEDEBUG_TX 1566 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1567 sc->jme_txmbufm[cons]->dm_nsegs); 1568 #endif 1569 if (status & JME_TD_OWN) 1570 break; 1571 1572 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1573 if_statinc(ifp, if_oerrors); 1574 else { 1575 if_statinc(ifp, if_opackets); 1576 if ((status & JME_TD_COLLISION) != 0) { 1577 if_statadd(ifp, if_collisions, 1578 le32toh(desc->buflen) & 1579 JME_TD_BUF_LEN_MASK); 1580 } 1581 } 1582 /* 1583 * Only the first descriptor of multi-descriptor 1584 * transmission is updated so driver have to skip entire 1585 * chained buffers for the transmitted frame. In other 1586 * words, JME_TD_OWN bit is valid only at the first 1587 * descriptor of a multi-descriptor transmission. 1588 */ 1589 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1590 cons0 = cons; 1591 JME_DESC_INC(cons, JME_NBUFS); 1592 for (seg = 1; seg < nsegs + 1; seg++) { 1593 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1594 cons * sizeof(struct jme_desc), 1595 sizeof(struct jme_desc), 1596 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1597 sc->jme_txring[cons].flags = 0; 1598 JME_DESC_INC(cons, JME_NBUFS); 1599 } 1600 /* Reclaim transferred mbufs. */ 1601 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1602 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1603 BUS_DMASYNC_POSTWRITE); 1604 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1605 1606 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1607 m_freem(sc->jme_txmbuf[cons0]); 1608 sc->jme_txmbuf[cons0] = NULL; 1609 sc->jme_tx_cnt -= nsegs + 1; 1610 KASSERT(sc->jme_tx_cnt >= 0); 1611 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1612 } 1613 sc->jme_tx_cons = cons; 1614 /* Unarm watchdog timer when there are no pending descriptors in queue. */ 1615 if (sc->jme_tx_cnt == 0) 1616 ifp->if_timer = 0; 1617 #ifdef JMEDEBUG_TX 1618 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1619 #endif 1620 } 1621 1622 static void 1623 jme_ifstart(struct ifnet *ifp) 1624 { 1625 jme_softc_t *sc = ifp->if_softc; 1626 struct mbuf *mb_head; 1627 int enq, error; 1628 1629 /* 1630 * check if we can free some desc. 1631 * Clear TX interrupt status to reset TX coalescing counters. 1632 */ 1633 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1634 JME_INTR_STATUS, INTR_TXQ_COMP); 1635 jme_txeof(sc); 1636 1637 if ((sc->jme_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1638 return; 1639 for (enq = 0;; enq++) { 1640 nexttx: 1641 /* Grab a paquet for output */ 1642 IFQ_POLL(&ifp->if_snd, mb_head); 1643 if (mb_head == NULL) { 1644 #ifdef JMEDEBUG_TX 1645 printf("%s: nothing to send\n", __func__); 1646 #endif 1647 break; 1648 } 1649 /* try to add this mbuf to the TX ring */ 1650 if ((error = jme_encap(sc, mb_head)) != 0) { 1651 if (error == EFBIG) { 1652 /* This error is fatal to the packet. */ 1653 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1654 m_freem(mb_head); 1655 if_statinc(ifp, if_oerrors); 1656 goto nexttx; 1657 } 1658 /* resource shortage, try again later */ 1659 ifp->if_flags |= IFF_OACTIVE; 1660 break; 1661 } 1662 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1663 1664 /* Pass packet to bpf if there is a listener */ 1665 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1666 } 1667 #ifdef JMEDEBUG_TX 1668 printf("jme_ifstart enq %d\n", enq); 1669 #endif 1670 if (enq) { 1671 /* 1672 * Set a 5 second timer just in case we don't hear from 1673 * the card again. 1674 */ 1675 ifp->if_timer = 5; 1676 /* 1677 * Reading TXCSR takes very long time under heavy load 1678 * so cache TXCSR value and writes the ORed value with 1679 * the kick command to the TXCSR. This saves one register 1680 * access cycle. 1681 */ 1682 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1683 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1684 #ifdef JMEDEBUG_TX 1685 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1686 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1687 "JME_TXTRHD 0x%x\n", 1688 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1689 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1690 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1691 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1692 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1693 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1694 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1695 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1696 #endif 1697 } 1698 } 1699 1700 static void 1701 jme_ifwatchdog(struct ifnet *ifp) 1702 { 1703 jme_softc_t *sc = ifp->if_softc; 1704 1705 if ((ifp->if_flags & IFF_RUNNING) == 0) 1706 return; 1707 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1708 if_statinc(ifp, if_oerrors); 1709 jme_init(ifp, 0); 1710 } 1711 1712 static int 1713 jme_mediachange(struct ifnet *ifp) 1714 { 1715 int error; 1716 jme_softc_t *sc = ifp->if_softc; 1717 1718 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1719 error = 0; 1720 else if (error != 0) { 1721 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1722 return error; 1723 } 1724 return 0; 1725 } 1726 1727 static void 1728 jme_ticks(void *v) 1729 { 1730 jme_softc_t *sc = v; 1731 int s = splnet(); 1732 1733 /* Tick the MII. */ 1734 mii_tick(&sc->jme_mii); 1735 1736 /* every seconds */ 1737 callout_schedule(&sc->jme_tick_ch, hz); 1738 splx(s); 1739 } 1740 1741 static void 1742 jme_mac_config(jme_softc_t *sc) 1743 { 1744 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1745 struct mii_data *mii = &sc->jme_mii; 1746 1747 ghc = 0; 1748 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1749 rxmac &= ~RXMAC_FC_ENB; 1750 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1751 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1752 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1753 txpause &= ~TXPFC_PAUSE_ENB; 1754 1755 if (mii->mii_media_active & IFM_FDX) { 1756 ghc |= GHC_FULL_DUPLEX; 1757 rxmac &= ~RXMAC_COLL_DET_ENB; 1758 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1759 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1760 TXMAC_FRAME_BURST); 1761 /* Disable retry transmit timer/retry limit. */ 1762 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1763 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1764 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1765 } else { 1766 rxmac |= RXMAC_COLL_DET_ENB; 1767 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1768 /* Enable retry transmit timer/retry limit. */ 1769 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1770 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1771 } 1772 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1773 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1774 case IFM_10_T: 1775 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1776 break; 1777 case IFM_100_TX: 1778 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1779 break; 1780 case IFM_1000_T: 1781 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1782 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1783 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1784 break; 1785 default: 1786 break; 1787 } 1788 if ((sc->jme_flags & JME_FLAG_GIGA) && 1789 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1790 /* 1791 * Workaround occasional packet loss issue of JMC250 A2 1792 * when it runs on half-duplex media. 1793 */ 1794 #ifdef JMEDEBUG 1795 printf("JME250 A2 workaround\n"); 1796 #endif 1797 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1798 JME_GPREG1); 1799 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1800 gpreg &= ~GPREG1_HDPX_FIX; 1801 else 1802 gpreg |= GPREG1_HDPX_FIX; 1803 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1804 JME_GPREG1, gpreg); 1805 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1806 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1807 /* Extend interface FIFO depth. */ 1808 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1809 0x1B, 0x0000); 1810 } else { 1811 /* Select default interface FIFO depth. */ 1812 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1813 0x1B, 0x0004); 1814 } 1815 } 1816 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1817 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1818 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1819 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1820 } 1821 1822 static void 1823 jme_set_filter(jme_softc_t *sc) 1824 { 1825 struct ethercom *ec = &sc->jme_ec; 1826 struct ifnet *ifp = &sc->jme_if; 1827 struct ether_multistep step; 1828 struct ether_multi *enm; 1829 uint32_t hash[2] = {0, 0}; 1830 int i; 1831 uint32_t rxcfg; 1832 1833 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1834 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1835 RXMAC_ALLMULTI); 1836 /* Always accept frames destined to our station address. */ 1837 rxcfg |= RXMAC_UNICAST; 1838 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1839 rxcfg |= RXMAC_BROADCAST; 1840 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1841 if ((ifp->if_flags & IFF_PROMISC) != 0) 1842 rxcfg |= RXMAC_PROMISC; 1843 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1844 rxcfg |= RXMAC_ALLMULTI; 1845 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1846 JME_MAR0, 0xFFFFFFFF); 1847 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1848 JME_MAR1, 0xFFFFFFFF); 1849 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1850 JME_RXMAC, rxcfg); 1851 return; 1852 } 1853 /* 1854 * Set up the multicast address filter by passing all multicast 1855 * addresses through a CRC generator, and then using the low-order 1856 * 6 bits as an index into the 64 bit multicast hash table. The 1857 * high order bits select the register, while the rest of the bits 1858 * select the bit within the register. 1859 */ 1860 rxcfg |= RXMAC_MULTICAST; 1861 memset(hash, 0, sizeof(hash)); 1862 1863 ETHER_LOCK(ec); 1864 ETHER_FIRST_MULTI(step, ec, enm); 1865 while (enm != NULL) { 1866 #ifdef JEMDBUG 1867 printf("%s: addrs %s %s\n", __func__, 1868 ether_sprintf(enm->enm_addrlo), 1869 ether_sprintf(enm->enm_addrhi)); 1870 #endif 1871 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1872 i = ether_crc32_be(enm->enm_addrlo, 6); 1873 /* Just want the 6 least significant bits. */ 1874 i &= 0x3f; 1875 hash[i / 32] |= 1 << (i%32); 1876 } else { 1877 hash[0] = hash[1] = 0xffffffff; 1878 sc->jme_if.if_flags |= IFF_ALLMULTI; 1879 break; 1880 } 1881 ETHER_NEXT_MULTI(step, enm); 1882 } 1883 ETHER_UNLOCK(ec); 1884 #ifdef JMEDEBUG 1885 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1886 #endif 1887 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1888 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1889 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1890 } 1891 1892 #if 0 1893 static int 1894 jme_multicast_hash(uint8_t *a) 1895 { 1896 int hash; 1897 1898 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1899 #define xor8(a,b,c,d,e,f,g,h) \ 1900 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1901 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1902 1903 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1904 DA(a,36), DA(a,42)); 1905 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1906 DA(a,37), DA(a,43)) << 1; 1907 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1908 DA(a,38), DA(a,44)) << 2; 1909 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1910 DA(a,39), DA(a,45)) << 3; 1911 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1912 DA(a,40), DA(a,46)) << 4; 1913 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1914 DA(a,41), DA(a,47)) << 5; 1915 1916 return hash; 1917 } 1918 #endif 1919 1920 static int 1921 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1922 { 1923 uint32_t reg; 1924 int i; 1925 1926 *val = 0; 1927 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1928 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1929 JME_SMBCSR); 1930 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1931 break; 1932 delay(10); 1933 } 1934 1935 if (i == 0) { 1936 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1937 return (ETIMEDOUT); 1938 } 1939 1940 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1941 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1942 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1943 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1944 delay(10); 1945 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1946 JME_SMBINTF); 1947 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1948 break; 1949 } 1950 1951 if (i == 0) { 1952 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1953 return (ETIMEDOUT); 1954 } 1955 1956 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1957 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1958 return (0); 1959 } 1960 1961 1962 static int 1963 jme_eeprom_macaddr(struct jme_softc *sc) 1964 { 1965 uint8_t eaddr[ETHER_ADDR_LEN]; 1966 uint8_t fup, reg, val; 1967 uint32_t offset; 1968 int match; 1969 1970 offset = 0; 1971 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1972 fup != JME_EEPROM_SIG0) 1973 return (ENOENT); 1974 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1975 fup != JME_EEPROM_SIG1) 1976 return (ENOENT); 1977 match = 0; 1978 do { 1979 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 1980 break; 1981 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 1982 == (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 1983 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 1984 break; 1985 if (reg >= JME_PAR0 && 1986 reg < JME_PAR0 + ETHER_ADDR_LEN) { 1987 if (jme_eeprom_read_byte(sc, offset + 2, 1988 &val) != 0) 1989 break; 1990 eaddr[reg - JME_PAR0] = val; 1991 match++; 1992 } 1993 } 1994 if (fup & JME_EEPROM_DESC_END) 1995 break; 1996 1997 /* Try next eeprom descriptor. */ 1998 offset += JME_EEPROM_DESC_BYTES; 1999 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2000 2001 if (match == ETHER_ADDR_LEN) { 2002 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2003 return (0); 2004 } 2005 2006 return (ENOENT); 2007 } 2008 2009 static int 2010 jme_reg_macaddr(struct jme_softc *sc) 2011 { 2012 uint32_t par0, par1; 2013 2014 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2015 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2016 par1 &= 0xffff; 2017 if ((par0 == 0 && par1 == 0) || 2018 (par0 == 0xffffffff && par1 == 0xffff)) { 2019 return (ENOENT); 2020 } else { 2021 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2022 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2023 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2024 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2025 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2026 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2027 } 2028 return (0); 2029 } 2030 2031 /* 2032 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2033 * set up in jme_pci_attach() 2034 */ 2035 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2036 { 2037 int rc; 2038 const struct sysctlnode *node; 2039 2040 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2041 0, CTLTYPE_NODE, "jme", 2042 SYSCTL_DESCR("jme interface controls"), 2043 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2044 goto err; 2045 } 2046 2047 jme_root_num = node->sysctl_num; 2048 return; 2049 2050 err: 2051 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2052 } 2053 2054 static int 2055 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2056 { 2057 int error, t; 2058 struct sysctlnode node; 2059 struct jme_softc *sc; 2060 uint32_t reg; 2061 2062 node = *rnode; 2063 sc = node.sysctl_data; 2064 t = sc->jme_intrxto; 2065 node.sysctl_data = &t; 2066 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2067 if (error || newp == NULL) 2068 return error; 2069 2070 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2071 return EINVAL; 2072 2073 /* 2074 * update the softc with sysctl-changed value, and mark 2075 * for hardware update 2076 */ 2077 sc->jme_intrxto = t; 2078 /* Configure Rx queue 0 packet completion coalescing. */ 2079 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2080 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2081 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2082 return 0; 2083 } 2084 2085 static int 2086 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2087 { 2088 int error, t; 2089 struct sysctlnode node; 2090 struct jme_softc *sc; 2091 uint32_t reg; 2092 2093 node = *rnode; 2094 sc = node.sysctl_data; 2095 t = sc->jme_intrxct; 2096 node.sysctl_data = &t; 2097 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2098 if (error || newp == NULL) 2099 return error; 2100 2101 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2102 return EINVAL; 2103 2104 /* 2105 * update the softc with sysctl-changed value, and mark 2106 * for hardware update 2107 */ 2108 sc->jme_intrxct = t; 2109 /* Configure Rx queue 0 packet completion coalescing. */ 2110 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2111 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2112 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2113 return 0; 2114 } 2115 2116 static int 2117 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2118 { 2119 int error, t; 2120 struct sysctlnode node; 2121 struct jme_softc *sc; 2122 uint32_t reg; 2123 2124 node = *rnode; 2125 sc = node.sysctl_data; 2126 t = sc->jme_inttxto; 2127 node.sysctl_data = &t; 2128 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2129 if (error || newp == NULL) 2130 return error; 2131 2132 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2133 return EINVAL; 2134 2135 /* 2136 * update the softc with sysctl-changed value, and mark 2137 * for hardware update 2138 */ 2139 sc->jme_inttxto = t; 2140 /* Configure Tx queue 0 packet completion coalescing. */ 2141 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2142 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2143 reg |= PCCTX_COAL_TXQ0; 2144 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2145 return 0; 2146 } 2147 2148 static int 2149 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2150 { 2151 int error, t; 2152 struct sysctlnode node; 2153 struct jme_softc *sc; 2154 uint32_t reg; 2155 2156 node = *rnode; 2157 sc = node.sysctl_data; 2158 t = sc->jme_inttxct; 2159 node.sysctl_data = &t; 2160 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2161 if (error || newp == NULL) 2162 return error; 2163 2164 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2165 return EINVAL; 2166 2167 /* 2168 * update the softc with sysctl-changed value, and mark 2169 * for hardware update 2170 */ 2171 sc->jme_inttxct = t; 2172 /* Configure Tx queue 0 packet completion coalescing. */ 2173 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2174 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2175 reg |= PCCTX_COAL_TXQ0; 2176 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2177 return 0; 2178 } 2179