1 /* $NetBSD: if_jme.c,v 1.19 2012/02/02 19:43:05 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.19 2012/02/02 19:43:05 tls Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 74 #include <sys/device.h> 75 #include <sys/syslog.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #if defined(SIOCSIFMEDIA) 80 #include <net/if_media.h> 81 #endif 82 #include <net/if_types.h> 83 #include <net/if_dl.h> 84 #include <net/route.h> 85 #include <net/netisr.h> 86 87 #include <net/bpf.h> 88 #include <net/bpfdesc.h> 89 90 #include <sys/rnd.h> 91 92 #include <netinet/in.h> 93 #include <netinet/in_systm.h> 94 #include <netinet/ip.h> 95 96 #ifdef INET 97 #include <netinet/in_var.h> 98 #endif 99 100 #include <netinet/tcp.h> 101 102 #include <net/if_ether.h> 103 #if defined(INET) 104 #include <netinet/if_inarp.h> 105 #endif 106 107 #include <sys/bus.h> 108 #include <sys/intr.h> 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 #include <dev/pci/if_jmereg.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/miivar.h> 117 118 struct jme_product_desc { 119 u_int32_t jme_product; 120 const char *jme_desc; 121 }; 122 123 /* number of entries in transmit and receive rings */ 124 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 125 126 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 127 128 /* Water mark to kick reclaiming Tx buffers. */ 129 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 130 131 132 struct jme_softc { 133 device_t jme_dev; /* base device */ 134 bus_space_tag_t jme_bt_mac; 135 bus_space_handle_t jme_bh_mac; /* Mac registers */ 136 bus_space_tag_t jme_bt_phy; 137 bus_space_handle_t jme_bh_phy; /* PHY registers */ 138 bus_space_tag_t jme_bt_misc; 139 bus_space_handle_t jme_bh_misc; /* Misc registers */ 140 bus_dma_tag_t jme_dmatag; 141 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 142 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 143 struct jme_desc* jme_txring; /* transmit ring */ 144 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 145 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 146 int jme_tx_cons; /* transmit ring consumer */ 147 int jme_tx_prod; /* transmit ring producer */ 148 int jme_tx_cnt; /* transmit ring active count */ 149 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 150 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 151 struct jme_desc* jme_rxring; /* receive ring */ 152 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 153 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 154 int jme_rx_cons; /* receive ring consumer */ 155 int jme_rx_prod; /* receive ring producer */ 156 void* jme_ih; /* our interrupt */ 157 struct ethercom jme_ec; 158 struct callout jme_tick_ch; /* tick callout */ 159 u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 160 u_int8_t jme_phyaddr; /* address of integrated phy */ 161 u_int8_t jme_chip_rev; /* chip revision */ 162 u_int8_t jme_rev; /* PCI revision */ 163 mii_data_t jme_mii; /* mii bus */ 164 u_int32_t jme_flags; /* device features, see below */ 165 uint32_t jme_txcsr; /* TX config register */ 166 uint32_t jme_rxcsr; /* RX config register */ 167 krndsource_t rnd_source; 168 /* interrupt coalition parameters */ 169 struct sysctllog *jme_clog; 170 int jme_intrxto; /* interrupt RX timeout */ 171 int jme_intrxct; /* interrupt RX packets counter */ 172 int jme_inttxto; /* interrupt TX timeout */ 173 int jme_inttxct; /* interrupt TX packets counter */ 174 }; 175 176 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 177 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 178 179 180 #define jme_if jme_ec.ec_if 181 #define jme_bpf jme_if.if_bpf 182 183 typedef struct jme_softc jme_softc_t; 184 typedef u_long ioctl_cmd_t; 185 186 static int jme_pci_match(device_t, cfdata_t, void *); 187 static void jme_pci_attach(device_t, device_t, void *); 188 static void jme_intr_rx(jme_softc_t *); 189 static int jme_intr(void *); 190 191 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 192 static int jme_mediachange(struct ifnet *); 193 static void jme_ifwatchdog(struct ifnet *); 194 static bool jme_shutdown(device_t, int); 195 196 static void jme_txeof(struct jme_softc *); 197 static void jme_ifstart(struct ifnet *); 198 static void jme_reset(jme_softc_t *); 199 static int jme_ifinit(struct ifnet *); 200 static int jme_init(struct ifnet *, int); 201 static void jme_stop(struct ifnet *, int); 202 // static void jme_restart(void *); 203 static void jme_ticks(void *); 204 static void jme_mac_config(jme_softc_t *); 205 static void jme_set_filter(jme_softc_t *); 206 207 int jme_mii_read(device_t, int, int); 208 void jme_mii_write(device_t, int, int, int); 209 void jme_statchg(device_t); 210 211 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 212 static int jme_eeprom_macaddr(struct jme_softc *); 213 static int jme_reg_macaddr(struct jme_softc *); 214 215 #define JME_TIMEOUT 1000 216 #define JME_PHY_TIMEOUT 1000 217 #define JME_EEPROM_TIMEOUT 1000 218 219 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 220 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 221 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 222 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 223 static int jme_root_num; 224 225 226 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 227 jme_pci_match, jme_pci_attach, NULL, NULL); 228 229 static const struct jme_product_desc jme_products[] = { 230 { PCI_PRODUCT_JMICRON_JMC250, 231 "JMicron JMC250 Gigabit Ethernet Controller" }, 232 { PCI_PRODUCT_JMICRON_JMC260, 233 "JMicron JMC260 Gigabit Ethernet Controller" }, 234 { 0, NULL }, 235 }; 236 237 static const struct jme_product_desc *jme_lookup_product(uint32_t); 238 239 static const struct jme_product_desc * 240 jme_lookup_product(uint32_t id) 241 { 242 const struct jme_product_desc *jp; 243 244 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 245 if (PCI_PRODUCT(id) == jp->jme_product) 246 return jp; 247 248 return NULL; 249 } 250 251 static int 252 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 253 { 254 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 255 256 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 257 return 0; 258 259 if (jme_lookup_product(pa->pa_id) != NULL) 260 return 1; 261 262 return 0; 263 } 264 265 static void 266 jme_pci_attach(device_t parent, device_t self, void *aux) 267 { 268 jme_softc_t *sc = device_private(self); 269 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 270 const struct jme_product_desc *jp; 271 struct ifnet * const ifp = &sc->jme_if; 272 bus_space_tag_t iot1, iot2, memt; 273 bus_space_handle_t ioh1, ioh2, memh; 274 bus_size_t size, size2; 275 pci_intr_handle_t intrhandle; 276 const char *intrstr; 277 pcireg_t csr; 278 int nsegs, i; 279 const struct sysctlnode *node; 280 int jme_nodenum; 281 282 sc->jme_dev = self; 283 aprint_normal("\n"); 284 callout_init(&sc->jme_tick_ch, 0); 285 286 jp = jme_lookup_product(pa->pa_id); 287 if (jp == NULL) 288 panic("jme_pci_attach: impossible"); 289 290 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 291 sc->jme_flags = JME_FLAG_GIGA; 292 293 /* 294 * Map the card space. Try Mem first. 295 */ 296 if (pci_mapreg_map(pa, JME_PCI_BAR0, 297 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 298 0, &memt, &memh, NULL, &size) == 0) { 299 sc->jme_bt_mac = memt; 300 sc->jme_bh_mac = memh; 301 sc->jme_bt_phy = memt; 302 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 303 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 304 aprint_error_dev(self, "can't subregion PHY space\n"); 305 bus_space_unmap(memt, memh, size); 306 return; 307 } 308 sc->jme_bt_misc = memt; 309 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 310 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 311 aprint_error_dev(self, "can't subregion misc space\n"); 312 bus_space_unmap(memt, memh, size); 313 return; 314 } 315 } else { 316 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 317 0, &iot1, &ioh1, NULL, &size) != 0) { 318 aprint_error_dev(self, "can't map I/O space 1\n"); 319 return; 320 } 321 sc->jme_bt_mac = iot1; 322 sc->jme_bh_mac = ioh1; 323 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 324 0, &iot2, &ioh2, NULL, &size2) != 0) { 325 aprint_error_dev(self, "can't map I/O space 2\n"); 326 bus_space_unmap(iot1, ioh1, size); 327 return; 328 } 329 sc->jme_bt_phy = iot2; 330 sc->jme_bh_phy = ioh2; 331 sc->jme_bt_misc = iot2; 332 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 333 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 334 aprint_error_dev(self, "can't subregion misc space\n"); 335 bus_space_unmap(iot1, ioh1, size); 336 bus_space_unmap(iot2, ioh2, size2); 337 return; 338 } 339 } 340 341 if (pci_dma64_available(pa)) 342 sc->jme_dmatag = pa->pa_dmat64; 343 else 344 sc->jme_dmatag = pa->pa_dmat; 345 346 /* Enable the device. */ 347 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 348 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 349 csr | PCI_COMMAND_MASTER_ENABLE); 350 351 aprint_normal_dev(self, "%s\n", jp->jme_desc); 352 353 sc->jme_rev = PCI_REVISION(pa->pa_class); 354 355 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 356 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 357 CHIPMODE_NOT_FPGA) 358 sc->jme_flags |= JME_FLAG_FPGA; 359 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 360 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 361 "0x%x", sc->jme_rev, sc->jme_chip_rev); 362 if (sc->jme_flags & JME_FLAG_FPGA) 363 aprint_verbose(" FPGA revision: 0x%x", 364 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 365 aprint_verbose("\n"); 366 367 /* 368 * Save PHY address. 369 * Integrated JR0211 has fixed PHY address whereas FPGA version 370 * requires PHY probing to get correct PHY address. 371 */ 372 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 373 sc->jme_phyaddr = 374 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 375 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 376 } else 377 sc->jme_phyaddr = 0; 378 379 380 jme_reset(sc); 381 382 /* read mac addr */ 383 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 384 aprint_error_dev(self, "error reading Ethernet address\n"); 385 /* return; */ 386 } 387 aprint_normal_dev(self, "Ethernet address %s\n", 388 ether_sprintf(sc->jme_enaddr)); 389 390 /* Map and establish interrupts */ 391 if (pci_intr_map(pa, &intrhandle)) { 392 aprint_error_dev(self, "couldn't map interrupt\n"); 393 return; 394 } 395 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 396 sc->jme_if.if_softc = sc; 397 sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 398 jme_intr, sc); 399 if (sc->jme_ih == NULL) { 400 aprint_error_dev(self, "couldn't establish interrupt"); 401 if (intrstr != NULL) 402 aprint_error(" at %s", intrstr); 403 aprint_error("\n"); 404 return; 405 } 406 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 407 408 /* allocate and map DMA-safe memory for transmit ring */ 409 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 410 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 411 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 412 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 413 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 414 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 415 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 416 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 417 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 418 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 419 return; 420 } 421 /* allocate and map DMA-safe memory for receive ring */ 422 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 423 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 424 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 425 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 426 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 427 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 428 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 429 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 430 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 431 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 432 return; 433 } 434 for (i = 0; i < JME_NBUFS; i++) { 435 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 436 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 437 JME_NBUFS, JME_MAX_TX_LEN, 0, 438 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 439 &sc->jme_txmbufm[i]) != 0) { 440 aprint_error_dev(self, "can't allocate DMA TX map\n"); 441 return; 442 } 443 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 444 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 445 &sc->jme_rxmbufm[i]) != 0) { 446 aprint_error_dev(self, "can't allocate DMA RX map\n"); 447 return; 448 } 449 } 450 /* 451 * Initialize our media structures and probe the MII. 452 * 453 * Note that we don't care about the media instance. We 454 * are expecting to have multiple PHYs on the 10/100 cards, 455 * and on those cards we exclude the internal PHY from providing 456 * 10baseT. By ignoring the instance, it allows us to not have 457 * to specify it on the command line when switching media. 458 */ 459 sc->jme_mii.mii_ifp = ifp; 460 sc->jme_mii.mii_readreg = jme_mii_read; 461 sc->jme_mii.mii_writereg = jme_mii_write; 462 sc->jme_mii.mii_statchg = jme_statchg; 463 sc->jme_ec.ec_mii = &sc->jme_mii; 464 ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange, 465 ether_mediastatus); 466 mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY, 467 MII_OFFSET_ANY, 0); 468 if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) { 469 ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 470 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE); 471 } else 472 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO); 473 474 /* 475 * We can support 802.1Q VLAN-sized frames. 476 */ 477 sc->jme_ec.ec_capabilities |= 478 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 479 480 if (sc->jme_flags & JME_FLAG_GIGA) 481 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 482 483 484 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 485 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 486 ifp->if_ioctl = jme_ifioctl; 487 ifp->if_start = jme_ifstart; 488 ifp->if_watchdog = jme_ifwatchdog; 489 ifp->if_init = jme_ifinit; 490 ifp->if_stop = jme_stop; 491 ifp->if_timer = 0; 492 ifp->if_capabilities |= 493 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 494 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 495 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 496 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 497 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 498 IFCAP_TSOv4 | IFCAP_TSOv6; 499 IFQ_SET_READY(&ifp->if_snd); 500 if_attach(ifp); 501 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 502 503 /* 504 * Add shutdown hook so that DMA is disabled prior to reboot. 505 */ 506 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 507 pmf_class_network_register(self, ifp); 508 else 509 aprint_error_dev(self, "couldn't establish power handler\n"); 510 511 rnd_attach_source(&sc->rnd_source, device_xname(self), 512 RND_TYPE_NET, 0); 513 514 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 515 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 516 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 517 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 518 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 519 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 520 SYSCTL_DESCR("jme per-controller controls"), 521 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 522 CTL_EOL) != 0) { 523 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 524 return; 525 } 526 jme_nodenum = node->sysctl_num; 527 528 /* interrupt moderation sysctls */ 529 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 530 CTLFLAG_READWRITE, 531 CTLTYPE_INT, "int_rxto", 532 SYSCTL_DESCR("jme RX interrupt moderation timer"), 533 jme_sysctl_intrxto, 0, sc, 534 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 535 CTL_EOL) != 0) { 536 aprint_normal_dev(sc->jme_dev, 537 "couldn't create int_rxto sysctl node\n"); 538 } 539 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 540 CTLFLAG_READWRITE, 541 CTLTYPE_INT, "int_rxct", 542 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 543 jme_sysctl_intrxct, 0, sc, 544 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 545 CTL_EOL) != 0) { 546 aprint_normal_dev(sc->jme_dev, 547 "couldn't create int_rxct sysctl node\n"); 548 } 549 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 550 CTLFLAG_READWRITE, 551 CTLTYPE_INT, "int_txto", 552 SYSCTL_DESCR("jme TX interrupt moderation timer"), 553 jme_sysctl_inttxto, 0, sc, 554 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 555 CTL_EOL) != 0) { 556 aprint_normal_dev(sc->jme_dev, 557 "couldn't create int_txto sysctl node\n"); 558 } 559 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 560 CTLFLAG_READWRITE, 561 CTLTYPE_INT, "int_txct", 562 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 563 jme_sysctl_inttxct, 0, sc, 564 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 565 CTL_EOL) != 0) { 566 aprint_normal_dev(sc->jme_dev, 567 "couldn't create int_txct sysctl node\n"); 568 } 569 } 570 571 static void 572 jme_stop_rx(jme_softc_t *sc) 573 { 574 uint32_t reg; 575 int i; 576 577 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 578 if ((reg & RXCSR_RX_ENB) == 0) 579 return; 580 reg &= ~RXCSR_RX_ENB; 581 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 582 for (i = JME_TIMEOUT / 10; i > 0; i--) { 583 DELAY(10); 584 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 585 JME_RXCSR) & RXCSR_RX_ENB) == 0) 586 break; 587 } 588 if (i == 0) 589 aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n"); 590 591 } 592 593 static void 594 jme_stop_tx(jme_softc_t *sc) 595 { 596 uint32_t reg; 597 int i; 598 599 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 600 if ((reg & TXCSR_TX_ENB) == 0) 601 return; 602 reg &= ~TXCSR_TX_ENB; 603 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 604 for (i = JME_TIMEOUT / 10; i > 0; i--) { 605 DELAY(10); 606 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 607 JME_TXCSR) & TXCSR_TX_ENB) == 0) 608 break; 609 } 610 if (i == 0) 611 aprint_error_dev(sc->jme_dev, 612 "stopping transmitter timeout!\n"); 613 } 614 615 static void 616 jme_reset(jme_softc_t *sc) 617 { 618 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 619 DELAY(10); 620 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 621 } 622 623 static bool 624 jme_shutdown(device_t self, int howto) 625 { 626 jme_softc_t *sc; 627 struct ifnet *ifp; 628 629 sc = device_private(self); 630 ifp = &sc->jme_if; 631 jme_stop(ifp, 1); 632 633 return true; 634 } 635 636 static void 637 jme_stop(struct ifnet *ifp, int disable) 638 { 639 jme_softc_t *sc = ifp->if_softc; 640 int i; 641 /* Stop receiver, transmitter. */ 642 jme_stop_rx(sc); 643 jme_stop_tx(sc); 644 /* free receive mbufs */ 645 for (i = 0; i < JME_NBUFS; i++) { 646 if (sc->jme_rxmbuf[i]) { 647 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 648 m_freem(sc->jme_rxmbuf[i]); 649 } 650 sc->jme_rxmbuf[i] = NULL; 651 } 652 /* process completed transmits */ 653 jme_txeof(sc); 654 /* free abort pending transmits */ 655 for (i = 0; i < JME_NBUFS; i++) { 656 if (sc->jme_txmbuf[i]) { 657 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 658 m_freem(sc->jme_txmbuf[i]); 659 sc->jme_txmbuf[i] = NULL; 660 } 661 } 662 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 663 ifp->if_timer = 0; 664 } 665 666 #if 0 667 static void 668 jme_restart(void *v) 669 { 670 671 jme_init(v); 672 } 673 #endif 674 675 static int 676 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 677 { 678 int error; 679 bus_dmamap_t map; 680 int i = sc->jme_rx_prod; 681 682 if (sc->jme_rxmbuf[i] != NULL) { 683 aprint_error_dev(sc->jme_dev, 684 "mbuf already here: rxprod %d rxcons %d\n", 685 sc->jme_rx_prod, sc->jme_rx_cons); 686 if (m) 687 m_freem(m); 688 return EINVAL; 689 } 690 691 if (m == NULL) { 692 sc->jme_rxmbuf[i] = NULL; 693 MGETHDR(m, M_DONTWAIT, MT_DATA); 694 if (m == NULL) 695 return (ENOBUFS); 696 MCLGET(m, M_DONTWAIT); 697 if ((m->m_flags & M_EXT) == 0) { 698 m_freem(m); 699 return (ENOBUFS); 700 } 701 } 702 map = sc->jme_rxmbufm[i]; 703 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 704 KASSERT(m->m_len == MCLBYTES); 705 706 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 707 BUS_DMA_READ|BUS_DMA_NOWAIT); 708 if (error) { 709 sc->jme_rxmbuf[i] = NULL; 710 aprint_error_dev(sc->jme_dev, 711 "unable to load rx DMA map %d, error = %d\n", 712 i, error); 713 m_freem(m); 714 return (error); 715 } 716 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 717 BUS_DMASYNC_PREREAD); 718 719 sc->jme_rxmbuf[i] = m; 720 721 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 722 sc->jme_rxring[i].addr_lo = 723 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 724 sc->jme_rxring[i].addr_hi = 725 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 726 sc->jme_rxring[i].flags = 727 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 728 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 729 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 730 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 731 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 732 return (0); 733 } 734 735 static int 736 jme_ifinit(struct ifnet *ifp) 737 { 738 return jme_init(ifp, 1); 739 } 740 741 static int 742 jme_init(struct ifnet *ifp, int do_ifinit) 743 { 744 jme_softc_t *sc = ifp->if_softc; 745 int i, s; 746 uint8_t eaddr[ETHER_ADDR_LEN]; 747 uint32_t reg; 748 749 s = splnet(); 750 /* cancel any pending IO */ 751 jme_stop(ifp, 1); 752 jme_reset(sc); 753 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 754 splx(s); 755 return 0; 756 } 757 /* allocate receive ring */ 758 sc->jme_rx_prod = 0; 759 for (i = 0; i < JME_NBUFS; i++) { 760 if (jme_add_rxbuf(sc, NULL) < 0) { 761 aprint_error_dev(sc->jme_dev, 762 "can't allocate rx mbuf\n"); 763 for (i--; i >= 0; i--) { 764 bus_dmamap_unload(sc->jme_dmatag, 765 sc->jme_rxmbufm[i]); 766 m_freem(sc->jme_rxmbuf[i]); 767 sc->jme_rxmbuf[i] = NULL; 768 } 769 splx(s); 770 return ENOMEM; 771 } 772 } 773 /* init TX ring */ 774 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 775 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 776 0, JME_NBUFS * sizeof(struct jme_desc), 777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 778 for (i = 0; i < JME_NBUFS; i++) 779 sc->jme_txmbuf[i] = NULL; 780 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 781 782 /* Reprogram the station address. */ 783 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 784 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 785 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 786 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 787 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 788 789 /* 790 * Configure Tx queue. 791 * Tx priority queue weight value : 0 792 * Tx FIFO threshold for processing next packet : 16QW 793 * Maximum Tx DMA length : 512 794 * Allow Tx DMA burst. 795 */ 796 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 797 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 798 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 799 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 800 sc->jme_txcsr |= TXCSR_DMA_BURST; 801 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 802 JME_TXCSR, sc->jme_txcsr); 803 804 /* Set Tx descriptor counter. */ 805 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 806 JME_TXQDC, JME_NBUFS); 807 808 /* Set Tx ring address to the hardware. */ 809 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 810 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 811 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 812 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 813 814 /* Configure TxMAC parameters. */ 815 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 816 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 817 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 818 819 /* 820 * Configure Rx queue. 821 * FIFO full threshold for transmitting Tx pause packet : 128T 822 * FIFO threshold for processing next packet : 128QW 823 * Rx queue 0 select 824 * Max Rx DMA length : 128 825 * Rx descriptor retry : 32 826 * Rx descriptor retry time gap : 256ns 827 * Don't receive runt/bad frame. 828 */ 829 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 830 /* 831 * Since Rx FIFO size is 4K bytes, receiving frames larger 832 * than 4K bytes will suffer from Rx FIFO overruns. So 833 * decrease FIFO threshold to reduce the FIFO overruns for 834 * frames larger than 4000 bytes. 835 * For best performance of standard MTU sized frames use 836 * maximum allowable FIFO threshold, 128QW. 837 */ 838 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 839 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 840 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 841 else 842 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 843 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 844 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 845 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 846 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 847 JME_RXCSR, sc->jme_rxcsr); 848 849 /* Set Rx descriptor counter. */ 850 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 851 JME_RXQDC, JME_NBUFS); 852 853 /* Set Rx ring address to the hardware. */ 854 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 855 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 856 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 857 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 858 859 /* Clear receive filter. */ 860 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 861 /* Set up the receive filter. */ 862 jme_set_filter(sc); 863 864 /* 865 * Disable all WOL bits as WOL can interfere normal Rx 866 * operation. Also clear WOL detection status bits. 867 */ 868 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 869 reg &= ~PMCS_WOL_ENB_MASK; 870 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 871 872 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 873 /* 874 * Pad 10bytes right before received frame. This will greatly 875 * help Rx performance on strict-alignment architectures as 876 * it does not need to copy the frame to align the payload. 877 */ 878 reg |= RXMAC_PAD_10BYTES; 879 if ((ifp->if_capenable & 880 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx| 881 IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0) 882 reg |= RXMAC_CSUM_ENB; 883 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 884 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 885 886 /* Configure general purpose reg0 */ 887 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 888 reg &= ~GPREG0_PCC_UNIT_MASK; 889 /* Set PCC timer resolution to micro-seconds unit. */ 890 reg |= GPREG0_PCC_UNIT_US; 891 /* 892 * Disable all shadow register posting as we have to read 893 * JME_INTR_STATUS register in jme_int_task. Also it seems 894 * that it's hard to synchronize interrupt status between 895 * hardware and software with shadow posting due to 896 * requirements of bus_dmamap_sync(9). 897 */ 898 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 899 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 900 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 901 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 902 /* Disable posting of DW0. */ 903 reg &= ~GPREG0_POST_DW0_ENB; 904 /* Clear PME message. */ 905 reg &= ~GPREG0_PME_ENB; 906 /* Set PHY address. */ 907 reg &= ~GPREG0_PHY_ADDR_MASK; 908 reg |= sc->jme_phyaddr; 909 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 910 911 /* Configure Tx queue 0 packet completion coalescing. */ 912 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 913 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 914 reg |= PCCTX_COAL_TXQ0; 915 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 916 917 /* Configure Rx queue 0 packet completion coalescing. */ 918 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 919 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 920 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 921 922 /* Disable Timers */ 923 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 924 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 925 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 926 927 /* Configure retry transmit period, retry limit value. */ 928 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 929 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 930 TXTRHD_RT_PERIOD_MASK) | 931 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 932 TXTRHD_RT_LIMIT_SHIFT)); 933 934 /* Disable RSS. */ 935 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 936 JME_RSSC, RSSC_DIS_RSS); 937 938 /* Initialize the interrupt mask. */ 939 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 940 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 941 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 942 JME_INTR_STATUS, 0xFFFFFFFF); 943 944 /* set media, if not already handling a media change */ 945 if (do_ifinit) { 946 int error; 947 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 948 error = 0; 949 else if (error != 0) { 950 aprint_error_dev(sc->jme_dev, "could not set media\n"); 951 return error; 952 } 953 } 954 955 /* Program MAC with resolved speed/duplex/flow-control. */ 956 jme_mac_config(sc); 957 958 /* Start receiver/transmitter. */ 959 sc->jme_rx_cons = 0; 960 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 961 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 962 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 963 sc->jme_txcsr | TXCSR_TX_ENB); 964 965 /* start ticks calls */ 966 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 967 sc->jme_if.if_flags |= IFF_RUNNING; 968 sc->jme_if.if_flags &= ~IFF_OACTIVE; 969 splx(s); 970 return 0; 971 } 972 973 974 int 975 jme_mii_read(device_t self, int phy, int reg) 976 { 977 struct jme_softc *sc = device_private(self); 978 int val, i; 979 980 /* For FPGA version, PHY address 0 should be ignored. */ 981 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 982 if (phy == 0) 983 return (0); 984 } else { 985 if (sc->jme_phyaddr != phy) 986 return (0); 987 } 988 989 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 990 SMI_OP_READ | SMI_OP_EXECUTE | 991 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 992 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 993 delay(10); 994 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 995 JME_SMI)) & SMI_OP_EXECUTE) == 0) 996 break; 997 } 998 999 if (i == 0) { 1000 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 1001 return (0); 1002 } 1003 1004 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 1005 } 1006 1007 void 1008 jme_mii_write(device_t self, int phy, int reg, int val) 1009 { 1010 struct jme_softc *sc = device_private(self); 1011 int i; 1012 1013 /* For FPGA version, PHY address 0 should be ignored. */ 1014 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1015 if (phy == 0) 1016 return; 1017 } else { 1018 if (sc->jme_phyaddr != phy) 1019 return; 1020 } 1021 1022 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1023 SMI_OP_WRITE | SMI_OP_EXECUTE | 1024 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1025 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1026 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1027 delay(10); 1028 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1029 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1030 break; 1031 } 1032 1033 if (i == 0) 1034 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1035 1036 return; 1037 } 1038 1039 void 1040 jme_statchg(device_t self) 1041 { 1042 jme_softc_t *sc = device_private(self); 1043 struct ifnet *ifp = &sc->jme_if; 1044 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) 1045 jme_init(ifp, 0); 1046 } 1047 1048 static void 1049 jme_intr_rx(jme_softc_t *sc) { 1050 struct mbuf *m, *mhead; 1051 bus_dmamap_t mmap; 1052 struct ifnet *ifp = &sc->jme_if; 1053 uint32_t flags, buflen; 1054 int i, ipackets, nsegs, seg, error; 1055 struct jme_desc *desc; 1056 1057 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1058 sizeof(struct jme_desc) * JME_NBUFS, 1059 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1060 #ifdef JMEDEBUG_RX 1061 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1062 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1063 #endif 1064 ipackets = 0; 1065 while((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) 1066 == 0) { 1067 i = sc->jme_rx_cons; 1068 desc = &sc->jme_rxring[i]; 1069 #ifdef JMEDEBUG_RX 1070 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1071 i, le32toh(desc->flags), le32toh(desc->buflen)); 1072 #endif 1073 if (sc->jme_rxmbuf[i] == NULL) { 1074 if ((error = jme_add_rxbuf(sc, NULL)) != 0) { 1075 aprint_error_dev(sc->jme_dev, 1076 "can't add new mbuf to empty slot: %d\n", 1077 error); 1078 break; 1079 } 1080 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1081 i = sc->jme_rx_cons; 1082 continue; 1083 } 1084 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1085 break; 1086 1087 buflen = le32toh(desc->buflen); 1088 nsegs = JME_RX_NSEGS(buflen); 1089 flags = le32toh(desc->flags); 1090 if ((buflen & JME_RX_ERR_STAT) != 0 || 1091 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1092 JME_RX_BYTES(buflen) > 1093 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1094 #ifdef JMEDEBUG_RX 1095 printf("rx error flags 0x%x buflen 0x%x\n", 1096 flags, buflen); 1097 #endif 1098 ifp->if_ierrors++; 1099 /* reuse the mbufs */ 1100 for (seg = 0; seg < nsegs; seg++) { 1101 m = sc->jme_rxmbuf[i]; 1102 sc->jme_rxmbuf[i] = NULL; 1103 mmap = sc->jme_rxmbufm[i]; 1104 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1105 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1106 bus_dmamap_unload(sc->jme_dmatag, mmap); 1107 if ((error = jme_add_rxbuf(sc, m)) != 0) 1108 aprint_error_dev(sc->jme_dev, 1109 "can't reuse mbuf: %d\n", error); 1110 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1111 i = sc->jme_rx_cons; 1112 } 1113 continue; 1114 } 1115 /* receive this packet */ 1116 mhead = m = sc->jme_rxmbuf[i]; 1117 sc->jme_rxmbuf[i] = NULL; 1118 mmap = sc->jme_rxmbufm[i]; 1119 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1120 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1121 bus_dmamap_unload(sc->jme_dmatag, mmap); 1122 /* add a new buffer to chain */ 1123 if (jme_add_rxbuf(sc, NULL) != 0) { 1124 if ((error = jme_add_rxbuf(sc, m)) != 0) 1125 aprint_error_dev(sc->jme_dev, 1126 "can't reuse mbuf: %d\n", error); 1127 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1128 i = sc->jme_rx_cons; 1129 for (seg = 1; seg < nsegs; seg++) { 1130 m = sc->jme_rxmbuf[i]; 1131 sc->jme_rxmbuf[i] = NULL; 1132 mmap = sc->jme_rxmbufm[i]; 1133 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1134 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1135 bus_dmamap_unload(sc->jme_dmatag, mmap); 1136 if ((error = jme_add_rxbuf(sc, m)) != 0) 1137 aprint_error_dev(sc->jme_dev, 1138 "can't reuse mbuf: %d\n", error); 1139 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1140 i = sc->jme_rx_cons; 1141 } 1142 ifp->if_ierrors++; 1143 continue; 1144 } 1145 1146 /* build mbuf chain: head, then remaining segments */ 1147 m->m_pkthdr.rcvif = ifp; 1148 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1149 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1150 m->m_pkthdr.len; 1151 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1152 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1153 for (seg = 1; seg < nsegs; seg++) { 1154 i = sc->jme_rx_cons; 1155 m = sc->jme_rxmbuf[i]; 1156 sc->jme_rxmbuf[i] = NULL; 1157 mmap = sc->jme_rxmbufm[i]; 1158 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1159 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1160 bus_dmamap_unload(sc->jme_dmatag, mmap); 1161 if ((error = jme_add_rxbuf(sc, NULL)) != 0) 1162 aprint_error_dev(sc->jme_dev, 1163 "can't add new mbuf: %d\n", error); 1164 m->m_flags &= ~M_PKTHDR; 1165 m_cat(mhead, m); 1166 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1167 } 1168 /* and adjust last mbuf's size */ 1169 if (nsegs > 1) { 1170 m->m_len = 1171 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1172 } 1173 ifp->if_ipackets++; 1174 ipackets++; 1175 bpf_mtap(ifp, mhead); 1176 1177 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1178 (flags & JME_RD_IPV4)) { 1179 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1180 if (!(flags & JME_RD_IPCSUM)) 1181 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1182 } 1183 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1184 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1185 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1186 if (!(flags & JME_RD_TCPCSUM)) 1187 mhead->m_pkthdr.csum_flags |= 1188 M_CSUM_TCP_UDP_BAD; 1189 } 1190 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1191 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1192 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1193 if (!(flags & JME_RD_UDPCSUM)) 1194 mhead->m_pkthdr.csum_flags |= 1195 M_CSUM_TCP_UDP_BAD; 1196 } 1197 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1198 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1199 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1200 if (!(flags & JME_RD_TCPCSUM)) 1201 mhead->m_pkthdr.csum_flags |= 1202 M_CSUM_TCP_UDP_BAD; 1203 } 1204 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1205 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1206 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1207 if (!(flags & JME_RD_UDPCSUM)) 1208 mhead->m_pkthdr.csum_flags |= 1209 M_CSUM_TCP_UDP_BAD; 1210 } 1211 if (flags & JME_RD_VLAN_TAG) { 1212 /* pass to vlan_input() */ 1213 VLAN_INPUT_TAG(ifp, mhead, 1214 (flags & JME_RD_VLAN_MASK), continue); 1215 } 1216 (*ifp->if_input)(ifp, mhead); 1217 } 1218 if (ipackets) 1219 rnd_add_uint32(&sc->rnd_source, ipackets); 1220 } 1221 1222 static int 1223 jme_intr(void *v) 1224 { 1225 jme_softc_t *sc = v; 1226 uint32_t istatus; 1227 1228 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1229 JME_INTR_STATUS); 1230 if (istatus == 0 || istatus == 0xFFFFFFFF) 1231 return 0; 1232 /* Disable interrupts. */ 1233 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1234 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1235 again: 1236 /* and update istatus */ 1237 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1238 JME_INTR_STATUS); 1239 if ((istatus & JME_INTRS_CHECK) == 0) 1240 goto done; 1241 /* Reset PCC counter/timer and Ack interrupts. */ 1242 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1243 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1244 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1245 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1246 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1247 JME_INTR_STATUS, istatus); 1248 1249 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1250 goto done; 1251 #ifdef JMEDEBUG_RX 1252 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1253 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1254 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1255 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1256 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1257 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1258 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1259 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1260 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1261 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1262 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1263 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1264 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1265 #endif 1266 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1267 jme_intr_rx(sc); 1268 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1269 /* 1270 * Notify hardware availability of new Rx 1271 * buffers. 1272 * Reading RXCSR takes very long time under 1273 * heavy load so cache RXCSR value and writes 1274 * the ORed value with the kick command to 1275 * the RXCSR. This saves one register access 1276 * cycle. 1277 */ 1278 sc->jme_rx_cons = 0; 1279 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1280 JME_RXCSR, 1281 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1282 } 1283 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1284 jme_ifstart(&sc->jme_if); 1285 1286 goto again; 1287 1288 done: 1289 /* enable interrupts. */ 1290 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1291 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1292 return 1; 1293 } 1294 1295 1296 static int 1297 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1298 { 1299 struct jme_softc *sc = ifp->if_softc; 1300 int s, error; 1301 struct ifreq *ifr; 1302 struct ifcapreq *ifcr; 1303 1304 s = splnet(); 1305 /* 1306 * we can't support at the same time jumbo frames and 1307 * TX checksums offload/TSO 1308 */ 1309 switch(cmd) { 1310 case SIOCSIFMTU: 1311 ifr = data; 1312 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1313 (ifp->if_capenable & ( 1314 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1315 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1316 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1317 splx(s); 1318 return EINVAL; 1319 } 1320 break; 1321 case SIOCSIFCAP: 1322 ifcr = data; 1323 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1324 (ifcr->ifcr_capenable & ( 1325 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1326 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1327 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1328 splx(s); 1329 return EINVAL; 1330 } 1331 break; 1332 } 1333 1334 error = ether_ioctl(ifp, cmd, data); 1335 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1336 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1337 jme_set_filter(sc); 1338 error = 0; 1339 } else { 1340 error = jme_init(ifp, 0); 1341 } 1342 } 1343 splx(s); 1344 return error; 1345 } 1346 1347 static int 1348 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1349 { 1350 struct jme_desc *txd; 1351 struct jme_desc *desc; 1352 struct mbuf *m; 1353 struct m_tag *mtag; 1354 int error, i, prod, headdsc, nsegs; 1355 uint32_t cflags, tso_segsz; 1356 1357 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){ 1358 /* 1359 * Due to the adherence to NDIS specification JMC250 1360 * assumes upper stack computed TCP pseudo checksum 1361 * without including payload length. This breaks 1362 * checksum offload for TSO case so recompute TCP 1363 * pseudo checksum for JMC250. Hopefully this wouldn't 1364 * be much burden on modern CPUs. 1365 */ 1366 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1367 int iphl = v4 ? 1368 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1369 M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data); 1370 /* 1371 * note: we support vlan offloading, so we should never have 1372 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1373 * right. 1374 */ 1375 int hlen = ETHER_HDR_LEN + iphl; 1376 1377 if (__predict_false((*m_head)->m_len < 1378 (hlen + sizeof(struct tcphdr)))) { 1379 /* 1380 * TCP/IP headers are not in the first mbuf; we need 1381 * to do this the slow and painful way. Let's just 1382 * hope this doesn't happen very often. 1383 */ 1384 struct tcphdr th; 1385 1386 m_copydata((*m_head), hlen, sizeof(th), &th); 1387 if (v4) { 1388 struct ip ip; 1389 1390 m_copydata((*m_head), ETHER_HDR_LEN, 1391 sizeof(ip), &ip); 1392 ip.ip_len = 0; 1393 m_copyback((*m_head), 1394 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1395 sizeof(ip.ip_len), &ip.ip_len); 1396 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1397 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1398 } else { 1399 #if INET6 1400 struct ip6_hdr ip6; 1401 1402 m_copydata((*m_head), ETHER_HDR_LEN, 1403 sizeof(ip6), &ip6); 1404 ip6.ip6_plen = 0; 1405 m_copyback((*m_head), ETHER_HDR_LEN + 1406 offsetof(struct ip6_hdr, ip6_plen), 1407 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1408 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1409 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1410 #endif /* INET6 */ 1411 } 1412 m_copyback((*m_head), 1413 hlen + offsetof(struct tcphdr, th_sum), 1414 sizeof(th.th_sum), &th.th_sum); 1415 1416 hlen += th.th_off << 2; 1417 } else { 1418 /* 1419 * TCP/IP headers are in the first mbuf; we can do 1420 * this the easy way. 1421 */ 1422 struct tcphdr *th; 1423 1424 if (v4) { 1425 struct ip *ip = 1426 (void *)(mtod((*m_head), char *) + 1427 ETHER_HDR_LEN); 1428 th = (void *)(mtod((*m_head), char *) + hlen); 1429 1430 ip->ip_len = 0; 1431 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1432 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1433 } else { 1434 #if INET6 1435 struct ip6_hdr *ip6 = 1436 (void *)(mtod((*m_head), char *) + 1437 ETHER_HDR_LEN); 1438 th = (void *)(mtod((*m_head), char *) + hlen); 1439 1440 ip6->ip6_plen = 0; 1441 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1442 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1443 #endif /* INET6 */ 1444 } 1445 hlen += th->th_off << 2; 1446 } 1447 1448 } 1449 1450 prod = sc->jme_tx_prod; 1451 txd = &sc->jme_txring[prod]; 1452 1453 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1454 *m_head, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1455 if (error) { 1456 if (error == EFBIG) { 1457 log(LOG_ERR, "%s: Tx packet consumes too many " 1458 "DMA segments, dropping...\n", 1459 device_xname(sc->jme_dev)); 1460 m_freem(*m_head); 1461 m_head = NULL; 1462 } 1463 return (error); 1464 } 1465 /* 1466 * Check descriptor overrun. Leave one free descriptor. 1467 * Since we always use 64bit address mode for transmitting, 1468 * each Tx request requires one more dummy descriptor. 1469 */ 1470 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1471 #ifdef JMEDEBUG_TX 1472 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1473 #endif 1474 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1475 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1476 return (ENOBUFS); 1477 } 1478 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1479 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1480 1481 m = *m_head; 1482 cflags = 0; 1483 tso_segsz = 0; 1484 /* Configure checksum offload and TSO. */ 1485 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) { 1486 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1487 cflags |= JME_TD_TSO; 1488 } else { 1489 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1490 cflags |= JME_TD_IPCSUM; 1491 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0) 1492 cflags |= JME_TD_TCPCSUM; 1493 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0) 1494 cflags |= JME_TD_UDPCSUM; 1495 } 1496 /* Configure VLAN. */ 1497 if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) { 1498 cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); 1499 cflags |= JME_TD_VLAN_TAG; 1500 } 1501 1502 desc = &sc->jme_txring[prod]; 1503 desc->flags = htole32(cflags); 1504 desc->buflen = htole32(tso_segsz); 1505 desc->addr_hi = htole32(m->m_pkthdr.len); 1506 desc->addr_lo = 0; 1507 headdsc = prod; 1508 sc->jme_tx_cnt++; 1509 JME_DESC_INC(prod, JME_NBUFS); 1510 for (i = 0; i < nsegs; i++) { 1511 desc = &sc->jme_txring[prod]; 1512 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1513 desc->buflen = 1514 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1515 desc->addr_hi = htole32( 1516 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1517 desc->addr_lo = htole32( 1518 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1519 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1520 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1521 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1522 sc->jme_txmbuf[prod] = NULL; 1523 sc->jme_tx_cnt++; 1524 JME_DESC_INC(prod, JME_NBUFS); 1525 } 1526 1527 /* Update producer index. */ 1528 sc->jme_tx_prod = prod; 1529 #ifdef JMEDEBUG_TX 1530 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1531 #endif 1532 /* 1533 * Finally request interrupt and give the first descriptor 1534 * owenership to hardware. 1535 */ 1536 desc = &sc->jme_txring[headdsc]; 1537 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1538 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1539 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1540 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1541 1542 sc->jme_txmbuf[headdsc] = m; 1543 return (0); 1544 } 1545 1546 static void 1547 jme_txeof(struct jme_softc *sc) 1548 { 1549 struct ifnet *ifp; 1550 struct jme_desc *desc; 1551 uint32_t status; 1552 int cons, cons0, nsegs, seg; 1553 1554 ifp = &sc->jme_if; 1555 1556 #ifdef JMEDEBUG_TX 1557 printf("jme_txeof cons %d prod %d\n", 1558 sc->jme_tx_cons, sc->jme_tx_prod); 1559 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1560 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1561 "JME_TXTRHD 0x%x\n", 1562 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1563 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1564 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1565 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1566 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1567 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1568 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1569 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1570 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1571 desc = &sc->jme_txring[cons]; 1572 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1573 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1574 JME_DESC_INC(cons, JME_NBUFS); 1575 } 1576 #endif 1577 1578 cons = sc->jme_tx_cons; 1579 if (cons == sc->jme_tx_prod) 1580 return; 1581 1582 /* 1583 * Go through our Tx list and free mbufs for those 1584 * frames which have been transmitted. 1585 */ 1586 for (; cons != sc->jme_tx_prod;) { 1587 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1588 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1589 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1590 1591 desc = &sc->jme_txring[cons]; 1592 status = le32toh(desc->flags); 1593 #ifdef JMEDEBUG_TX 1594 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1595 sc->jme_txmbufm[cons]->dm_nsegs); 1596 #endif 1597 if (status & JME_TD_OWN) 1598 break; 1599 1600 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1601 ifp->if_oerrors++; 1602 else { 1603 ifp->if_opackets++; 1604 if ((status & JME_TD_COLLISION) != 0) 1605 ifp->if_collisions += 1606 le32toh(desc->buflen) & 1607 JME_TD_BUF_LEN_MASK; 1608 } 1609 /* 1610 * Only the first descriptor of multi-descriptor 1611 * transmission is updated so driver have to skip entire 1612 * chained buffers for the transmiited frame. In other 1613 * words, JME_TD_OWN bit is valid only at the first 1614 * descriptor of a multi-descriptor transmission. 1615 */ 1616 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1617 cons0 = cons; 1618 JME_DESC_INC(cons, JME_NBUFS); 1619 for (seg = 1; seg < nsegs + 1; seg++) { 1620 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1621 cons * sizeof(struct jme_desc), 1622 sizeof(struct jme_desc), 1623 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1624 sc->jme_txring[cons].flags = 0; 1625 JME_DESC_INC(cons, JME_NBUFS); 1626 } 1627 /* Reclaim transferred mbufs. */ 1628 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1629 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1630 BUS_DMASYNC_POSTWRITE); 1631 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1632 1633 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1634 m_freem(sc->jme_txmbuf[cons0]); 1635 sc->jme_txmbuf[cons0] = NULL; 1636 sc->jme_tx_cnt -= nsegs + 1; 1637 KASSERT(sc->jme_tx_cnt >= 0); 1638 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1639 } 1640 sc->jme_tx_cons = cons; 1641 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1642 if (sc->jme_tx_cnt == 0) 1643 ifp->if_timer = 0; 1644 #ifdef JMEDEBUG_TX 1645 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1646 #endif 1647 } 1648 1649 static void 1650 jme_ifstart(struct ifnet *ifp) 1651 { 1652 jme_softc_t *sc = ifp->if_softc; 1653 struct mbuf *mb_head; 1654 int enq; 1655 1656 /* 1657 * check if we can free some desc. 1658 * Clear TX interrupt status to reset TX coalescing counters. 1659 */ 1660 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1661 JME_INTR_STATUS, INTR_TXQ_COMP); 1662 jme_txeof(sc); 1663 1664 if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1665 return; 1666 for (enq = 0;; enq++) { 1667 nexttx: 1668 /* Grab a paquet for output */ 1669 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1670 if (mb_head == NULL) { 1671 #ifdef JMEDEBUG_TX 1672 printf("%s: nothing to send\n", __func__); 1673 #endif 1674 break; 1675 } 1676 /* try to add this mbuf to the TX ring */ 1677 if (jme_encap(sc, &mb_head)) { 1678 if (mb_head == NULL) { 1679 ifp->if_oerrors++; 1680 /* packet dropped, try next one */ 1681 goto nexttx; 1682 } 1683 /* resource shortage, try again later */ 1684 IF_PREPEND(&ifp->if_snd, mb_head); 1685 ifp->if_flags |= IFF_OACTIVE; 1686 break; 1687 } 1688 /* Pass packet to bpf if there is a listener */ 1689 bpf_mtap(ifp, mb_head); 1690 } 1691 #ifdef JMEDEBUG_TX 1692 printf("jme_ifstart enq %d\n", enq); 1693 #endif 1694 if (enq) { 1695 /* 1696 * Set a 5 second timer just in case we don't hear from 1697 * the card again. 1698 */ 1699 ifp->if_timer = 5; 1700 /* 1701 * Reading TXCSR takes very long time under heavy load 1702 * so cache TXCSR value and writes the ORed value with 1703 * the kick command to the TXCSR. This saves one register 1704 * access cycle. 1705 */ 1706 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1707 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1708 #ifdef JMEDEBUG_TX 1709 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1710 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1711 "JME_TXTRHD 0x%x\n", 1712 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1713 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1714 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1715 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1716 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1717 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1718 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1719 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1720 #endif 1721 } 1722 } 1723 1724 static void 1725 jme_ifwatchdog(struct ifnet *ifp) 1726 { 1727 jme_softc_t *sc = ifp->if_softc; 1728 1729 if ((ifp->if_flags & IFF_RUNNING) == 0) 1730 return; 1731 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1732 ifp->if_oerrors++; 1733 jme_init(ifp, 0); 1734 } 1735 1736 static int 1737 jme_mediachange(struct ifnet *ifp) 1738 { 1739 int error; 1740 jme_softc_t *sc = ifp->if_softc; 1741 1742 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1743 error = 0; 1744 else if (error != 0) { 1745 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1746 return error; 1747 } 1748 return 0; 1749 } 1750 1751 static void 1752 jme_ticks(void *v) 1753 { 1754 jme_softc_t *sc = v; 1755 int s = splnet(); 1756 1757 /* Tick the MII. */ 1758 mii_tick(&sc->jme_mii); 1759 1760 /* every seconds */ 1761 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1762 splx(s); 1763 } 1764 1765 static void 1766 jme_mac_config(jme_softc_t *sc) 1767 { 1768 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1769 struct mii_data *mii = &sc->jme_mii; 1770 1771 ghc = 0; 1772 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1773 rxmac &= ~RXMAC_FC_ENB; 1774 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1775 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1776 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1777 txpause &= ~TXPFC_PAUSE_ENB; 1778 1779 if (mii->mii_media_active & IFM_FDX) { 1780 ghc |= GHC_FULL_DUPLEX; 1781 rxmac &= ~RXMAC_COLL_DET_ENB; 1782 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1783 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1784 TXMAC_FRAME_BURST); 1785 /* Disable retry transmit timer/retry limit. */ 1786 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1787 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1788 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1789 } else { 1790 rxmac |= RXMAC_COLL_DET_ENB; 1791 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1792 /* Enable retry transmit timer/retry limit. */ 1793 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1794 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1795 } 1796 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1797 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1798 case IFM_10_T: 1799 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1800 break; 1801 case IFM_100_TX: 1802 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1803 break; 1804 case IFM_1000_T: 1805 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1806 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1807 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1808 break; 1809 default: 1810 break; 1811 } 1812 if ((sc->jme_flags & JME_FLAG_GIGA) && 1813 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1814 /* 1815 * Workaround occasional packet loss issue of JMC250 A2 1816 * when it runs on half-duplex media. 1817 */ 1818 #ifdef JMEDEBUG 1819 printf("JME250 A2 workaround\n"); 1820 #endif 1821 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1822 JME_GPREG1); 1823 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1824 gpreg &= ~GPREG1_HDPX_FIX; 1825 else 1826 gpreg |= GPREG1_HDPX_FIX; 1827 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1828 JME_GPREG1, gpreg); 1829 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1830 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1831 /* Extend interface FIFO depth. */ 1832 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1833 0x1B, 0x0000); 1834 } else { 1835 /* Select default interface FIFO depth. */ 1836 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1837 0x1B, 0x0004); 1838 } 1839 } 1840 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1841 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1842 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1843 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1844 } 1845 1846 static void 1847 jme_set_filter(jme_softc_t *sc) 1848 { 1849 struct ifnet *ifp = &sc->jme_if; 1850 struct ether_multistep step; 1851 struct ether_multi *enm; 1852 uint32_t hash[2] = {0, 0}; 1853 int i; 1854 uint32_t rxcfg; 1855 1856 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1857 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1858 RXMAC_ALLMULTI); 1859 /* Always accept frames destined to our station address. */ 1860 rxcfg |= RXMAC_UNICAST; 1861 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1862 rxcfg |= RXMAC_BROADCAST; 1863 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1864 if ((ifp->if_flags & IFF_PROMISC) != 0) 1865 rxcfg |= RXMAC_PROMISC; 1866 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1867 rxcfg |= RXMAC_ALLMULTI; 1868 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1869 JME_MAR0, 0xFFFFFFFF); 1870 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1871 JME_MAR1, 0xFFFFFFFF); 1872 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1873 JME_RXMAC, rxcfg); 1874 return; 1875 } 1876 /* 1877 * Set up the multicast address filter by passing all multicast 1878 * addresses through a CRC generator, and then using the low-order 1879 * 6 bits as an index into the 64 bit multicast hash table. The 1880 * high order bits select the register, while the rest of the bits 1881 * select the bit within the register. 1882 */ 1883 rxcfg |= RXMAC_MULTICAST; 1884 memset(hash, 0, sizeof(hash)); 1885 1886 ETHER_FIRST_MULTI(step, &sc->jme_ec, enm); 1887 while (enm != NULL) { 1888 #ifdef JEMDBUG 1889 printf("%s: addrs %s %s\n", __func__, 1890 ether_sprintf(enm->enm_addrlo), 1891 ether_sprintf(enm->enm_addrhi)); 1892 #endif 1893 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1894 i = ether_crc32_be(enm->enm_addrlo, 6); 1895 /* Just want the 6 least significant bits. */ 1896 i &= 0x3f; 1897 hash[i / 32] |= 1 << (i%32); 1898 } else { 1899 hash[0] = hash[1] = 0xffffffff; 1900 sc->jme_if.if_flags |= IFF_ALLMULTI; 1901 break; 1902 } 1903 ETHER_NEXT_MULTI(step, enm); 1904 } 1905 #ifdef JMEDEBUG 1906 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1907 #endif 1908 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1909 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1910 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1911 } 1912 1913 #if 0 1914 static int 1915 jme_multicast_hash(uint8_t *a) 1916 { 1917 int hash; 1918 1919 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1920 #define xor8(a,b,c,d,e,f,g,h) \ 1921 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1922 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1923 1924 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1925 DA(a,36), DA(a,42)); 1926 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1927 DA(a,37), DA(a,43)) << 1; 1928 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1929 DA(a,38), DA(a,44)) << 2; 1930 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1931 DA(a,39), DA(a,45)) << 3; 1932 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1933 DA(a,40), DA(a,46)) << 4; 1934 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1935 DA(a,41), DA(a,47)) << 5; 1936 1937 return hash; 1938 } 1939 #endif 1940 1941 static int 1942 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1943 { 1944 uint32_t reg; 1945 int i; 1946 1947 *val = 0; 1948 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1949 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1950 JME_SMBCSR); 1951 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1952 break; 1953 delay(10); 1954 } 1955 1956 if (i == 0) { 1957 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1958 return (ETIMEDOUT); 1959 } 1960 1961 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1962 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1963 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1964 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1965 delay(10); 1966 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1967 JME_SMBINTF); 1968 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1969 break; 1970 } 1971 1972 if (i == 0) { 1973 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1974 return (ETIMEDOUT); 1975 } 1976 1977 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1978 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1979 return (0); 1980 } 1981 1982 1983 static int 1984 jme_eeprom_macaddr(struct jme_softc *sc) 1985 { 1986 uint8_t eaddr[ETHER_ADDR_LEN]; 1987 uint8_t fup, reg, val; 1988 uint32_t offset; 1989 int match; 1990 1991 offset = 0; 1992 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1993 fup != JME_EEPROM_SIG0) 1994 return (ENOENT); 1995 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1996 fup != JME_EEPROM_SIG1) 1997 return (ENOENT); 1998 match = 0; 1999 do { 2000 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 2001 break; 2002 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 2003 == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) { 2004 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 2005 break; 2006 if (reg >= JME_PAR0 && 2007 reg < JME_PAR0 + ETHER_ADDR_LEN) { 2008 if (jme_eeprom_read_byte(sc, offset + 2, 2009 &val) != 0) 2010 break; 2011 eaddr[reg - JME_PAR0] = val; 2012 match++; 2013 } 2014 } 2015 if (fup & JME_EEPROM_DESC_END) 2016 break; 2017 2018 /* Try next eeprom descriptor. */ 2019 offset += JME_EEPROM_DESC_BYTES; 2020 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2021 2022 if (match == ETHER_ADDR_LEN) { 2023 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2024 return (0); 2025 } 2026 2027 return (ENOENT); 2028 } 2029 2030 static int 2031 jme_reg_macaddr(struct jme_softc *sc) 2032 { 2033 uint32_t par0, par1; 2034 2035 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2036 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2037 par1 &= 0xffff; 2038 if ((par0 == 0 && par1 == 0) || 2039 (par0 == 0xffffffff && par1 == 0xffff)) { 2040 return (ENOENT); 2041 } else { 2042 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2043 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2044 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2045 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2046 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2047 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2048 } 2049 return (0); 2050 } 2051 2052 /* 2053 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2054 * set up in jme_pci_attach() 2055 */ 2056 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2057 { 2058 int rc; 2059 const struct sysctlnode *node; 2060 2061 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2062 0, CTLTYPE_NODE, "hw", NULL, 2063 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2064 goto err; 2065 } 2066 2067 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2068 0, CTLTYPE_NODE, "jme", 2069 SYSCTL_DESCR("jme interface controls"), 2070 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2071 goto err; 2072 } 2073 2074 jme_root_num = node->sysctl_num; 2075 return; 2076 2077 err: 2078 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2079 } 2080 2081 static int 2082 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2083 { 2084 int error, t; 2085 struct sysctlnode node; 2086 struct jme_softc *sc; 2087 uint32_t reg; 2088 2089 node = *rnode; 2090 sc = node.sysctl_data; 2091 t = sc->jme_intrxto; 2092 node.sysctl_data = &t; 2093 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2094 if (error || newp == NULL) 2095 return error; 2096 2097 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2098 return EINVAL; 2099 2100 /* 2101 * update the softc with sysctl-changed value, and mark 2102 * for hardware update 2103 */ 2104 sc->jme_intrxto = t; 2105 /* Configure Rx queue 0 packet completion coalescing. */ 2106 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2107 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2108 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2109 return 0; 2110 } 2111 2112 static int 2113 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2114 { 2115 int error, t; 2116 struct sysctlnode node; 2117 struct jme_softc *sc; 2118 uint32_t reg; 2119 2120 node = *rnode; 2121 sc = node.sysctl_data; 2122 t = sc->jme_intrxct; 2123 node.sysctl_data = &t; 2124 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2125 if (error || newp == NULL) 2126 return error; 2127 2128 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2129 return EINVAL; 2130 2131 /* 2132 * update the softc with sysctl-changed value, and mark 2133 * for hardware update 2134 */ 2135 sc->jme_intrxct = t; 2136 /* Configure Rx queue 0 packet completion coalescing. */ 2137 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2138 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2139 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2140 return 0; 2141 } 2142 2143 static int 2144 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2145 { 2146 int error, t; 2147 struct sysctlnode node; 2148 struct jme_softc *sc; 2149 uint32_t reg; 2150 2151 node = *rnode; 2152 sc = node.sysctl_data; 2153 t = sc->jme_inttxto; 2154 node.sysctl_data = &t; 2155 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2156 if (error || newp == NULL) 2157 return error; 2158 2159 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2160 return EINVAL; 2161 2162 /* 2163 * update the softc with sysctl-changed value, and mark 2164 * for hardware update 2165 */ 2166 sc->jme_inttxto = t; 2167 /* Configure Tx queue 0 packet completion coalescing. */ 2168 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2169 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2170 reg |= PCCTX_COAL_TXQ0; 2171 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2172 return 0; 2173 } 2174 2175 static int 2176 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2177 { 2178 int error, t; 2179 struct sysctlnode node; 2180 struct jme_softc *sc; 2181 uint32_t reg; 2182 2183 node = *rnode; 2184 sc = node.sysctl_data; 2185 t = sc->jme_inttxct; 2186 node.sysctl_data = &t; 2187 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2188 if (error || newp == NULL) 2189 return error; 2190 2191 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2192 return EINVAL; 2193 2194 /* 2195 * update the softc with sysctl-changed value, and mark 2196 * for hardware update 2197 */ 2198 sc->jme_inttxct = t; 2199 /* Configure Tx queue 0 packet completion coalescing. */ 2200 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2201 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2202 reg |= PCCTX_COAL_TXQ0; 2203 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2204 return 0; 2205 } 2206