1 /* $NetBSD: if_jme.c,v 1.55 2022/09/02 23:48:10 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.55 2022/09/02 23:48:10 thorpej Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 74 #include <sys/device.h> 75 #include <sys/syslog.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_media.h> 80 #include <net/if_types.h> 81 #include <net/if_dl.h> 82 #include <net/route.h> 83 #include <net/bpf.h> 84 85 #include <sys/rndsource.h> 86 87 #include <netinet/in.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/ip.h> 90 #include <netinet/ip_var.h> 91 92 #include <netinet6/ip6_var.h> 93 94 #ifdef INET 95 #include <netinet/in_var.h> 96 #endif 97 98 #include <netinet/tcp.h> 99 #include <netinet/tcp_timer.h> 100 #include <netinet/tcp_var.h> 101 102 #include <net/if_ether.h> 103 #if defined(INET) 104 #include <netinet/if_inarp.h> 105 #endif 106 107 #include <sys/bus.h> 108 #include <sys/intr.h> 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 #include <dev/pci/if_jmereg.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/miivar.h> 117 118 /* number of entries in transmit and receive rings */ 119 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 120 121 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 122 123 /* Water mark to kick reclaiming Tx buffers. */ 124 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 125 126 127 struct jme_softc { 128 device_t jme_dev; /* base device */ 129 bus_space_tag_t jme_bt_mac; 130 bus_space_handle_t jme_bh_mac; /* Mac registers */ 131 bus_space_tag_t jme_bt_phy; 132 bus_space_handle_t jme_bh_phy; /* PHY registers */ 133 bus_space_tag_t jme_bt_misc; 134 bus_space_handle_t jme_bh_misc; /* Misc registers */ 135 bus_dma_tag_t jme_dmatag; 136 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 137 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 138 struct jme_desc* jme_txring; /* transmit ring */ 139 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 140 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 141 int jme_tx_cons; /* transmit ring consumer */ 142 int jme_tx_prod; /* transmit ring producer */ 143 int jme_tx_cnt; /* transmit ring active count */ 144 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 145 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 146 struct jme_desc* jme_rxring; /* receive ring */ 147 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 148 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 149 int jme_rx_cons; /* receive ring consumer */ 150 int jme_rx_prod; /* receive ring producer */ 151 void* jme_ih; /* our interrupt */ 152 struct ethercom jme_ec; 153 struct callout jme_tick_ch; /* tick callout */ 154 uint8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 155 uint8_t jme_phyaddr; /* address of integrated phy */ 156 uint8_t jme_chip_rev; /* chip revision */ 157 uint8_t jme_rev; /* PCI revision */ 158 mii_data_t jme_mii; /* mii bus */ 159 uint32_t jme_flags; /* device features, see below */ 160 uint32_t jme_txcsr; /* TX config register */ 161 uint32_t jme_rxcsr; /* RX config register */ 162 krndsource_t rnd_source; 163 /* interrupt coalition parameters */ 164 struct sysctllog *jme_clog; 165 int jme_intrxto; /* interrupt RX timeout */ 166 int jme_intrxct; /* interrupt RX packets counter */ 167 int jme_inttxto; /* interrupt TX timeout */ 168 int jme_inttxct; /* interrupt TX packets counter */ 169 }; 170 171 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 172 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 173 174 175 #define jme_if jme_ec.ec_if 176 #define jme_bpf jme_if.if_bpf 177 178 typedef struct jme_softc jme_softc_t; 179 typedef u_long ioctl_cmd_t; 180 181 static int jme_pci_match(device_t, cfdata_t, void *); 182 static void jme_pci_attach(device_t, device_t, void *); 183 static void jme_intr_rx(jme_softc_t *); 184 static int jme_intr(void *); 185 186 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 187 static int jme_mediachange(struct ifnet *); 188 static void jme_ifwatchdog(struct ifnet *); 189 static bool jme_shutdown(device_t, int); 190 191 static void jme_txeof(struct jme_softc *); 192 static void jme_ifstart(struct ifnet *); 193 static void jme_reset(jme_softc_t *); 194 static int jme_ifinit(struct ifnet *); 195 static int jme_init(struct ifnet *, int); 196 static void jme_stop(struct ifnet *, int); 197 // static void jme_restart(void *); 198 static void jme_ticks(void *); 199 static void jme_mac_config(jme_softc_t *); 200 static void jme_set_filter(jme_softc_t *); 201 202 static int jme_mii_read(device_t, int, int, uint16_t *); 203 static int jme_mii_write(device_t, int, int, uint16_t); 204 static void jme_statchg(struct ifnet *); 205 206 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 207 static int jme_eeprom_macaddr(struct jme_softc *); 208 static int jme_reg_macaddr(struct jme_softc *); 209 210 #define JME_TIMEOUT 1000 211 #define JME_PHY_TIMEOUT 1000 212 #define JME_EEPROM_TIMEOUT 1000 213 214 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 215 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 216 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 217 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 218 static int jme_root_num; 219 220 221 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 222 jme_pci_match, jme_pci_attach, NULL, NULL); 223 224 static const struct device_compatible_entry compat_data[] = { 225 { .id = PCI_ID_CODE(PCI_VENDOR_JMICRON, 226 PCI_PRODUCT_JMICRON_JMC250), 227 .data = "JMicron JMC250 Gigabit Ethernet Controller" }, 228 229 { .id = PCI_ID_CODE(PCI_VENDOR_JMICRON, 230 PCI_PRODUCT_JMICRON_JMC260), 231 .data = "JMicron JMC260 Gigabit Ethernet Controller" }, 232 233 PCI_COMPAT_EOL 234 }; 235 236 static int 237 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 238 { 239 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 240 241 return pci_compatible_match(pa, compat_data); 242 } 243 244 static void 245 jme_pci_attach(device_t parent, device_t self, void *aux) 246 { 247 jme_softc_t *sc = device_private(self); 248 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 249 const struct device_compatible_entry *dce; 250 struct ifnet * const ifp = &sc->jme_if; 251 struct mii_data * const mii = &sc->jme_mii; 252 bus_space_tag_t iot1, iot2, memt; 253 bus_space_handle_t ioh1, ioh2, memh; 254 bus_size_t size, size2; 255 pci_intr_handle_t intrhandle; 256 const char *intrstr; 257 pcireg_t csr; 258 int nsegs, i; 259 const struct sysctlnode *node; 260 int jme_nodenum; 261 char intrbuf[PCI_INTRSTR_LEN]; 262 263 sc->jme_dev = self; 264 aprint_normal("\n"); 265 callout_init(&sc->jme_tick_ch, 0); 266 callout_setfunc(&sc->jme_tick_ch, jme_ticks, sc); 267 268 dce = pci_compatible_lookup(pa, compat_data); 269 KASSERT(dce != NULL); 270 271 if (PCI_PRODUCT(dce->id) == PCI_PRODUCT_JMICRON_JMC250) 272 sc->jme_flags = JME_FLAG_GIGA; 273 274 /* 275 * Map the card space. Try Mem first. 276 */ 277 if (pci_mapreg_map(pa, JME_PCI_BAR0, 278 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 279 0, &memt, &memh, NULL, &size) == 0) { 280 sc->jme_bt_mac = memt; 281 sc->jme_bh_mac = memh; 282 sc->jme_bt_phy = memt; 283 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 284 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 285 aprint_error_dev(self, "can't subregion PHY space\n"); 286 bus_space_unmap(memt, memh, size); 287 return; 288 } 289 sc->jme_bt_misc = memt; 290 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 291 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 292 aprint_error_dev(self, "can't subregion misc space\n"); 293 bus_space_unmap(memt, memh, size); 294 return; 295 } 296 } else { 297 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 298 0, &iot1, &ioh1, NULL, &size) != 0) { 299 aprint_error_dev(self, "can't map I/O space 1\n"); 300 return; 301 } 302 sc->jme_bt_mac = iot1; 303 sc->jme_bh_mac = ioh1; 304 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 305 0, &iot2, &ioh2, NULL, &size2) != 0) { 306 aprint_error_dev(self, "can't map I/O space 2\n"); 307 bus_space_unmap(iot1, ioh1, size); 308 return; 309 } 310 sc->jme_bt_phy = iot2; 311 sc->jme_bh_phy = ioh2; 312 sc->jme_bt_misc = iot2; 313 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 314 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 315 aprint_error_dev(self, "can't subregion misc space\n"); 316 bus_space_unmap(iot1, ioh1, size); 317 bus_space_unmap(iot2, ioh2, size2); 318 return; 319 } 320 } 321 322 if (pci_dma64_available(pa)) 323 sc->jme_dmatag = pa->pa_dmat64; 324 else 325 sc->jme_dmatag = pa->pa_dmat; 326 327 /* Enable the device. */ 328 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 329 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 330 csr | PCI_COMMAND_MASTER_ENABLE); 331 332 aprint_normal_dev(self, "%s\n", (const char *)dce->data); 333 334 sc->jme_rev = PCI_REVISION(pa->pa_class); 335 336 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 337 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 338 CHIPMODE_NOT_FPGA) 339 sc->jme_flags |= JME_FLAG_FPGA; 340 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 341 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 342 "0x%x", sc->jme_rev, sc->jme_chip_rev); 343 if (sc->jme_flags & JME_FLAG_FPGA) 344 aprint_verbose(" FPGA revision: 0x%x", 345 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 346 aprint_verbose("\n"); 347 348 /* 349 * Save PHY address. 350 * Integrated JR0211 has fixed PHY address whereas FPGA version 351 * requires PHY probing to get correct PHY address. 352 */ 353 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 354 sc->jme_phyaddr = 355 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 356 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 357 } else 358 sc->jme_phyaddr = 0; 359 360 361 jme_reset(sc); 362 363 /* read mac addr */ 364 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 365 aprint_error_dev(self, "error reading Ethernet address\n"); 366 /* return; */ 367 } 368 aprint_normal_dev(self, "Ethernet address %s\n", 369 ether_sprintf(sc->jme_enaddr)); 370 371 /* Map and establish interrupts */ 372 if (pci_intr_map(pa, &intrhandle)) { 373 aprint_error_dev(self, "couldn't map interrupt\n"); 374 return; 375 } 376 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 377 sc->jme_if.if_softc = sc; 378 sc->jme_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 379 jme_intr, sc, device_xname(self)); 380 if (sc->jme_ih == NULL) { 381 aprint_error_dev(self, "couldn't establish interrupt"); 382 if (intrstr != NULL) 383 aprint_error(" at %s", intrstr); 384 aprint_error("\n"); 385 return; 386 } 387 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 388 389 /* allocate and map DMA-safe memory for transmit ring */ 390 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 391 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 392 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 393 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 394 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 395 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 396 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 397 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 398 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 399 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 400 return; 401 } 402 /* allocate and map DMA-safe memory for receive ring */ 403 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 404 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 405 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 406 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 407 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 408 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 409 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 410 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 411 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 412 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 413 return; 414 } 415 for (i = 0; i < JME_NBUFS; i++) { 416 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 417 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 418 JME_NBUFS, JME_MAX_TX_LEN, 0, 419 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 420 &sc->jme_txmbufm[i]) != 0) { 421 aprint_error_dev(self, "can't allocate DMA TX map\n"); 422 return; 423 } 424 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 425 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 426 &sc->jme_rxmbufm[i]) != 0) { 427 aprint_error_dev(self, "can't allocate DMA RX map\n"); 428 return; 429 } 430 } 431 /* 432 * Initialize our media structures and probe the MII. 433 * 434 * Note that we don't care about the media instance. We 435 * are expecting to have multiple PHYs on the 10/100 cards, 436 * and on those cards we exclude the internal PHY from providing 437 * 10baseT. By ignoring the instance, it allows us to not have 438 * to specify it on the command line when switching media. 439 */ 440 mii->mii_ifp = ifp; 441 mii->mii_readreg = jme_mii_read; 442 mii->mii_writereg = jme_mii_write; 443 mii->mii_statchg = jme_statchg; 444 sc->jme_ec.ec_mii = mii; 445 ifmedia_init(&mii->mii_media, IFM_IMASK, jme_mediachange, 446 ether_mediastatus); 447 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 448 if (LIST_FIRST(&mii->mii_phys) == NULL) { 449 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 450 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 451 } else 452 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 453 454 /* 455 * We can support 802.1Q VLAN-sized frames. 456 */ 457 sc->jme_ec.ec_capabilities |= 458 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 459 sc->jme_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 460 461 if (sc->jme_flags & JME_FLAG_GIGA) 462 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 463 464 465 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 466 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 467 ifp->if_ioctl = jme_ifioctl; 468 ifp->if_start = jme_ifstart; 469 ifp->if_watchdog = jme_ifwatchdog; 470 ifp->if_init = jme_ifinit; 471 ifp->if_stop = jme_stop; 472 ifp->if_timer = 0; 473 ifp->if_capabilities |= 474 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 475 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 476 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 477 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 478 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 479 IFCAP_TSOv4 | IFCAP_TSOv6; 480 IFQ_SET_READY(&ifp->if_snd); 481 if_attach(ifp); 482 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 483 484 /* 485 * Add shutdown hook so that DMA is disabled prior to reboot. 486 */ 487 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 488 pmf_class_network_register(self, ifp); 489 else 490 aprint_error_dev(self, "couldn't establish power handler\n"); 491 492 rnd_attach_source(&sc->rnd_source, device_xname(self), 493 RND_TYPE_NET, RND_FLAG_DEFAULT); 494 495 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 496 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 497 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 498 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 499 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 500 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 501 SYSCTL_DESCR("jme per-controller controls"), 502 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 503 CTL_EOL) != 0) { 504 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 505 return; 506 } 507 jme_nodenum = node->sysctl_num; 508 509 /* interrupt moderation sysctls */ 510 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 511 CTLFLAG_READWRITE, 512 CTLTYPE_INT, "int_rxto", 513 SYSCTL_DESCR("jme RX interrupt moderation timer"), 514 jme_sysctl_intrxto, 0, (void *)sc, 515 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 516 CTL_EOL) != 0) { 517 aprint_normal_dev(sc->jme_dev, 518 "couldn't create int_rxto sysctl node\n"); 519 } 520 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 521 CTLFLAG_READWRITE, 522 CTLTYPE_INT, "int_rxct", 523 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 524 jme_sysctl_intrxct, 0, (void *)sc, 525 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 526 CTL_EOL) != 0) { 527 aprint_normal_dev(sc->jme_dev, 528 "couldn't create int_rxct sysctl node\n"); 529 } 530 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 531 CTLFLAG_READWRITE, 532 CTLTYPE_INT, "int_txto", 533 SYSCTL_DESCR("jme TX interrupt moderation timer"), 534 jme_sysctl_inttxto, 0, (void *)sc, 535 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 536 CTL_EOL) != 0) { 537 aprint_normal_dev(sc->jme_dev, 538 "couldn't create int_txto sysctl node\n"); 539 } 540 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 541 CTLFLAG_READWRITE, 542 CTLTYPE_INT, "int_txct", 543 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 544 jme_sysctl_inttxct, 0, (void *)sc, 545 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 546 CTL_EOL) != 0) { 547 aprint_normal_dev(sc->jme_dev, 548 "couldn't create int_txct sysctl node\n"); 549 } 550 } 551 552 static void 553 jme_stop_rx(jme_softc_t *sc) 554 { 555 uint32_t reg; 556 int i; 557 558 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 559 if ((reg & RXCSR_RX_ENB) == 0) 560 return; 561 reg &= ~RXCSR_RX_ENB; 562 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 563 for (i = JME_TIMEOUT / 10; i > 0; i--) { 564 DELAY(10); 565 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 566 JME_RXCSR) & RXCSR_RX_ENB) == 0) 567 break; 568 } 569 if (i == 0) 570 aprint_error_dev(sc->jme_dev, "stopping receiver timeout!\n"); 571 572 } 573 574 static void 575 jme_stop_tx(jme_softc_t *sc) 576 { 577 uint32_t reg; 578 int i; 579 580 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 581 if ((reg & TXCSR_TX_ENB) == 0) 582 return; 583 reg &= ~TXCSR_TX_ENB; 584 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 585 for (i = JME_TIMEOUT / 10; i > 0; i--) { 586 DELAY(10); 587 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 588 JME_TXCSR) & TXCSR_TX_ENB) == 0) 589 break; 590 } 591 if (i == 0) 592 aprint_error_dev(sc->jme_dev, 593 "stopping transmitter timeout!\n"); 594 } 595 596 static void 597 jme_reset(jme_softc_t *sc) 598 { 599 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 600 DELAY(10); 601 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 602 } 603 604 static bool 605 jme_shutdown(device_t self, int howto) 606 { 607 jme_softc_t *sc; 608 struct ifnet *ifp; 609 610 sc = device_private(self); 611 ifp = &sc->jme_if; 612 jme_stop(ifp, 1); 613 614 return true; 615 } 616 617 static void 618 jme_stop(struct ifnet *ifp, int disable) 619 { 620 jme_softc_t *sc = ifp->if_softc; 621 int i; 622 /* Stop receiver, transmitter. */ 623 jme_stop_rx(sc); 624 jme_stop_tx(sc); 625 /* free receive mbufs */ 626 for (i = 0; i < JME_NBUFS; i++) { 627 if (sc->jme_rxmbuf[i]) { 628 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 629 m_freem(sc->jme_rxmbuf[i]); 630 } 631 sc->jme_rxmbuf[i] = NULL; 632 } 633 /* process completed transmits */ 634 jme_txeof(sc); 635 /* free abort pending transmits */ 636 for (i = 0; i < JME_NBUFS; i++) { 637 if (sc->jme_txmbuf[i]) { 638 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 639 m_freem(sc->jme_txmbuf[i]); 640 sc->jme_txmbuf[i] = NULL; 641 } 642 } 643 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 644 ifp->if_timer = 0; 645 } 646 647 #if 0 648 static void 649 jme_restart(void *v) 650 { 651 652 jme_init(v); 653 } 654 #endif 655 656 static int 657 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 658 { 659 int error; 660 bus_dmamap_t map; 661 int i = sc->jme_rx_prod; 662 663 if (sc->jme_rxmbuf[i] != NULL) { 664 aprint_error_dev(sc->jme_dev, 665 "mbuf already here: rxprod %d rxcons %d\n", 666 sc->jme_rx_prod, sc->jme_rx_cons); 667 if (m) 668 m_freem(m); 669 return EINVAL; 670 } 671 672 if (m == NULL) { 673 sc->jme_rxmbuf[i] = NULL; 674 MGETHDR(m, M_DONTWAIT, MT_DATA); 675 if (m == NULL) 676 return (ENOBUFS); 677 MCLGET(m, M_DONTWAIT); 678 if ((m->m_flags & M_EXT) == 0) { 679 m_freem(m); 680 return (ENOBUFS); 681 } 682 } 683 map = sc->jme_rxmbufm[i]; 684 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 685 KASSERT(m->m_len == MCLBYTES); 686 687 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 688 BUS_DMA_READ | BUS_DMA_NOWAIT); 689 if (error) { 690 sc->jme_rxmbuf[i] = NULL; 691 aprint_error_dev(sc->jme_dev, 692 "unable to load rx DMA map %d, error = %d\n", 693 i, error); 694 m_freem(m); 695 return (error); 696 } 697 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 698 BUS_DMASYNC_PREREAD); 699 700 sc->jme_rxmbuf[i] = m; 701 702 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 703 sc->jme_rxring[i].addr_lo = 704 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 705 sc->jme_rxring[i].addr_hi = 706 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 707 sc->jme_rxring[i].flags = 708 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 709 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 710 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 712 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 713 return (0); 714 } 715 716 static int 717 jme_ifinit(struct ifnet *ifp) 718 { 719 return jme_init(ifp, 1); 720 } 721 722 static int 723 jme_init(struct ifnet *ifp, int do_ifinit) 724 { 725 jme_softc_t *sc = ifp->if_softc; 726 int i, s; 727 uint8_t eaddr[ETHER_ADDR_LEN]; 728 uint32_t reg; 729 730 s = splnet(); 731 /* cancel any pending IO */ 732 jme_stop(ifp, 1); 733 jme_reset(sc); 734 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 735 splx(s); 736 return 0; 737 } 738 /* allocate receive ring */ 739 sc->jme_rx_prod = 0; 740 for (i = 0; i < JME_NBUFS; i++) { 741 if (jme_add_rxbuf(sc, NULL) < 0) { 742 aprint_error_dev(sc->jme_dev, 743 "can't allocate rx mbuf\n"); 744 for (i--; i >= 0; i--) { 745 bus_dmamap_unload(sc->jme_dmatag, 746 sc->jme_rxmbufm[i]); 747 m_freem(sc->jme_rxmbuf[i]); 748 sc->jme_rxmbuf[i] = NULL; 749 } 750 splx(s); 751 return ENOMEM; 752 } 753 } 754 /* init TX ring */ 755 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 756 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 757 0, JME_NBUFS * sizeof(struct jme_desc), 758 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 759 for (i = 0; i < JME_NBUFS; i++) 760 sc->jme_txmbuf[i] = NULL; 761 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 762 763 /* Reprogram the station address. */ 764 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 765 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 766 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 767 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 768 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 769 770 /* 771 * Configure Tx queue. 772 * Tx priority queue weight value : 0 773 * Tx FIFO threshold for processing next packet : 16QW 774 * Maximum Tx DMA length : 512 775 * Allow Tx DMA burst. 776 */ 777 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 778 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 779 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 780 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 781 sc->jme_txcsr |= TXCSR_DMA_BURST; 782 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 783 JME_TXCSR, sc->jme_txcsr); 784 785 /* Set Tx descriptor counter. */ 786 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 787 JME_TXQDC, JME_NBUFS); 788 789 /* Set Tx ring address to the hardware. */ 790 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 791 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 792 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 793 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 794 795 /* Configure TxMAC parameters. */ 796 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 797 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 798 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 799 800 /* 801 * Configure Rx queue. 802 * FIFO full threshold for transmitting Tx pause packet : 128T 803 * FIFO threshold for processing next packet : 128QW 804 * Rx queue 0 select 805 * Max Rx DMA length : 128 806 * Rx descriptor retry : 32 807 * Rx descriptor retry time gap : 256ns 808 * Don't receive runt/bad frame. 809 */ 810 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 811 /* 812 * Since Rx FIFO size is 4K bytes, receiving frames larger 813 * than 4K bytes will suffer from Rx FIFO overruns. So 814 * decrease FIFO threshold to reduce the FIFO overruns for 815 * frames larger than 4000 bytes. 816 * For best performance of standard MTU sized frames use 817 * maximum allowable FIFO threshold, 128QW. 818 */ 819 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 820 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 821 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 822 else 823 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 824 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 825 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 826 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 827 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 828 JME_RXCSR, sc->jme_rxcsr); 829 830 /* Set Rx descriptor counter. */ 831 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 832 JME_RXQDC, JME_NBUFS); 833 834 /* Set Rx ring address to the hardware. */ 835 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 836 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 837 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 838 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 839 840 /* Clear receive filter. */ 841 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 842 /* Set up the receive filter. */ 843 jme_set_filter(sc); 844 845 /* 846 * Disable all WOL bits as WOL can interfere normal Rx 847 * operation. Also clear WOL detection status bits. 848 */ 849 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 850 reg &= ~PMCS_WOL_ENB_MASK; 851 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 852 853 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 854 /* 855 * Pad 10bytes right before received frame. This will greatly 856 * help Rx performance on strict-alignment architectures as 857 * it does not need to copy the frame to align the payload. 858 */ 859 reg |= RXMAC_PAD_10BYTES; 860 if ((ifp->if_capenable & 861 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 862 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) != 0) 863 reg |= RXMAC_CSUM_ENB; 864 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 865 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 866 867 /* Configure general purpose reg0 */ 868 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 869 reg &= ~GPREG0_PCC_UNIT_MASK; 870 /* Set PCC timer resolution to micro-seconds unit. */ 871 reg |= GPREG0_PCC_UNIT_US; 872 /* 873 * Disable all shadow register posting as we have to read 874 * JME_INTR_STATUS register in jme_int_task. Also it seems 875 * that it's hard to synchronize interrupt status between 876 * hardware and software with shadow posting due to 877 * requirements of bus_dmamap_sync(9). 878 */ 879 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 880 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 881 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 882 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 883 /* Disable posting of DW0. */ 884 reg &= ~GPREG0_POST_DW0_ENB; 885 /* Clear PME message. */ 886 reg &= ~GPREG0_PME_ENB; 887 /* Set PHY address. */ 888 reg &= ~GPREG0_PHY_ADDR_MASK; 889 reg |= sc->jme_phyaddr; 890 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 891 892 /* Configure Tx queue 0 packet completion coalescing. */ 893 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 894 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 895 reg |= PCCTX_COAL_TXQ0; 896 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 897 898 /* Configure Rx queue 0 packet completion coalescing. */ 899 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 900 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 901 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 902 903 /* Disable Timers */ 904 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 905 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 906 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 907 908 /* Configure retry transmit period, retry limit value. */ 909 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 910 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 911 TXTRHD_RT_PERIOD_MASK) | 912 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 913 TXTRHD_RT_LIMIT_SHIFT)); 914 915 /* Disable RSS. */ 916 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 917 JME_RSSC, RSSC_DIS_RSS); 918 919 /* Initialize the interrupt mask. */ 920 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 921 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 922 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 923 JME_INTR_STATUS, 0xFFFFFFFF); 924 925 /* set media, if not already handling a media change */ 926 if (do_ifinit) { 927 int error; 928 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 929 error = 0; 930 else if (error != 0) { 931 aprint_error_dev(sc->jme_dev, "could not set media\n"); 932 splx(s); 933 return error; 934 } 935 } 936 937 /* Program MAC with resolved speed/duplex/flow-control. */ 938 jme_mac_config(sc); 939 940 /* Start receiver/transmitter. */ 941 sc->jme_rx_cons = 0; 942 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 943 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 944 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 945 sc->jme_txcsr | TXCSR_TX_ENB); 946 947 /* start ticks calls */ 948 callout_schedule(&sc->jme_tick_ch, hz); 949 sc->jme_if.if_flags |= IFF_RUNNING; 950 sc->jme_if.if_flags &= ~IFF_OACTIVE; 951 splx(s); 952 return 0; 953 } 954 955 static int 956 jme_mii_read(device_t self, int phy, int reg, uint16_t *val) 957 { 958 struct jme_softc *sc = device_private(self); 959 int data, i; 960 961 /* For FPGA version, PHY address 0 should be ignored. */ 962 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 963 if (phy == 0) 964 return -1; 965 } else { 966 if (sc->jme_phyaddr != phy) 967 return -1; 968 } 969 970 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 971 SMI_OP_READ | SMI_OP_EXECUTE | 972 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 973 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 974 delay(10); 975 if (((data = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 976 JME_SMI)) & SMI_OP_EXECUTE) == 0) 977 break; 978 } 979 980 if (i == 0) { 981 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 982 return ETIMEDOUT; 983 } 984 985 *val = (data & SMI_DATA_MASK) >> SMI_DATA_SHIFT; 986 return 0; 987 } 988 989 static int 990 jme_mii_write(device_t self, int phy, int reg, uint16_t val) 991 { 992 struct jme_softc *sc = device_private(self); 993 int i; 994 995 /* For FPGA version, PHY address 0 should be ignored. */ 996 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 997 if (phy == 0) 998 return -1; 999 } else { 1000 if (sc->jme_phyaddr != phy) 1001 return -1; 1002 } 1003 1004 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1005 SMI_OP_WRITE | SMI_OP_EXECUTE | 1006 (((uint32_t)val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1007 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1008 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1009 delay(10); 1010 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1011 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1012 break; 1013 } 1014 1015 if (i == 0) { 1016 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1017 return ETIMEDOUT; 1018 } 1019 1020 return 0; 1021 } 1022 1023 static void 1024 jme_statchg(struct ifnet *ifp) 1025 { 1026 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1027 jme_init(ifp, 0); 1028 } 1029 1030 static void 1031 jme_intr_rx(jme_softc_t *sc) { 1032 struct mbuf *m, *mhead; 1033 bus_dmamap_t mmap; 1034 struct ifnet *ifp = &sc->jme_if; 1035 uint32_t flags, buflen; 1036 int i, ipackets, nsegs, seg, error; 1037 struct jme_desc *desc; 1038 1039 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1040 sizeof(struct jme_desc) * JME_NBUFS, 1041 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1042 #ifdef JMEDEBUG_RX 1043 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1044 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1045 #endif 1046 ipackets = 0; 1047 while ((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) 1048 == 0) { 1049 i = sc->jme_rx_cons; 1050 desc = &sc->jme_rxring[i]; 1051 #ifdef JMEDEBUG_RX 1052 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1053 i, le32toh(desc->flags), le32toh(desc->buflen)); 1054 #endif 1055 if (sc->jme_rxmbuf[i] == NULL) { 1056 if ((error = jme_add_rxbuf(sc, NULL)) != 0) { 1057 aprint_error_dev(sc->jme_dev, 1058 "can't add new mbuf to empty slot: %d\n", 1059 error); 1060 break; 1061 } 1062 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1063 i = sc->jme_rx_cons; 1064 continue; 1065 } 1066 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1067 break; 1068 1069 buflen = le32toh(desc->buflen); 1070 nsegs = JME_RX_NSEGS(buflen); 1071 flags = le32toh(desc->flags); 1072 if ((buflen & JME_RX_ERR_STAT) != 0 || 1073 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1074 JME_RX_BYTES(buflen) > 1075 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1076 #ifdef JMEDEBUG_RX 1077 printf("rx error flags 0x%x buflen 0x%x\n", 1078 flags, buflen); 1079 #endif 1080 if_statinc(ifp, if_ierrors); 1081 /* reuse the mbufs */ 1082 for (seg = 0; seg < nsegs; seg++) { 1083 m = sc->jme_rxmbuf[i]; 1084 sc->jme_rxmbuf[i] = NULL; 1085 mmap = sc->jme_rxmbufm[i]; 1086 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1087 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1088 bus_dmamap_unload(sc->jme_dmatag, mmap); 1089 if ((error = jme_add_rxbuf(sc, m)) != 0) 1090 aprint_error_dev(sc->jme_dev, 1091 "can't reuse mbuf: %d\n", error); 1092 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1093 i = sc->jme_rx_cons; 1094 } 1095 continue; 1096 } 1097 /* receive this packet */ 1098 mhead = m = sc->jme_rxmbuf[i]; 1099 sc->jme_rxmbuf[i] = NULL; 1100 mmap = sc->jme_rxmbufm[i]; 1101 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1102 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1103 bus_dmamap_unload(sc->jme_dmatag, mmap); 1104 /* add a new buffer to chain */ 1105 if (jme_add_rxbuf(sc, NULL) != 0) { 1106 if ((error = jme_add_rxbuf(sc, m)) != 0) 1107 aprint_error_dev(sc->jme_dev, 1108 "can't reuse mbuf: %d\n", error); 1109 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1110 i = sc->jme_rx_cons; 1111 for (seg = 1; seg < nsegs; seg++) { 1112 m = sc->jme_rxmbuf[i]; 1113 sc->jme_rxmbuf[i] = NULL; 1114 mmap = sc->jme_rxmbufm[i]; 1115 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1116 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1117 bus_dmamap_unload(sc->jme_dmatag, mmap); 1118 if ((error = jme_add_rxbuf(sc, m)) != 0) 1119 aprint_error_dev(sc->jme_dev, 1120 "can't reuse mbuf: %d\n", error); 1121 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1122 i = sc->jme_rx_cons; 1123 } 1124 if_statinc(ifp, if_ierrors); 1125 continue; 1126 } 1127 1128 /* build mbuf chain: head, then remaining segments */ 1129 m_set_rcvif(m, ifp); 1130 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1131 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1132 m->m_pkthdr.len; 1133 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1134 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1135 for (seg = 1; seg < nsegs; seg++) { 1136 i = sc->jme_rx_cons; 1137 m = sc->jme_rxmbuf[i]; 1138 sc->jme_rxmbuf[i] = NULL; 1139 mmap = sc->jme_rxmbufm[i]; 1140 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1141 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1142 bus_dmamap_unload(sc->jme_dmatag, mmap); 1143 if ((error = jme_add_rxbuf(sc, NULL)) != 0) 1144 aprint_error_dev(sc->jme_dev, 1145 "can't add new mbuf: %d\n", error); 1146 m->m_flags &= ~M_PKTHDR; 1147 m_cat(mhead, m); 1148 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1149 } 1150 /* and adjust last mbuf's size */ 1151 if (nsegs > 1) { 1152 m->m_len = 1153 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1154 } 1155 ipackets++; 1156 1157 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1158 (flags & JME_RD_IPV4)) { 1159 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1160 if (!(flags & JME_RD_IPCSUM)) 1161 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1162 } 1163 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1164 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1165 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1166 if (!(flags & JME_RD_TCPCSUM)) 1167 mhead->m_pkthdr.csum_flags |= 1168 M_CSUM_TCP_UDP_BAD; 1169 } 1170 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1171 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1172 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1173 if (!(flags & JME_RD_UDPCSUM)) 1174 mhead->m_pkthdr.csum_flags |= 1175 M_CSUM_TCP_UDP_BAD; 1176 } 1177 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1178 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1179 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1180 if (!(flags & JME_RD_TCPCSUM)) 1181 mhead->m_pkthdr.csum_flags |= 1182 M_CSUM_TCP_UDP_BAD; 1183 } 1184 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1185 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1186 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1187 if (!(flags & JME_RD_UDPCSUM)) 1188 mhead->m_pkthdr.csum_flags |= 1189 M_CSUM_TCP_UDP_BAD; 1190 } 1191 if (flags & JME_RD_VLAN_TAG) { 1192 /* pass to vlan_input() */ 1193 vlan_set_tag(mhead, (flags & JME_RD_VLAN_MASK)); 1194 } 1195 if_percpuq_enqueue(ifp->if_percpuq, mhead); 1196 } 1197 if (ipackets) 1198 rnd_add_uint32(&sc->rnd_source, ipackets); 1199 } 1200 1201 static int 1202 jme_intr(void *v) 1203 { 1204 jme_softc_t *sc = v; 1205 uint32_t istatus; 1206 1207 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1208 JME_INTR_STATUS); 1209 if (istatus == 0 || istatus == 0xFFFFFFFF) 1210 return 0; 1211 /* Disable interrupts. */ 1212 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1213 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1214 again: 1215 /* and update istatus */ 1216 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1217 JME_INTR_STATUS); 1218 if ((istatus & JME_INTRS_CHECK) == 0) 1219 goto done; 1220 /* Reset PCC counter/timer and Ack interrupts. */ 1221 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1222 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1223 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1224 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1225 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1226 JME_INTR_STATUS, istatus); 1227 1228 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1229 goto done; 1230 #ifdef JMEDEBUG_RX 1231 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1232 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1233 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1234 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1235 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1236 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1237 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1238 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1239 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1240 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1241 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1242 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1243 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1244 #endif 1245 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1246 jme_intr_rx(sc); 1247 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1248 /* 1249 * Notify hardware availability of new Rx 1250 * buffers. 1251 * Reading RXCSR takes very long time under 1252 * heavy load so cache RXCSR value and writes 1253 * the ORed value with the kick command to 1254 * the RXCSR. This saves one register access 1255 * cycle. 1256 */ 1257 sc->jme_rx_cons = 0; 1258 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1259 JME_RXCSR, 1260 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1261 } 1262 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1263 jme_ifstart(&sc->jme_if); 1264 1265 goto again; 1266 1267 done: 1268 /* enable interrupts. */ 1269 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1270 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1271 return 1; 1272 } 1273 1274 1275 static int 1276 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1277 { 1278 struct jme_softc *sc = ifp->if_softc; 1279 int s, error; 1280 struct ifreq *ifr; 1281 struct ifcapreq *ifcr; 1282 1283 s = splnet(); 1284 /* 1285 * we can't support at the same time jumbo frames and 1286 * TX checksums offload/TSO 1287 */ 1288 switch (cmd) { 1289 case SIOCSIFMTU: 1290 ifr = data; 1291 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1292 (ifp->if_capenable & ( 1293 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1294 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1295 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1296 splx(s); 1297 return EINVAL; 1298 } 1299 break; 1300 case SIOCSIFCAP: 1301 ifcr = data; 1302 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1303 (ifcr->ifcr_capenable & ( 1304 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1305 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1306 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1307 splx(s); 1308 return EINVAL; 1309 } 1310 break; 1311 } 1312 1313 error = ether_ioctl(ifp, cmd, data); 1314 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1315 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1316 jme_set_filter(sc); 1317 error = 0; 1318 } else { 1319 error = jme_init(ifp, 0); 1320 } 1321 } 1322 splx(s); 1323 return error; 1324 } 1325 1326 static int 1327 jme_encap(struct jme_softc *sc, struct mbuf * const m) 1328 { 1329 struct jme_desc *desc; 1330 int error, i, prod, headdsc, nsegs; 1331 uint32_t cflags, tso_segsz; 1332 1333 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1334 /* 1335 * Due to the adherence to NDIS specification JMC250 1336 * assumes upper stack computed TCP pseudo checksum 1337 * without including payload length. This breaks 1338 * checksum offload for TSO case so recompute TCP 1339 * pseudo checksum for JMC250. Hopefully this wouldn't 1340 * be much burden on modern CPUs. 1341 */ 1342 bool v4 = (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1343 int iphl = v4 ? 1344 M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data) : 1345 M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data); 1346 /* 1347 * note: we support vlan offloading, so we should never have 1348 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1349 * right. 1350 */ 1351 int hlen = ETHER_HDR_LEN + iphl; 1352 1353 if (__predict_false(m->m_len < 1354 (hlen + sizeof(struct tcphdr)))) { 1355 /* 1356 * 1357 * TCP/IP headers are not in the first mbuf; we need 1358 * to do this the slow and painful way. Let's just 1359 * hope this doesn't happen very often. 1360 */ 1361 struct tcphdr th; 1362 1363 m_copydata(m, hlen, sizeof(th), &th); 1364 if (v4) { 1365 struct ip ip; 1366 1367 m_copydata(m, ETHER_HDR_LEN, sizeof(ip), &ip); 1368 ip.ip_len = 0; 1369 m_copyback(m, 1370 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1371 sizeof(ip.ip_len), &ip.ip_len); 1372 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1373 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1374 } else { 1375 #if INET6 1376 struct ip6_hdr ip6; 1377 1378 m_copydata(m, ETHER_HDR_LEN, 1379 sizeof(ip6), &ip6); 1380 ip6.ip6_plen = 0; 1381 m_copyback(m, ETHER_HDR_LEN + 1382 offsetof(struct ip6_hdr, ip6_plen), 1383 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1384 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1385 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1386 #endif /* INET6 */ 1387 } 1388 m_copyback(m, hlen + offsetof(struct tcphdr, th_sum), 1389 sizeof(th.th_sum), &th.th_sum); 1390 1391 hlen += th.th_off << 2; 1392 } else { 1393 /* 1394 * TCP/IP headers are in the first mbuf; we can do 1395 * this the easy way. 1396 */ 1397 struct tcphdr *th; 1398 1399 if (v4) { 1400 struct ip *ip = 1401 (void *)(mtod(m, char *) + 1402 ETHER_HDR_LEN); 1403 th = (void *)(mtod(m, char *) + hlen); 1404 1405 ip->ip_len = 0; 1406 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1407 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1408 } else { 1409 #if INET6 1410 struct ip6_hdr *ip6 = 1411 (void *)(mtod(m, char *) + 1412 ETHER_HDR_LEN); 1413 th = (void *)(mtod(m, char *) + hlen); 1414 1415 ip6->ip6_plen = 0; 1416 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1417 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1418 #endif /* INET6 */ 1419 } 1420 hlen += th->th_off << 2; 1421 } 1422 } 1423 1424 prod = sc->jme_tx_prod; 1425 1426 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1427 m, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1428 if (error) { 1429 if (error == EFBIG) { 1430 log(LOG_ERR, "%s: Tx packet consumes too many " 1431 "DMA segments, dropping...\n", 1432 device_xname(sc->jme_dev)); 1433 /* Caller will free the packet. */ 1434 } 1435 return (error); 1436 } 1437 /* 1438 * Check descriptor overrun. Leave one free descriptor. 1439 * Since we always use 64bit address mode for transmitting, 1440 * each Tx request requires one more dummy descriptor. 1441 */ 1442 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1443 #ifdef JMEDEBUG_TX 1444 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1445 #endif 1446 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1447 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1448 return (ENOBUFS); 1449 } 1450 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1451 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1452 1453 cflags = 0; 1454 tso_segsz = 0; 1455 /* Configure checksum offload and TSO. */ 1456 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1457 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1458 cflags |= JME_TD_TSO; 1459 } else { 1460 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1461 cflags |= JME_TD_IPCSUM; 1462 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) 1463 != 0) 1464 cflags |= JME_TD_TCPCSUM; 1465 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) 1466 != 0) 1467 cflags |= JME_TD_UDPCSUM; 1468 } 1469 /* Configure VLAN. */ 1470 if (vlan_has_tag(m)) { 1471 cflags |= (vlan_get_tag(m) & JME_TD_VLAN_MASK); 1472 cflags |= JME_TD_VLAN_TAG; 1473 } 1474 1475 desc = &sc->jme_txring[prod]; 1476 desc->flags = htole32(cflags); 1477 desc->buflen = htole32(tso_segsz); 1478 desc->addr_hi = htole32(m->m_pkthdr.len); 1479 desc->addr_lo = 0; 1480 headdsc = prod; 1481 sc->jme_tx_cnt++; 1482 JME_DESC_INC(prod, JME_NBUFS); 1483 for (i = 0; i < nsegs; i++) { 1484 desc = &sc->jme_txring[prod]; 1485 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1486 desc->buflen = 1487 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1488 desc->addr_hi = htole32( 1489 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1490 desc->addr_lo = htole32( 1491 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1492 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1493 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1495 sc->jme_txmbuf[prod] = NULL; 1496 sc->jme_tx_cnt++; 1497 JME_DESC_INC(prod, JME_NBUFS); 1498 } 1499 1500 /* Update producer index. */ 1501 sc->jme_tx_prod = prod; 1502 #ifdef JMEDEBUG_TX 1503 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1504 #endif 1505 /* 1506 * Finally request interrupt and give the first descriptor 1507 * ownership to hardware. 1508 */ 1509 desc = &sc->jme_txring[headdsc]; 1510 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1511 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1512 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1513 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1514 1515 sc->jme_txmbuf[headdsc] = m; 1516 return (0); 1517 } 1518 1519 static void 1520 jme_txeof(struct jme_softc *sc) 1521 { 1522 struct ifnet *ifp; 1523 struct jme_desc *desc; 1524 uint32_t status; 1525 int cons, cons0, nsegs, seg; 1526 1527 ifp = &sc->jme_if; 1528 1529 #ifdef JMEDEBUG_TX 1530 printf("jme_txeof cons %d prod %d\n", 1531 sc->jme_tx_cons, sc->jme_tx_prod); 1532 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1533 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1534 "JME_TXTRHD 0x%x\n", 1535 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1536 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1537 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1538 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1539 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1540 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1541 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1542 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1543 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1544 desc = &sc->jme_txring[cons]; 1545 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1546 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1547 JME_DESC_INC(cons, JME_NBUFS); 1548 } 1549 #endif 1550 1551 cons = sc->jme_tx_cons; 1552 if (cons == sc->jme_tx_prod) 1553 return; 1554 1555 /* 1556 * Go through our Tx list and free mbufs for those 1557 * frames which have been transmitted. 1558 */ 1559 for (; cons != sc->jme_tx_prod;) { 1560 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1561 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1562 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1563 1564 desc = &sc->jme_txring[cons]; 1565 status = le32toh(desc->flags); 1566 #ifdef JMEDEBUG_TX 1567 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1568 sc->jme_txmbufm[cons]->dm_nsegs); 1569 #endif 1570 if (status & JME_TD_OWN) 1571 break; 1572 1573 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1574 if_statinc(ifp, if_oerrors); 1575 else { 1576 if_statinc(ifp, if_opackets); 1577 if ((status & JME_TD_COLLISION) != 0) { 1578 if_statadd(ifp, if_collisions, 1579 le32toh(desc->buflen) & 1580 JME_TD_BUF_LEN_MASK); 1581 } 1582 } 1583 /* 1584 * Only the first descriptor of multi-descriptor 1585 * transmission is updated so driver have to skip entire 1586 * chained buffers for the transmitted frame. In other 1587 * words, JME_TD_OWN bit is valid only at the first 1588 * descriptor of a multi-descriptor transmission. 1589 */ 1590 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1591 cons0 = cons; 1592 JME_DESC_INC(cons, JME_NBUFS); 1593 for (seg = 1; seg < nsegs + 1; seg++) { 1594 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1595 cons * sizeof(struct jme_desc), 1596 sizeof(struct jme_desc), 1597 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1598 sc->jme_txring[cons].flags = 0; 1599 JME_DESC_INC(cons, JME_NBUFS); 1600 } 1601 /* Reclaim transferred mbufs. */ 1602 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1603 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1604 BUS_DMASYNC_POSTWRITE); 1605 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1606 1607 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1608 m_freem(sc->jme_txmbuf[cons0]); 1609 sc->jme_txmbuf[cons0] = NULL; 1610 sc->jme_tx_cnt -= nsegs + 1; 1611 KASSERT(sc->jme_tx_cnt >= 0); 1612 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1613 } 1614 sc->jme_tx_cons = cons; 1615 /* Unarm watchdog timer when there are no pending descriptors in queue. */ 1616 if (sc->jme_tx_cnt == 0) 1617 ifp->if_timer = 0; 1618 #ifdef JMEDEBUG_TX 1619 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1620 #endif 1621 } 1622 1623 static void 1624 jme_ifstart(struct ifnet *ifp) 1625 { 1626 jme_softc_t *sc = ifp->if_softc; 1627 struct mbuf *mb_head; 1628 int enq, error; 1629 1630 /* 1631 * check if we can free some desc. 1632 * Clear TX interrupt status to reset TX coalescing counters. 1633 */ 1634 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1635 JME_INTR_STATUS, INTR_TXQ_COMP); 1636 jme_txeof(sc); 1637 1638 if ((sc->jme_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1639 return; 1640 for (enq = 0;; enq++) { 1641 nexttx: 1642 /* Grab a paquet for output */ 1643 IFQ_POLL(&ifp->if_snd, mb_head); 1644 if (mb_head == NULL) { 1645 #ifdef JMEDEBUG_TX 1646 printf("%s: nothing to send\n", __func__); 1647 #endif 1648 break; 1649 } 1650 /* try to add this mbuf to the TX ring */ 1651 if ((error = jme_encap(sc, mb_head)) != 0) { 1652 if (error == EFBIG) { 1653 /* This error is fatal to the packet. */ 1654 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1655 m_freem(mb_head); 1656 if_statinc(ifp, if_oerrors); 1657 goto nexttx; 1658 } 1659 /* resource shortage, try again later */ 1660 ifp->if_flags |= IFF_OACTIVE; 1661 break; 1662 } 1663 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1664 1665 /* Pass packet to bpf if there is a listener */ 1666 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1667 } 1668 #ifdef JMEDEBUG_TX 1669 printf("jme_ifstart enq %d\n", enq); 1670 #endif 1671 if (enq) { 1672 /* 1673 * Set a 5 second timer just in case we don't hear from 1674 * the card again. 1675 */ 1676 ifp->if_timer = 5; 1677 /* 1678 * Reading TXCSR takes very long time under heavy load 1679 * so cache TXCSR value and writes the ORed value with 1680 * the kick command to the TXCSR. This saves one register 1681 * access cycle. 1682 */ 1683 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1684 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1685 #ifdef JMEDEBUG_TX 1686 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1687 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1688 "JME_TXTRHD 0x%x\n", 1689 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1690 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1691 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1692 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1693 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1694 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1695 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1696 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1697 #endif 1698 } 1699 } 1700 1701 static void 1702 jme_ifwatchdog(struct ifnet *ifp) 1703 { 1704 jme_softc_t *sc = ifp->if_softc; 1705 1706 if ((ifp->if_flags & IFF_RUNNING) == 0) 1707 return; 1708 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1709 if_statinc(ifp, if_oerrors); 1710 jme_init(ifp, 0); 1711 } 1712 1713 static int 1714 jme_mediachange(struct ifnet *ifp) 1715 { 1716 int error; 1717 jme_softc_t *sc = ifp->if_softc; 1718 1719 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1720 error = 0; 1721 else if (error != 0) { 1722 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1723 return error; 1724 } 1725 return 0; 1726 } 1727 1728 static void 1729 jme_ticks(void *v) 1730 { 1731 jme_softc_t *sc = v; 1732 int s = splnet(); 1733 1734 /* Tick the MII. */ 1735 mii_tick(&sc->jme_mii); 1736 1737 /* every seconds */ 1738 callout_schedule(&sc->jme_tick_ch, hz); 1739 splx(s); 1740 } 1741 1742 static void 1743 jme_mac_config(jme_softc_t *sc) 1744 { 1745 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1746 struct mii_data *mii = &sc->jme_mii; 1747 1748 ghc = 0; 1749 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1750 rxmac &= ~RXMAC_FC_ENB; 1751 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1752 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1753 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1754 txpause &= ~TXPFC_PAUSE_ENB; 1755 1756 if (mii->mii_media_active & IFM_FDX) { 1757 ghc |= GHC_FULL_DUPLEX; 1758 rxmac &= ~RXMAC_COLL_DET_ENB; 1759 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1760 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1761 TXMAC_FRAME_BURST); 1762 /* Disable retry transmit timer/retry limit. */ 1763 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1764 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1765 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1766 } else { 1767 rxmac |= RXMAC_COLL_DET_ENB; 1768 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1769 /* Enable retry transmit timer/retry limit. */ 1770 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1771 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1772 } 1773 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1774 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1775 case IFM_10_T: 1776 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1777 break; 1778 case IFM_100_TX: 1779 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1780 break; 1781 case IFM_1000_T: 1782 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1783 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1784 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1785 break; 1786 default: 1787 break; 1788 } 1789 if ((sc->jme_flags & JME_FLAG_GIGA) && 1790 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1791 /* 1792 * Workaround occasional packet loss issue of JMC250 A2 1793 * when it runs on half-duplex media. 1794 */ 1795 #ifdef JMEDEBUG 1796 printf("JME250 A2 workaround\n"); 1797 #endif 1798 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1799 JME_GPREG1); 1800 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1801 gpreg &= ~GPREG1_HDPX_FIX; 1802 else 1803 gpreg |= GPREG1_HDPX_FIX; 1804 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1805 JME_GPREG1, gpreg); 1806 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1807 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1808 /* Extend interface FIFO depth. */ 1809 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1810 0x1B, 0x0000); 1811 } else { 1812 /* Select default interface FIFO depth. */ 1813 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1814 0x1B, 0x0004); 1815 } 1816 } 1817 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1818 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1819 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1820 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1821 } 1822 1823 static void 1824 jme_set_filter(jme_softc_t *sc) 1825 { 1826 struct ethercom *ec = &sc->jme_ec; 1827 struct ifnet *ifp = &sc->jme_if; 1828 struct ether_multistep step; 1829 struct ether_multi *enm; 1830 uint32_t hash[2] = {0, 0}; 1831 int i; 1832 uint32_t rxcfg; 1833 1834 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1835 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1836 RXMAC_ALLMULTI); 1837 /* Always accept frames destined to our station address. */ 1838 rxcfg |= RXMAC_UNICAST; 1839 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1840 rxcfg |= RXMAC_BROADCAST; 1841 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1842 if ((ifp->if_flags & IFF_PROMISC) != 0) 1843 rxcfg |= RXMAC_PROMISC; 1844 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1845 rxcfg |= RXMAC_ALLMULTI; 1846 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1847 JME_MAR0, 0xFFFFFFFF); 1848 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1849 JME_MAR1, 0xFFFFFFFF); 1850 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1851 JME_RXMAC, rxcfg); 1852 return; 1853 } 1854 /* 1855 * Set up the multicast address filter by passing all multicast 1856 * addresses through a CRC generator, and then using the low-order 1857 * 6 bits as an index into the 64 bit multicast hash table. The 1858 * high order bits select the register, while the rest of the bits 1859 * select the bit within the register. 1860 */ 1861 rxcfg |= RXMAC_MULTICAST; 1862 memset(hash, 0, sizeof(hash)); 1863 1864 ETHER_LOCK(ec); 1865 ETHER_FIRST_MULTI(step, ec, enm); 1866 while (enm != NULL) { 1867 #ifdef JEMDBUG 1868 printf("%s: addrs %s %s\n", __func__, 1869 ether_sprintf(enm->enm_addrlo), 1870 ether_sprintf(enm->enm_addrhi)); 1871 #endif 1872 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1873 i = ether_crc32_be(enm->enm_addrlo, 6); 1874 /* Just want the 6 least significant bits. */ 1875 i &= 0x3f; 1876 hash[i / 32] |= 1 << (i%32); 1877 } else { 1878 hash[0] = hash[1] = 0xffffffff; 1879 sc->jme_if.if_flags |= IFF_ALLMULTI; 1880 break; 1881 } 1882 ETHER_NEXT_MULTI(step, enm); 1883 } 1884 ETHER_UNLOCK(ec); 1885 #ifdef JMEDEBUG 1886 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1887 #endif 1888 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1889 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1890 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1891 } 1892 1893 #if 0 1894 static int 1895 jme_multicast_hash(uint8_t *a) 1896 { 1897 int hash; 1898 1899 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1900 #define xor8(a,b,c,d,e,f,g,h) \ 1901 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1902 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1903 1904 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1905 DA(a,36), DA(a,42)); 1906 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1907 DA(a,37), DA(a,43)) << 1; 1908 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1909 DA(a,38), DA(a,44)) << 2; 1910 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1911 DA(a,39), DA(a,45)) << 3; 1912 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1913 DA(a,40), DA(a,46)) << 4; 1914 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1915 DA(a,41), DA(a,47)) << 5; 1916 1917 return hash; 1918 } 1919 #endif 1920 1921 static int 1922 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1923 { 1924 uint32_t reg; 1925 int i; 1926 1927 *val = 0; 1928 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1929 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1930 JME_SMBCSR); 1931 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1932 break; 1933 delay(10); 1934 } 1935 1936 if (i == 0) { 1937 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1938 return (ETIMEDOUT); 1939 } 1940 1941 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1942 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1943 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1944 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1945 delay(10); 1946 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1947 JME_SMBINTF); 1948 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1949 break; 1950 } 1951 1952 if (i == 0) { 1953 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1954 return (ETIMEDOUT); 1955 } 1956 1957 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1958 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1959 return (0); 1960 } 1961 1962 1963 static int 1964 jme_eeprom_macaddr(struct jme_softc *sc) 1965 { 1966 uint8_t eaddr[ETHER_ADDR_LEN]; 1967 uint8_t fup, reg, val; 1968 uint32_t offset; 1969 int match; 1970 1971 offset = 0; 1972 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1973 fup != JME_EEPROM_SIG0) 1974 return (ENOENT); 1975 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1976 fup != JME_EEPROM_SIG1) 1977 return (ENOENT); 1978 match = 0; 1979 do { 1980 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 1981 break; 1982 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 1983 == (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 1984 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 1985 break; 1986 if (reg >= JME_PAR0 && 1987 reg < JME_PAR0 + ETHER_ADDR_LEN) { 1988 if (jme_eeprom_read_byte(sc, offset + 2, 1989 &val) != 0) 1990 break; 1991 eaddr[reg - JME_PAR0] = val; 1992 match++; 1993 } 1994 } 1995 if (fup & JME_EEPROM_DESC_END) 1996 break; 1997 1998 /* Try next eeprom descriptor. */ 1999 offset += JME_EEPROM_DESC_BYTES; 2000 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2001 2002 if (match == ETHER_ADDR_LEN) { 2003 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2004 return (0); 2005 } 2006 2007 return (ENOENT); 2008 } 2009 2010 static int 2011 jme_reg_macaddr(struct jme_softc *sc) 2012 { 2013 uint32_t par0, par1; 2014 2015 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2016 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2017 par1 &= 0xffff; 2018 if ((par0 == 0 && par1 == 0) || 2019 (par0 == 0xffffffff && par1 == 0xffff)) { 2020 return (ENOENT); 2021 } else { 2022 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2023 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2024 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2025 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2026 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2027 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2028 } 2029 return (0); 2030 } 2031 2032 /* 2033 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2034 * set up in jme_pci_attach() 2035 */ 2036 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2037 { 2038 int rc; 2039 const struct sysctlnode *node; 2040 2041 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2042 0, CTLTYPE_NODE, "jme", 2043 SYSCTL_DESCR("jme interface controls"), 2044 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2045 goto err; 2046 } 2047 2048 jme_root_num = node->sysctl_num; 2049 return; 2050 2051 err: 2052 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2053 } 2054 2055 static int 2056 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2057 { 2058 int error, t; 2059 struct sysctlnode node; 2060 struct jme_softc *sc; 2061 uint32_t reg; 2062 2063 node = *rnode; 2064 sc = node.sysctl_data; 2065 t = sc->jme_intrxto; 2066 node.sysctl_data = &t; 2067 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2068 if (error || newp == NULL) 2069 return error; 2070 2071 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2072 return EINVAL; 2073 2074 /* 2075 * update the softc with sysctl-changed value, and mark 2076 * for hardware update 2077 */ 2078 sc->jme_intrxto = t; 2079 /* Configure Rx queue 0 packet completion coalescing. */ 2080 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2081 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2082 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2083 return 0; 2084 } 2085 2086 static int 2087 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2088 { 2089 int error, t; 2090 struct sysctlnode node; 2091 struct jme_softc *sc; 2092 uint32_t reg; 2093 2094 node = *rnode; 2095 sc = node.sysctl_data; 2096 t = sc->jme_intrxct; 2097 node.sysctl_data = &t; 2098 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2099 if (error || newp == NULL) 2100 return error; 2101 2102 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2103 return EINVAL; 2104 2105 /* 2106 * update the softc with sysctl-changed value, and mark 2107 * for hardware update 2108 */ 2109 sc->jme_intrxct = t; 2110 /* Configure Rx queue 0 packet completion coalescing. */ 2111 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2112 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2113 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2114 return 0; 2115 } 2116 2117 static int 2118 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2119 { 2120 int error, t; 2121 struct sysctlnode node; 2122 struct jme_softc *sc; 2123 uint32_t reg; 2124 2125 node = *rnode; 2126 sc = node.sysctl_data; 2127 t = sc->jme_inttxto; 2128 node.sysctl_data = &t; 2129 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2130 if (error || newp == NULL) 2131 return error; 2132 2133 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2134 return EINVAL; 2135 2136 /* 2137 * update the softc with sysctl-changed value, and mark 2138 * for hardware update 2139 */ 2140 sc->jme_inttxto = t; 2141 /* Configure Tx queue 0 packet completion coalescing. */ 2142 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2143 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2144 reg |= PCCTX_COAL_TXQ0; 2145 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2146 return 0; 2147 } 2148 2149 static int 2150 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2151 { 2152 int error, t; 2153 struct sysctlnode node; 2154 struct jme_softc *sc; 2155 uint32_t reg; 2156 2157 node = *rnode; 2158 sc = node.sysctl_data; 2159 t = sc->jme_inttxct; 2160 node.sysctl_data = &t; 2161 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2162 if (error || newp == NULL) 2163 return error; 2164 2165 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2166 return EINVAL; 2167 2168 /* 2169 * update the softc with sysctl-changed value, and mark 2170 * for hardware update 2171 */ 2172 sc->jme_inttxct = t; 2173 /* Configure Tx queue 0 packet completion coalescing. */ 2174 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2175 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2176 reg |= PCCTX_COAL_TXQ0; 2177 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2178 return 0; 2179 } 2180