1 /* $NetBSD: if_jme.c,v 1.11 2009/09/27 12:52:59 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice unmodified, this list of conditions, and the following 41 * disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 */ 58 59 60 /* 61 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 62 * Ethernet Controllers. 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.11 2009/09/27 12:52:59 tsutsui Exp $"); 67 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/mbuf.h> 72 #include <sys/protosw.h> 73 #include <sys/socket.h> 74 #include <sys/ioctl.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 79 #include <sys/device.h> 80 #include <sys/syslog.h> 81 #include <sys/sysctl.h> 82 83 #include <net/if.h> 84 #if defined(SIOCSIFMEDIA) 85 #include <net/if_media.h> 86 #endif 87 #include <net/if_types.h> 88 #include <net/if_dl.h> 89 #include <net/route.h> 90 #include <net/netisr.h> 91 92 #include "bpfilter.h" 93 #if NBPFILTER > 0 94 #include <net/bpf.h> 95 #include <net/bpfdesc.h> 96 #endif 97 98 #include "rnd.h" 99 #if NRND > 0 100 #include <sys/rnd.h> 101 #endif 102 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/ip.h> 106 107 #ifdef INET 108 #include <netinet/in_var.h> 109 #endif 110 111 #include <netinet/tcp.h> 112 113 #include <net/if_ether.h> 114 #include <uvm/uvm_extern.h> 115 #if defined(INET) 116 #include <netinet/if_inarp.h> 117 #endif 118 119 #include <sys/bus.h> 120 #include <sys/intr.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 #include <dev/pci/if_jmereg.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 struct jme_product_desc { 131 u_int32_t jme_product; 132 const char *jme_desc; 133 }; 134 135 /* number of entries in transmit and receive rings */ 136 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 137 138 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 139 140 /* Water mark to kick reclaiming Tx buffers. */ 141 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 142 143 144 struct jme_softc { 145 device_t jme_dev; /* base device */ 146 bus_space_tag_t jme_bt_mac; 147 bus_space_handle_t jme_bh_mac; /* Mac registers */ 148 bus_space_tag_t jme_bt_phy; 149 bus_space_handle_t jme_bh_phy; /* PHY registers */ 150 bus_space_tag_t jme_bt_misc; 151 bus_space_handle_t jme_bh_misc; /* Misc registers */ 152 bus_dma_tag_t jme_dmatag; 153 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 154 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 155 struct jme_desc* jme_txring; /* transmit ring */ 156 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 157 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 158 int jme_tx_cons; /* transmit ring consumer */ 159 int jme_tx_prod; /* transmit ring producer */ 160 int jme_tx_cnt; /* transmit ring active count */ 161 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 162 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 163 struct jme_desc* jme_rxring; /* receive ring */ 164 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 165 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 166 int jme_rx_cons; /* receive ring consumer */ 167 int jme_rx_prod; /* receive ring producer */ 168 void* jme_ih; /* our interrupt */ 169 struct ethercom jme_ec; 170 struct callout jme_tick_ch; /* tick callout */ 171 u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 172 u_int8_t jme_phyaddr; /* address of integrated phy */ 173 u_int8_t jme_chip_rev; /* chip revision */ 174 u_int8_t jme_rev; /* PCI revision */ 175 mii_data_t jme_mii; /* mii bus */ 176 u_int32_t jme_flags; /* device features, see below */ 177 uint32_t jme_txcsr; /* TX config register */ 178 uint32_t jme_rxcsr; /* RX config register */ 179 #if NRND > 0 180 rndsource_element_t rnd_source; 181 #endif 182 /* interrupt coalition parameters */ 183 struct sysctllog *jme_clog; 184 int jme_intrxto; /* interrupt RX timeout */ 185 int jme_intrxct; /* interrupt RX packets counter */ 186 int jme_inttxto; /* interrupt TX timeout */ 187 int jme_inttxct; /* interrupt TX packets counter */ 188 }; 189 190 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 191 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 192 193 194 #define jme_if jme_ec.ec_if 195 #define jme_bpf jme_if.if_bpf 196 197 typedef struct jme_softc jme_softc_t; 198 typedef u_long ioctl_cmd_t; 199 200 static int jme_pci_match(device_t, cfdata_t, void *); 201 static void jme_pci_attach(device_t, device_t, void *); 202 static void jme_intr_rx(jme_softc_t *); 203 static int jme_intr(void *); 204 205 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 206 static int jme_mediachange(struct ifnet *); 207 static void jme_ifwatchdog(struct ifnet *); 208 static bool jme_shutdown(device_t, int); 209 210 static void jme_txeof(struct jme_softc *); 211 static void jme_ifstart(struct ifnet *); 212 static void jme_reset(jme_softc_t *); 213 static int jme_ifinit(struct ifnet *); 214 static int jme_init(struct ifnet *, int); 215 static void jme_stop(struct ifnet *, int); 216 // static void jme_restart(void *); 217 static void jme_ticks(void *); 218 static void jme_mac_config(jme_softc_t *); 219 static void jme_set_filter(jme_softc_t *); 220 221 int jme_mii_read(device_t, int, int); 222 void jme_mii_write(device_t, int, int, int); 223 void jme_statchg(device_t); 224 225 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 226 static int jme_eeprom_macaddr(struct jme_softc *); 227 228 #define JME_TIMEOUT 1000 229 #define JME_PHY_TIMEOUT 1000 230 #define JME_EEPROM_TIMEOUT 1000 231 232 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 233 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 234 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 235 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 236 static int jme_root_num; 237 238 239 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 240 jme_pci_match, jme_pci_attach, NULL, NULL); 241 242 static const struct jme_product_desc jme_products[] = { 243 { PCI_PRODUCT_JMICRON_JMC250, 244 "JMicron JMC250 Gigabit Ethernet Controller" }, 245 { PCI_PRODUCT_JMICRON_JMC260, 246 "JMicron JMC260 Gigabit Ethernet Controller" }, 247 { 0, NULL }, 248 }; 249 250 static const struct jme_product_desc *jme_lookup_product(uint32_t); 251 252 static const struct jme_product_desc * 253 jme_lookup_product(uint32_t id) 254 { 255 const struct jme_product_desc *jp; 256 257 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 258 if (PCI_PRODUCT(id) == jp->jme_product) 259 return jp; 260 261 return NULL; 262 } 263 264 static int 265 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 266 { 267 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 268 269 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 270 return 0; 271 272 if (jme_lookup_product(pa->pa_id) != NULL) 273 return 1; 274 275 return 0; 276 } 277 278 static void 279 jme_pci_attach(device_t parent, device_t self, void *aux) 280 { 281 jme_softc_t *sc = device_private(self); 282 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 283 const struct jme_product_desc *jp; 284 struct ifnet * const ifp = &sc->jme_if; 285 bus_space_tag_t iot1, iot2, memt; 286 bus_space_handle_t ioh1, ioh2, memh; 287 bus_size_t size, size2; 288 pci_intr_handle_t intrhandle; 289 const char *intrstr; 290 pcireg_t csr; 291 int nsegs, i; 292 const struct sysctlnode *node; 293 int jme_nodenum; 294 295 sc->jme_dev = self; 296 aprint_normal("\n"); 297 callout_init(&sc->jme_tick_ch, 0); 298 299 jp = jme_lookup_product(pa->pa_id); 300 if (jp == NULL) 301 panic("jme_pci_attach: impossible"); 302 303 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 304 sc->jme_flags = JME_FLAG_GIGA; 305 306 /* 307 * Map the card space. Try Mem first. 308 */ 309 if (pci_mapreg_map(pa, JME_PCI_BAR0, 310 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 311 0, &memt, &memh, NULL, &size) == 0) { 312 sc->jme_bt_mac = memt; 313 sc->jme_bh_mac = memh; 314 sc->jme_bt_phy = memt; 315 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 316 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 317 aprint_error_dev(self, "can't subregion PHY space\n"); 318 bus_space_unmap(memt, memh, size); 319 return; 320 } 321 sc->jme_bt_misc = memt; 322 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 323 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 324 aprint_error_dev(self, "can't subregion misc space\n"); 325 bus_space_unmap(memt, memh, size); 326 return; 327 } 328 } else { 329 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 330 0, &iot1, &ioh1, NULL, &size) != 0) { 331 aprint_error_dev(self, "can't map I/O space 1\n"); 332 return; 333 } 334 sc->jme_bt_mac = iot1; 335 sc->jme_bh_mac = ioh1; 336 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 337 0, &iot2, &ioh2, NULL, &size2) != 0) { 338 aprint_error_dev(self, "can't map I/O space 2\n"); 339 bus_space_unmap(iot1, ioh1, size); 340 return; 341 } 342 sc->jme_bt_phy = iot2; 343 sc->jme_bh_phy = ioh2; 344 sc->jme_bt_misc = iot2; 345 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 346 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 347 aprint_error_dev(self, "can't subregion misc space\n"); 348 bus_space_unmap(iot1, ioh1, size); 349 bus_space_unmap(iot2, ioh2, size2); 350 return; 351 } 352 } 353 354 if (pci_dma64_available(pa)) 355 sc->jme_dmatag = pa->pa_dmat64; 356 else 357 sc->jme_dmatag = pa->pa_dmat; 358 359 /* Enable the device. */ 360 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 361 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 362 csr | PCI_COMMAND_MASTER_ENABLE); 363 364 aprint_normal_dev(self, "%s\n", jp->jme_desc); 365 366 sc->jme_rev = PCI_REVISION(pa->pa_class); 367 368 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 369 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 370 CHIPMODE_NOT_FPGA) 371 sc->jme_flags |= JME_FLAG_FPGA; 372 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 373 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 374 "0x%x", sc->jme_rev, sc->jme_chip_rev); 375 if (sc->jme_flags & JME_FLAG_FPGA) 376 aprint_verbose(" FPGA revision: 0x%x", 377 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 378 aprint_verbose("\n"); 379 380 /* 381 * Save PHY address. 382 * Integrated JR0211 has fixed PHY address whereas FPGA version 383 * requires PHY probing to get correct PHY address. 384 */ 385 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 386 sc->jme_phyaddr = 387 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 388 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 389 } else 390 sc->jme_phyaddr = 0; 391 392 393 jme_reset(sc); 394 395 /* read mac addr */ 396 if (jme_eeprom_macaddr(sc)) { 397 aprint_error_dev(self, "error reading Ethernet address\n"); 398 /* return; */ 399 } 400 aprint_normal_dev(self, "Ethernet address %s\n", 401 ether_sprintf(sc->jme_enaddr)); 402 403 /* Map and establish interrupts */ 404 if (pci_intr_map(pa, &intrhandle)) { 405 aprint_error_dev(self, "couldn't map interrupt\n"); 406 return; 407 } 408 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 409 sc->jme_if.if_softc = sc; 410 sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 411 jme_intr, sc); 412 if (sc->jme_ih == NULL) { 413 aprint_error_dev(self, "couldn't establish interrupt"); 414 if (intrstr != NULL) 415 aprint_error(" at %s", intrstr); 416 aprint_error("\n"); 417 return; 418 } 419 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 420 421 /* allocate and map DMA-safe memory for transmit ring */ 422 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 423 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 424 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 425 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 426 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 427 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 428 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 429 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 430 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 431 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 432 return; 433 } 434 /* allocate and map DMA-safe memory for receive ring */ 435 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 436 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 437 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 438 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 439 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 440 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 441 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 442 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 443 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 444 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 445 return; 446 } 447 for (i = 0; i < JME_NBUFS; i++) { 448 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 449 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 450 JME_NBUFS, JME_MAX_TX_LEN, 0, BUS_DMA_NOWAIT, 451 &sc->jme_txmbufm[i]) != 0) { 452 aprint_error_dev(self, "can't allocate DMA TX map\n"); 453 return; 454 } 455 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 456 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT, 457 &sc->jme_rxmbufm[i]) != 0) { 458 aprint_error_dev(self, "can't allocate DMA RX map\n"); 459 return; 460 } 461 } 462 /* 463 * Initialize our media structures and probe the MII. 464 * 465 * Note that we don't care about the media instance. We 466 * are expecting to have multiple PHYs on the 10/100 cards, 467 * and on those cards we exclude the internal PHY from providing 468 * 10baseT. By ignoring the instance, it allows us to not have 469 * to specify it on the command line when switching media. 470 */ 471 sc->jme_mii.mii_ifp = ifp; 472 sc->jme_mii.mii_readreg = jme_mii_read; 473 sc->jme_mii.mii_writereg = jme_mii_write; 474 sc->jme_mii.mii_statchg = jme_statchg; 475 sc->jme_ec.ec_mii = &sc->jme_mii; 476 ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange, 477 ether_mediastatus); 478 mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY, 479 MII_OFFSET_ANY, 0); 480 if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) { 481 ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 482 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE); 483 } else 484 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO); 485 486 /* 487 * We can support 802.1Q VLAN-sized frames. 488 */ 489 sc->jme_ec.ec_capabilities |= 490 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 491 492 if (sc->jme_flags & JME_FLAG_GIGA) 493 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 494 495 496 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 497 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 498 ifp->if_ioctl = jme_ifioctl; 499 ifp->if_start = jme_ifstart; 500 ifp->if_watchdog = jme_ifwatchdog; 501 ifp->if_init = jme_ifinit; 502 ifp->if_stop = jme_stop; 503 ifp->if_timer = 0; 504 ifp->if_capabilities |= 505 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 506 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 507 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 508 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 509 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 510 IFCAP_TSOv4 | IFCAP_TSOv6; 511 IFQ_SET_READY(&ifp->if_snd); 512 if_attach(ifp); 513 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 514 515 /* 516 * Add shutdown hook so that DMA is disabled prior to reboot. 517 */ 518 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 519 pmf_class_network_register(self, ifp); 520 else 521 aprint_error_dev(self, "couldn't establish power handler\n"); 522 523 #if NRND > 0 524 rnd_attach_source(&sc->rnd_source, device_xname(self), 525 RND_TYPE_NET, 0); 526 #endif 527 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 528 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 529 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 530 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 531 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 532 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 533 SYSCTL_DESCR("jme per-controller controls"), 534 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 535 CTL_EOL) != 0) { 536 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 537 return; 538 } 539 jme_nodenum = node->sysctl_num; 540 541 /* interrupt moderation sysctls */ 542 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 543 CTLFLAG_READWRITE, 544 CTLTYPE_INT, "int_rxto", 545 SYSCTL_DESCR("jme RX interrupt moderation timer"), 546 jme_sysctl_intrxto, 0, sc, 547 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 548 CTL_EOL) != 0) { 549 aprint_normal_dev(sc->jme_dev, 550 "couldn't create int_rxto sysctl node\n"); 551 } 552 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 553 CTLFLAG_READWRITE, 554 CTLTYPE_INT, "int_rxct", 555 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 556 jme_sysctl_intrxct, 0, sc, 557 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 558 CTL_EOL) != 0) { 559 aprint_normal_dev(sc->jme_dev, 560 "couldn't create int_rxct sysctl node\n"); 561 } 562 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 563 CTLFLAG_READWRITE, 564 CTLTYPE_INT, "int_txto", 565 SYSCTL_DESCR("jme TX interrupt moderation timer"), 566 jme_sysctl_inttxto, 0, sc, 567 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 568 CTL_EOL) != 0) { 569 aprint_normal_dev(sc->jme_dev, 570 "couldn't create int_txto sysctl node\n"); 571 } 572 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 573 CTLFLAG_READWRITE, 574 CTLTYPE_INT, "int_txct", 575 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 576 jme_sysctl_inttxct, 0, sc, 577 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 578 CTL_EOL) != 0) { 579 aprint_normal_dev(sc->jme_dev, 580 "couldn't create int_txct sysctl node\n"); 581 } 582 } 583 584 static void 585 jme_stop_rx(jme_softc_t *sc) 586 { 587 uint32_t reg; 588 int i; 589 590 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 591 if ((reg & RXCSR_RX_ENB) == 0) 592 return; 593 reg &= ~RXCSR_RX_ENB; 594 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 595 for (i = JME_TIMEOUT / 10; i > 0; i--) { 596 DELAY(10); 597 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 598 JME_RXCSR) & RXCSR_RX_ENB) == 0) 599 break; 600 } 601 if (i == 0) 602 aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n"); 603 604 } 605 606 static void 607 jme_stop_tx(jme_softc_t *sc) 608 { 609 uint32_t reg; 610 int i; 611 612 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 613 if ((reg & TXCSR_TX_ENB) == 0) 614 return; 615 reg &= ~TXCSR_TX_ENB; 616 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 617 for (i = JME_TIMEOUT / 10; i > 0; i--) { 618 DELAY(10); 619 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 620 JME_TXCSR) & TXCSR_TX_ENB) == 0) 621 break; 622 } 623 if (i == 0) 624 aprint_error_dev(sc->jme_dev, 625 "stopping transmitter timeout!\n"); 626 } 627 628 static void 629 jme_reset(jme_softc_t *sc) 630 { 631 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 632 DELAY(10); 633 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 634 } 635 636 static bool 637 jme_shutdown(device_t self, int howto) 638 { 639 jme_softc_t *sc; 640 struct ifnet *ifp; 641 642 sc = device_private(self); 643 ifp = &sc->jme_if; 644 jme_stop(ifp, 1); 645 646 return true; 647 } 648 649 static void 650 jme_stop(struct ifnet *ifp, int disable) 651 { 652 jme_softc_t *sc = ifp->if_softc; 653 int i; 654 /* Stop receiver, transmitter. */ 655 jme_stop_rx(sc); 656 jme_stop_tx(sc); 657 /* free receive mbufs */ 658 for (i = 0; i < JME_NBUFS; i++) { 659 if (sc->jme_rxmbuf[i]) { 660 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 661 m_freem(sc->jme_rxmbuf[i]); 662 } 663 sc->jme_rxmbuf[i] = NULL; 664 } 665 /* process completed transmits */ 666 jme_txeof(sc); 667 /* free abort pending transmits */ 668 for (i = 0; i < JME_NBUFS; i++) { 669 if (sc->jme_txmbuf[i]) { 670 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 671 m_freem(sc->jme_txmbuf[i]); 672 sc->jme_txmbuf[i] = NULL; 673 } 674 } 675 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 676 ifp->if_timer = 0; 677 } 678 679 #if 0 680 static void 681 jme_restart(void *v) 682 { 683 684 jme_init(v); 685 } 686 #endif 687 688 static int 689 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 690 { 691 int error; 692 bus_dmamap_t map; 693 int i = sc->jme_rx_prod; 694 695 if (sc->jme_rxmbuf[i] != NULL) { 696 aprint_error_dev(sc->jme_dev, 697 "mbuf already here: rxprod %d rxcons %d\n", 698 sc->jme_rx_prod, sc->jme_rx_cons); 699 if (m) 700 m_freem(m); 701 return EINVAL; 702 } 703 704 if (m == NULL) { 705 sc->jme_rxmbuf[i] = NULL; 706 MGETHDR(m, M_DONTWAIT, MT_DATA); 707 if (m == NULL) 708 return (ENOBUFS); 709 MCLGET(m, M_DONTWAIT); 710 if ((m->m_flags & M_EXT) == 0) { 711 m_freem(m); 712 return (ENOBUFS); 713 } 714 } 715 map = sc->jme_rxmbufm[i]; 716 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 717 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 718 BUS_DMA_READ|BUS_DMA_NOWAIT); 719 if (error) { 720 sc->jme_rxmbuf[i] = NULL; 721 aprint_error_dev(sc->jme_dev, 722 "unable to load rx DMA map %d, error = %d\n", 723 i, error); 724 m_freem(m); 725 return (error); 726 } 727 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 728 BUS_DMASYNC_PREREAD); 729 730 sc->jme_rxmbuf[i] = m; 731 732 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 733 sc->jme_rxring[i].addr_lo = 734 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 735 sc->jme_rxring[i].addr_hi = 736 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 737 sc->jme_rxring[i].flags = 738 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 739 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 740 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 741 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 742 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 743 return (0); 744 } 745 746 static int 747 jme_ifinit(struct ifnet *ifp) 748 { 749 return jme_init(ifp, 1); 750 } 751 752 static int 753 jme_init(struct ifnet *ifp, int do_ifinit) 754 { 755 jme_softc_t *sc = ifp->if_softc; 756 int i, s; 757 uint8_t eaddr[ETHER_ADDR_LEN]; 758 uint32_t reg; 759 760 s = splnet(); 761 /* cancel any pending IO */ 762 jme_stop(ifp, 1); 763 jme_reset(sc); 764 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 765 splx(s); 766 return 0; 767 } 768 /* allocate receive ring */ 769 sc->jme_rx_prod = 0; 770 for (i = 0; i < JME_NBUFS; i++) { 771 if (jme_add_rxbuf(sc, NULL) < 0) { 772 aprint_error_dev(sc->jme_dev, 773 "can't allocate rx mbuf\n"); 774 for (i--; i >= 0; i--) { 775 bus_dmamap_unload(sc->jme_dmatag, 776 sc->jme_rxmbufm[i]); 777 m_freem(sc->jme_rxmbuf[i]); 778 sc->jme_rxmbuf[i] = NULL; 779 } 780 splx(s); 781 return ENOMEM; 782 } 783 } 784 /* init TX ring */ 785 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 786 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 787 0, JME_NBUFS * sizeof(struct jme_desc), 788 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 789 for (i = 0; i < JME_NBUFS; i++) 790 sc->jme_txmbuf[i] = NULL; 791 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 792 793 /* Reprogram the station address. */ 794 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 795 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 796 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 797 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 798 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 799 800 /* 801 * Configure Tx queue. 802 * Tx priority queue weight value : 0 803 * Tx FIFO threshold for processing next packet : 16QW 804 * Maximum Tx DMA length : 512 805 * Allow Tx DMA burst. 806 */ 807 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 808 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 809 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 810 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 811 sc->jme_txcsr |= TXCSR_DMA_BURST; 812 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 813 JME_TXCSR, sc->jme_txcsr); 814 815 /* Set Tx descriptor counter. */ 816 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 817 JME_TXQDC, JME_NBUFS); 818 819 /* Set Tx ring address to the hardware. */ 820 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 821 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 822 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 823 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 824 825 /* Configure TxMAC parameters. */ 826 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 827 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 828 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 829 830 /* 831 * Configure Rx queue. 832 * FIFO full threshold for transmitting Tx pause packet : 128T 833 * FIFO threshold for processing next packet : 128QW 834 * Rx queue 0 select 835 * Max Rx DMA length : 128 836 * Rx descriptor retry : 32 837 * Rx descriptor retry time gap : 256ns 838 * Don't receive runt/bad frame. 839 */ 840 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 841 /* 842 * Since Rx FIFO size is 4K bytes, receiving frames larger 843 * than 4K bytes will suffer from Rx FIFO overruns. So 844 * decrease FIFO threshold to reduce the FIFO overruns for 845 * frames larger than 4000 bytes. 846 * For best performance of standard MTU sized frames use 847 * maximum allowable FIFO threshold, 128QW. 848 */ 849 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 850 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 851 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 852 else 853 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 854 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 855 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 856 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 857 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 858 JME_RXCSR, sc->jme_rxcsr); 859 860 /* Set Rx descriptor counter. */ 861 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 862 JME_RXQDC, JME_NBUFS); 863 864 /* Set Rx ring address to the hardware. */ 865 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 866 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 867 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 868 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 869 870 /* Clear receive filter. */ 871 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 872 /* Set up the receive filter. */ 873 jme_set_filter(sc); 874 875 /* 876 * Disable all WOL bits as WOL can interfere normal Rx 877 * operation. Also clear WOL detection status bits. 878 */ 879 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 880 reg &= ~PMCS_WOL_ENB_MASK; 881 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 882 883 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 884 /* 885 * Pad 10bytes right before received frame. This will greatly 886 * help Rx performance on strict-alignment architectures as 887 * it does not need to copy the frame to align the payload. 888 */ 889 reg |= RXMAC_PAD_10BYTES; 890 if ((ifp->if_capenable & 891 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx| 892 IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0) 893 reg |= RXMAC_CSUM_ENB; 894 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 895 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 896 897 /* Configure general purpose reg0 */ 898 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 899 reg &= ~GPREG0_PCC_UNIT_MASK; 900 /* Set PCC timer resolution to micro-seconds unit. */ 901 reg |= GPREG0_PCC_UNIT_US; 902 /* 903 * Disable all shadow register posting as we have to read 904 * JME_INTR_STATUS register in jme_int_task. Also it seems 905 * that it's hard to synchronize interrupt status between 906 * hardware and software with shadow posting due to 907 * requirements of bus_dmamap_sync(9). 908 */ 909 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 910 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 911 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 912 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 913 /* Disable posting of DW0. */ 914 reg &= ~GPREG0_POST_DW0_ENB; 915 /* Clear PME message. */ 916 reg &= ~GPREG0_PME_ENB; 917 /* Set PHY address. */ 918 reg &= ~GPREG0_PHY_ADDR_MASK; 919 reg |= sc->jme_phyaddr; 920 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 921 922 /* Configure Tx queue 0 packet completion coalescing. */ 923 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 924 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 925 reg |= PCCTX_COAL_TXQ0; 926 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 927 928 /* Configure Rx queue 0 packet completion coalescing. */ 929 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 930 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 931 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 932 933 /* Disable Timers */ 934 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 935 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 936 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 937 938 /* Configure retry transmit period, retry limit value. */ 939 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 940 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 941 TXTRHD_RT_PERIOD_MASK) | 942 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 943 TXTRHD_RT_LIMIT_SHIFT)); 944 945 /* Disable RSS. */ 946 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 947 JME_RSSC, RSSC_DIS_RSS); 948 949 /* Initialize the interrupt mask. */ 950 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 951 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 952 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 953 JME_INTR_STATUS, 0xFFFFFFFF); 954 955 /* set media, if not already handling a media change */ 956 if (do_ifinit) { 957 int error; 958 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 959 error = 0; 960 else if (error != 0) { 961 aprint_error_dev(sc->jme_dev, "could not set media\n"); 962 return error; 963 } 964 } 965 966 /* Program MAC with resolved speed/duplex/flow-control. */ 967 jme_mac_config(sc); 968 969 /* Start receiver/transmitter. */ 970 sc->jme_rx_cons = 0; 971 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 972 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 973 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 974 sc->jme_txcsr | TXCSR_TX_ENB); 975 976 /* start ticks calls */ 977 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 978 sc->jme_if.if_flags |= IFF_RUNNING; 979 sc->jme_if.if_flags &= ~IFF_OACTIVE; 980 splx(s); 981 return 0; 982 } 983 984 985 int 986 jme_mii_read(device_t self, int phy, int reg) 987 { 988 struct jme_softc *sc = device_private(self); 989 int val, i; 990 991 /* For FPGA version, PHY address 0 should be ignored. */ 992 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 993 if (phy == 0) 994 return (0); 995 } else { 996 if (sc->jme_phyaddr != phy) 997 return (0); 998 } 999 1000 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1001 SMI_OP_READ | SMI_OP_EXECUTE | 1002 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1003 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1004 delay(10); 1005 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1006 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1007 break; 1008 } 1009 1010 if (i == 0) { 1011 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 1012 return (0); 1013 } 1014 1015 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 1016 } 1017 1018 void 1019 jme_mii_write(device_t self, int phy, int reg, int val) 1020 { 1021 struct jme_softc *sc = device_private(self); 1022 int i; 1023 1024 /* For FPGA version, PHY address 0 should be ignored. */ 1025 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1026 if (phy == 0) 1027 return; 1028 } else { 1029 if (sc->jme_phyaddr != phy) 1030 return; 1031 } 1032 1033 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1034 SMI_OP_WRITE | SMI_OP_EXECUTE | 1035 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1036 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1037 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1038 delay(10); 1039 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1040 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1041 break; 1042 } 1043 1044 if (i == 0) 1045 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1046 1047 return; 1048 } 1049 1050 void 1051 jme_statchg(device_t self) 1052 { 1053 jme_softc_t *sc = device_private(self); 1054 struct ifnet *ifp = &sc->jme_if; 1055 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) 1056 jme_init(ifp, 0); 1057 } 1058 1059 static void 1060 jme_intr_rx(jme_softc_t *sc) { 1061 struct mbuf *m, *mhead; 1062 struct ifnet *ifp = &sc->jme_if; 1063 uint32_t flags, buflen; 1064 int i, ipackets, nsegs, seg, error; 1065 struct jme_desc *desc; 1066 1067 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1068 sizeof(struct jme_desc) * JME_NBUFS, 1069 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1070 #ifdef JMEDEBUG_RX 1071 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1072 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1073 #endif 1074 ipackets = 0; 1075 while((le32toh(sc->jme_rxring[ sc->jme_rx_cons].flags) & JME_RD_OWN) 1076 == 0) { 1077 i = sc->jme_rx_cons; 1078 desc = &sc->jme_rxring[i]; 1079 #ifdef JMEDEBUG_RX 1080 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1081 i, le32toh(desc->flags), le32toh(desc->buflen)); 1082 #endif 1083 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1084 break; 1085 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmbufm[i], 0, 1086 sc->jme_rxmbufm[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); 1087 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 1088 1089 buflen = le32toh(desc->buflen); 1090 nsegs = JME_RX_NSEGS(buflen); 1091 flags = le32toh(desc->flags); 1092 if ((buflen & JME_RX_ERR_STAT) != 0 || 1093 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1094 JME_RX_BYTES(buflen) > 1095 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1096 #ifdef JMEDEBUG_RX 1097 printf("rx error flags 0x%x buflen 0x%x\n", 1098 flags, buflen); 1099 #endif 1100 ifp->if_ierrors++; 1101 /* reuse the mbufs */ 1102 for (seg = 0; seg < nsegs; seg++) { 1103 m = sc->jme_rxmbuf[i]; 1104 sc->jme_rxmbuf[i] = NULL; 1105 if ((error = jme_add_rxbuf(sc, m)) != 0) 1106 aprint_error_dev(sc->jme_dev, 1107 "can't reuse mbuf: %d\n", error); 1108 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1109 i = sc->jme_rx_cons; 1110 } 1111 continue; 1112 } 1113 /* receive this packet */ 1114 mhead = m = sc->jme_rxmbuf[i]; 1115 sc->jme_rxmbuf[i] = NULL; 1116 /* add a new buffer to chain */ 1117 if (jme_add_rxbuf(sc, NULL) == ENOBUFS) { 1118 for (seg = 0; seg < nsegs; seg++) { 1119 m = sc->jme_rxmbuf[i]; 1120 sc->jme_rxmbuf[i] = NULL; 1121 if ((error = jme_add_rxbuf(sc, m)) != 0) 1122 aprint_error_dev(sc->jme_dev, 1123 "can't reuse mbuf: %d\n", error); 1124 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1125 i = sc->jme_rx_cons; 1126 } 1127 ifp->if_ierrors++; 1128 continue; 1129 } 1130 1131 /* build mbuf chain: head, then remaining segments */ 1132 m->m_pkthdr.rcvif = ifp; 1133 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1134 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1135 m->m_pkthdr.len; 1136 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1137 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1138 for (seg = 1; seg < nsegs; seg++) { 1139 i = sc->jme_rx_cons; 1140 m = sc->jme_rxmbuf[i]; 1141 sc->jme_rxmbuf[i] = NULL; 1142 (void)jme_add_rxbuf(sc, NULL); 1143 m->m_flags &= ~M_PKTHDR; 1144 m_cat(mhead, m); 1145 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1146 } 1147 /* and adjust last mbuf's size */ 1148 if (nsegs > 1) { 1149 m->m_len = 1150 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1151 } 1152 ifp->if_ipackets++; 1153 ipackets++; 1154 #if NBPFILTER > 0 1155 if (ifp->if_bpf) 1156 bpf_mtap(ifp->if_bpf, mhead); 1157 #endif /* NBPFILTER > 0 */ 1158 1159 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1160 (flags & JME_RD_IPV4)) { 1161 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1162 if (!(flags & JME_RD_IPCSUM)) 1163 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1164 } 1165 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1166 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1167 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1168 if (!(flags & JME_RD_TCPCSUM)) 1169 mhead->m_pkthdr.csum_flags |= 1170 M_CSUM_TCP_UDP_BAD; 1171 } 1172 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1173 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1174 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1175 if (!(flags & JME_RD_UDPCSUM)) 1176 mhead->m_pkthdr.csum_flags |= 1177 M_CSUM_TCP_UDP_BAD; 1178 } 1179 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1180 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1181 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1182 if (!(flags & JME_RD_TCPCSUM)) 1183 mhead->m_pkthdr.csum_flags |= 1184 M_CSUM_TCP_UDP_BAD; 1185 } 1186 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1187 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1188 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1189 if (!(flags & JME_RD_UDPCSUM)) 1190 mhead->m_pkthdr.csum_flags |= 1191 M_CSUM_TCP_UDP_BAD; 1192 } 1193 if (flags & JME_RD_VLAN_TAG) { 1194 /* pass to vlan_input() */ 1195 VLAN_INPUT_TAG(ifp, mhead, 1196 (flags & JME_RD_VLAN_MASK), continue); 1197 } 1198 (*ifp->if_input)(ifp, mhead); 1199 } 1200 #if NRND > 0 1201 if (ipackets && RND_ENABLED(&sc->rnd_source)) 1202 rnd_add_uint32(&sc->rnd_source, ipackets); 1203 #endif /* NRND > 0 */ 1204 1205 } 1206 1207 static int 1208 jme_intr(void *v) 1209 { 1210 jme_softc_t *sc = v; 1211 uint32_t istatus; 1212 1213 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1214 JME_INTR_STATUS); 1215 if (istatus == 0 || istatus == 0xFFFFFFFF) 1216 return 0; 1217 /* Disable interrupts. */ 1218 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1219 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1220 again: 1221 /* and update istatus */ 1222 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1223 JME_INTR_STATUS); 1224 if ((istatus & JME_INTRS_CHECK) == 0) 1225 goto done; 1226 /* Reset PCC counter/timer and Ack interrupts. */ 1227 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1228 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1229 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1230 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1231 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1232 JME_INTR_STATUS, istatus); 1233 1234 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1235 goto done; 1236 #ifdef JMEDEBUG_RX 1237 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1238 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1239 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1240 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1241 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1242 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1243 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1244 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1245 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1246 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1247 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1248 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1249 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1250 #endif 1251 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1252 jme_intr_rx(sc); 1253 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1254 /* 1255 * Notify hardware availability of new Rx 1256 * buffers. 1257 * Reading RXCSR takes very long time under 1258 * heavy load so cache RXCSR value and writes 1259 * the ORed value with the kick command to 1260 * the RXCSR. This saves one register access 1261 * cycle. 1262 */ 1263 sc->jme_rx_cons = 0; 1264 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1265 JME_RXCSR, 1266 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1267 } 1268 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1269 jme_ifstart(&sc->jme_if); 1270 1271 goto again; 1272 1273 done: 1274 /* enable interrupts. */ 1275 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1276 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1277 return 1; 1278 } 1279 1280 1281 static int 1282 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1283 { 1284 struct jme_softc *sc = ifp->if_softc; 1285 int s, error; 1286 struct ifreq *ifr; 1287 struct ifcapreq *ifcr; 1288 1289 s = splnet(); 1290 /* 1291 * we can't support at the same time jumbo frames and 1292 * TX checksums offload/TSO 1293 */ 1294 switch(cmd) { 1295 case SIOCSIFMTU: 1296 ifr = data; 1297 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1298 (ifp->if_capenable & ( 1299 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1300 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1301 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1302 splx(s); 1303 return EINVAL; 1304 } 1305 break; 1306 case SIOCSIFCAP: 1307 ifcr = data; 1308 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1309 (ifcr->ifcr_capenable & ( 1310 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1311 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1312 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1313 splx(s); 1314 return EINVAL; 1315 } 1316 break; 1317 } 1318 1319 error = ether_ioctl(ifp, cmd, data); 1320 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1321 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1322 jme_set_filter(sc); 1323 error = 0; 1324 } else { 1325 error = jme_init(ifp, 0); 1326 } 1327 } 1328 splx(s); 1329 return error; 1330 } 1331 1332 static int 1333 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1334 { 1335 struct jme_desc *txd; 1336 struct jme_desc *desc; 1337 struct mbuf *m; 1338 struct m_tag *mtag; 1339 int error, i, prod, headdsc, nsegs; 1340 uint32_t cflags, tso_segsz; 1341 1342 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){ 1343 /* 1344 * Due to the adherence to NDIS specification JMC250 1345 * assumes upper stack computed TCP pseudo checksum 1346 * without including payload length. This breaks 1347 * checksum offload for TSO case so recompute TCP 1348 * pseudo checksum for JMC250. Hopefully this wouldn't 1349 * be much burden on modern CPUs. 1350 */ 1351 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1352 int iphl = v4 ? 1353 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1354 M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data); 1355 /* 1356 * note: we support vlan offloading, so we should never have 1357 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1358 * right. 1359 */ 1360 int hlen = ETHER_HDR_LEN + iphl; 1361 1362 if (__predict_false((*m_head)->m_len < 1363 (hlen + sizeof(struct tcphdr)))) { 1364 /* 1365 * TCP/IP headers are not in the first mbuf; we need 1366 * to do this the slow and painful way. Let's just 1367 * hope this doesn't happen very often. 1368 */ 1369 struct tcphdr th; 1370 1371 m_copydata((*m_head), hlen, sizeof(th), &th); 1372 if (v4) { 1373 struct ip ip; 1374 1375 m_copydata((*m_head), ETHER_HDR_LEN, 1376 sizeof(ip), &ip); 1377 ip.ip_len = 0; 1378 m_copyback((*m_head), 1379 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1380 sizeof(ip.ip_len), &ip.ip_len); 1381 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1382 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1383 } else { 1384 #if INET6 1385 struct ip6_hdr ip6; 1386 1387 m_copydata((*m_head), ETHER_HDR_LEN, 1388 sizeof(ip6), &ip6); 1389 ip6.ip6_plen = 0; 1390 m_copyback((*m_head), ETHER_HDR_LEN + 1391 offsetof(struct ip6_hdr, ip6_plen), 1392 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1393 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1394 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1395 #endif /* INET6 */ 1396 } 1397 m_copyback((*m_head), 1398 hlen + offsetof(struct tcphdr, th_sum), 1399 sizeof(th.th_sum), &th.th_sum); 1400 1401 hlen += th.th_off << 2; 1402 } else { 1403 /* 1404 * TCP/IP headers are in the first mbuf; we can do 1405 * this the easy way. 1406 */ 1407 struct tcphdr *th; 1408 1409 if (v4) { 1410 struct ip *ip = 1411 (void *)(mtod((*m_head), char *) + 1412 ETHER_HDR_LEN); 1413 th = (void *)(mtod((*m_head), char *) + hlen); 1414 1415 ip->ip_len = 0; 1416 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1417 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1418 } else { 1419 #if INET6 1420 struct ip6_hdr *ip6 = 1421 (void *)(mtod((*m_head), char *) + 1422 ETHER_HDR_LEN); 1423 th = (void *)(mtod((*m_head), char *) + hlen); 1424 1425 ip6->ip6_plen = 0; 1426 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1427 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1428 #endif /* INET6 */ 1429 } 1430 hlen += th->th_off << 2; 1431 } 1432 1433 } 1434 1435 prod = sc->jme_tx_prod; 1436 txd = &sc->jme_txring[prod]; 1437 1438 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1439 *m_head, BUS_DMA_WRITE); 1440 if (error) { 1441 if (error == EFBIG) { 1442 log(LOG_ERR, "%s: Tx packet consumes too many " 1443 "DMA segments, dropping...\n", 1444 device_xname(sc->jme_dev)); 1445 m_freem(*m_head); 1446 m_head = NULL; 1447 } 1448 return (error); 1449 } 1450 /* 1451 * Check descriptor overrun. Leave one free descriptor. 1452 * Since we always use 64bit address mode for transmitting, 1453 * each Tx request requires one more dummy descriptor. 1454 */ 1455 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1456 #ifdef JMEDEBUG_TX 1457 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1458 #endif 1459 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1460 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1461 return (ENOBUFS); 1462 } 1463 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1464 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1465 1466 m = *m_head; 1467 cflags = 0; 1468 tso_segsz = 0; 1469 /* Configure checksum offload and TSO. */ 1470 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) { 1471 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1472 cflags |= JME_TD_TSO; 1473 } else { 1474 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1475 cflags |= JME_TD_IPCSUM; 1476 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0) 1477 cflags |= JME_TD_TCPCSUM; 1478 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0) 1479 cflags |= JME_TD_UDPCSUM; 1480 } 1481 /* Configure VLAN. */ 1482 if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) { 1483 cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); 1484 cflags |= JME_TD_VLAN_TAG; 1485 } 1486 1487 desc = &sc->jme_txring[prod]; 1488 desc->flags = htole32(cflags); 1489 desc->buflen = htole32(tso_segsz); 1490 desc->addr_hi = htole32(m->m_pkthdr.len); 1491 desc->addr_lo = 0; 1492 headdsc = prod; 1493 sc->jme_tx_cnt++; 1494 JME_DESC_INC(prod, JME_NBUFS); 1495 for (i = 0; i < nsegs; i++) { 1496 desc = &sc->jme_txring[prod]; 1497 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1498 desc->buflen = 1499 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1500 desc->addr_hi = htole32( 1501 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1502 desc->addr_lo = htole32( 1503 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1504 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1505 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1506 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1507 sc->jme_txmbuf[prod] = NULL; 1508 sc->jme_tx_cnt++; 1509 JME_DESC_INC(prod, JME_NBUFS); 1510 } 1511 1512 /* Update producer index. */ 1513 sc->jme_tx_prod = prod; 1514 #ifdef JMEDEBUG_TX 1515 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1516 #endif 1517 /* 1518 * Finally request interrupt and give the first descriptor 1519 * owenership to hardware. 1520 */ 1521 desc = &sc->jme_txring[headdsc]; 1522 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1523 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1524 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1526 1527 sc->jme_txmbuf[headdsc] = m; 1528 return (0); 1529 } 1530 1531 static void 1532 jme_txeof(struct jme_softc *sc) 1533 { 1534 struct ifnet *ifp; 1535 struct jme_desc *desc; 1536 uint32_t status; 1537 int cons, cons0, nsegs, seg; 1538 1539 ifp = &sc->jme_if; 1540 1541 #ifdef JMEDEBUG_TX 1542 printf("jme_txeof cons %d prod %d\n", 1543 sc->jme_tx_cons, sc->jme_tx_prod); 1544 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1545 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1546 "JME_TXTRHD 0x%x\n", 1547 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1548 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1549 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1550 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1551 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1552 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1553 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1554 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1555 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1556 desc = &sc->jme_txring[cons]; 1557 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1558 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1559 JME_DESC_INC(cons, JME_NBUFS); 1560 } 1561 #endif 1562 1563 cons = sc->jme_tx_cons; 1564 if (cons == sc->jme_tx_prod) 1565 return; 1566 1567 /* 1568 * Go through our Tx list and free mbufs for those 1569 * frames which have been transmitted. 1570 */ 1571 for (; cons != sc->jme_tx_prod;) { 1572 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1573 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1574 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1575 1576 desc = &sc->jme_txring[cons]; 1577 status = le32toh(desc->flags); 1578 #ifdef JMEDEBUG_TX 1579 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1580 sc->jme_txmbufm[cons]->dm_nsegs); 1581 #endif 1582 if (status & JME_TD_OWN) 1583 break; 1584 1585 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1586 ifp->if_oerrors++; 1587 else { 1588 ifp->if_opackets++; 1589 if ((status & JME_TD_COLLISION) != 0) 1590 ifp->if_collisions += 1591 le32toh(desc->buflen) & 1592 JME_TD_BUF_LEN_MASK; 1593 } 1594 /* 1595 * Only the first descriptor of multi-descriptor 1596 * transmission is updated so driver have to skip entire 1597 * chained buffers for the transmiited frame. In other 1598 * words, JME_TD_OWN bit is valid only at the first 1599 * descriptor of a multi-descriptor transmission. 1600 */ 1601 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1602 cons0 = cons; 1603 JME_DESC_INC(cons, JME_NBUFS); 1604 for (seg = 1; seg < nsegs + 1; seg++) { 1605 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1606 cons * sizeof(struct jme_desc), 1607 sizeof(struct jme_desc), 1608 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1609 sc->jme_txring[cons].flags = 0; 1610 JME_DESC_INC(cons, JME_NBUFS); 1611 } 1612 /* Reclaim transferred mbufs. */ 1613 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1614 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1615 BUS_DMASYNC_POSTWRITE); 1616 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1617 1618 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1619 m_freem(sc->jme_txmbuf[cons0]); 1620 sc->jme_txmbuf[cons0] = NULL; 1621 sc->jme_tx_cnt -= nsegs + 1; 1622 KASSERT(sc->jme_tx_cnt >= 0); 1623 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1624 } 1625 sc->jme_tx_cons = cons; 1626 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1627 if (sc->jme_tx_cnt == 0) 1628 ifp->if_timer = 0; 1629 #ifdef JMEDEBUG_TX 1630 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1631 #endif 1632 } 1633 1634 static void 1635 jme_ifstart(struct ifnet *ifp) 1636 { 1637 jme_softc_t *sc = ifp->if_softc; 1638 struct mbuf *mb_head; 1639 int enq; 1640 1641 /* 1642 * check if we can free some desc. 1643 * Clear TX interrupt status to reset TX coalescing counters. 1644 */ 1645 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1646 JME_INTR_STATUS, INTR_TXQ_COMP); 1647 jme_txeof(sc); 1648 1649 if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1650 return; 1651 for (enq = 0;; enq++) { 1652 nexttx: 1653 /* Grab a paquet for output */ 1654 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1655 if (mb_head == NULL) { 1656 #ifdef JMEDEBUG_TX 1657 printf("%s: nothing to send\n", __func__); 1658 #endif 1659 break; 1660 } 1661 /* try to add this mbuf to the TX ring */ 1662 if (jme_encap(sc, &mb_head)) { 1663 if (mb_head == NULL) { 1664 ifp->if_oerrors++; 1665 /* packet dropped, try next one */ 1666 goto nexttx; 1667 } 1668 /* resource shortage, try again later */ 1669 IF_PREPEND(&ifp->if_snd, mb_head); 1670 ifp->if_flags |= IFF_OACTIVE; 1671 break; 1672 } 1673 #if NBPFILTER > 0 1674 /* Pass packet to bpf if there is a listener */ 1675 if (ifp->if_bpf) 1676 bpf_mtap(ifp->if_bpf, mb_head); 1677 #endif 1678 } 1679 #ifdef JMEDEBUG_TX 1680 printf("jme_ifstart enq %d\n", enq); 1681 #endif 1682 if (enq) { 1683 /* 1684 * Set a 5 second timer just in case we don't hear from 1685 * the card again. 1686 */ 1687 ifp->if_timer = 5; 1688 /* 1689 * Reading TXCSR takes very long time under heavy load 1690 * so cache TXCSR value and writes the ORed value with 1691 * the kick command to the TXCSR. This saves one register 1692 * access cycle. 1693 */ 1694 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1695 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1696 #ifdef JMEDEBUG_TX 1697 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1698 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1699 "JME_TXTRHD 0x%x\n", 1700 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1701 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1702 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1703 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1704 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1705 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1706 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1707 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1708 #endif 1709 } 1710 } 1711 1712 static void 1713 jme_ifwatchdog(struct ifnet *ifp) 1714 { 1715 jme_softc_t *sc = ifp->if_softc; 1716 1717 if ((ifp->if_flags & IFF_RUNNING) == 0) 1718 return; 1719 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1720 ifp->if_oerrors++; 1721 jme_init(ifp, 0); 1722 } 1723 1724 static int 1725 jme_mediachange(struct ifnet *ifp) 1726 { 1727 int error; 1728 jme_softc_t *sc = ifp->if_softc; 1729 1730 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1731 error = 0; 1732 else if (error != 0) { 1733 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1734 return error; 1735 } 1736 return 0; 1737 } 1738 1739 static void 1740 jme_ticks(void *v) 1741 { 1742 jme_softc_t *sc = v; 1743 int s = splnet(); 1744 1745 /* Tick the MII. */ 1746 mii_tick(&sc->jme_mii); 1747 1748 /* every seconds */ 1749 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1750 splx(s); 1751 } 1752 1753 static void 1754 jme_mac_config(jme_softc_t *sc) 1755 { 1756 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1757 struct mii_data *mii = &sc->jme_mii; 1758 1759 ghc = 0; 1760 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1761 rxmac &= ~RXMAC_FC_ENB; 1762 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1763 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1764 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1765 txpause &= ~TXPFC_PAUSE_ENB; 1766 1767 if (mii->mii_media_active & IFM_FDX) { 1768 ghc |= GHC_FULL_DUPLEX; 1769 rxmac &= ~RXMAC_COLL_DET_ENB; 1770 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1771 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1772 TXMAC_FRAME_BURST); 1773 /* Disable retry transmit timer/retry limit. */ 1774 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1775 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1776 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1777 } else { 1778 rxmac |= RXMAC_COLL_DET_ENB; 1779 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1780 /* Enable retry transmit timer/retry limit. */ 1781 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1782 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1783 } 1784 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1785 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1786 case IFM_10_T: 1787 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1788 break; 1789 case IFM_100_TX: 1790 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1791 break; 1792 case IFM_1000_T: 1793 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1794 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1795 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1796 break; 1797 default: 1798 break; 1799 } 1800 if ((sc->jme_flags & JME_FLAG_GIGA) && 1801 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1802 /* 1803 * Workaround occasional packet loss issue of JMC250 A2 1804 * when it runs on half-duplex media. 1805 */ 1806 #ifdef JMEDEBUG 1807 printf("JME250 A2 workaround\n"); 1808 #endif 1809 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1810 JME_GPREG1); 1811 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1812 gpreg &= ~GPREG1_HDPX_FIX; 1813 else 1814 gpreg |= GPREG1_HDPX_FIX; 1815 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1816 JME_GPREG1, gpreg); 1817 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1818 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1819 /* Extend interface FIFO depth. */ 1820 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1821 0x1B, 0x0000); 1822 } else { 1823 /* Select default interface FIFO depth. */ 1824 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1825 0x1B, 0x0004); 1826 } 1827 } 1828 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1829 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1830 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1831 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1832 } 1833 1834 static void 1835 jme_set_filter(jme_softc_t *sc) 1836 { 1837 struct ifnet *ifp = &sc->jme_if; 1838 struct ether_multistep step; 1839 struct ether_multi *enm; 1840 uint32_t hash[2] = {0, 0}; 1841 int i; 1842 uint32_t rxcfg; 1843 1844 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1845 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1846 RXMAC_ALLMULTI); 1847 /* Always accept frames destined to our station address. */ 1848 rxcfg |= RXMAC_UNICAST; 1849 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1850 rxcfg |= RXMAC_BROADCAST; 1851 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1852 if ((ifp->if_flags & IFF_PROMISC) != 0) 1853 rxcfg |= RXMAC_PROMISC; 1854 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1855 rxcfg |= RXMAC_ALLMULTI; 1856 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1857 JME_MAR0, 0xFFFFFFFF); 1858 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1859 JME_MAR1, 0xFFFFFFFF); 1860 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1861 JME_RXMAC, rxcfg); 1862 return; 1863 } 1864 /* 1865 * Set up the multicast address filter by passing all multicast 1866 * addresses through a CRC generator, and then using the low-order 1867 * 6 bits as an index into the 64 bit multicast hash table. The 1868 * high order bits select the register, while the rest of the bits 1869 * select the bit within the register. 1870 */ 1871 rxcfg |= RXMAC_MULTICAST; 1872 memset(hash, 0, sizeof(hash)); 1873 1874 ETHER_FIRST_MULTI(step, &sc->jme_ec, enm); 1875 while (enm != NULL) { 1876 #ifdef JEMDBUG 1877 printf("%s: addrs %s %s\n", __func__, 1878 ether_sprintf(enm->enm_addrlo), 1879 ether_sprintf(enm->enm_addrhi)); 1880 #endif 1881 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1882 i = ether_crc32_be(enm->enm_addrlo, 6); 1883 /* Just want the 6 least significant bits. */ 1884 i &= 0x3f; 1885 hash[i / 32] |= 1 << (i%32); 1886 } else { 1887 hash[0] = hash[1] = 0xffffffff; 1888 sc->jme_if.if_flags |= IFF_ALLMULTI; 1889 break; 1890 } 1891 ETHER_NEXT_MULTI(step, enm); 1892 } 1893 #ifdef JMEDEBUG 1894 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1895 #endif 1896 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1897 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1898 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1899 } 1900 1901 #if 0 1902 static int 1903 jme_multicast_hash(uint8_t *a) 1904 { 1905 int hash; 1906 1907 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1908 #define xor8(a,b,c,d,e,f,g,h) \ 1909 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1910 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1911 1912 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1913 DA(a,36), DA(a,42)); 1914 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1915 DA(a,37), DA(a,43)) << 1; 1916 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1917 DA(a,38), DA(a,44)) << 2; 1918 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1919 DA(a,39), DA(a,45)) << 3; 1920 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1921 DA(a,40), DA(a,46)) << 4; 1922 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1923 DA(a,41), DA(a,47)) << 5; 1924 1925 return hash; 1926 } 1927 #endif 1928 1929 static int 1930 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1931 { 1932 uint32_t reg; 1933 int i; 1934 1935 *val = 0; 1936 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1937 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1938 JME_SMBCSR); 1939 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1940 break; 1941 delay(10); 1942 } 1943 1944 if (i == 0) { 1945 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1946 return (ETIMEDOUT); 1947 } 1948 1949 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1950 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1951 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1952 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1953 delay(10); 1954 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1955 JME_SMBINTF); 1956 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1957 break; 1958 } 1959 1960 if (i == 0) { 1961 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1962 return (ETIMEDOUT); 1963 } 1964 1965 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1966 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1967 return (0); 1968 } 1969 1970 1971 static int 1972 jme_eeprom_macaddr(struct jme_softc *sc) 1973 { 1974 uint8_t eaddr[ETHER_ADDR_LEN]; 1975 uint8_t fup, reg, val; 1976 uint32_t offset; 1977 int match; 1978 1979 offset = 0; 1980 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1981 fup != JME_EEPROM_SIG0) 1982 return (ENOENT); 1983 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1984 fup != JME_EEPROM_SIG1) 1985 return (ENOENT); 1986 match = 0; 1987 do { 1988 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 1989 break; 1990 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 1991 == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) { 1992 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 1993 break; 1994 if (reg >= JME_PAR0 && 1995 reg < JME_PAR0 + ETHER_ADDR_LEN) { 1996 if (jme_eeprom_read_byte(sc, offset + 2, 1997 &val) != 0) 1998 break; 1999 eaddr[reg - JME_PAR0] = val; 2000 match++; 2001 } 2002 } 2003 if (fup & JME_EEPROM_DESC_END) 2004 break; 2005 2006 /* Try next eeprom descriptor. */ 2007 offset += JME_EEPROM_DESC_BYTES; 2008 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2009 2010 if (match == ETHER_ADDR_LEN) { 2011 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2012 return (0); 2013 } 2014 2015 return (ENOENT); 2016 } 2017 2018 /* 2019 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2020 * set up in jme_pci_attach() 2021 */ 2022 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2023 { 2024 int rc; 2025 const struct sysctlnode *node; 2026 2027 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2028 0, CTLTYPE_NODE, "hw", NULL, 2029 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2030 goto err; 2031 } 2032 2033 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2034 0, CTLTYPE_NODE, "jme", 2035 SYSCTL_DESCR("jme interface controls"), 2036 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2037 goto err; 2038 } 2039 2040 jme_root_num = node->sysctl_num; 2041 return; 2042 2043 err: 2044 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2045 } 2046 2047 static int 2048 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2049 { 2050 int error, t; 2051 struct sysctlnode node; 2052 struct jme_softc *sc; 2053 uint32_t reg; 2054 2055 node = *rnode; 2056 sc = node.sysctl_data; 2057 t = sc->jme_intrxto; 2058 node.sysctl_data = &t; 2059 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2060 if (error || newp == NULL) 2061 return error; 2062 2063 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2064 return EINVAL; 2065 2066 /* 2067 * update the softc with sysctl-changed value, and mark 2068 * for hardware update 2069 */ 2070 sc->jme_intrxto = t; 2071 /* Configure Rx queue 0 packet completion coalescing. */ 2072 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2073 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2074 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2075 return 0; 2076 } 2077 2078 static int 2079 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2080 { 2081 int error, t; 2082 struct sysctlnode node; 2083 struct jme_softc *sc; 2084 uint32_t reg; 2085 2086 node = *rnode; 2087 sc = node.sysctl_data; 2088 t = sc->jme_intrxct; 2089 node.sysctl_data = &t; 2090 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2091 if (error || newp == NULL) 2092 return error; 2093 2094 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2095 return EINVAL; 2096 2097 /* 2098 * update the softc with sysctl-changed value, and mark 2099 * for hardware update 2100 */ 2101 sc->jme_intrxct = t; 2102 /* Configure Rx queue 0 packet completion coalescing. */ 2103 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2104 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2105 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2106 return 0; 2107 } 2108 2109 static int 2110 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2111 { 2112 int error, t; 2113 struct sysctlnode node; 2114 struct jme_softc *sc; 2115 uint32_t reg; 2116 2117 node = *rnode; 2118 sc = node.sysctl_data; 2119 t = sc->jme_inttxto; 2120 node.sysctl_data = &t; 2121 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2122 if (error || newp == NULL) 2123 return error; 2124 2125 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2126 return EINVAL; 2127 2128 /* 2129 * update the softc with sysctl-changed value, and mark 2130 * for hardware update 2131 */ 2132 sc->jme_inttxto = t; 2133 /* Configure Tx queue 0 packet completion coalescing. */ 2134 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2135 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2136 reg |= PCCTX_COAL_TXQ0; 2137 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2138 return 0; 2139 } 2140 2141 static int 2142 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2143 { 2144 int error, t; 2145 struct sysctlnode node; 2146 struct jme_softc *sc; 2147 uint32_t reg; 2148 2149 node = *rnode; 2150 sc = node.sysctl_data; 2151 t = sc->jme_inttxct; 2152 node.sysctl_data = &t; 2153 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2154 if (error || newp == NULL) 2155 return error; 2156 2157 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2158 return EINVAL; 2159 2160 /* 2161 * update the softc with sysctl-changed value, and mark 2162 * for hardware update 2163 */ 2164 sc->jme_inttxct = t; 2165 /* Configure Tx queue 0 packet completion coalescing. */ 2166 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2167 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2168 reg |= PCCTX_COAL_TXQ0; 2169 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2170 return 0; 2171 } 2172