1 /* $NetBSD: if_jme.c,v 1.50 2021/05/08 00:27:02 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.50 2021/05/08 00:27:02 thorpej Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 74 #include <sys/device.h> 75 #include <sys/syslog.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_media.h> 80 #include <net/if_types.h> 81 #include <net/if_dl.h> 82 #include <net/route.h> 83 #include <net/netisr.h> 84 #include <net/bpf.h> 85 86 #include <sys/rndsource.h> 87 88 #include <netinet/in.h> 89 #include <netinet/in_systm.h> 90 #include <netinet/ip.h> 91 92 #ifdef INET 93 #include <netinet/in_var.h> 94 #endif 95 96 #include <netinet/tcp.h> 97 98 #include <net/if_ether.h> 99 #if defined(INET) 100 #include <netinet/if_inarp.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/if_jmereg.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 /* number of entries in transmit and receive rings */ 115 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 116 117 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 118 119 /* Water mark to kick reclaiming Tx buffers. */ 120 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 121 122 123 struct jme_softc { 124 device_t jme_dev; /* base device */ 125 bus_space_tag_t jme_bt_mac; 126 bus_space_handle_t jme_bh_mac; /* Mac registers */ 127 bus_space_tag_t jme_bt_phy; 128 bus_space_handle_t jme_bh_phy; /* PHY registers */ 129 bus_space_tag_t jme_bt_misc; 130 bus_space_handle_t jme_bh_misc; /* Misc registers */ 131 bus_dma_tag_t jme_dmatag; 132 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 133 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 134 struct jme_desc* jme_txring; /* transmit ring */ 135 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 136 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 137 int jme_tx_cons; /* transmit ring consumer */ 138 int jme_tx_prod; /* transmit ring producer */ 139 int jme_tx_cnt; /* transmit ring active count */ 140 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 141 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 142 struct jme_desc* jme_rxring; /* receive ring */ 143 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 144 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 145 int jme_rx_cons; /* receive ring consumer */ 146 int jme_rx_prod; /* receive ring producer */ 147 void* jme_ih; /* our interrupt */ 148 struct ethercom jme_ec; 149 struct callout jme_tick_ch; /* tick callout */ 150 uint8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 151 uint8_t jme_phyaddr; /* address of integrated phy */ 152 uint8_t jme_chip_rev; /* chip revision */ 153 uint8_t jme_rev; /* PCI revision */ 154 mii_data_t jme_mii; /* mii bus */ 155 uint32_t jme_flags; /* device features, see below */ 156 uint32_t jme_txcsr; /* TX config register */ 157 uint32_t jme_rxcsr; /* RX config register */ 158 krndsource_t rnd_source; 159 /* interrupt coalition parameters */ 160 struct sysctllog *jme_clog; 161 int jme_intrxto; /* interrupt RX timeout */ 162 int jme_intrxct; /* interrupt RX packets counter */ 163 int jme_inttxto; /* interrupt TX timeout */ 164 int jme_inttxct; /* interrupt TX packets counter */ 165 }; 166 167 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 168 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 169 170 171 #define jme_if jme_ec.ec_if 172 #define jme_bpf jme_if.if_bpf 173 174 typedef struct jme_softc jme_softc_t; 175 typedef u_long ioctl_cmd_t; 176 177 static int jme_pci_match(device_t, cfdata_t, void *); 178 static void jme_pci_attach(device_t, device_t, void *); 179 static void jme_intr_rx(jme_softc_t *); 180 static int jme_intr(void *); 181 182 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 183 static int jme_mediachange(struct ifnet *); 184 static void jme_ifwatchdog(struct ifnet *); 185 static bool jme_shutdown(device_t, int); 186 187 static void jme_txeof(struct jme_softc *); 188 static void jme_ifstart(struct ifnet *); 189 static void jme_reset(jme_softc_t *); 190 static int jme_ifinit(struct ifnet *); 191 static int jme_init(struct ifnet *, int); 192 static void jme_stop(struct ifnet *, int); 193 // static void jme_restart(void *); 194 static void jme_ticks(void *); 195 static void jme_mac_config(jme_softc_t *); 196 static void jme_set_filter(jme_softc_t *); 197 198 static int jme_mii_read(device_t, int, int, uint16_t *); 199 static int jme_mii_write(device_t, int, int, uint16_t); 200 static void jme_statchg(struct ifnet *); 201 202 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 203 static int jme_eeprom_macaddr(struct jme_softc *); 204 static int jme_reg_macaddr(struct jme_softc *); 205 206 #define JME_TIMEOUT 1000 207 #define JME_PHY_TIMEOUT 1000 208 #define JME_EEPROM_TIMEOUT 1000 209 210 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 211 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 212 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 213 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 214 static int jme_root_num; 215 216 217 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 218 jme_pci_match, jme_pci_attach, NULL, NULL); 219 220 static const struct device_compatible_entry compat_data[] = { 221 { .id = PCI_ID_CODE(PCI_VENDOR_JMICRON, 222 PCI_PRODUCT_JMICRON_JMC250), 223 .data = "JMicron JMC250 Gigabit Ethernet Controller" }, 224 225 { .id = PCI_ID_CODE(PCI_VENDOR_JMICRON, 226 PCI_PRODUCT_JMICRON_JMC260), 227 .data = "JMicron JMC260 Gigabit Ethernet Controller" }, 228 229 PCI_COMPAT_EOL 230 }; 231 232 static int 233 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 234 { 235 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 236 237 return pci_compatible_match(pa, compat_data); 238 } 239 240 static void 241 jme_pci_attach(device_t parent, device_t self, void *aux) 242 { 243 jme_softc_t *sc = device_private(self); 244 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 245 const struct device_compatible_entry *dce; 246 struct ifnet * const ifp = &sc->jme_if; 247 struct mii_data * const mii = &sc->jme_mii; 248 bus_space_tag_t iot1, iot2, memt; 249 bus_space_handle_t ioh1, ioh2, memh; 250 bus_size_t size, size2; 251 pci_intr_handle_t intrhandle; 252 const char *intrstr; 253 pcireg_t csr; 254 int nsegs, i; 255 const struct sysctlnode *node; 256 int jme_nodenum; 257 char intrbuf[PCI_INTRSTR_LEN]; 258 259 sc->jme_dev = self; 260 aprint_normal("\n"); 261 callout_init(&sc->jme_tick_ch, 0); 262 callout_setfunc(&sc->jme_tick_ch, jme_ticks, sc); 263 264 dce = pci_compatible_lookup(pa, compat_data); 265 KASSERT(dce != NULL); 266 267 if (PCI_PRODUCT(dce->id) == PCI_PRODUCT_JMICRON_JMC250) 268 sc->jme_flags = JME_FLAG_GIGA; 269 270 /* 271 * Map the card space. Try Mem first. 272 */ 273 if (pci_mapreg_map(pa, JME_PCI_BAR0, 274 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 275 0, &memt, &memh, NULL, &size) == 0) { 276 sc->jme_bt_mac = memt; 277 sc->jme_bh_mac = memh; 278 sc->jme_bt_phy = memt; 279 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 280 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 281 aprint_error_dev(self, "can't subregion PHY space\n"); 282 bus_space_unmap(memt, memh, size); 283 return; 284 } 285 sc->jme_bt_misc = memt; 286 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 287 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 288 aprint_error_dev(self, "can't subregion misc space\n"); 289 bus_space_unmap(memt, memh, size); 290 return; 291 } 292 } else { 293 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 294 0, &iot1, &ioh1, NULL, &size) != 0) { 295 aprint_error_dev(self, "can't map I/O space 1\n"); 296 return; 297 } 298 sc->jme_bt_mac = iot1; 299 sc->jme_bh_mac = ioh1; 300 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 301 0, &iot2, &ioh2, NULL, &size2) != 0) { 302 aprint_error_dev(self, "can't map I/O space 2\n"); 303 bus_space_unmap(iot1, ioh1, size); 304 return; 305 } 306 sc->jme_bt_phy = iot2; 307 sc->jme_bh_phy = ioh2; 308 sc->jme_bt_misc = iot2; 309 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 310 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 311 aprint_error_dev(self, "can't subregion misc space\n"); 312 bus_space_unmap(iot1, ioh1, size); 313 bus_space_unmap(iot2, ioh2, size2); 314 return; 315 } 316 } 317 318 if (pci_dma64_available(pa)) 319 sc->jme_dmatag = pa->pa_dmat64; 320 else 321 sc->jme_dmatag = pa->pa_dmat; 322 323 /* Enable the device. */ 324 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 325 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 326 csr | PCI_COMMAND_MASTER_ENABLE); 327 328 aprint_normal_dev(self, "%s\n", (const char *)dce->data); 329 330 sc->jme_rev = PCI_REVISION(pa->pa_class); 331 332 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 333 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 334 CHIPMODE_NOT_FPGA) 335 sc->jme_flags |= JME_FLAG_FPGA; 336 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 337 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 338 "0x%x", sc->jme_rev, sc->jme_chip_rev); 339 if (sc->jme_flags & JME_FLAG_FPGA) 340 aprint_verbose(" FPGA revision: 0x%x", 341 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 342 aprint_verbose("\n"); 343 344 /* 345 * Save PHY address. 346 * Integrated JR0211 has fixed PHY address whereas FPGA version 347 * requires PHY probing to get correct PHY address. 348 */ 349 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 350 sc->jme_phyaddr = 351 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 352 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 353 } else 354 sc->jme_phyaddr = 0; 355 356 357 jme_reset(sc); 358 359 /* read mac addr */ 360 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 361 aprint_error_dev(self, "error reading Ethernet address\n"); 362 /* return; */ 363 } 364 aprint_normal_dev(self, "Ethernet address %s\n", 365 ether_sprintf(sc->jme_enaddr)); 366 367 /* Map and establish interrupts */ 368 if (pci_intr_map(pa, &intrhandle)) { 369 aprint_error_dev(self, "couldn't map interrupt\n"); 370 return; 371 } 372 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 373 sc->jme_if.if_softc = sc; 374 sc->jme_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 375 jme_intr, sc, device_xname(self)); 376 if (sc->jme_ih == NULL) { 377 aprint_error_dev(self, "couldn't establish interrupt"); 378 if (intrstr != NULL) 379 aprint_error(" at %s", intrstr); 380 aprint_error("\n"); 381 return; 382 } 383 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 384 385 /* allocate and map DMA-safe memory for transmit ring */ 386 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 387 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 388 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 389 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 390 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 391 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 392 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 393 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 394 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 395 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 396 return; 397 } 398 /* allocate and map DMA-safe memory for receive ring */ 399 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 400 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 401 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 402 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 403 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 404 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 405 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 406 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 407 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 408 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 409 return; 410 } 411 for (i = 0; i < JME_NBUFS; i++) { 412 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 413 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 414 JME_NBUFS, JME_MAX_TX_LEN, 0, 415 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 416 &sc->jme_txmbufm[i]) != 0) { 417 aprint_error_dev(self, "can't allocate DMA TX map\n"); 418 return; 419 } 420 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 421 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 422 &sc->jme_rxmbufm[i]) != 0) { 423 aprint_error_dev(self, "can't allocate DMA RX map\n"); 424 return; 425 } 426 } 427 /* 428 * Initialize our media structures and probe the MII. 429 * 430 * Note that we don't care about the media instance. We 431 * are expecting to have multiple PHYs on the 10/100 cards, 432 * and on those cards we exclude the internal PHY from providing 433 * 10baseT. By ignoring the instance, it allows us to not have 434 * to specify it on the command line when switching media. 435 */ 436 mii->mii_ifp = ifp; 437 mii->mii_readreg = jme_mii_read; 438 mii->mii_writereg = jme_mii_write; 439 mii->mii_statchg = jme_statchg; 440 sc->jme_ec.ec_mii = mii; 441 ifmedia_init(&mii->mii_media, IFM_IMASK, jme_mediachange, 442 ether_mediastatus); 443 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 444 if (LIST_FIRST(&mii->mii_phys) == NULL) { 445 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 446 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 447 } else 448 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 449 450 /* 451 * We can support 802.1Q VLAN-sized frames. 452 */ 453 sc->jme_ec.ec_capabilities |= 454 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 455 sc->jme_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 456 457 if (sc->jme_flags & JME_FLAG_GIGA) 458 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 459 460 461 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 462 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 463 ifp->if_ioctl = jme_ifioctl; 464 ifp->if_start = jme_ifstart; 465 ifp->if_watchdog = jme_ifwatchdog; 466 ifp->if_init = jme_ifinit; 467 ifp->if_stop = jme_stop; 468 ifp->if_timer = 0; 469 ifp->if_capabilities |= 470 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 471 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 472 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 473 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 474 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 475 IFCAP_TSOv4 | IFCAP_TSOv6; 476 IFQ_SET_READY(&ifp->if_snd); 477 if_attach(ifp); 478 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 479 480 /* 481 * Add shutdown hook so that DMA is disabled prior to reboot. 482 */ 483 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 484 pmf_class_network_register(self, ifp); 485 else 486 aprint_error_dev(self, "couldn't establish power handler\n"); 487 488 rnd_attach_source(&sc->rnd_source, device_xname(self), 489 RND_TYPE_NET, RND_FLAG_DEFAULT); 490 491 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 492 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 493 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 494 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 495 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 496 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 497 SYSCTL_DESCR("jme per-controller controls"), 498 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 499 CTL_EOL) != 0) { 500 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 501 return; 502 } 503 jme_nodenum = node->sysctl_num; 504 505 /* interrupt moderation sysctls */ 506 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 507 CTLFLAG_READWRITE, 508 CTLTYPE_INT, "int_rxto", 509 SYSCTL_DESCR("jme RX interrupt moderation timer"), 510 jme_sysctl_intrxto, 0, (void *)sc, 511 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 512 CTL_EOL) != 0) { 513 aprint_normal_dev(sc->jme_dev, 514 "couldn't create int_rxto sysctl node\n"); 515 } 516 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 517 CTLFLAG_READWRITE, 518 CTLTYPE_INT, "int_rxct", 519 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 520 jme_sysctl_intrxct, 0, (void *)sc, 521 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 522 CTL_EOL) != 0) { 523 aprint_normal_dev(sc->jme_dev, 524 "couldn't create int_rxct sysctl node\n"); 525 } 526 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 527 CTLFLAG_READWRITE, 528 CTLTYPE_INT, "int_txto", 529 SYSCTL_DESCR("jme TX interrupt moderation timer"), 530 jme_sysctl_inttxto, 0, (void *)sc, 531 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 532 CTL_EOL) != 0) { 533 aprint_normal_dev(sc->jme_dev, 534 "couldn't create int_txto sysctl node\n"); 535 } 536 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 537 CTLFLAG_READWRITE, 538 CTLTYPE_INT, "int_txct", 539 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 540 jme_sysctl_inttxct, 0, (void *)sc, 541 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 542 CTL_EOL) != 0) { 543 aprint_normal_dev(sc->jme_dev, 544 "couldn't create int_txct sysctl node\n"); 545 } 546 } 547 548 static void 549 jme_stop_rx(jme_softc_t *sc) 550 { 551 uint32_t reg; 552 int i; 553 554 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 555 if ((reg & RXCSR_RX_ENB) == 0) 556 return; 557 reg &= ~RXCSR_RX_ENB; 558 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 559 for (i = JME_TIMEOUT / 10; i > 0; i--) { 560 DELAY(10); 561 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 562 JME_RXCSR) & RXCSR_RX_ENB) == 0) 563 break; 564 } 565 if (i == 0) 566 aprint_error_dev(sc->jme_dev, "stopping receiver timeout!\n"); 567 568 } 569 570 static void 571 jme_stop_tx(jme_softc_t *sc) 572 { 573 uint32_t reg; 574 int i; 575 576 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 577 if ((reg & TXCSR_TX_ENB) == 0) 578 return; 579 reg &= ~TXCSR_TX_ENB; 580 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 581 for (i = JME_TIMEOUT / 10; i > 0; i--) { 582 DELAY(10); 583 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 584 JME_TXCSR) & TXCSR_TX_ENB) == 0) 585 break; 586 } 587 if (i == 0) 588 aprint_error_dev(sc->jme_dev, 589 "stopping transmitter timeout!\n"); 590 } 591 592 static void 593 jme_reset(jme_softc_t *sc) 594 { 595 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 596 DELAY(10); 597 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 598 } 599 600 static bool 601 jme_shutdown(device_t self, int howto) 602 { 603 jme_softc_t *sc; 604 struct ifnet *ifp; 605 606 sc = device_private(self); 607 ifp = &sc->jme_if; 608 jme_stop(ifp, 1); 609 610 return true; 611 } 612 613 static void 614 jme_stop(struct ifnet *ifp, int disable) 615 { 616 jme_softc_t *sc = ifp->if_softc; 617 int i; 618 /* Stop receiver, transmitter. */ 619 jme_stop_rx(sc); 620 jme_stop_tx(sc); 621 /* free receive mbufs */ 622 for (i = 0; i < JME_NBUFS; i++) { 623 if (sc->jme_rxmbuf[i]) { 624 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 625 m_freem(sc->jme_rxmbuf[i]); 626 } 627 sc->jme_rxmbuf[i] = NULL; 628 } 629 /* process completed transmits */ 630 jme_txeof(sc); 631 /* free abort pending transmits */ 632 for (i = 0; i < JME_NBUFS; i++) { 633 if (sc->jme_txmbuf[i]) { 634 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 635 m_freem(sc->jme_txmbuf[i]); 636 sc->jme_txmbuf[i] = NULL; 637 } 638 } 639 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 640 ifp->if_timer = 0; 641 } 642 643 #if 0 644 static void 645 jme_restart(void *v) 646 { 647 648 jme_init(v); 649 } 650 #endif 651 652 static int 653 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 654 { 655 int error; 656 bus_dmamap_t map; 657 int i = sc->jme_rx_prod; 658 659 if (sc->jme_rxmbuf[i] != NULL) { 660 aprint_error_dev(sc->jme_dev, 661 "mbuf already here: rxprod %d rxcons %d\n", 662 sc->jme_rx_prod, sc->jme_rx_cons); 663 if (m) 664 m_freem(m); 665 return EINVAL; 666 } 667 668 if (m == NULL) { 669 sc->jme_rxmbuf[i] = NULL; 670 MGETHDR(m, M_DONTWAIT, MT_DATA); 671 if (m == NULL) 672 return (ENOBUFS); 673 MCLGET(m, M_DONTWAIT); 674 if ((m->m_flags & M_EXT) == 0) { 675 m_freem(m); 676 return (ENOBUFS); 677 } 678 } 679 map = sc->jme_rxmbufm[i]; 680 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 681 KASSERT(m->m_len == MCLBYTES); 682 683 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 684 BUS_DMA_READ | BUS_DMA_NOWAIT); 685 if (error) { 686 sc->jme_rxmbuf[i] = NULL; 687 aprint_error_dev(sc->jme_dev, 688 "unable to load rx DMA map %d, error = %d\n", 689 i, error); 690 m_freem(m); 691 return (error); 692 } 693 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 694 BUS_DMASYNC_PREREAD); 695 696 sc->jme_rxmbuf[i] = m; 697 698 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 699 sc->jme_rxring[i].addr_lo = 700 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 701 sc->jme_rxring[i].addr_hi = 702 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 703 sc->jme_rxring[i].flags = 704 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 705 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 706 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 708 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 709 return (0); 710 } 711 712 static int 713 jme_ifinit(struct ifnet *ifp) 714 { 715 return jme_init(ifp, 1); 716 } 717 718 static int 719 jme_init(struct ifnet *ifp, int do_ifinit) 720 { 721 jme_softc_t *sc = ifp->if_softc; 722 int i, s; 723 uint8_t eaddr[ETHER_ADDR_LEN]; 724 uint32_t reg; 725 726 s = splnet(); 727 /* cancel any pending IO */ 728 jme_stop(ifp, 1); 729 jme_reset(sc); 730 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 731 splx(s); 732 return 0; 733 } 734 /* allocate receive ring */ 735 sc->jme_rx_prod = 0; 736 for (i = 0; i < JME_NBUFS; i++) { 737 if (jme_add_rxbuf(sc, NULL) < 0) { 738 aprint_error_dev(sc->jme_dev, 739 "can't allocate rx mbuf\n"); 740 for (i--; i >= 0; i--) { 741 bus_dmamap_unload(sc->jme_dmatag, 742 sc->jme_rxmbufm[i]); 743 m_freem(sc->jme_rxmbuf[i]); 744 sc->jme_rxmbuf[i] = NULL; 745 } 746 splx(s); 747 return ENOMEM; 748 } 749 } 750 /* init TX ring */ 751 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 752 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 753 0, JME_NBUFS * sizeof(struct jme_desc), 754 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 755 for (i = 0; i < JME_NBUFS; i++) 756 sc->jme_txmbuf[i] = NULL; 757 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 758 759 /* Reprogram the station address. */ 760 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 761 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 762 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 763 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 764 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 765 766 /* 767 * Configure Tx queue. 768 * Tx priority queue weight value : 0 769 * Tx FIFO threshold for processing next packet : 16QW 770 * Maximum Tx DMA length : 512 771 * Allow Tx DMA burst. 772 */ 773 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 774 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 775 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 776 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 777 sc->jme_txcsr |= TXCSR_DMA_BURST; 778 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 779 JME_TXCSR, sc->jme_txcsr); 780 781 /* Set Tx descriptor counter. */ 782 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 783 JME_TXQDC, JME_NBUFS); 784 785 /* Set Tx ring address to the hardware. */ 786 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 787 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 788 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 789 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 790 791 /* Configure TxMAC parameters. */ 792 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 793 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 794 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 795 796 /* 797 * Configure Rx queue. 798 * FIFO full threshold for transmitting Tx pause packet : 128T 799 * FIFO threshold for processing next packet : 128QW 800 * Rx queue 0 select 801 * Max Rx DMA length : 128 802 * Rx descriptor retry : 32 803 * Rx descriptor retry time gap : 256ns 804 * Don't receive runt/bad frame. 805 */ 806 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 807 /* 808 * Since Rx FIFO size is 4K bytes, receiving frames larger 809 * than 4K bytes will suffer from Rx FIFO overruns. So 810 * decrease FIFO threshold to reduce the FIFO overruns for 811 * frames larger than 4000 bytes. 812 * For best performance of standard MTU sized frames use 813 * maximum allowable FIFO threshold, 128QW. 814 */ 815 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 816 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 817 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 818 else 819 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 820 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 821 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 822 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 823 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 824 JME_RXCSR, sc->jme_rxcsr); 825 826 /* Set Rx descriptor counter. */ 827 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 828 JME_RXQDC, JME_NBUFS); 829 830 /* Set Rx ring address to the hardware. */ 831 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 832 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 833 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 834 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 835 836 /* Clear receive filter. */ 837 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 838 /* Set up the receive filter. */ 839 jme_set_filter(sc); 840 841 /* 842 * Disable all WOL bits as WOL can interfere normal Rx 843 * operation. Also clear WOL detection status bits. 844 */ 845 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 846 reg &= ~PMCS_WOL_ENB_MASK; 847 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 848 849 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 850 /* 851 * Pad 10bytes right before received frame. This will greatly 852 * help Rx performance on strict-alignment architectures as 853 * it does not need to copy the frame to align the payload. 854 */ 855 reg |= RXMAC_PAD_10BYTES; 856 if ((ifp->if_capenable & 857 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 858 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) != 0) 859 reg |= RXMAC_CSUM_ENB; 860 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 861 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 862 863 /* Configure general purpose reg0 */ 864 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 865 reg &= ~GPREG0_PCC_UNIT_MASK; 866 /* Set PCC timer resolution to micro-seconds unit. */ 867 reg |= GPREG0_PCC_UNIT_US; 868 /* 869 * Disable all shadow register posting as we have to read 870 * JME_INTR_STATUS register in jme_int_task. Also it seems 871 * that it's hard to synchronize interrupt status between 872 * hardware and software with shadow posting due to 873 * requirements of bus_dmamap_sync(9). 874 */ 875 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 876 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 877 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 878 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 879 /* Disable posting of DW0. */ 880 reg &= ~GPREG0_POST_DW0_ENB; 881 /* Clear PME message. */ 882 reg &= ~GPREG0_PME_ENB; 883 /* Set PHY address. */ 884 reg &= ~GPREG0_PHY_ADDR_MASK; 885 reg |= sc->jme_phyaddr; 886 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 887 888 /* Configure Tx queue 0 packet completion coalescing. */ 889 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 890 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 891 reg |= PCCTX_COAL_TXQ0; 892 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 893 894 /* Configure Rx queue 0 packet completion coalescing. */ 895 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 896 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 897 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 898 899 /* Disable Timers */ 900 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 901 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 902 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 903 904 /* Configure retry transmit period, retry limit value. */ 905 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 906 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 907 TXTRHD_RT_PERIOD_MASK) | 908 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 909 TXTRHD_RT_LIMIT_SHIFT)); 910 911 /* Disable RSS. */ 912 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 913 JME_RSSC, RSSC_DIS_RSS); 914 915 /* Initialize the interrupt mask. */ 916 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 917 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 918 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 919 JME_INTR_STATUS, 0xFFFFFFFF); 920 921 /* set media, if not already handling a media change */ 922 if (do_ifinit) { 923 int error; 924 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 925 error = 0; 926 else if (error != 0) { 927 aprint_error_dev(sc->jme_dev, "could not set media\n"); 928 splx(s); 929 return error; 930 } 931 } 932 933 /* Program MAC with resolved speed/duplex/flow-control. */ 934 jme_mac_config(sc); 935 936 /* Start receiver/transmitter. */ 937 sc->jme_rx_cons = 0; 938 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 939 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 940 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 941 sc->jme_txcsr | TXCSR_TX_ENB); 942 943 /* start ticks calls */ 944 callout_schedule(&sc->jme_tick_ch, hz); 945 sc->jme_if.if_flags |= IFF_RUNNING; 946 sc->jme_if.if_flags &= ~IFF_OACTIVE; 947 splx(s); 948 return 0; 949 } 950 951 static int 952 jme_mii_read(device_t self, int phy, int reg, uint16_t *val) 953 { 954 struct jme_softc *sc = device_private(self); 955 int data, i; 956 957 /* For FPGA version, PHY address 0 should be ignored. */ 958 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 959 if (phy == 0) 960 return -1; 961 } else { 962 if (sc->jme_phyaddr != phy) 963 return -1; 964 } 965 966 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 967 SMI_OP_READ | SMI_OP_EXECUTE | 968 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 969 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 970 delay(10); 971 if (((data = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 972 JME_SMI)) & SMI_OP_EXECUTE) == 0) 973 break; 974 } 975 976 if (i == 0) { 977 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 978 return ETIMEDOUT; 979 } 980 981 *val = (data & SMI_DATA_MASK) >> SMI_DATA_SHIFT; 982 return 0; 983 } 984 985 static int 986 jme_mii_write(device_t self, int phy, int reg, uint16_t val) 987 { 988 struct jme_softc *sc = device_private(self); 989 int i; 990 991 /* For FPGA version, PHY address 0 should be ignored. */ 992 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 993 if (phy == 0) 994 return -1; 995 } else { 996 if (sc->jme_phyaddr != phy) 997 return -1; 998 } 999 1000 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1001 SMI_OP_WRITE | SMI_OP_EXECUTE | 1002 (((uint32_t)val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1003 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1004 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1005 delay(10); 1006 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1007 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1008 break; 1009 } 1010 1011 if (i == 0) { 1012 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1013 return ETIMEDOUT; 1014 } 1015 1016 return 0; 1017 } 1018 1019 static void 1020 jme_statchg(struct ifnet *ifp) 1021 { 1022 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1023 jme_init(ifp, 0); 1024 } 1025 1026 static void 1027 jme_intr_rx(jme_softc_t *sc) { 1028 struct mbuf *m, *mhead; 1029 bus_dmamap_t mmap; 1030 struct ifnet *ifp = &sc->jme_if; 1031 uint32_t flags, buflen; 1032 int i, ipackets, nsegs, seg, error; 1033 struct jme_desc *desc; 1034 1035 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1036 sizeof(struct jme_desc) * JME_NBUFS, 1037 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1038 #ifdef JMEDEBUG_RX 1039 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1040 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1041 #endif 1042 ipackets = 0; 1043 while ((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) 1044 == 0) { 1045 i = sc->jme_rx_cons; 1046 desc = &sc->jme_rxring[i]; 1047 #ifdef JMEDEBUG_RX 1048 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1049 i, le32toh(desc->flags), le32toh(desc->buflen)); 1050 #endif 1051 if (sc->jme_rxmbuf[i] == NULL) { 1052 if ((error = jme_add_rxbuf(sc, NULL)) != 0) { 1053 aprint_error_dev(sc->jme_dev, 1054 "can't add new mbuf to empty slot: %d\n", 1055 error); 1056 break; 1057 } 1058 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1059 i = sc->jme_rx_cons; 1060 continue; 1061 } 1062 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1063 break; 1064 1065 buflen = le32toh(desc->buflen); 1066 nsegs = JME_RX_NSEGS(buflen); 1067 flags = le32toh(desc->flags); 1068 if ((buflen & JME_RX_ERR_STAT) != 0 || 1069 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1070 JME_RX_BYTES(buflen) > 1071 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1072 #ifdef JMEDEBUG_RX 1073 printf("rx error flags 0x%x buflen 0x%x\n", 1074 flags, buflen); 1075 #endif 1076 if_statinc(ifp, if_ierrors); 1077 /* reuse the mbufs */ 1078 for (seg = 0; seg < nsegs; seg++) { 1079 m = sc->jme_rxmbuf[i]; 1080 sc->jme_rxmbuf[i] = NULL; 1081 mmap = sc->jme_rxmbufm[i]; 1082 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1083 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1084 bus_dmamap_unload(sc->jme_dmatag, mmap); 1085 if ((error = jme_add_rxbuf(sc, m)) != 0) 1086 aprint_error_dev(sc->jme_dev, 1087 "can't reuse mbuf: %d\n", error); 1088 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1089 i = sc->jme_rx_cons; 1090 } 1091 continue; 1092 } 1093 /* receive this packet */ 1094 mhead = m = sc->jme_rxmbuf[i]; 1095 sc->jme_rxmbuf[i] = NULL; 1096 mmap = sc->jme_rxmbufm[i]; 1097 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1098 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1099 bus_dmamap_unload(sc->jme_dmatag, mmap); 1100 /* add a new buffer to chain */ 1101 if (jme_add_rxbuf(sc, NULL) != 0) { 1102 if ((error = jme_add_rxbuf(sc, m)) != 0) 1103 aprint_error_dev(sc->jme_dev, 1104 "can't reuse mbuf: %d\n", error); 1105 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1106 i = sc->jme_rx_cons; 1107 for (seg = 1; seg < nsegs; seg++) { 1108 m = sc->jme_rxmbuf[i]; 1109 sc->jme_rxmbuf[i] = NULL; 1110 mmap = sc->jme_rxmbufm[i]; 1111 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1112 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1113 bus_dmamap_unload(sc->jme_dmatag, mmap); 1114 if ((error = jme_add_rxbuf(sc, m)) != 0) 1115 aprint_error_dev(sc->jme_dev, 1116 "can't reuse mbuf: %d\n", error); 1117 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1118 i = sc->jme_rx_cons; 1119 } 1120 if_statinc(ifp, if_ierrors); 1121 continue; 1122 } 1123 1124 /* build mbuf chain: head, then remaining segments */ 1125 m_set_rcvif(m, ifp); 1126 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1127 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1128 m->m_pkthdr.len; 1129 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1130 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1131 for (seg = 1; seg < nsegs; seg++) { 1132 i = sc->jme_rx_cons; 1133 m = sc->jme_rxmbuf[i]; 1134 sc->jme_rxmbuf[i] = NULL; 1135 mmap = sc->jme_rxmbufm[i]; 1136 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1137 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1138 bus_dmamap_unload(sc->jme_dmatag, mmap); 1139 if ((error = jme_add_rxbuf(sc, NULL)) != 0) 1140 aprint_error_dev(sc->jme_dev, 1141 "can't add new mbuf: %d\n", error); 1142 m->m_flags &= ~M_PKTHDR; 1143 m_cat(mhead, m); 1144 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1145 } 1146 /* and adjust last mbuf's size */ 1147 if (nsegs > 1) { 1148 m->m_len = 1149 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1150 } 1151 ipackets++; 1152 1153 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1154 (flags & JME_RD_IPV4)) { 1155 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1156 if (!(flags & JME_RD_IPCSUM)) 1157 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1158 } 1159 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1160 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1161 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1162 if (!(flags & JME_RD_TCPCSUM)) 1163 mhead->m_pkthdr.csum_flags |= 1164 M_CSUM_TCP_UDP_BAD; 1165 } 1166 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1167 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1168 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1169 if (!(flags & JME_RD_UDPCSUM)) 1170 mhead->m_pkthdr.csum_flags |= 1171 M_CSUM_TCP_UDP_BAD; 1172 } 1173 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1174 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1175 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1176 if (!(flags & JME_RD_TCPCSUM)) 1177 mhead->m_pkthdr.csum_flags |= 1178 M_CSUM_TCP_UDP_BAD; 1179 } 1180 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1181 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1182 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1183 if (!(flags & JME_RD_UDPCSUM)) 1184 mhead->m_pkthdr.csum_flags |= 1185 M_CSUM_TCP_UDP_BAD; 1186 } 1187 if (flags & JME_RD_VLAN_TAG) { 1188 /* pass to vlan_input() */ 1189 vlan_set_tag(mhead, (flags & JME_RD_VLAN_MASK)); 1190 } 1191 if_percpuq_enqueue(ifp->if_percpuq, mhead); 1192 } 1193 if (ipackets) 1194 rnd_add_uint32(&sc->rnd_source, ipackets); 1195 } 1196 1197 static int 1198 jme_intr(void *v) 1199 { 1200 jme_softc_t *sc = v; 1201 uint32_t istatus; 1202 1203 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1204 JME_INTR_STATUS); 1205 if (istatus == 0 || istatus == 0xFFFFFFFF) 1206 return 0; 1207 /* Disable interrupts. */ 1208 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1209 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1210 again: 1211 /* and update istatus */ 1212 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1213 JME_INTR_STATUS); 1214 if ((istatus & JME_INTRS_CHECK) == 0) 1215 goto done; 1216 /* Reset PCC counter/timer and Ack interrupts. */ 1217 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1218 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1219 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1220 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1221 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1222 JME_INTR_STATUS, istatus); 1223 1224 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1225 goto done; 1226 #ifdef JMEDEBUG_RX 1227 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1228 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1229 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1230 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1231 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1232 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1233 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1234 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1235 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1236 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1237 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1238 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1239 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1240 #endif 1241 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1242 jme_intr_rx(sc); 1243 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1244 /* 1245 * Notify hardware availability of new Rx 1246 * buffers. 1247 * Reading RXCSR takes very long time under 1248 * heavy load so cache RXCSR value and writes 1249 * the ORed value with the kick command to 1250 * the RXCSR. This saves one register access 1251 * cycle. 1252 */ 1253 sc->jme_rx_cons = 0; 1254 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1255 JME_RXCSR, 1256 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1257 } 1258 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1259 jme_ifstart(&sc->jme_if); 1260 1261 goto again; 1262 1263 done: 1264 /* enable interrupts. */ 1265 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1266 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1267 return 1; 1268 } 1269 1270 1271 static int 1272 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1273 { 1274 struct jme_softc *sc = ifp->if_softc; 1275 int s, error; 1276 struct ifreq *ifr; 1277 struct ifcapreq *ifcr; 1278 1279 s = splnet(); 1280 /* 1281 * we can't support at the same time jumbo frames and 1282 * TX checksums offload/TSO 1283 */ 1284 switch (cmd) { 1285 case SIOCSIFMTU: 1286 ifr = data; 1287 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1288 (ifp->if_capenable & ( 1289 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1290 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1291 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1292 splx(s); 1293 return EINVAL; 1294 } 1295 break; 1296 case SIOCSIFCAP: 1297 ifcr = data; 1298 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1299 (ifcr->ifcr_capenable & ( 1300 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | 1301 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv6_Tx | 1302 IFCAP_CSUM_UDPv6_Tx | IFCAP_TSOv4 | IFCAP_TSOv6)) != 0) { 1303 splx(s); 1304 return EINVAL; 1305 } 1306 break; 1307 } 1308 1309 error = ether_ioctl(ifp, cmd, data); 1310 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1311 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1312 jme_set_filter(sc); 1313 error = 0; 1314 } else { 1315 error = jme_init(ifp, 0); 1316 } 1317 } 1318 splx(s); 1319 return error; 1320 } 1321 1322 static int 1323 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1324 { 1325 struct jme_desc *desc; 1326 struct mbuf *m; 1327 int error, i, prod, headdsc, nsegs; 1328 uint32_t cflags, tso_segsz; 1329 1330 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) 1331 != 0) { 1332 /* 1333 * Due to the adherence to NDIS specification JMC250 1334 * assumes upper stack computed TCP pseudo checksum 1335 * without including payload length. This breaks 1336 * checksum offload for TSO case so recompute TCP 1337 * pseudo checksum for JMC250. Hopefully this wouldn't 1338 * be much burden on modern CPUs. 1339 */ 1340 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1341 int iphl = v4 ? 1342 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1343 M_CSUM_DATA_IPv6_IPHL((*m_head)->m_pkthdr.csum_data); 1344 /* 1345 * note: we support vlan offloading, so we should never have 1346 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1347 * right. 1348 */ 1349 int hlen = ETHER_HDR_LEN + iphl; 1350 1351 if (__predict_false((*m_head)->m_len < 1352 (hlen + sizeof(struct tcphdr)))) { 1353 /* 1354 * TCP/IP headers are not in the first mbuf; we need 1355 * to do this the slow and painful way. Let's just 1356 * hope this doesn't happen very often. 1357 */ 1358 struct tcphdr th; 1359 1360 m_copydata((*m_head), hlen, sizeof(th), &th); 1361 if (v4) { 1362 struct ip ip; 1363 1364 m_copydata((*m_head), ETHER_HDR_LEN, 1365 sizeof(ip), &ip); 1366 ip.ip_len = 0; 1367 m_copyback((*m_head), 1368 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1369 sizeof(ip.ip_len), &ip.ip_len); 1370 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1371 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1372 } else { 1373 #if INET6 1374 struct ip6_hdr ip6; 1375 1376 m_copydata((*m_head), ETHER_HDR_LEN, 1377 sizeof(ip6), &ip6); 1378 ip6.ip6_plen = 0; 1379 m_copyback((*m_head), ETHER_HDR_LEN + 1380 offsetof(struct ip6_hdr, ip6_plen), 1381 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1382 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1383 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1384 #endif /* INET6 */ 1385 } 1386 m_copyback((*m_head), 1387 hlen + offsetof(struct tcphdr, th_sum), 1388 sizeof(th.th_sum), &th.th_sum); 1389 1390 hlen += th.th_off << 2; 1391 } else { 1392 /* 1393 * TCP/IP headers are in the first mbuf; we can do 1394 * this the easy way. 1395 */ 1396 struct tcphdr *th; 1397 1398 if (v4) { 1399 struct ip *ip = 1400 (void *)(mtod((*m_head), char *) + 1401 ETHER_HDR_LEN); 1402 th = (void *)(mtod((*m_head), char *) + hlen); 1403 1404 ip->ip_len = 0; 1405 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1406 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1407 } else { 1408 #if INET6 1409 struct ip6_hdr *ip6 = 1410 (void *)(mtod((*m_head), char *) + 1411 ETHER_HDR_LEN); 1412 th = (void *)(mtod((*m_head), char *) + hlen); 1413 1414 ip6->ip6_plen = 0; 1415 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1416 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1417 #endif /* INET6 */ 1418 } 1419 hlen += th->th_off << 2; 1420 } 1421 1422 } 1423 1424 prod = sc->jme_tx_prod; 1425 1426 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1427 *m_head, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1428 if (error) { 1429 if (error == EFBIG) { 1430 log(LOG_ERR, "%s: Tx packet consumes too many " 1431 "DMA segments, dropping...\n", 1432 device_xname(sc->jme_dev)); 1433 m_freem(*m_head); 1434 *m_head = NULL; 1435 } 1436 return (error); 1437 } 1438 /* 1439 * Check descriptor overrun. Leave one free descriptor. 1440 * Since we always use 64bit address mode for transmitting, 1441 * each Tx request requires one more dummy descriptor. 1442 */ 1443 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1444 #ifdef JMEDEBUG_TX 1445 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1446 #endif 1447 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1448 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1449 return (ENOBUFS); 1450 } 1451 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1452 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1453 1454 m = *m_head; 1455 cflags = 0; 1456 tso_segsz = 0; 1457 /* Configure checksum offload and TSO. */ 1458 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1459 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1460 cflags |= JME_TD_TSO; 1461 } else { 1462 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1463 cflags |= JME_TD_IPCSUM; 1464 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) 1465 != 0) 1466 cflags |= JME_TD_TCPCSUM; 1467 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) 1468 != 0) 1469 cflags |= JME_TD_UDPCSUM; 1470 } 1471 /* Configure VLAN. */ 1472 if (vlan_has_tag(m)) { 1473 cflags |= (vlan_get_tag(m) & JME_TD_VLAN_MASK); 1474 cflags |= JME_TD_VLAN_TAG; 1475 } 1476 1477 desc = &sc->jme_txring[prod]; 1478 desc->flags = htole32(cflags); 1479 desc->buflen = htole32(tso_segsz); 1480 desc->addr_hi = htole32(m->m_pkthdr.len); 1481 desc->addr_lo = 0; 1482 headdsc = prod; 1483 sc->jme_tx_cnt++; 1484 JME_DESC_INC(prod, JME_NBUFS); 1485 for (i = 0; i < nsegs; i++) { 1486 desc = &sc->jme_txring[prod]; 1487 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1488 desc->buflen = 1489 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1490 desc->addr_hi = htole32( 1491 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1492 desc->addr_lo = htole32( 1493 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1494 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1495 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1496 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1497 sc->jme_txmbuf[prod] = NULL; 1498 sc->jme_tx_cnt++; 1499 JME_DESC_INC(prod, JME_NBUFS); 1500 } 1501 1502 /* Update producer index. */ 1503 sc->jme_tx_prod = prod; 1504 #ifdef JMEDEBUG_TX 1505 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1506 #endif 1507 /* 1508 * Finally request interrupt and give the first descriptor 1509 * ownership to hardware. 1510 */ 1511 desc = &sc->jme_txring[headdsc]; 1512 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1513 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1514 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1515 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1516 1517 sc->jme_txmbuf[headdsc] = m; 1518 return (0); 1519 } 1520 1521 static void 1522 jme_txeof(struct jme_softc *sc) 1523 { 1524 struct ifnet *ifp; 1525 struct jme_desc *desc; 1526 uint32_t status; 1527 int cons, cons0, nsegs, seg; 1528 1529 ifp = &sc->jme_if; 1530 1531 #ifdef JMEDEBUG_TX 1532 printf("jme_txeof cons %d prod %d\n", 1533 sc->jme_tx_cons, sc->jme_tx_prod); 1534 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1535 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1536 "JME_TXTRHD 0x%x\n", 1537 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1538 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1539 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1540 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1541 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1542 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1543 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1544 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1545 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1546 desc = &sc->jme_txring[cons]; 1547 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1548 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1549 JME_DESC_INC(cons, JME_NBUFS); 1550 } 1551 #endif 1552 1553 cons = sc->jme_tx_cons; 1554 if (cons == sc->jme_tx_prod) 1555 return; 1556 1557 /* 1558 * Go through our Tx list and free mbufs for those 1559 * frames which have been transmitted. 1560 */ 1561 for (; cons != sc->jme_tx_prod;) { 1562 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1563 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1564 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1565 1566 desc = &sc->jme_txring[cons]; 1567 status = le32toh(desc->flags); 1568 #ifdef JMEDEBUG_TX 1569 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1570 sc->jme_txmbufm[cons]->dm_nsegs); 1571 #endif 1572 if (status & JME_TD_OWN) 1573 break; 1574 1575 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1576 if_statinc(ifp, if_oerrors); 1577 else { 1578 if_statinc(ifp, if_opackets); 1579 if ((status & JME_TD_COLLISION) != 0) { 1580 if_statadd(ifp, if_collisions, 1581 le32toh(desc->buflen) & 1582 JME_TD_BUF_LEN_MASK); 1583 } 1584 } 1585 /* 1586 * Only the first descriptor of multi-descriptor 1587 * transmission is updated so driver have to skip entire 1588 * chained buffers for the transmitted frame. In other 1589 * words, JME_TD_OWN bit is valid only at the first 1590 * descriptor of a multi-descriptor transmission. 1591 */ 1592 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1593 cons0 = cons; 1594 JME_DESC_INC(cons, JME_NBUFS); 1595 for (seg = 1; seg < nsegs + 1; seg++) { 1596 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1597 cons * sizeof(struct jme_desc), 1598 sizeof(struct jme_desc), 1599 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1600 sc->jme_txring[cons].flags = 0; 1601 JME_DESC_INC(cons, JME_NBUFS); 1602 } 1603 /* Reclaim transferred mbufs. */ 1604 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1605 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1606 BUS_DMASYNC_POSTWRITE); 1607 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1608 1609 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1610 m_freem(sc->jme_txmbuf[cons0]); 1611 sc->jme_txmbuf[cons0] = NULL; 1612 sc->jme_tx_cnt -= nsegs + 1; 1613 KASSERT(sc->jme_tx_cnt >= 0); 1614 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1615 } 1616 sc->jme_tx_cons = cons; 1617 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1618 if (sc->jme_tx_cnt == 0) 1619 ifp->if_timer = 0; 1620 #ifdef JMEDEBUG_TX 1621 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1622 #endif 1623 } 1624 1625 static void 1626 jme_ifstart(struct ifnet *ifp) 1627 { 1628 jme_softc_t *sc = ifp->if_softc; 1629 struct mbuf *mb_head; 1630 int enq; 1631 1632 /* 1633 * check if we can free some desc. 1634 * Clear TX interrupt status to reset TX coalescing counters. 1635 */ 1636 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1637 JME_INTR_STATUS, INTR_TXQ_COMP); 1638 jme_txeof(sc); 1639 1640 if ((sc->jme_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1641 return; 1642 for (enq = 0;; enq++) { 1643 nexttx: 1644 /* Grab a paquet for output */ 1645 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1646 if (mb_head == NULL) { 1647 #ifdef JMEDEBUG_TX 1648 printf("%s: nothing to send\n", __func__); 1649 #endif 1650 break; 1651 } 1652 /* try to add this mbuf to the TX ring */ 1653 if (jme_encap(sc, &mb_head)) { 1654 if (mb_head == NULL) { 1655 if_statinc(ifp, if_oerrors); 1656 /* packet dropped, try next one */ 1657 goto nexttx; 1658 } 1659 /* resource shortage, try again later */ 1660 IF_PREPEND(&ifp->if_snd, mb_head); 1661 ifp->if_flags |= IFF_OACTIVE; 1662 break; 1663 } 1664 /* Pass packet to bpf if there is a listener */ 1665 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1666 } 1667 #ifdef JMEDEBUG_TX 1668 printf("jme_ifstart enq %d\n", enq); 1669 #endif 1670 if (enq) { 1671 /* 1672 * Set a 5 second timer just in case we don't hear from 1673 * the card again. 1674 */ 1675 ifp->if_timer = 5; 1676 /* 1677 * Reading TXCSR takes very long time under heavy load 1678 * so cache TXCSR value and writes the ORed value with 1679 * the kick command to the TXCSR. This saves one register 1680 * access cycle. 1681 */ 1682 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1683 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1684 #ifdef JMEDEBUG_TX 1685 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1686 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1687 "JME_TXTRHD 0x%x\n", 1688 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1689 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1690 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1691 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1692 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1693 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1694 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1695 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1696 #endif 1697 } 1698 } 1699 1700 static void 1701 jme_ifwatchdog(struct ifnet *ifp) 1702 { 1703 jme_softc_t *sc = ifp->if_softc; 1704 1705 if ((ifp->if_flags & IFF_RUNNING) == 0) 1706 return; 1707 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1708 if_statinc(ifp, if_oerrors); 1709 jme_init(ifp, 0); 1710 } 1711 1712 static int 1713 jme_mediachange(struct ifnet *ifp) 1714 { 1715 int error; 1716 jme_softc_t *sc = ifp->if_softc; 1717 1718 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1719 error = 0; 1720 else if (error != 0) { 1721 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1722 return error; 1723 } 1724 return 0; 1725 } 1726 1727 static void 1728 jme_ticks(void *v) 1729 { 1730 jme_softc_t *sc = v; 1731 int s = splnet(); 1732 1733 /* Tick the MII. */ 1734 mii_tick(&sc->jme_mii); 1735 1736 /* every seconds */ 1737 callout_schedule(&sc->jme_tick_ch, hz); 1738 splx(s); 1739 } 1740 1741 static void 1742 jme_mac_config(jme_softc_t *sc) 1743 { 1744 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1745 struct mii_data *mii = &sc->jme_mii; 1746 1747 ghc = 0; 1748 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1749 rxmac &= ~RXMAC_FC_ENB; 1750 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1751 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1752 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1753 txpause &= ~TXPFC_PAUSE_ENB; 1754 1755 if (mii->mii_media_active & IFM_FDX) { 1756 ghc |= GHC_FULL_DUPLEX; 1757 rxmac &= ~RXMAC_COLL_DET_ENB; 1758 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1759 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1760 TXMAC_FRAME_BURST); 1761 /* Disable retry transmit timer/retry limit. */ 1762 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1763 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1764 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1765 } else { 1766 rxmac |= RXMAC_COLL_DET_ENB; 1767 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1768 /* Enable retry transmit timer/retry limit. */ 1769 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1770 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1771 } 1772 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1773 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1774 case IFM_10_T: 1775 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1776 break; 1777 case IFM_100_TX: 1778 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1779 break; 1780 case IFM_1000_T: 1781 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1782 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1783 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1784 break; 1785 default: 1786 break; 1787 } 1788 if ((sc->jme_flags & JME_FLAG_GIGA) && 1789 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1790 /* 1791 * Workaround occasional packet loss issue of JMC250 A2 1792 * when it runs on half-duplex media. 1793 */ 1794 #ifdef JMEDEBUG 1795 printf("JME250 A2 workaround\n"); 1796 #endif 1797 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1798 JME_GPREG1); 1799 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1800 gpreg &= ~GPREG1_HDPX_FIX; 1801 else 1802 gpreg |= GPREG1_HDPX_FIX; 1803 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1804 JME_GPREG1, gpreg); 1805 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1806 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1807 /* Extend interface FIFO depth. */ 1808 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1809 0x1B, 0x0000); 1810 } else { 1811 /* Select default interface FIFO depth. */ 1812 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1813 0x1B, 0x0004); 1814 } 1815 } 1816 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1817 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1818 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1819 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1820 } 1821 1822 static void 1823 jme_set_filter(jme_softc_t *sc) 1824 { 1825 struct ethercom *ec = &sc->jme_ec; 1826 struct ifnet *ifp = &sc->jme_if; 1827 struct ether_multistep step; 1828 struct ether_multi *enm; 1829 uint32_t hash[2] = {0, 0}; 1830 int i; 1831 uint32_t rxcfg; 1832 1833 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1834 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1835 RXMAC_ALLMULTI); 1836 /* Always accept frames destined to our station address. */ 1837 rxcfg |= RXMAC_UNICAST; 1838 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1839 rxcfg |= RXMAC_BROADCAST; 1840 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1841 if ((ifp->if_flags & IFF_PROMISC) != 0) 1842 rxcfg |= RXMAC_PROMISC; 1843 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1844 rxcfg |= RXMAC_ALLMULTI; 1845 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1846 JME_MAR0, 0xFFFFFFFF); 1847 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1848 JME_MAR1, 0xFFFFFFFF); 1849 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1850 JME_RXMAC, rxcfg); 1851 return; 1852 } 1853 /* 1854 * Set up the multicast address filter by passing all multicast 1855 * addresses through a CRC generator, and then using the low-order 1856 * 6 bits as an index into the 64 bit multicast hash table. The 1857 * high order bits select the register, while the rest of the bits 1858 * select the bit within the register. 1859 */ 1860 rxcfg |= RXMAC_MULTICAST; 1861 memset(hash, 0, sizeof(hash)); 1862 1863 ETHER_LOCK(ec); 1864 ETHER_FIRST_MULTI(step, ec, enm); 1865 while (enm != NULL) { 1866 #ifdef JEMDBUG 1867 printf("%s: addrs %s %s\n", __func__, 1868 ether_sprintf(enm->enm_addrlo), 1869 ether_sprintf(enm->enm_addrhi)); 1870 #endif 1871 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1872 i = ether_crc32_be(enm->enm_addrlo, 6); 1873 /* Just want the 6 least significant bits. */ 1874 i &= 0x3f; 1875 hash[i / 32] |= 1 << (i%32); 1876 } else { 1877 hash[0] = hash[1] = 0xffffffff; 1878 sc->jme_if.if_flags |= IFF_ALLMULTI; 1879 break; 1880 } 1881 ETHER_NEXT_MULTI(step, enm); 1882 } 1883 ETHER_UNLOCK(ec); 1884 #ifdef JMEDEBUG 1885 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1886 #endif 1887 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1888 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1889 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1890 } 1891 1892 #if 0 1893 static int 1894 jme_multicast_hash(uint8_t *a) 1895 { 1896 int hash; 1897 1898 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1899 #define xor8(a,b,c,d,e,f,g,h) \ 1900 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1901 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1902 1903 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1904 DA(a,36), DA(a,42)); 1905 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1906 DA(a,37), DA(a,43)) << 1; 1907 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1908 DA(a,38), DA(a,44)) << 2; 1909 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1910 DA(a,39), DA(a,45)) << 3; 1911 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1912 DA(a,40), DA(a,46)) << 4; 1913 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1914 DA(a,41), DA(a,47)) << 5; 1915 1916 return hash; 1917 } 1918 #endif 1919 1920 static int 1921 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1922 { 1923 uint32_t reg; 1924 int i; 1925 1926 *val = 0; 1927 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1928 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1929 JME_SMBCSR); 1930 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1931 break; 1932 delay(10); 1933 } 1934 1935 if (i == 0) { 1936 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1937 return (ETIMEDOUT); 1938 } 1939 1940 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1941 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1942 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1943 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1944 delay(10); 1945 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1946 JME_SMBINTF); 1947 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1948 break; 1949 } 1950 1951 if (i == 0) { 1952 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1953 return (ETIMEDOUT); 1954 } 1955 1956 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1957 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1958 return (0); 1959 } 1960 1961 1962 static int 1963 jme_eeprom_macaddr(struct jme_softc *sc) 1964 { 1965 uint8_t eaddr[ETHER_ADDR_LEN]; 1966 uint8_t fup, reg, val; 1967 uint32_t offset; 1968 int match; 1969 1970 offset = 0; 1971 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1972 fup != JME_EEPROM_SIG0) 1973 return (ENOENT); 1974 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1975 fup != JME_EEPROM_SIG1) 1976 return (ENOENT); 1977 match = 0; 1978 do { 1979 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 1980 break; 1981 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 1982 == (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 1983 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 1984 break; 1985 if (reg >= JME_PAR0 && 1986 reg < JME_PAR0 + ETHER_ADDR_LEN) { 1987 if (jme_eeprom_read_byte(sc, offset + 2, 1988 &val) != 0) 1989 break; 1990 eaddr[reg - JME_PAR0] = val; 1991 match++; 1992 } 1993 } 1994 if (fup & JME_EEPROM_DESC_END) 1995 break; 1996 1997 /* Try next eeprom descriptor. */ 1998 offset += JME_EEPROM_DESC_BYTES; 1999 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2000 2001 if (match == ETHER_ADDR_LEN) { 2002 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2003 return (0); 2004 } 2005 2006 return (ENOENT); 2007 } 2008 2009 static int 2010 jme_reg_macaddr(struct jme_softc *sc) 2011 { 2012 uint32_t par0, par1; 2013 2014 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2015 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2016 par1 &= 0xffff; 2017 if ((par0 == 0 && par1 == 0) || 2018 (par0 == 0xffffffff && par1 == 0xffff)) { 2019 return (ENOENT); 2020 } else { 2021 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2022 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2023 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2024 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2025 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2026 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2027 } 2028 return (0); 2029 } 2030 2031 /* 2032 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2033 * set up in jme_pci_attach() 2034 */ 2035 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2036 { 2037 int rc; 2038 const struct sysctlnode *node; 2039 2040 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2041 0, CTLTYPE_NODE, "jme", 2042 SYSCTL_DESCR("jme interface controls"), 2043 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2044 goto err; 2045 } 2046 2047 jme_root_num = node->sysctl_num; 2048 return; 2049 2050 err: 2051 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2052 } 2053 2054 static int 2055 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2056 { 2057 int error, t; 2058 struct sysctlnode node; 2059 struct jme_softc *sc; 2060 uint32_t reg; 2061 2062 node = *rnode; 2063 sc = node.sysctl_data; 2064 t = sc->jme_intrxto; 2065 node.sysctl_data = &t; 2066 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2067 if (error || newp == NULL) 2068 return error; 2069 2070 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2071 return EINVAL; 2072 2073 /* 2074 * update the softc with sysctl-changed value, and mark 2075 * for hardware update 2076 */ 2077 sc->jme_intrxto = t; 2078 /* Configure Rx queue 0 packet completion coalescing. */ 2079 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2080 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2081 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2082 return 0; 2083 } 2084 2085 static int 2086 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2087 { 2088 int error, t; 2089 struct sysctlnode node; 2090 struct jme_softc *sc; 2091 uint32_t reg; 2092 2093 node = *rnode; 2094 sc = node.sysctl_data; 2095 t = sc->jme_intrxct; 2096 node.sysctl_data = &t; 2097 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2098 if (error || newp == NULL) 2099 return error; 2100 2101 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2102 return EINVAL; 2103 2104 /* 2105 * update the softc with sysctl-changed value, and mark 2106 * for hardware update 2107 */ 2108 sc->jme_intrxct = t; 2109 /* Configure Rx queue 0 packet completion coalescing. */ 2110 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2111 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2112 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2113 return 0; 2114 } 2115 2116 static int 2117 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2118 { 2119 int error, t; 2120 struct sysctlnode node; 2121 struct jme_softc *sc; 2122 uint32_t reg; 2123 2124 node = *rnode; 2125 sc = node.sysctl_data; 2126 t = sc->jme_inttxto; 2127 node.sysctl_data = &t; 2128 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2129 if (error || newp == NULL) 2130 return error; 2131 2132 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2133 return EINVAL; 2134 2135 /* 2136 * update the softc with sysctl-changed value, and mark 2137 * for hardware update 2138 */ 2139 sc->jme_inttxto = t; 2140 /* Configure Tx queue 0 packet completion coalescing. */ 2141 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2142 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2143 reg |= PCCTX_COAL_TXQ0; 2144 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2145 return 0; 2146 } 2147 2148 static int 2149 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2150 { 2151 int error, t; 2152 struct sysctlnode node; 2153 struct jme_softc *sc; 2154 uint32_t reg; 2155 2156 node = *rnode; 2157 sc = node.sysctl_data; 2158 t = sc->jme_inttxct; 2159 node.sysctl_data = &t; 2160 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2161 if (error || newp == NULL) 2162 return error; 2163 2164 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2165 return EINVAL; 2166 2167 /* 2168 * update the softc with sysctl-changed value, and mark 2169 * for hardware update 2170 */ 2171 sc->jme_inttxct = t; 2172 /* Configure Tx queue 0 packet completion coalescing. */ 2173 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2174 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2175 reg |= PCCTX_COAL_TXQ0; 2176 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2177 return 0; 2178 } 2179