1 /* $NetBSD: if_jme.c,v 1.4 2008/10/16 21:22:32 abs Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice unmodified, this list of conditions, and the following 41 * disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 */ 58 59 60 /* 61 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 62 * Ethernet Controllers. 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.4 2008/10/16 21:22:32 abs Exp $"); 67 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/mbuf.h> 72 #include <sys/protosw.h> 73 #include <sys/socket.h> 74 #include <sys/ioctl.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 79 #include <sys/device.h> 80 #include <sys/syslog.h> 81 #include <sys/sysctl.h> 82 83 #include <net/if.h> 84 #if defined(SIOCSIFMEDIA) 85 #include <net/if_media.h> 86 #endif 87 #include <net/if_types.h> 88 #include <net/if_dl.h> 89 #include <net/route.h> 90 #include <net/netisr.h> 91 92 #include "bpfilter.h" 93 #if NBPFILTER > 0 94 #include <net/bpf.h> 95 #include <net/bpfdesc.h> 96 #endif 97 98 #include "rnd.h" 99 #if NRND > 0 100 #include <sys/rnd.h> 101 #endif 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #include <netinet/tcp.h> 109 #endif 110 111 112 #include <net/if_ether.h> 113 #include <uvm/uvm_extern.h> 114 #if defined(INET) 115 #include <netinet/if_inarp.h> 116 #endif 117 118 #include <sys/bus.h> 119 #include <sys/intr.h> 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 #include <dev/pci/if_jmereg.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 129 struct jme_product_desc { 130 u_int32_t jme_product; 131 const char *jme_desc; 132 }; 133 134 /* number of entries in transmit and receive rings */ 135 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 136 137 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 138 139 /* Water mark to kick reclaiming Tx buffers. */ 140 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 141 142 143 struct jme_softc { 144 device_t jme_dev; /* base device */ 145 bus_space_tag_t jme_bt_mac; 146 bus_space_handle_t jme_bh_mac; /* Mac registers */ 147 bus_space_tag_t jme_bt_phy; 148 bus_space_handle_t jme_bh_phy; /* PHY registers */ 149 bus_space_tag_t jme_bt_misc; 150 bus_space_handle_t jme_bh_misc; /* Misc registers */ 151 bus_dma_tag_t jme_dmatag; 152 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 153 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 154 struct jme_desc* jme_txring; /* transmit ring */ 155 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 156 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 157 int jme_tx_cons; /* transmit ring consumer */ 158 int jme_tx_prod; /* transmit ring producer */ 159 int jme_tx_cnt; /* transmit ring active count */ 160 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 161 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 162 struct jme_desc* jme_rxring; /* receive ring */ 163 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 164 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 165 int jme_rx_cons; /* receive ring consumer */ 166 int jme_rx_prod; /* receive ring producer */ 167 void* jme_ih; /* our interrupt */ 168 struct ethercom jme_ec; 169 struct callout jme_tick_ch; /* tick callout */ 170 u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 171 u_int8_t jme_phyaddr; /* address of integrated phy */ 172 u_int8_t jme_chip_rev; /* chip revision */ 173 u_int8_t jme_rev; /* PCI revision */ 174 mii_data_t jme_mii; /* mii bus */ 175 u_int32_t jme_flags; /* device features, see below */ 176 uint32_t jme_txcsr; /* TX config register */ 177 uint32_t jme_rxcsr; /* RX config register */ 178 #if NRND > 0 179 rndsource_element_t rnd_source; 180 #endif 181 /* interrupt coalition parameters */ 182 struct sysctllog *jme_clog; 183 int jme_intrxto; /* interrupt RX timeout */ 184 int jme_intrxct; /* interrupt RX packets counter */ 185 int jme_inttxto; /* interrupt TX timeout */ 186 int jme_inttxct; /* interrupt TX packets counter */ 187 }; 188 189 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 190 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 191 192 193 #define jme_if jme_ec.ec_if 194 #define jme_bpf jme_if.if_bpf 195 196 typedef struct jme_softc jme_softc_t; 197 typedef u_long ioctl_cmd_t; 198 199 static int jme_pci_match(device_t, cfdata_t, void *); 200 static void jme_pci_attach(device_t, device_t, void *); 201 static void jme_intr_rx(jme_softc_t *); 202 static int jme_intr(void *); 203 204 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 205 static int jme_mediachange(struct ifnet *); 206 static void jme_ifwatchdog(struct ifnet *); 207 static void jme_shutdown(void *); 208 209 static void jme_txeof(struct jme_softc *); 210 static void jme_ifstart(struct ifnet *); 211 static void jme_reset(jme_softc_t *); 212 static int jme_ifinit(struct ifnet *); 213 static int jme_init(struct ifnet *, int); 214 static void jme_stop(struct ifnet *, int); 215 // static void jme_restart(void *); 216 static void jme_ticks(void *); 217 static void jme_mac_config(jme_softc_t *); 218 static void jme_set_filter(jme_softc_t *); 219 220 int jme_mii_read(device_t, int, int); 221 void jme_mii_write(device_t, int, int, int); 222 void jme_statchg(device_t); 223 224 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 225 static int jme_eeprom_macaddr(struct jme_softc *); 226 227 #define JME_TIMEOUT 1000 228 #define JME_PHY_TIMEOUT 1000 229 #define JME_EEPROM_TIMEOUT 1000 230 231 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 232 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 233 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 234 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 235 static int jme_root_num; 236 237 238 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 239 jme_pci_match, jme_pci_attach, NULL, NULL); 240 241 static const struct jme_product_desc jme_products[] = { 242 { PCI_PRODUCT_JMICRON_JMC250, 243 "JMicron JMC250 Gigabit Ethernet Controller" }, 244 { PCI_PRODUCT_JMICRON_JMC260, 245 "JMicron JMC260 Gigabit Ethernet Controller" }, 246 { 0, NULL }, 247 }; 248 249 static const struct jme_product_desc *jme_lookup_product(uint32_t); 250 251 static const struct jme_product_desc * 252 jme_lookup_product(uint32_t id) 253 { 254 const struct jme_product_desc *jp; 255 256 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 257 if (PCI_PRODUCT(id) == jp->jme_product) 258 return jp; 259 260 return NULL; 261 } 262 263 static int 264 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 267 268 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 269 return 0; 270 271 if (jme_lookup_product(pa->pa_id) != NULL) 272 return 1; 273 274 return 0; 275 } 276 277 static void 278 jme_pci_attach(device_t parent, device_t self, void *aux) 279 { 280 jme_softc_t *sc = device_private(self); 281 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 282 const struct jme_product_desc *jp; 283 struct ifnet * const ifp = &sc->jme_if; 284 bus_space_tag_t iot1, iot2, memt; 285 bus_space_handle_t ioh1, ioh2, memh; 286 bus_size_t size, size2; 287 pci_intr_handle_t intrhandle; 288 const char *intrstr; 289 pcireg_t csr; 290 int nsegs, i; 291 const struct sysctlnode *node; 292 int jme_nodenum; 293 294 sc->jme_dev = self; 295 aprint_normal("\n"); 296 callout_init(&sc->jme_tick_ch, 0); 297 298 jp = jme_lookup_product(pa->pa_id); 299 if (jp == NULL) 300 panic("jme_pci_attach: impossible"); 301 302 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 303 sc->jme_flags = JME_FLAG_GIGA; 304 305 /* 306 * Map the card space. Try Mem first. 307 */ 308 if (pci_mapreg_map(pa, JME_PCI_BAR0, 309 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 310 0, &memt, &memh, NULL, &size) == 0) { 311 sc->jme_bt_mac = memt; 312 sc->jme_bh_mac = memh; 313 sc->jme_bt_phy = memt; 314 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 315 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 316 aprint_error_dev(self, "can't subregion PHY space\n"); 317 bus_space_unmap(memt, memh, size); 318 return; 319 } 320 sc->jme_bt_misc = memt; 321 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 322 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 323 aprint_error_dev(self, "can't subregion misc space\n"); 324 bus_space_unmap(memt, memh, size); 325 return; 326 } 327 } else { 328 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 329 0, &iot1, &ioh1, NULL, &size) != 0) { 330 aprint_error_dev(self, "can't map I/O space 1\n"); 331 return; 332 } 333 sc->jme_bt_mac = iot1; 334 sc->jme_bh_mac = ioh1; 335 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 336 0, &iot2, &ioh2, NULL, &size2) != 0) { 337 aprint_error_dev(self, "can't map I/O space 2\n"); 338 bus_space_unmap(iot1, ioh1, size); 339 return; 340 } 341 sc->jme_bt_phy = iot2; 342 sc->jme_bh_phy = ioh2; 343 sc->jme_bt_misc = iot2; 344 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 345 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 346 aprint_error_dev(self, "can't subregion misc space\n"); 347 bus_space_unmap(iot1, ioh1, size); 348 bus_space_unmap(iot2, ioh2, size2); 349 return; 350 } 351 } 352 353 if (pci_dma64_available(pa)) 354 sc->jme_dmatag = pa->pa_dmat64; 355 else 356 sc->jme_dmatag = pa->pa_dmat; 357 358 /* Enable the device. */ 359 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 360 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 361 csr | PCI_COMMAND_MASTER_ENABLE); 362 363 aprint_normal_dev(self, "%s\n", jp->jme_desc); 364 365 sc->jme_rev = PCI_REVISION(pa->pa_class); 366 367 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 368 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 369 CHIPMODE_NOT_FPGA) 370 sc->jme_flags |= JME_FLAG_FPGA; 371 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 372 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 373 "0x%x", sc->jme_rev, sc->jme_chip_rev); 374 if (sc->jme_flags & JME_FLAG_FPGA) 375 aprint_verbose(" FPGA revision: 0x%x", 376 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 377 aprint_verbose("\n"); 378 379 /* 380 * Save PHY address. 381 * Integrated JR0211 has fixed PHY address whereas FPGA version 382 * requires PHY probing to get correct PHY address. 383 */ 384 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 385 sc->jme_phyaddr = 386 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 387 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 388 } else 389 sc->jme_phyaddr = 0; 390 391 392 jme_reset(sc); 393 394 /* read mac addr */ 395 if (jme_eeprom_macaddr(sc)) { 396 aprint_error_dev(self, "error reading Ethernet address\n"); 397 /* return; */ 398 } 399 aprint_normal_dev(self, "Ethernet address %s\n", 400 ether_sprintf(sc->jme_enaddr)); 401 402 /* Map and establish interrupts */ 403 if (pci_intr_map(pa, &intrhandle)) { 404 aprint_error_dev(self, "couldn't map interrupt\n"); 405 return; 406 } 407 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 408 sc->jme_if.if_softc = sc; 409 sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 410 jme_intr, sc); 411 if (sc->jme_ih == NULL) { 412 aprint_error_dev(self, "couldn't establish interrupt"); 413 if (intrstr != NULL) 414 aprint_error(" at %s", intrstr); 415 aprint_error("\n"); 416 return; 417 } 418 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 419 420 /* allocate and map DMA-safe memory for transmit ring */ 421 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 422 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 423 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 424 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 425 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 426 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 427 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 428 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 429 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 430 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 431 return; 432 } 433 /* allocate and map DMA-safe memory for receive ring */ 434 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 435 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 436 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 437 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 438 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 439 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 440 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 441 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 442 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 443 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 444 return; 445 } 446 for (i = 0; i < JME_NBUFS; i++) { 447 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 448 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 449 JME_NBUFS, JME_MAX_TX_LEN, 0, BUS_DMA_NOWAIT, 450 &sc->jme_txmbufm[i]) != 0) { 451 aprint_error_dev(self, "can't allocate DMA TX map\n"); 452 return; 453 } 454 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 455 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT, 456 &sc->jme_rxmbufm[i]) != 0) { 457 aprint_error_dev(self, "can't allocate DMA RX map\n"); 458 return; 459 } 460 } 461 /* 462 * Add shutdown hook so that DMA is disabled prior to reboot. 463 */ 464 (void)shutdownhook_establish(jme_shutdown, ifp); 465 466 /* 467 * Initialize our media structures and probe the MII. 468 * 469 * Note that we don't care about the media instance. We 470 * are expecting to have multiple PHYs on the 10/100 cards, 471 * and on those cards we exclude the internal PHY from providing 472 * 10baseT. By ignoring the instance, it allows us to not have 473 * to specify it on the command line when switching media. 474 */ 475 sc->jme_mii.mii_ifp = ifp; 476 sc->jme_mii.mii_readreg = jme_mii_read; 477 sc->jme_mii.mii_writereg = jme_mii_write; 478 sc->jme_mii.mii_statchg = jme_statchg; 479 sc->jme_ec.ec_mii = &sc->jme_mii; 480 ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange, 481 ether_mediastatus); 482 mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY, 483 MII_OFFSET_ANY, 0); 484 if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) { 485 ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 486 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE); 487 } else 488 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO); 489 490 /* 491 * We can support 802.1Q VLAN-sized frames. 492 */ 493 sc->jme_ec.ec_capabilities |= 494 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 495 496 if (sc->jme_flags & JME_FLAG_GIGA) 497 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 498 499 500 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 501 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 502 ifp->if_ioctl = jme_ifioctl; 503 ifp->if_start = jme_ifstart; 504 ifp->if_watchdog = jme_ifwatchdog; 505 ifp->if_init = jme_ifinit; 506 ifp->if_stop = jme_stop; 507 ifp->if_timer = 0; 508 ifp->if_capabilities |= 509 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 510 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 511 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 512 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 513 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 514 IFCAP_TSOv4 | IFCAP_TSOv6; 515 IFQ_SET_READY(&ifp->if_snd); 516 if_attach(ifp); 517 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 518 519 #if NRND > 0 520 rnd_attach_source(&sc->rnd_source, device_xname(self), 521 RND_TYPE_NET, 0); 522 #endif 523 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 524 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 525 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 526 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 527 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 528 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 529 SYSCTL_DESCR("jme per-controller controls"), 530 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 531 CTL_EOL) != 0) { 532 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 533 return; 534 } 535 jme_nodenum = node->sysctl_num; 536 537 /* interrupt moderation sysctls */ 538 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 539 CTLFLAG_READWRITE, 540 CTLTYPE_INT, "int_rxto", 541 SYSCTL_DESCR("jme RX interrupt moderation timer"), 542 jme_sysctl_intrxto, 0, sc, 543 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 544 CTL_EOL) != 0) { 545 aprint_normal_dev(sc->jme_dev, 546 "couldn't create int_rxto sysctl node\n"); 547 } 548 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 549 CTLFLAG_READWRITE, 550 CTLTYPE_INT, "int_rxct", 551 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 552 jme_sysctl_intrxct, 0, sc, 553 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 554 CTL_EOL) != 0) { 555 aprint_normal_dev(sc->jme_dev, 556 "couldn't create int_rxct sysctl node\n"); 557 } 558 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 559 CTLFLAG_READWRITE, 560 CTLTYPE_INT, "int_txto", 561 SYSCTL_DESCR("jme TX interrupt moderation timer"), 562 jme_sysctl_inttxto, 0, sc, 563 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 564 CTL_EOL) != 0) { 565 aprint_normal_dev(sc->jme_dev, 566 "couldn't create int_txto sysctl node\n"); 567 } 568 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 569 CTLFLAG_READWRITE, 570 CTLTYPE_INT, "int_txct", 571 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 572 jme_sysctl_inttxct, 0, sc, 573 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 574 CTL_EOL) != 0) { 575 aprint_normal_dev(sc->jme_dev, 576 "couldn't create int_txct sysctl node\n"); 577 } 578 } 579 580 static void 581 jme_stop_rx(jme_softc_t *sc) 582 { 583 uint32_t reg; 584 int i; 585 586 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 587 if ((reg & RXCSR_RX_ENB) == 0) 588 return; 589 reg &= ~RXCSR_RX_ENB; 590 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 591 for (i = JME_TIMEOUT / 10; i > 0; i--) { 592 DELAY(10); 593 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 594 JME_RXCSR) & RXCSR_RX_ENB) == 0) 595 break; 596 } 597 if (i == 0) 598 aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n"); 599 600 } 601 602 static void 603 jme_stop_tx(jme_softc_t *sc) 604 { 605 uint32_t reg; 606 int i; 607 608 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 609 if ((reg & TXCSR_TX_ENB) == 0) 610 return; 611 reg &= ~TXCSR_TX_ENB; 612 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 613 for (i = JME_TIMEOUT / 10; i > 0; i--) { 614 DELAY(10); 615 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 616 JME_TXCSR) & TXCSR_TX_ENB) == 0) 617 break; 618 } 619 if (i == 0) 620 aprint_error_dev(sc->jme_dev, 621 "stopping transmitter timeout!\n"); 622 } 623 624 static void 625 jme_reset(jme_softc_t *sc) 626 { 627 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 628 DELAY(10); 629 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 630 } 631 632 static void 633 jme_shutdown(void *v) 634 { 635 636 jme_stop(v, 1); 637 } 638 639 static void 640 jme_stop(struct ifnet *ifp, int disable) 641 { 642 jme_softc_t *sc = ifp->if_softc; 643 int i; 644 /* Stop receiver, transmitter. */ 645 jme_stop_rx(sc); 646 jme_stop_tx(sc); 647 /* free receive mbufs */ 648 for (i = 0; i < JME_NBUFS; i++) { 649 if (sc->jme_rxmbuf[i]) { 650 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 651 m_freem(sc->jme_rxmbuf[i]); 652 } 653 sc->jme_rxmbuf[i] = NULL; 654 } 655 /* process completed transmits */ 656 jme_txeof(sc); 657 /* free abort pending transmits */ 658 for (i = 0; i < JME_NBUFS; i++) { 659 if (sc->jme_txmbuf[i]) { 660 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 661 m_freem(sc->jme_txmbuf[i]); 662 sc->jme_txmbuf[i] = NULL; 663 } 664 } 665 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 666 ifp->if_timer = 0; 667 } 668 669 #if 0 670 static void 671 jme_restart(void *v) 672 { 673 674 jme_init(v); 675 } 676 #endif 677 678 static int 679 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 680 { 681 int error; 682 bus_dmamap_t map; 683 int i = sc->jme_rx_prod; 684 685 if (sc->jme_rxmbuf[i] != NULL) { 686 aprint_error_dev(sc->jme_dev, 687 "mbuf already here: rxprod %d rxcons %d\n", 688 sc->jme_rx_prod, sc->jme_rx_cons); 689 if (m) 690 m_freem(m); 691 return EINVAL; 692 } 693 694 if (m == NULL) { 695 sc->jme_rxmbuf[i] = NULL; 696 MGETHDR(m, M_DONTWAIT, MT_DATA); 697 if (m == NULL) 698 return (ENOBUFS); 699 MCLGET(m, M_DONTWAIT); 700 if ((m->m_flags & M_EXT) == 0) { 701 m_freem(m); 702 return (ENOBUFS); 703 } 704 } 705 map = sc->jme_rxmbufm[i]; 706 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 707 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 708 BUS_DMA_READ|BUS_DMA_NOWAIT); 709 if (error) { 710 sc->jme_rxmbuf[i] = NULL; 711 aprint_error_dev(sc->jme_dev, 712 "unable to load rx DMA map %d, error = %d\n", 713 i, error); 714 m_freem(m); 715 return (error); 716 } 717 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 718 BUS_DMASYNC_PREREAD); 719 720 sc->jme_rxmbuf[i] = m; 721 722 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 723 sc->jme_rxring[i].addr_lo = 724 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 725 sc->jme_rxring[i].addr_hi = 726 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 727 sc->jme_rxring[i].flags = 728 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 729 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 730 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 732 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 733 return (0); 734 } 735 736 static int 737 jme_ifinit(struct ifnet *ifp) 738 { 739 return jme_init(ifp, 1); 740 } 741 742 static int 743 jme_init(struct ifnet *ifp, int do_ifinit) 744 { 745 jme_softc_t *sc = ifp->if_softc; 746 int i, s; 747 uint8_t eaddr[ETHER_ADDR_LEN]; 748 uint32_t reg; 749 750 s = splnet(); 751 /* cancel any pending IO */ 752 jme_stop(ifp, 1); 753 jme_reset(sc); 754 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 755 splx(s); 756 return 0; 757 } 758 /* allocate receive ring */ 759 sc->jme_rx_prod = 0; 760 for (i = 0; i < JME_NBUFS; i++) { 761 if (jme_add_rxbuf(sc, NULL) < 0) { 762 aprint_error_dev(sc->jme_dev, 763 "can't allocate rx mbuf\n"); 764 for (i--; i >= 0; i--) { 765 bus_dmamap_unload(sc->jme_dmatag, 766 sc->jme_rxmbufm[i]); 767 m_freem(sc->jme_rxmbuf[i]); 768 sc->jme_rxmbuf[i] = NULL; 769 } 770 splx(s); 771 return ENOMEM; 772 } 773 } 774 /* init TX ring */ 775 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 776 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 777 0, JME_NBUFS * sizeof(struct jme_desc), 778 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 779 for (i = 0; i < JME_NBUFS; i++) 780 sc->jme_txmbuf[i] = NULL; 781 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 782 783 /* Reprogram the station address. */ 784 bcopy(CLLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 785 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 786 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 787 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 788 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 789 790 /* 791 * Configure Tx queue. 792 * Tx priority queue weight value : 0 793 * Tx FIFO threshold for processing next packet : 16QW 794 * Maximum Tx DMA length : 512 795 * Allow Tx DMA burst. 796 */ 797 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 798 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 799 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 800 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 801 sc->jme_txcsr |= TXCSR_DMA_BURST; 802 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 803 JME_TXCSR, sc->jme_txcsr); 804 805 /* Set Tx descriptor counter. */ 806 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 807 JME_TXQDC, JME_NBUFS); 808 809 /* Set Tx ring address to the hardware. */ 810 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 811 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 812 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 813 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 814 815 /* Configure TxMAC parameters. */ 816 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 817 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 818 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 819 820 /* 821 * Configure Rx queue. 822 * FIFO full threshold for transmitting Tx pause packet : 128T 823 * FIFO threshold for processing next packet : 128QW 824 * Rx queue 0 select 825 * Max Rx DMA length : 128 826 * Rx descriptor retry : 32 827 * Rx descriptor retry time gap : 256ns 828 * Don't receive runt/bad frame. 829 */ 830 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 831 /* 832 * Since Rx FIFO size is 4K bytes, receiving frames larger 833 * than 4K bytes will suffer from Rx FIFO overruns. So 834 * decrease FIFO threshold to reduce the FIFO overruns for 835 * frames larger than 4000 bytes. 836 * For best performance of standard MTU sized frames use 837 * maximum allowable FIFO threshold, 128QW. 838 */ 839 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 840 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 841 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 842 else 843 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 844 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 845 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 846 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 847 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 848 JME_RXCSR, sc->jme_rxcsr); 849 850 /* Set Rx descriptor counter. */ 851 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 852 JME_RXQDC, JME_NBUFS); 853 854 /* Set Rx ring address to the hardware. */ 855 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 856 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 857 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 858 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 859 860 /* Clear receive filter. */ 861 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 862 /* Set up the receive filter. */ 863 jme_set_filter(sc); 864 865 /* 866 * Disable all WOL bits as WOL can interfere normal Rx 867 * operation. Also clear WOL detection status bits. 868 */ 869 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 870 reg &= ~PMCS_WOL_ENB_MASK; 871 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 872 873 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 874 /* 875 * Pad 10bytes right before received frame. This will greatly 876 * help Rx performance on strict-alignment architectures as 877 * it does not need to copy the frame to align the payload. 878 */ 879 reg |= RXMAC_PAD_10BYTES; 880 if ((ifp->if_capenable & 881 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx| 882 IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0) 883 reg |= RXMAC_CSUM_ENB; 884 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 885 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 886 887 /* Configure general purpose reg0 */ 888 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 889 reg &= ~GPREG0_PCC_UNIT_MASK; 890 /* Set PCC timer resolution to micro-seconds unit. */ 891 reg |= GPREG0_PCC_UNIT_US; 892 /* 893 * Disable all shadow register posting as we have to read 894 * JME_INTR_STATUS register in jme_int_task. Also it seems 895 * that it's hard to synchronize interrupt status between 896 * hardware and software with shadow posting due to 897 * requirements of bus_dmamap_sync(9). 898 */ 899 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 900 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 901 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 902 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 903 /* Disable posting of DW0. */ 904 reg &= ~GPREG0_POST_DW0_ENB; 905 /* Clear PME message. */ 906 reg &= ~GPREG0_PME_ENB; 907 /* Set PHY address. */ 908 reg &= ~GPREG0_PHY_ADDR_MASK; 909 reg |= sc->jme_phyaddr; 910 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 911 912 /* Configure Tx queue 0 packet completion coalescing. */ 913 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 914 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 915 reg |= PCCTX_COAL_TXQ0; 916 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 917 918 /* Configure Rx queue 0 packet completion coalescing. */ 919 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 920 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 921 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 922 923 /* Disable Timer 1 and Timer 2. */ 924 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 925 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 926 927 /* Configure retry transmit period, retry limit value. */ 928 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 929 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 930 TXTRHD_RT_PERIOD_MASK) | 931 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 932 TXTRHD_RT_LIMIT_SHIFT)); 933 934 /* Disable RSS. */ 935 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 936 JME_RSSC, RSSC_DIS_RSS); 937 938 /* Initialize the interrupt mask. */ 939 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 940 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 941 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 942 JME_INTR_STATUS, 0xFFFFFFFF); 943 944 /* set media, if not already handling a media change */ 945 if (do_ifinit) { 946 int error; 947 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 948 error = 0; 949 else if (error != 0) { 950 aprint_error_dev(sc->jme_dev, "could not set media\n"); 951 return error; 952 } 953 } 954 955 /* Program MAC with resolved speed/duplex/flow-control. */ 956 jme_mac_config(sc); 957 958 /* Start receiver/transmitter. */ 959 sc->jme_rx_cons = 0; 960 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 961 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 962 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 963 sc->jme_txcsr | TXCSR_TX_ENB); 964 965 /* start ticks calls */ 966 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 967 sc->jme_if.if_flags |= IFF_RUNNING; 968 sc->jme_if.if_flags &= ~IFF_OACTIVE; 969 splx(s); 970 return 0; 971 } 972 973 974 int 975 jme_mii_read(device_t self, int phy, int reg) 976 { 977 struct jme_softc *sc = device_private(self); 978 int val, i; 979 980 /* For FPGA version, PHY address 0 should be ignored. */ 981 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 982 if (phy == 0) 983 return (0); 984 } else { 985 if (sc->jme_phyaddr != phy) 986 return (0); 987 } 988 989 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 990 SMI_OP_READ | SMI_OP_EXECUTE | 991 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 992 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 993 delay(10); 994 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 995 JME_SMI)) & SMI_OP_EXECUTE) == 0) 996 break; 997 } 998 999 if (i == 0) { 1000 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 1001 return (0); 1002 } 1003 1004 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 1005 } 1006 1007 void 1008 jme_mii_write(device_t self, int phy, int reg, int val) 1009 { 1010 struct jme_softc *sc = device_private(self); 1011 int i; 1012 1013 /* For FPGA version, PHY address 0 should be ignored. */ 1014 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1015 if (phy == 0) 1016 return; 1017 } else { 1018 if (sc->jme_phyaddr != phy) 1019 return; 1020 } 1021 1022 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1023 SMI_OP_WRITE | SMI_OP_EXECUTE | 1024 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1025 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1026 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1027 delay(10); 1028 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1029 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1030 break; 1031 } 1032 1033 if (i == 0) 1034 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1035 1036 return; 1037 } 1038 1039 void 1040 jme_statchg(device_t self) 1041 { 1042 jme_softc_t *sc = device_private(self); 1043 struct ifnet *ifp = &sc->jme_if; 1044 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) 1045 jme_init(ifp, 0); 1046 } 1047 1048 static void 1049 jme_intr_rx(jme_softc_t *sc) { 1050 struct mbuf *m, *mhead; 1051 struct ifnet *ifp = &sc->jme_if; 1052 uint32_t flags, buflen; 1053 int i, ipackets, nsegs, seg, error; 1054 struct jme_desc *desc; 1055 1056 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1057 sizeof(struct jme_desc) * JME_NBUFS, 1058 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1059 #ifdef JMEDEBUG_RX 1060 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1061 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1062 #endif 1063 ipackets = 0; 1064 while((le32toh(sc->jme_rxring[ sc->jme_rx_cons].flags) & JME_RD_OWN) 1065 == 0) { 1066 i = sc->jme_rx_cons; 1067 desc = &sc->jme_rxring[i]; 1068 #ifdef JMEDEBUG_RX 1069 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1070 i, le32toh(desc->flags), le32toh(desc->buflen)); 1071 #endif 1072 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1073 break; 1074 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmbufm[i], 0, 1075 sc->jme_rxmbufm[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); 1076 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 1077 1078 buflen = le32toh(desc->buflen); 1079 nsegs = JME_RX_NSEGS(buflen); 1080 flags = le32toh(desc->flags); 1081 if ((buflen & JME_RX_ERR_STAT) != 0 || 1082 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1083 JME_RX_BYTES(buflen) > 1084 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1085 #ifdef JMEDEBUG_RX 1086 printf("rx error flags 0x%x buflen 0x%x\n", 1087 flags, buflen); 1088 #endif 1089 ifp->if_ierrors++; 1090 /* reuse the mbufs */ 1091 for (seg = 0; seg < nsegs; seg++) { 1092 m = sc->jme_rxmbuf[i]; 1093 sc->jme_rxmbuf[i] = NULL; 1094 if ((error = jme_add_rxbuf(sc, m)) != 0) 1095 aprint_error_dev(sc->jme_dev, 1096 "can't reuse mbuf: %d\n", error); 1097 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1098 i = sc->jme_rx_cons; 1099 } 1100 continue; 1101 } 1102 /* receive this packet */ 1103 mhead = m = sc->jme_rxmbuf[i]; 1104 sc->jme_rxmbuf[i] = NULL; 1105 /* add a new buffer to chain */ 1106 if (jme_add_rxbuf(sc, NULL) == ENOBUFS) { 1107 for (seg = 0; seg < nsegs; seg++) { 1108 m = sc->jme_rxmbuf[i]; 1109 sc->jme_rxmbuf[i] = NULL; 1110 if ((error = jme_add_rxbuf(sc, m)) != 0) 1111 aprint_error_dev(sc->jme_dev, 1112 "can't reuse mbuf: %d\n", error); 1113 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1114 i = sc->jme_rx_cons; 1115 } 1116 ifp->if_ierrors++; 1117 continue; 1118 } 1119 1120 /* build mbuf chain: head, then remaining segments */ 1121 m->m_pkthdr.rcvif = ifp; 1122 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1123 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1124 m->m_pkthdr.len; 1125 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1126 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1127 for (seg = 1; seg < nsegs; seg++) { 1128 i = sc->jme_rx_cons; 1129 m = sc->jme_rxmbuf[i]; 1130 sc->jme_rxmbuf[i] = NULL; 1131 (void)jme_add_rxbuf(sc, NULL); 1132 m->m_flags &= ~M_PKTHDR; 1133 m_cat(mhead, m); 1134 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1135 } 1136 /* and adjust last mbuf's size */ 1137 if (nsegs > 1) { 1138 m->m_len = 1139 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1140 } 1141 ifp->if_ipackets++; 1142 ipackets++; 1143 #if NBPFILTER > 0 1144 if (ifp->if_bpf) 1145 bpf_mtap(ifp->if_bpf, mhead); 1146 #endif /* NBPFILTER > 0 */ 1147 1148 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1149 (flags & JME_RD_IPV4)) { 1150 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1151 if (!(flags & JME_RD_IPCSUM)) 1152 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1153 } 1154 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1155 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1156 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1157 if (!(flags & JME_RD_TCPCSUM)) 1158 mhead->m_pkthdr.csum_flags |= 1159 M_CSUM_TCP_UDP_BAD; 1160 } 1161 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1162 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1163 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1164 if (!(flags & JME_RD_UDPCSUM)) 1165 mhead->m_pkthdr.csum_flags |= 1166 M_CSUM_TCP_UDP_BAD; 1167 } 1168 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1169 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1170 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1171 if (!(flags & JME_RD_TCPCSUM)) 1172 mhead->m_pkthdr.csum_flags |= 1173 M_CSUM_TCP_UDP_BAD; 1174 } 1175 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1176 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1177 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1178 if (!(flags & JME_RD_UDPCSUM)) 1179 mhead->m_pkthdr.csum_flags |= 1180 M_CSUM_TCP_UDP_BAD; 1181 } 1182 if (flags & JME_RD_VLAN_TAG) { 1183 /* pass to vlan_input() */ 1184 VLAN_INPUT_TAG(ifp, mhead, 1185 (flags & JME_RD_VLAN_MASK), continue); 1186 } 1187 (*ifp->if_input)(ifp, mhead); 1188 } 1189 #if NRND > 0 1190 if (ipackets && RND_ENABLED(&sc->rnd_source)) 1191 rnd_add_uint32(&sc->rnd_source, ipackets); 1192 #endif /* NRND > 0 */ 1193 1194 } 1195 1196 static int 1197 jme_intr(void *v) 1198 { 1199 jme_softc_t *sc = v; 1200 uint32_t istatus; 1201 1202 again: 1203 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1204 JME_INTR_STATUS); 1205 1206 if ((istatus & JME_INTRS_CHECK) == 0 || istatus == 0xFFFFFFFF) 1207 goto done; 1208 /* Reset PCC counter/timer and Ack interrupts. */ 1209 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1210 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1211 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1212 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1213 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1214 JME_INTR_STATUS, istatus); 1215 1216 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1217 goto done; 1218 #ifdef JMEDEBUG_RX 1219 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1220 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1221 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1222 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1223 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1224 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1225 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1226 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1227 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1228 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1229 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1230 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1231 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1232 #endif 1233 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1234 jme_intr_rx(sc); 1235 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1236 /* 1237 * Notify hardware availability of new Rx 1238 * buffers. 1239 * Reading RXCSR takes very long time under 1240 * heavy load so cache RXCSR value and writes 1241 * the ORed value with the kick command to 1242 * the RXCSR. This saves one register access 1243 * cycle. 1244 */ 1245 sc->jme_rx_cons = 0; 1246 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1247 JME_RXCSR, 1248 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1249 } 1250 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1251 jme_ifstart(&sc->jme_if); 1252 1253 goto again; 1254 1255 done: 1256 return 1; 1257 } 1258 1259 1260 static int 1261 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1262 { 1263 struct jme_softc *sc = ifp->if_softc; 1264 int s, error; 1265 struct ifreq *ifr; 1266 struct ifcapreq *ifcr; 1267 1268 s = splnet(); 1269 /* 1270 * we can't support at the same time jumbo frames and 1271 * TX checksums offload/TSO 1272 */ 1273 switch(cmd) { 1274 case SIOCSIFMTU: 1275 ifr = data; 1276 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1277 (ifp->if_capenable & ( 1278 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1279 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1280 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1281 splx(s); 1282 return EINVAL; 1283 } 1284 break; 1285 case SIOCSIFCAP: 1286 ifcr = data; 1287 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1288 (ifcr->ifcr_capenable & ( 1289 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1290 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1291 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1292 splx(s); 1293 return EINVAL; 1294 } 1295 break; 1296 } 1297 1298 error = ether_ioctl(ifp, cmd, data); 1299 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1300 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1301 jme_set_filter(sc); 1302 error = 0; 1303 } else { 1304 error = jme_init(ifp, 0); 1305 } 1306 } 1307 splx(s); 1308 return error; 1309 } 1310 1311 static int 1312 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1313 { 1314 struct jme_desc *txd; 1315 struct jme_desc *desc; 1316 struct mbuf *m; 1317 struct m_tag *mtag; 1318 int error, i, prod, headdsc, nsegs; 1319 uint32_t cflags, tso_segsz; 1320 1321 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){ 1322 /* 1323 * Due to the adherence to NDIS specification JMC250 1324 * assumes upper stack computed TCP pseudo checksum 1325 * without including payload length. This breaks 1326 * checksum offload for TSO case so recompute TCP 1327 * pseudo checksum for JMC250. Hopefully this wouldn't 1328 * be much burden on modern CPUs. 1329 */ 1330 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1331 int iphl = v4 ? 1332 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1333 M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data); 1334 /* 1335 * note: we support vlan offloading, so we should never have 1336 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1337 * right. 1338 */ 1339 int hlen = ETHER_HDR_LEN + iphl; 1340 1341 if (__predict_false((*m_head)->m_len < 1342 (hlen + sizeof(struct tcphdr)))) { 1343 /* 1344 * TCP/IP headers are not in the first mbuf; we need 1345 * to do this the slow and painful way. Let's just 1346 * hope this doesn't happen very often. 1347 */ 1348 struct tcphdr th; 1349 1350 m_copydata((*m_head), hlen, sizeof(th), &th); 1351 if (v4) { 1352 struct ip ip; 1353 1354 m_copydata((*m_head), ETHER_HDR_LEN, 1355 sizeof(ip), &ip); 1356 ip.ip_len = 0; 1357 m_copyback((*m_head), 1358 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1359 sizeof(ip.ip_len), &ip.ip_len); 1360 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1361 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1362 } else { 1363 #if INET6 1364 struct ip6_hdr ip6; 1365 1366 m_copydata((*m_head), ETHER_HDR_LEN, 1367 sizeof(ip6), &ip6); 1368 ip6.ip6_plen = 0; 1369 m_copyback((*m_head), ETHER_HDR_LEN + 1370 offsetof(struct ip6_hdr, ip6_plen), 1371 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1372 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1373 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1374 #endif /* INET6 */ 1375 } 1376 m_copyback((*m_head), 1377 hlen + offsetof(struct tcphdr, th_sum), 1378 sizeof(th.th_sum), &th.th_sum); 1379 1380 hlen += th.th_off << 2; 1381 } else { 1382 /* 1383 * TCP/IP headers are in the first mbuf; we can do 1384 * this the easy way. 1385 */ 1386 struct tcphdr *th; 1387 1388 if (v4) { 1389 struct ip *ip = 1390 (void *)(mtod((*m_head), char *) + 1391 ETHER_HDR_LEN); 1392 th = (void *)(mtod((*m_head), char *) + hlen); 1393 1394 ip->ip_len = 0; 1395 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1396 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1397 } else { 1398 #if INET6 1399 struct ip6_hdr *ip6 = 1400 (void *)(mtod((*m_head), char *) + 1401 ETHER_HDR_LEN); 1402 th = (void *)(mtod((*m_head), char *) + hlen); 1403 1404 ip6->ip6_plen = 0; 1405 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1406 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1407 #endif /* INET6 */ 1408 } 1409 hlen += th->th_off << 2; 1410 } 1411 1412 } 1413 1414 prod = sc->jme_tx_prod; 1415 txd = &sc->jme_txring[prod]; 1416 1417 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1418 *m_head, BUS_DMA_WRITE); 1419 if (error) { 1420 if (error == EFBIG) { 1421 log(LOG_ERR, "%s: Tx packet consumes too many " 1422 "DMA segments, dropping...\n", 1423 device_xname(sc->jme_dev)); 1424 m_freem(*m_head); 1425 m_head = NULL; 1426 } 1427 return (error); 1428 } 1429 /* 1430 * Check descriptor overrun. Leave one free descriptor. 1431 * Since we always use 64bit address mode for transmitting, 1432 * each Tx request requires one more dummy descriptor. 1433 */ 1434 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1435 #ifdef JMEDEBUG_TX 1436 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1437 #endif 1438 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1439 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1440 return (ENOBUFS); 1441 } 1442 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1443 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1444 1445 m = *m_head; 1446 cflags = 0; 1447 tso_segsz = 0; 1448 /* Configure checksum offload and TSO. */ 1449 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) { 1450 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1451 cflags |= JME_TD_TSO; 1452 } else { 1453 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1454 cflags |= JME_TD_IPCSUM; 1455 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0) 1456 cflags |= JME_TD_TCPCSUM; 1457 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0) 1458 cflags |= JME_TD_UDPCSUM; 1459 } 1460 /* Configure VLAN. */ 1461 if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) { 1462 cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); 1463 cflags |= JME_TD_VLAN_TAG; 1464 } 1465 1466 desc = &sc->jme_txring[prod]; 1467 desc->flags = htole32(cflags); 1468 desc->buflen = htole32(tso_segsz); 1469 desc->addr_hi = htole32(m->m_pkthdr.len); 1470 desc->addr_lo = 0; 1471 headdsc = prod; 1472 sc->jme_tx_cnt++; 1473 JME_DESC_INC(prod, JME_NBUFS); 1474 for (i = 0; i < nsegs; i++) { 1475 desc = &sc->jme_txring[prod]; 1476 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1477 desc->buflen = 1478 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1479 desc->addr_hi = htole32( 1480 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1481 desc->addr_lo = htole32( 1482 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1483 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1484 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1486 sc->jme_txmbuf[prod] = NULL; 1487 sc->jme_tx_cnt++; 1488 JME_DESC_INC(prod, JME_NBUFS); 1489 } 1490 1491 /* Update producer index. */ 1492 sc->jme_tx_prod = prod; 1493 #ifdef JMEDEBUG_TX 1494 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1495 #endif 1496 /* 1497 * Finally request interrupt and give the first descriptor 1498 * owenership to hardware. 1499 */ 1500 desc = &sc->jme_txring[headdsc]; 1501 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1502 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1503 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1505 1506 sc->jme_txmbuf[headdsc] = m; 1507 return (0); 1508 } 1509 1510 static void 1511 jme_txeof(struct jme_softc *sc) 1512 { 1513 struct ifnet *ifp; 1514 struct jme_desc *desc; 1515 uint32_t status; 1516 int cons, cons0, nsegs, seg; 1517 1518 ifp = &sc->jme_if; 1519 1520 #ifdef JMEDEBUG_TX 1521 printf("jme_txeof cons %d prod %d\n", 1522 sc->jme_tx_cons, sc->jme_tx_prod); 1523 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1524 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1525 "JME_TXTRHD 0x%x\n", 1526 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1527 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1528 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1529 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1530 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1531 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1532 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1533 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1534 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1535 desc = &sc->jme_txring[cons]; 1536 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1537 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1538 JME_DESC_INC(cons, JME_NBUFS); 1539 } 1540 #endif 1541 1542 cons = sc->jme_tx_cons; 1543 if (cons == sc->jme_tx_prod) 1544 return; 1545 1546 /* 1547 * Go through our Tx list and free mbufs for those 1548 * frames which have been transmitted. 1549 */ 1550 for (; cons != sc->jme_tx_prod;) { 1551 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1552 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1553 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1554 1555 desc = &sc->jme_txring[cons]; 1556 status = le32toh(desc->flags); 1557 #ifdef JMEDEBUG_TX 1558 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1559 sc->jme_txmbufm[cons]->dm_nsegs); 1560 #endif 1561 if (status & JME_TD_OWN) 1562 break; 1563 1564 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1565 ifp->if_oerrors++; 1566 else { 1567 ifp->if_opackets++; 1568 if ((status & JME_TD_COLLISION) != 0) 1569 ifp->if_collisions += 1570 le32toh(desc->buflen) & 1571 JME_TD_BUF_LEN_MASK; 1572 } 1573 /* 1574 * Only the first descriptor of multi-descriptor 1575 * transmission is updated so driver have to skip entire 1576 * chained buffers for the transmiited frame. In other 1577 * words, JME_TD_OWN bit is valid only at the first 1578 * descriptor of a multi-descriptor transmission. 1579 */ 1580 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1581 cons0 = cons; 1582 JME_DESC_INC(cons, JME_NBUFS); 1583 for (seg = 1; seg < nsegs + 1; seg++) { 1584 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1585 cons * sizeof(struct jme_desc), 1586 sizeof(struct jme_desc), 1587 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1588 sc->jme_txring[cons].flags = 0; 1589 JME_DESC_INC(cons, JME_NBUFS); 1590 } 1591 /* Reclaim transferred mbufs. */ 1592 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1593 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1594 BUS_DMASYNC_POSTWRITE); 1595 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1596 1597 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1598 m_freem(sc->jme_txmbuf[cons0]); 1599 sc->jme_txmbuf[cons0] = NULL; 1600 sc->jme_tx_cnt -= nsegs + 1; 1601 KASSERT(sc->jme_tx_cnt >= 0); 1602 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1603 } 1604 sc->jme_tx_cons = cons; 1605 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1606 if (sc->jme_tx_cnt == 0) 1607 ifp->if_timer = 0; 1608 #ifdef JMEDEBUG_TX 1609 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1610 #endif 1611 } 1612 1613 static void 1614 jme_ifstart(struct ifnet *ifp) 1615 { 1616 jme_softc_t *sc = ifp->if_softc; 1617 struct mbuf *mb_head; 1618 int enq; 1619 1620 /* 1621 * check if we can free some desc. 1622 * Clear TX interrupt status to reset TX coalescing counters. 1623 */ 1624 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1625 JME_INTR_STATUS, INTR_TXQ_COMP); 1626 jme_txeof(sc); 1627 1628 if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1629 return; 1630 for (enq = 0;; enq++) { 1631 nexttx: 1632 /* Grab a paquet for output */ 1633 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1634 if (mb_head == NULL) { 1635 #ifdef JMEDEBUG_TX 1636 printf("%s: nothing to send\n", __func__); 1637 #endif 1638 break; 1639 } 1640 /* try to add this mbuf to the TX ring */ 1641 if (jme_encap(sc, &mb_head)) { 1642 if (mb_head == NULL) { 1643 ifp->if_oerrors++; 1644 /* packet dropped, try next one */ 1645 goto nexttx; 1646 } 1647 /* resource shortage, try again later */ 1648 IF_PREPEND(&ifp->if_snd, mb_head); 1649 ifp->if_flags |= IFF_OACTIVE; 1650 break; 1651 } 1652 #if NBPFILTER > 0 1653 /* Pass packet to bpf if there is a listener */ 1654 if (ifp->if_bpf) 1655 bpf_mtap(ifp->if_bpf, mb_head); 1656 #endif 1657 } 1658 #ifdef JMEDEBUG_TX 1659 printf("jme_ifstart enq %d\n", enq); 1660 #endif 1661 if (enq) { 1662 /* 1663 * Set a 5 second timer just in case we don't hear from 1664 * the card again. 1665 */ 1666 ifp->if_timer = 5; 1667 /* 1668 * Reading TXCSR takes very long time under heavy load 1669 * so cache TXCSR value and writes the ORed value with 1670 * the kick command to the TXCSR. This saves one register 1671 * access cycle. 1672 */ 1673 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1674 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1675 #ifdef JMEDEBUG_TX 1676 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1677 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1678 "JME_TXTRHD 0x%x\n", 1679 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1680 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1681 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1682 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1683 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1684 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1685 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1686 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1687 #endif 1688 } 1689 } 1690 1691 static void 1692 jme_ifwatchdog(struct ifnet *ifp) 1693 { 1694 jme_softc_t *sc = ifp->if_softc; 1695 1696 if ((ifp->if_flags & IFF_RUNNING) == 0) 1697 return; 1698 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1699 ifp->if_oerrors++; 1700 jme_init(ifp, 0); 1701 } 1702 1703 static int 1704 jme_mediachange(struct ifnet *ifp) 1705 { 1706 int error; 1707 jme_softc_t *sc = ifp->if_softc; 1708 1709 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1710 error = 0; 1711 else if (error != 0) { 1712 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1713 return error; 1714 } 1715 return 0; 1716 } 1717 1718 static void 1719 jme_ticks(void *v) 1720 { 1721 jme_softc_t *sc = v; 1722 int s = splnet(); 1723 1724 /* Tick the MII. */ 1725 mii_tick(&sc->jme_mii); 1726 1727 /* every seconds */ 1728 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1729 splx(s); 1730 } 1731 1732 static void 1733 jme_mac_config(jme_softc_t *sc) 1734 { 1735 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1736 struct mii_data *mii = &sc->jme_mii; 1737 1738 ghc = 0; 1739 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1740 rxmac &= ~RXMAC_FC_ENB; 1741 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1742 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1743 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1744 txpause &= ~TXPFC_PAUSE_ENB; 1745 1746 if (mii->mii_media_active & IFM_FDX) { 1747 ghc |= GHC_FULL_DUPLEX; 1748 rxmac &= ~RXMAC_COLL_DET_ENB; 1749 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1750 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1751 TXMAC_FRAME_BURST); 1752 /* Disable retry transmit timer/retry limit. */ 1753 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1754 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1755 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1756 } else { 1757 rxmac |= RXMAC_COLL_DET_ENB; 1758 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1759 /* Enable retry transmit timer/retry limit. */ 1760 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1761 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1762 } 1763 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1764 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1765 case IFM_10_T: 1766 ghc |= GHC_SPEED_10; 1767 break; 1768 case IFM_100_TX: 1769 ghc |= GHC_SPEED_100; 1770 break; 1771 case IFM_1000_T: 1772 ghc |= GHC_SPEED_1000; 1773 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1774 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1775 break; 1776 default: 1777 break; 1778 } 1779 if ((sc->jme_flags & JME_FLAG_GIGA) && 1780 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1781 /* 1782 * Workaround occasional packet loss issue of JMC250 A2 1783 * when it runs on half-duplex media. 1784 */ 1785 #ifdef JMEDEBUG 1786 printf("JME250 A2 workaround\n"); 1787 #endif 1788 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1789 JME_GPREG1); 1790 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1791 gpreg &= ~GPREG1_HDPX_FIX; 1792 else 1793 gpreg |= GPREG1_HDPX_FIX; 1794 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1795 JME_GPREG1, gpreg); 1796 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1797 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1798 /* Extend interface FIFO depth. */ 1799 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1800 0x1B, 0x0000); 1801 } else { 1802 /* Select default interface FIFO depth. */ 1803 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1804 0x1B, 0x0004); 1805 } 1806 } 1807 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1808 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1809 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1810 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1811 } 1812 1813 static void 1814 jme_set_filter(jme_softc_t *sc) 1815 { 1816 struct ifnet *ifp = &sc->jme_if; 1817 struct ether_multistep step; 1818 struct ether_multi *enm; 1819 uint32_t hash[2] = {0, 0}; 1820 int i; 1821 uint32_t rxcfg; 1822 1823 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1824 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1825 RXMAC_ALLMULTI); 1826 /* Always accept frames destined to our station address. */ 1827 rxcfg |= RXMAC_UNICAST; 1828 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1829 rxcfg |= RXMAC_BROADCAST; 1830 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1831 if ((ifp->if_flags & IFF_PROMISC) != 0) 1832 rxcfg |= RXMAC_PROMISC; 1833 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1834 rxcfg |= RXMAC_ALLMULTI; 1835 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1836 JME_MAR0, 0xFFFFFFFF); 1837 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1838 JME_MAR1, 0xFFFFFFFF); 1839 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1840 JME_RXMAC, rxcfg); 1841 return; 1842 } 1843 /* 1844 * Set up the multicast address filter by passing all multicast 1845 * addresses through a CRC generator, and then using the low-order 1846 * 6 bits as an index into the 64 bit multicast hash table. The 1847 * high order bits select the register, while the rest of the bits 1848 * select the bit within the register. 1849 */ 1850 rxcfg |= RXMAC_MULTICAST; 1851 bzero(hash, sizeof(hash)); 1852 1853 ETHER_FIRST_MULTI(step, &sc->jme_ec, enm); 1854 while (enm != NULL) { 1855 #ifdef JEMDBUG 1856 printf("%s: addrs %s %s\n", __func__, 1857 ether_sprintf(enm->enm_addrlo), 1858 ether_sprintf(enm->enm_addrhi)); 1859 #endif 1860 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1861 i = ether_crc32_be(enm->enm_addrlo, 6); 1862 /* Just want the 6 least significant bits. */ 1863 i &= 0x3f; 1864 hash[i / 32] |= 1 << (i%32); 1865 } else { 1866 hash[0] = hash[1] = 0xffffffff; 1867 sc->jme_if.if_flags |= IFF_ALLMULTI; 1868 break; 1869 } 1870 ETHER_NEXT_MULTI(step, enm); 1871 } 1872 #ifdef JMEDEBUG 1873 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1874 #endif 1875 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1876 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1877 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1878 } 1879 1880 #if 0 1881 static int 1882 jme_multicast_hash(uint8_t *a) 1883 { 1884 int hash; 1885 1886 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1887 #define xor8(a,b,c,d,e,f,g,h) \ 1888 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1889 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1890 1891 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1892 DA(a,36), DA(a,42)); 1893 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1894 DA(a,37), DA(a,43)) << 1; 1895 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1896 DA(a,38), DA(a,44)) << 2; 1897 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1898 DA(a,39), DA(a,45)) << 3; 1899 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1900 DA(a,40), DA(a,46)) << 4; 1901 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1902 DA(a,41), DA(a,47)) << 5; 1903 1904 return hash; 1905 } 1906 #endif 1907 1908 static int 1909 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1910 { 1911 uint32_t reg; 1912 int i; 1913 1914 *val = 0; 1915 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1916 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1917 JME_SMBCSR); 1918 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1919 break; 1920 delay(10); 1921 } 1922 1923 if (i == 0) { 1924 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1925 return (ETIMEDOUT); 1926 } 1927 1928 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1929 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1930 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1931 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1932 delay(10); 1933 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1934 JME_SMBINTF); 1935 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1936 break; 1937 } 1938 1939 if (i == 0) { 1940 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1941 return (ETIMEDOUT); 1942 } 1943 1944 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1945 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1946 return (0); 1947 } 1948 1949 1950 static int 1951 jme_eeprom_macaddr(struct jme_softc *sc) 1952 { 1953 uint8_t eaddr[ETHER_ADDR_LEN]; 1954 uint8_t fup, reg, val; 1955 uint32_t offset; 1956 int match; 1957 1958 offset = 0; 1959 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1960 fup != JME_EEPROM_SIG0) 1961 return (ENOENT); 1962 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1963 fup != JME_EEPROM_SIG1) 1964 return (ENOENT); 1965 match = 0; 1966 do { 1967 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 1968 break; 1969 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 1970 == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) { 1971 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 1972 break; 1973 if (reg >= JME_PAR0 && 1974 reg < JME_PAR0 + ETHER_ADDR_LEN) { 1975 if (jme_eeprom_read_byte(sc, offset + 2, 1976 &val) != 0) 1977 break; 1978 eaddr[reg - JME_PAR0] = val; 1979 match++; 1980 } 1981 } 1982 if (fup & JME_EEPROM_DESC_END) 1983 break; 1984 1985 /* Try next eeprom descriptor. */ 1986 offset += JME_EEPROM_DESC_BYTES; 1987 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 1988 1989 if (match == ETHER_ADDR_LEN) { 1990 bcopy(eaddr, sc->jme_enaddr, ETHER_ADDR_LEN); 1991 return (0); 1992 } 1993 1994 return (ENOENT); 1995 } 1996 1997 /* 1998 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 1999 * set up in jme_pci_attach() 2000 */ 2001 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2002 { 2003 int rc; 2004 const struct sysctlnode *node; 2005 2006 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2007 0, CTLTYPE_NODE, "hw", NULL, 2008 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2009 goto err; 2010 } 2011 2012 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2013 0, CTLTYPE_NODE, "jme", 2014 SYSCTL_DESCR("jme interface controls"), 2015 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2016 goto err; 2017 } 2018 2019 jme_root_num = node->sysctl_num; 2020 return; 2021 2022 err: 2023 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2024 } 2025 2026 static int 2027 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2028 { 2029 int error, t; 2030 struct sysctlnode node; 2031 struct jme_softc *sc; 2032 uint32_t reg; 2033 2034 node = *rnode; 2035 sc = node.sysctl_data; 2036 t = sc->jme_intrxto; 2037 node.sysctl_data = &t; 2038 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2039 if (error || newp == NULL) 2040 return error; 2041 2042 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2043 return EINVAL; 2044 2045 /* 2046 * update the softc with sysctl-changed value, and mark 2047 * for hardware update 2048 */ 2049 sc->jme_intrxto = t; 2050 /* Configure Rx queue 0 packet completion coalescing. */ 2051 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2052 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2053 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2054 return 0; 2055 } 2056 2057 static int 2058 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2059 { 2060 int error, t; 2061 struct sysctlnode node; 2062 struct jme_softc *sc; 2063 uint32_t reg; 2064 2065 node = *rnode; 2066 sc = node.sysctl_data; 2067 t = sc->jme_intrxct; 2068 node.sysctl_data = &t; 2069 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2070 if (error || newp == NULL) 2071 return error; 2072 2073 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2074 return EINVAL; 2075 2076 /* 2077 * update the softc with sysctl-changed value, and mark 2078 * for hardware update 2079 */ 2080 sc->jme_intrxct = t; 2081 /* Configure Rx queue 0 packet completion coalescing. */ 2082 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2083 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2084 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2085 return 0; 2086 } 2087 2088 static int 2089 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2090 { 2091 int error, t; 2092 struct sysctlnode node; 2093 struct jme_softc *sc; 2094 uint32_t reg; 2095 2096 node = *rnode; 2097 sc = node.sysctl_data; 2098 t = sc->jme_inttxto; 2099 node.sysctl_data = &t; 2100 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2101 if (error || newp == NULL) 2102 return error; 2103 2104 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2105 return EINVAL; 2106 2107 /* 2108 * update the softc with sysctl-changed value, and mark 2109 * for hardware update 2110 */ 2111 sc->jme_inttxto = t; 2112 /* Configure Tx queue 0 packet completion coalescing. */ 2113 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2114 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2115 reg |= PCCTX_COAL_TXQ0; 2116 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2117 return 0; 2118 } 2119 2120 static int 2121 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2122 { 2123 int error, t; 2124 struct sysctlnode node; 2125 struct jme_softc *sc; 2126 uint32_t reg; 2127 2128 node = *rnode; 2129 sc = node.sysctl_data; 2130 t = sc->jme_inttxct; 2131 node.sysctl_data = &t; 2132 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2133 if (error || newp == NULL) 2134 return error; 2135 2136 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2137 return EINVAL; 2138 2139 /* 2140 * update the softc with sysctl-changed value, and mark 2141 * for hardware update 2142 */ 2143 sc->jme_inttxct = t; 2144 /* Configure Tx queue 0 packet completion coalescing. */ 2145 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2146 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2147 reg |= PCCTX_COAL_TXQ0; 2148 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2149 return 0; 2150 } 2151