1 /* $NetBSD: if_jme.c,v 1.17 2011/03/30 18:11:37 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 54 55 /* 56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 57 * Ethernet Controllers. 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.17 2011/03/30 18:11:37 bouyer Exp $"); 62 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/mbuf.h> 67 #include <sys/protosw.h> 68 #include <sys/socket.h> 69 #include <sys/ioctl.h> 70 #include <sys/errno.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 74 #include <sys/device.h> 75 #include <sys/syslog.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #if defined(SIOCSIFMEDIA) 80 #include <net/if_media.h> 81 #endif 82 #include <net/if_types.h> 83 #include <net/if_dl.h> 84 #include <net/route.h> 85 #include <net/netisr.h> 86 87 #include <net/bpf.h> 88 #include <net/bpfdesc.h> 89 90 #include "rnd.h" 91 #if NRND > 0 92 #include <sys/rnd.h> 93 #endif 94 95 #include <netinet/in.h> 96 #include <netinet/in_systm.h> 97 #include <netinet/ip.h> 98 99 #ifdef INET 100 #include <netinet/in_var.h> 101 #endif 102 103 #include <netinet/tcp.h> 104 105 #include <net/if_ether.h> 106 #if defined(INET) 107 #include <netinet/if_inarp.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 #include <dev/pci/if_jmereg.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 struct jme_product_desc { 122 u_int32_t jme_product; 123 const char *jme_desc; 124 }; 125 126 /* number of entries in transmit and receive rings */ 127 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 128 129 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 130 131 /* Water mark to kick reclaiming Tx buffers. */ 132 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 133 134 135 struct jme_softc { 136 device_t jme_dev; /* base device */ 137 bus_space_tag_t jme_bt_mac; 138 bus_space_handle_t jme_bh_mac; /* Mac registers */ 139 bus_space_tag_t jme_bt_phy; 140 bus_space_handle_t jme_bh_phy; /* PHY registers */ 141 bus_space_tag_t jme_bt_misc; 142 bus_space_handle_t jme_bh_misc; /* Misc registers */ 143 bus_dma_tag_t jme_dmatag; 144 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 145 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 146 struct jme_desc* jme_txring; /* transmit ring */ 147 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 148 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 149 int jme_tx_cons; /* transmit ring consumer */ 150 int jme_tx_prod; /* transmit ring producer */ 151 int jme_tx_cnt; /* transmit ring active count */ 152 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 153 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 154 struct jme_desc* jme_rxring; /* receive ring */ 155 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 156 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 157 int jme_rx_cons; /* receive ring consumer */ 158 int jme_rx_prod; /* receive ring producer */ 159 void* jme_ih; /* our interrupt */ 160 struct ethercom jme_ec; 161 struct callout jme_tick_ch; /* tick callout */ 162 u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 163 u_int8_t jme_phyaddr; /* address of integrated phy */ 164 u_int8_t jme_chip_rev; /* chip revision */ 165 u_int8_t jme_rev; /* PCI revision */ 166 mii_data_t jme_mii; /* mii bus */ 167 u_int32_t jme_flags; /* device features, see below */ 168 uint32_t jme_txcsr; /* TX config register */ 169 uint32_t jme_rxcsr; /* RX config register */ 170 #if NRND > 0 171 rndsource_element_t rnd_source; 172 #endif 173 /* interrupt coalition parameters */ 174 struct sysctllog *jme_clog; 175 int jme_intrxto; /* interrupt RX timeout */ 176 int jme_intrxct; /* interrupt RX packets counter */ 177 int jme_inttxto; /* interrupt TX timeout */ 178 int jme_inttxct; /* interrupt TX packets counter */ 179 }; 180 181 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 182 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 183 184 185 #define jme_if jme_ec.ec_if 186 #define jme_bpf jme_if.if_bpf 187 188 typedef struct jme_softc jme_softc_t; 189 typedef u_long ioctl_cmd_t; 190 191 static int jme_pci_match(device_t, cfdata_t, void *); 192 static void jme_pci_attach(device_t, device_t, void *); 193 static void jme_intr_rx(jme_softc_t *); 194 static int jme_intr(void *); 195 196 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 197 static int jme_mediachange(struct ifnet *); 198 static void jme_ifwatchdog(struct ifnet *); 199 static bool jme_shutdown(device_t, int); 200 201 static void jme_txeof(struct jme_softc *); 202 static void jme_ifstart(struct ifnet *); 203 static void jme_reset(jme_softc_t *); 204 static int jme_ifinit(struct ifnet *); 205 static int jme_init(struct ifnet *, int); 206 static void jme_stop(struct ifnet *, int); 207 // static void jme_restart(void *); 208 static void jme_ticks(void *); 209 static void jme_mac_config(jme_softc_t *); 210 static void jme_set_filter(jme_softc_t *); 211 212 int jme_mii_read(device_t, int, int); 213 void jme_mii_write(device_t, int, int, int); 214 void jme_statchg(device_t); 215 216 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 217 static int jme_eeprom_macaddr(struct jme_softc *); 218 static int jme_reg_macaddr(struct jme_softc *); 219 220 #define JME_TIMEOUT 1000 221 #define JME_PHY_TIMEOUT 1000 222 #define JME_EEPROM_TIMEOUT 1000 223 224 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 225 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 226 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 227 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 228 static int jme_root_num; 229 230 231 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 232 jme_pci_match, jme_pci_attach, NULL, NULL); 233 234 static const struct jme_product_desc jme_products[] = { 235 { PCI_PRODUCT_JMICRON_JMC250, 236 "JMicron JMC250 Gigabit Ethernet Controller" }, 237 { PCI_PRODUCT_JMICRON_JMC260, 238 "JMicron JMC260 Gigabit Ethernet Controller" }, 239 { 0, NULL }, 240 }; 241 242 static const struct jme_product_desc *jme_lookup_product(uint32_t); 243 244 static const struct jme_product_desc * 245 jme_lookup_product(uint32_t id) 246 { 247 const struct jme_product_desc *jp; 248 249 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 250 if (PCI_PRODUCT(id) == jp->jme_product) 251 return jp; 252 253 return NULL; 254 } 255 256 static int 257 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 258 { 259 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 260 261 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 262 return 0; 263 264 if (jme_lookup_product(pa->pa_id) != NULL) 265 return 1; 266 267 return 0; 268 } 269 270 static void 271 jme_pci_attach(device_t parent, device_t self, void *aux) 272 { 273 jme_softc_t *sc = device_private(self); 274 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 275 const struct jme_product_desc *jp; 276 struct ifnet * const ifp = &sc->jme_if; 277 bus_space_tag_t iot1, iot2, memt; 278 bus_space_handle_t ioh1, ioh2, memh; 279 bus_size_t size, size2; 280 pci_intr_handle_t intrhandle; 281 const char *intrstr; 282 pcireg_t csr; 283 int nsegs, i; 284 const struct sysctlnode *node; 285 int jme_nodenum; 286 287 sc->jme_dev = self; 288 aprint_normal("\n"); 289 callout_init(&sc->jme_tick_ch, 0); 290 291 jp = jme_lookup_product(pa->pa_id); 292 if (jp == NULL) 293 panic("jme_pci_attach: impossible"); 294 295 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 296 sc->jme_flags = JME_FLAG_GIGA; 297 298 /* 299 * Map the card space. Try Mem first. 300 */ 301 if (pci_mapreg_map(pa, JME_PCI_BAR0, 302 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 303 0, &memt, &memh, NULL, &size) == 0) { 304 sc->jme_bt_mac = memt; 305 sc->jme_bh_mac = memh; 306 sc->jme_bt_phy = memt; 307 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 308 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 309 aprint_error_dev(self, "can't subregion PHY space\n"); 310 bus_space_unmap(memt, memh, size); 311 return; 312 } 313 sc->jme_bt_misc = memt; 314 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 315 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 316 aprint_error_dev(self, "can't subregion misc space\n"); 317 bus_space_unmap(memt, memh, size); 318 return; 319 } 320 } else { 321 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 322 0, &iot1, &ioh1, NULL, &size) != 0) { 323 aprint_error_dev(self, "can't map I/O space 1\n"); 324 return; 325 } 326 sc->jme_bt_mac = iot1; 327 sc->jme_bh_mac = ioh1; 328 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 329 0, &iot2, &ioh2, NULL, &size2) != 0) { 330 aprint_error_dev(self, "can't map I/O space 2\n"); 331 bus_space_unmap(iot1, ioh1, size); 332 return; 333 } 334 sc->jme_bt_phy = iot2; 335 sc->jme_bh_phy = ioh2; 336 sc->jme_bt_misc = iot2; 337 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 338 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 339 aprint_error_dev(self, "can't subregion misc space\n"); 340 bus_space_unmap(iot1, ioh1, size); 341 bus_space_unmap(iot2, ioh2, size2); 342 return; 343 } 344 } 345 346 if (pci_dma64_available(pa)) 347 sc->jme_dmatag = pa->pa_dmat64; 348 else 349 sc->jme_dmatag = pa->pa_dmat; 350 351 /* Enable the device. */ 352 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 353 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 354 csr | PCI_COMMAND_MASTER_ENABLE); 355 356 aprint_normal_dev(self, "%s\n", jp->jme_desc); 357 358 sc->jme_rev = PCI_REVISION(pa->pa_class); 359 360 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 361 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 362 CHIPMODE_NOT_FPGA) 363 sc->jme_flags |= JME_FLAG_FPGA; 364 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 365 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 366 "0x%x", sc->jme_rev, sc->jme_chip_rev); 367 if (sc->jme_flags & JME_FLAG_FPGA) 368 aprint_verbose(" FPGA revision: 0x%x", 369 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 370 aprint_verbose("\n"); 371 372 /* 373 * Save PHY address. 374 * Integrated JR0211 has fixed PHY address whereas FPGA version 375 * requires PHY probing to get correct PHY address. 376 */ 377 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 378 sc->jme_phyaddr = 379 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 380 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 381 } else 382 sc->jme_phyaddr = 0; 383 384 385 jme_reset(sc); 386 387 /* read mac addr */ 388 if (jme_eeprom_macaddr(sc) && jme_reg_macaddr(sc)) { 389 aprint_error_dev(self, "error reading Ethernet address\n"); 390 /* return; */ 391 } 392 aprint_normal_dev(self, "Ethernet address %s\n", 393 ether_sprintf(sc->jme_enaddr)); 394 395 /* Map and establish interrupts */ 396 if (pci_intr_map(pa, &intrhandle)) { 397 aprint_error_dev(self, "couldn't map interrupt\n"); 398 return; 399 } 400 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 401 sc->jme_if.if_softc = sc; 402 sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 403 jme_intr, sc); 404 if (sc->jme_ih == NULL) { 405 aprint_error_dev(self, "couldn't establish interrupt"); 406 if (intrstr != NULL) 407 aprint_error(" at %s", intrstr); 408 aprint_error("\n"); 409 return; 410 } 411 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 412 413 /* allocate and map DMA-safe memory for transmit ring */ 414 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 415 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 416 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 417 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 418 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 419 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 420 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 421 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 422 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 423 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 424 return; 425 } 426 /* allocate and map DMA-safe memory for receive ring */ 427 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 428 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 429 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 430 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 431 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 432 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 433 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 434 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 435 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 436 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 437 return; 438 } 439 for (i = 0; i < JME_NBUFS; i++) { 440 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 441 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 442 JME_NBUFS, JME_MAX_TX_LEN, 0, 443 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 444 &sc->jme_txmbufm[i]) != 0) { 445 aprint_error_dev(self, "can't allocate DMA TX map\n"); 446 return; 447 } 448 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 449 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 450 &sc->jme_rxmbufm[i]) != 0) { 451 aprint_error_dev(self, "can't allocate DMA RX map\n"); 452 return; 453 } 454 } 455 /* 456 * Initialize our media structures and probe the MII. 457 * 458 * Note that we don't care about the media instance. We 459 * are expecting to have multiple PHYs on the 10/100 cards, 460 * and on those cards we exclude the internal PHY from providing 461 * 10baseT. By ignoring the instance, it allows us to not have 462 * to specify it on the command line when switching media. 463 */ 464 sc->jme_mii.mii_ifp = ifp; 465 sc->jme_mii.mii_readreg = jme_mii_read; 466 sc->jme_mii.mii_writereg = jme_mii_write; 467 sc->jme_mii.mii_statchg = jme_statchg; 468 sc->jme_ec.ec_mii = &sc->jme_mii; 469 ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange, 470 ether_mediastatus); 471 mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY, 472 MII_OFFSET_ANY, 0); 473 if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) { 474 ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 475 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE); 476 } else 477 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO); 478 479 /* 480 * We can support 802.1Q VLAN-sized frames. 481 */ 482 sc->jme_ec.ec_capabilities |= 483 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 484 485 if (sc->jme_flags & JME_FLAG_GIGA) 486 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 487 488 489 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 490 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 491 ifp->if_ioctl = jme_ifioctl; 492 ifp->if_start = jme_ifstart; 493 ifp->if_watchdog = jme_ifwatchdog; 494 ifp->if_init = jme_ifinit; 495 ifp->if_stop = jme_stop; 496 ifp->if_timer = 0; 497 ifp->if_capabilities |= 498 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 499 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 500 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 501 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 502 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 503 IFCAP_TSOv4 | IFCAP_TSOv6; 504 IFQ_SET_READY(&ifp->if_snd); 505 if_attach(ifp); 506 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 507 508 /* 509 * Add shutdown hook so that DMA is disabled prior to reboot. 510 */ 511 if (pmf_device_register1(self, NULL, NULL, jme_shutdown)) 512 pmf_class_network_register(self, ifp); 513 else 514 aprint_error_dev(self, "couldn't establish power handler\n"); 515 516 #if NRND > 0 517 rnd_attach_source(&sc->rnd_source, device_xname(self), 518 RND_TYPE_NET, 0); 519 #endif 520 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 521 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 522 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 523 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 524 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 525 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 526 SYSCTL_DESCR("jme per-controller controls"), 527 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 528 CTL_EOL) != 0) { 529 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 530 return; 531 } 532 jme_nodenum = node->sysctl_num; 533 534 /* interrupt moderation sysctls */ 535 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 536 CTLFLAG_READWRITE, 537 CTLTYPE_INT, "int_rxto", 538 SYSCTL_DESCR("jme RX interrupt moderation timer"), 539 jme_sysctl_intrxto, 0, sc, 540 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 541 CTL_EOL) != 0) { 542 aprint_normal_dev(sc->jme_dev, 543 "couldn't create int_rxto sysctl node\n"); 544 } 545 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 546 CTLFLAG_READWRITE, 547 CTLTYPE_INT, "int_rxct", 548 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 549 jme_sysctl_intrxct, 0, sc, 550 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 551 CTL_EOL) != 0) { 552 aprint_normal_dev(sc->jme_dev, 553 "couldn't create int_rxct sysctl node\n"); 554 } 555 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 556 CTLFLAG_READWRITE, 557 CTLTYPE_INT, "int_txto", 558 SYSCTL_DESCR("jme TX interrupt moderation timer"), 559 jme_sysctl_inttxto, 0, sc, 560 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 561 CTL_EOL) != 0) { 562 aprint_normal_dev(sc->jme_dev, 563 "couldn't create int_txto sysctl node\n"); 564 } 565 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 566 CTLFLAG_READWRITE, 567 CTLTYPE_INT, "int_txct", 568 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 569 jme_sysctl_inttxct, 0, sc, 570 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 571 CTL_EOL) != 0) { 572 aprint_normal_dev(sc->jme_dev, 573 "couldn't create int_txct sysctl node\n"); 574 } 575 } 576 577 static void 578 jme_stop_rx(jme_softc_t *sc) 579 { 580 uint32_t reg; 581 int i; 582 583 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 584 if ((reg & RXCSR_RX_ENB) == 0) 585 return; 586 reg &= ~RXCSR_RX_ENB; 587 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 588 for (i = JME_TIMEOUT / 10; i > 0; i--) { 589 DELAY(10); 590 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 591 JME_RXCSR) & RXCSR_RX_ENB) == 0) 592 break; 593 } 594 if (i == 0) 595 aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n"); 596 597 } 598 599 static void 600 jme_stop_tx(jme_softc_t *sc) 601 { 602 uint32_t reg; 603 int i; 604 605 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 606 if ((reg & TXCSR_TX_ENB) == 0) 607 return; 608 reg &= ~TXCSR_TX_ENB; 609 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 610 for (i = JME_TIMEOUT / 10; i > 0; i--) { 611 DELAY(10); 612 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 613 JME_TXCSR) & TXCSR_TX_ENB) == 0) 614 break; 615 } 616 if (i == 0) 617 aprint_error_dev(sc->jme_dev, 618 "stopping transmitter timeout!\n"); 619 } 620 621 static void 622 jme_reset(jme_softc_t *sc) 623 { 624 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 625 DELAY(10); 626 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 627 } 628 629 static bool 630 jme_shutdown(device_t self, int howto) 631 { 632 jme_softc_t *sc; 633 struct ifnet *ifp; 634 635 sc = device_private(self); 636 ifp = &sc->jme_if; 637 jme_stop(ifp, 1); 638 639 return true; 640 } 641 642 static void 643 jme_stop(struct ifnet *ifp, int disable) 644 { 645 jme_softc_t *sc = ifp->if_softc; 646 int i; 647 /* Stop receiver, transmitter. */ 648 jme_stop_rx(sc); 649 jme_stop_tx(sc); 650 /* free receive mbufs */ 651 for (i = 0; i < JME_NBUFS; i++) { 652 if (sc->jme_rxmbuf[i]) { 653 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 654 m_freem(sc->jme_rxmbuf[i]); 655 } 656 sc->jme_rxmbuf[i] = NULL; 657 } 658 /* process completed transmits */ 659 jme_txeof(sc); 660 /* free abort pending transmits */ 661 for (i = 0; i < JME_NBUFS; i++) { 662 if (sc->jme_txmbuf[i]) { 663 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 664 m_freem(sc->jme_txmbuf[i]); 665 sc->jme_txmbuf[i] = NULL; 666 } 667 } 668 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 669 ifp->if_timer = 0; 670 } 671 672 #if 0 673 static void 674 jme_restart(void *v) 675 { 676 677 jme_init(v); 678 } 679 #endif 680 681 static int 682 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 683 { 684 int error; 685 bus_dmamap_t map; 686 int i = sc->jme_rx_prod; 687 688 if (sc->jme_rxmbuf[i] != NULL) { 689 aprint_error_dev(sc->jme_dev, 690 "mbuf already here: rxprod %d rxcons %d\n", 691 sc->jme_rx_prod, sc->jme_rx_cons); 692 if (m) 693 m_freem(m); 694 return EINVAL; 695 } 696 697 if (m == NULL) { 698 sc->jme_rxmbuf[i] = NULL; 699 MGETHDR(m, M_DONTWAIT, MT_DATA); 700 if (m == NULL) 701 return (ENOBUFS); 702 MCLGET(m, M_DONTWAIT); 703 if ((m->m_flags & M_EXT) == 0) { 704 m_freem(m); 705 return (ENOBUFS); 706 } 707 } 708 map = sc->jme_rxmbufm[i]; 709 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 710 KASSERT(m->m_len == MCLBYTES); 711 712 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 713 BUS_DMA_READ|BUS_DMA_NOWAIT); 714 if (error) { 715 sc->jme_rxmbuf[i] = NULL; 716 aprint_error_dev(sc->jme_dev, 717 "unable to load rx DMA map %d, error = %d\n", 718 i, error); 719 m_freem(m); 720 return (error); 721 } 722 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 723 BUS_DMASYNC_PREREAD); 724 725 sc->jme_rxmbuf[i] = m; 726 727 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 728 sc->jme_rxring[i].addr_lo = 729 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 730 sc->jme_rxring[i].addr_hi = 731 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 732 sc->jme_rxring[i].flags = 733 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 734 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 735 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 737 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 738 return (0); 739 } 740 741 static int 742 jme_ifinit(struct ifnet *ifp) 743 { 744 return jme_init(ifp, 1); 745 } 746 747 static int 748 jme_init(struct ifnet *ifp, int do_ifinit) 749 { 750 jme_softc_t *sc = ifp->if_softc; 751 int i, s; 752 uint8_t eaddr[ETHER_ADDR_LEN]; 753 uint32_t reg; 754 755 s = splnet(); 756 /* cancel any pending IO */ 757 jme_stop(ifp, 1); 758 jme_reset(sc); 759 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 760 splx(s); 761 return 0; 762 } 763 /* allocate receive ring */ 764 sc->jme_rx_prod = 0; 765 for (i = 0; i < JME_NBUFS; i++) { 766 if (jme_add_rxbuf(sc, NULL) < 0) { 767 aprint_error_dev(sc->jme_dev, 768 "can't allocate rx mbuf\n"); 769 for (i--; i >= 0; i--) { 770 bus_dmamap_unload(sc->jme_dmatag, 771 sc->jme_rxmbufm[i]); 772 m_freem(sc->jme_rxmbuf[i]); 773 sc->jme_rxmbuf[i] = NULL; 774 } 775 splx(s); 776 return ENOMEM; 777 } 778 } 779 /* init TX ring */ 780 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 781 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 782 0, JME_NBUFS * sizeof(struct jme_desc), 783 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 784 for (i = 0; i < JME_NBUFS; i++) 785 sc->jme_txmbuf[i] = NULL; 786 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 787 788 /* Reprogram the station address. */ 789 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 790 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 791 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 792 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 793 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 794 795 /* 796 * Configure Tx queue. 797 * Tx priority queue weight value : 0 798 * Tx FIFO threshold for processing next packet : 16QW 799 * Maximum Tx DMA length : 512 800 * Allow Tx DMA burst. 801 */ 802 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 803 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 804 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 805 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 806 sc->jme_txcsr |= TXCSR_DMA_BURST; 807 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 808 JME_TXCSR, sc->jme_txcsr); 809 810 /* Set Tx descriptor counter. */ 811 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 812 JME_TXQDC, JME_NBUFS); 813 814 /* Set Tx ring address to the hardware. */ 815 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 816 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 817 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 818 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 819 820 /* Configure TxMAC parameters. */ 821 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 822 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 823 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 824 825 /* 826 * Configure Rx queue. 827 * FIFO full threshold for transmitting Tx pause packet : 128T 828 * FIFO threshold for processing next packet : 128QW 829 * Rx queue 0 select 830 * Max Rx DMA length : 128 831 * Rx descriptor retry : 32 832 * Rx descriptor retry time gap : 256ns 833 * Don't receive runt/bad frame. 834 */ 835 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 836 /* 837 * Since Rx FIFO size is 4K bytes, receiving frames larger 838 * than 4K bytes will suffer from Rx FIFO overruns. So 839 * decrease FIFO threshold to reduce the FIFO overruns for 840 * frames larger than 4000 bytes. 841 * For best performance of standard MTU sized frames use 842 * maximum allowable FIFO threshold, 128QW. 843 */ 844 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 845 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 846 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 847 else 848 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 849 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 850 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 851 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 852 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 853 JME_RXCSR, sc->jme_rxcsr); 854 855 /* Set Rx descriptor counter. */ 856 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 857 JME_RXQDC, JME_NBUFS); 858 859 /* Set Rx ring address to the hardware. */ 860 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 861 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 862 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 863 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 864 865 /* Clear receive filter. */ 866 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 867 /* Set up the receive filter. */ 868 jme_set_filter(sc); 869 870 /* 871 * Disable all WOL bits as WOL can interfere normal Rx 872 * operation. Also clear WOL detection status bits. 873 */ 874 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 875 reg &= ~PMCS_WOL_ENB_MASK; 876 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 877 878 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 879 /* 880 * Pad 10bytes right before received frame. This will greatly 881 * help Rx performance on strict-alignment architectures as 882 * it does not need to copy the frame to align the payload. 883 */ 884 reg |= RXMAC_PAD_10BYTES; 885 if ((ifp->if_capenable & 886 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx| 887 IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0) 888 reg |= RXMAC_CSUM_ENB; 889 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 890 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 891 892 /* Configure general purpose reg0 */ 893 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 894 reg &= ~GPREG0_PCC_UNIT_MASK; 895 /* Set PCC timer resolution to micro-seconds unit. */ 896 reg |= GPREG0_PCC_UNIT_US; 897 /* 898 * Disable all shadow register posting as we have to read 899 * JME_INTR_STATUS register in jme_int_task. Also it seems 900 * that it's hard to synchronize interrupt status between 901 * hardware and software with shadow posting due to 902 * requirements of bus_dmamap_sync(9). 903 */ 904 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 905 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 906 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 907 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 908 /* Disable posting of DW0. */ 909 reg &= ~GPREG0_POST_DW0_ENB; 910 /* Clear PME message. */ 911 reg &= ~GPREG0_PME_ENB; 912 /* Set PHY address. */ 913 reg &= ~GPREG0_PHY_ADDR_MASK; 914 reg |= sc->jme_phyaddr; 915 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 916 917 /* Configure Tx queue 0 packet completion coalescing. */ 918 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 919 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 920 reg |= PCCTX_COAL_TXQ0; 921 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 922 923 /* Configure Rx queue 0 packet completion coalescing. */ 924 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 925 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 926 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 927 928 /* Disable Timers */ 929 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 930 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 931 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 932 933 /* Configure retry transmit period, retry limit value. */ 934 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 935 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 936 TXTRHD_RT_PERIOD_MASK) | 937 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 938 TXTRHD_RT_LIMIT_SHIFT)); 939 940 /* Disable RSS. */ 941 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 942 JME_RSSC, RSSC_DIS_RSS); 943 944 /* Initialize the interrupt mask. */ 945 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 946 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 947 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 948 JME_INTR_STATUS, 0xFFFFFFFF); 949 950 /* set media, if not already handling a media change */ 951 if (do_ifinit) { 952 int error; 953 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 954 error = 0; 955 else if (error != 0) { 956 aprint_error_dev(sc->jme_dev, "could not set media\n"); 957 return error; 958 } 959 } 960 961 /* Program MAC with resolved speed/duplex/flow-control. */ 962 jme_mac_config(sc); 963 964 /* Start receiver/transmitter. */ 965 sc->jme_rx_cons = 0; 966 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 967 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 968 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 969 sc->jme_txcsr | TXCSR_TX_ENB); 970 971 /* start ticks calls */ 972 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 973 sc->jme_if.if_flags |= IFF_RUNNING; 974 sc->jme_if.if_flags &= ~IFF_OACTIVE; 975 splx(s); 976 return 0; 977 } 978 979 980 int 981 jme_mii_read(device_t self, int phy, int reg) 982 { 983 struct jme_softc *sc = device_private(self); 984 int val, i; 985 986 /* For FPGA version, PHY address 0 should be ignored. */ 987 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 988 if (phy == 0) 989 return (0); 990 } else { 991 if (sc->jme_phyaddr != phy) 992 return (0); 993 } 994 995 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 996 SMI_OP_READ | SMI_OP_EXECUTE | 997 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 998 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 999 delay(10); 1000 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1001 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1002 break; 1003 } 1004 1005 if (i == 0) { 1006 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 1007 return (0); 1008 } 1009 1010 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 1011 } 1012 1013 void 1014 jme_mii_write(device_t self, int phy, int reg, int val) 1015 { 1016 struct jme_softc *sc = device_private(self); 1017 int i; 1018 1019 /* For FPGA version, PHY address 0 should be ignored. */ 1020 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1021 if (phy == 0) 1022 return; 1023 } else { 1024 if (sc->jme_phyaddr != phy) 1025 return; 1026 } 1027 1028 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1029 SMI_OP_WRITE | SMI_OP_EXECUTE | 1030 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1031 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1032 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1033 delay(10); 1034 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1035 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1036 break; 1037 } 1038 1039 if (i == 0) 1040 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1041 1042 return; 1043 } 1044 1045 void 1046 jme_statchg(device_t self) 1047 { 1048 jme_softc_t *sc = device_private(self); 1049 struct ifnet *ifp = &sc->jme_if; 1050 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) 1051 jme_init(ifp, 0); 1052 } 1053 1054 static void 1055 jme_intr_rx(jme_softc_t *sc) { 1056 struct mbuf *m, *mhead; 1057 bus_dmamap_t mmap; 1058 struct ifnet *ifp = &sc->jme_if; 1059 uint32_t flags, buflen; 1060 int i, ipackets, nsegs, seg, error; 1061 struct jme_desc *desc; 1062 1063 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1064 sizeof(struct jme_desc) * JME_NBUFS, 1065 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1066 #ifdef JMEDEBUG_RX 1067 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1068 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1069 #endif 1070 ipackets = 0; 1071 while((le32toh(sc->jme_rxring[sc->jme_rx_cons].flags) & JME_RD_OWN) 1072 == 0) { 1073 i = sc->jme_rx_cons; 1074 desc = &sc->jme_rxring[i]; 1075 #ifdef JMEDEBUG_RX 1076 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1077 i, le32toh(desc->flags), le32toh(desc->buflen)); 1078 #endif 1079 if (sc->jme_rxmbuf[i] == NULL) { 1080 if ((error = jme_add_rxbuf(sc, NULL)) != 0) { 1081 aprint_error_dev(sc->jme_dev, 1082 "can't add new mbuf to empty slot: %d\n", 1083 error); 1084 break; 1085 } 1086 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1087 i = sc->jme_rx_cons; 1088 continue; 1089 } 1090 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1091 break; 1092 1093 buflen = le32toh(desc->buflen); 1094 nsegs = JME_RX_NSEGS(buflen); 1095 flags = le32toh(desc->flags); 1096 if ((buflen & JME_RX_ERR_STAT) != 0 || 1097 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1098 JME_RX_BYTES(buflen) > 1099 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1100 #ifdef JMEDEBUG_RX 1101 printf("rx error flags 0x%x buflen 0x%x\n", 1102 flags, buflen); 1103 #endif 1104 ifp->if_ierrors++; 1105 /* reuse the mbufs */ 1106 for (seg = 0; seg < nsegs; seg++) { 1107 m = sc->jme_rxmbuf[i]; 1108 sc->jme_rxmbuf[i] = NULL; 1109 mmap = sc->jme_rxmbufm[i]; 1110 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1111 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1112 bus_dmamap_unload(sc->jme_dmatag, mmap); 1113 if ((error = jme_add_rxbuf(sc, m)) != 0) 1114 aprint_error_dev(sc->jme_dev, 1115 "can't reuse mbuf: %d\n", error); 1116 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1117 i = sc->jme_rx_cons; 1118 } 1119 continue; 1120 } 1121 /* receive this packet */ 1122 mhead = m = sc->jme_rxmbuf[i]; 1123 sc->jme_rxmbuf[i] = NULL; 1124 mmap = sc->jme_rxmbufm[i]; 1125 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1126 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1127 bus_dmamap_unload(sc->jme_dmatag, mmap); 1128 /* add a new buffer to chain */ 1129 if (jme_add_rxbuf(sc, NULL) != 0) { 1130 if ((error = jme_add_rxbuf(sc, m)) != 0) 1131 aprint_error_dev(sc->jme_dev, 1132 "can't reuse mbuf: %d\n", error); 1133 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1134 i = sc->jme_rx_cons; 1135 for (seg = 1; seg < nsegs; seg++) { 1136 m = sc->jme_rxmbuf[i]; 1137 sc->jme_rxmbuf[i] = NULL; 1138 mmap = sc->jme_rxmbufm[i]; 1139 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1140 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1141 bus_dmamap_unload(sc->jme_dmatag, mmap); 1142 if ((error = jme_add_rxbuf(sc, m)) != 0) 1143 aprint_error_dev(sc->jme_dev, 1144 "can't reuse mbuf: %d\n", error); 1145 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1146 i = sc->jme_rx_cons; 1147 } 1148 ifp->if_ierrors++; 1149 continue; 1150 } 1151 1152 /* build mbuf chain: head, then remaining segments */ 1153 m->m_pkthdr.rcvif = ifp; 1154 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1155 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1156 m->m_pkthdr.len; 1157 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1158 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1159 for (seg = 1; seg < nsegs; seg++) { 1160 i = sc->jme_rx_cons; 1161 m = sc->jme_rxmbuf[i]; 1162 sc->jme_rxmbuf[i] = NULL; 1163 mmap = sc->jme_rxmbufm[i]; 1164 bus_dmamap_sync(sc->jme_dmatag, mmap, 0, 1165 mmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1166 bus_dmamap_unload(sc->jme_dmatag, mmap); 1167 if ((error = jme_add_rxbuf(sc, NULL)) != 0) 1168 aprint_error_dev(sc->jme_dev, 1169 "can't add new mbuf: %d\n", error); 1170 m->m_flags &= ~M_PKTHDR; 1171 m_cat(mhead, m); 1172 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1173 } 1174 /* and adjust last mbuf's size */ 1175 if (nsegs > 1) { 1176 m->m_len = 1177 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1178 } 1179 ifp->if_ipackets++; 1180 ipackets++; 1181 bpf_mtap(ifp, mhead); 1182 1183 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1184 (flags & JME_RD_IPV4)) { 1185 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1186 if (!(flags & JME_RD_IPCSUM)) 1187 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1188 } 1189 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1190 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1191 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1192 if (!(flags & JME_RD_TCPCSUM)) 1193 mhead->m_pkthdr.csum_flags |= 1194 M_CSUM_TCP_UDP_BAD; 1195 } 1196 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1197 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1198 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1199 if (!(flags & JME_RD_UDPCSUM)) 1200 mhead->m_pkthdr.csum_flags |= 1201 M_CSUM_TCP_UDP_BAD; 1202 } 1203 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1204 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1205 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1206 if (!(flags & JME_RD_TCPCSUM)) 1207 mhead->m_pkthdr.csum_flags |= 1208 M_CSUM_TCP_UDP_BAD; 1209 } 1210 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1211 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1212 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1213 if (!(flags & JME_RD_UDPCSUM)) 1214 mhead->m_pkthdr.csum_flags |= 1215 M_CSUM_TCP_UDP_BAD; 1216 } 1217 if (flags & JME_RD_VLAN_TAG) { 1218 /* pass to vlan_input() */ 1219 VLAN_INPUT_TAG(ifp, mhead, 1220 (flags & JME_RD_VLAN_MASK), continue); 1221 } 1222 (*ifp->if_input)(ifp, mhead); 1223 } 1224 #if NRND > 0 1225 if (ipackets && RND_ENABLED(&sc->rnd_source)) 1226 rnd_add_uint32(&sc->rnd_source, ipackets); 1227 #endif /* NRND > 0 */ 1228 1229 } 1230 1231 static int 1232 jme_intr(void *v) 1233 { 1234 jme_softc_t *sc = v; 1235 uint32_t istatus; 1236 1237 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1238 JME_INTR_STATUS); 1239 if (istatus == 0 || istatus == 0xFFFFFFFF) 1240 return 0; 1241 /* Disable interrupts. */ 1242 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1243 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1244 again: 1245 /* and update istatus */ 1246 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1247 JME_INTR_STATUS); 1248 if ((istatus & JME_INTRS_CHECK) == 0) 1249 goto done; 1250 /* Reset PCC counter/timer and Ack interrupts. */ 1251 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1252 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1253 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1254 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1255 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1256 JME_INTR_STATUS, istatus); 1257 1258 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1259 goto done; 1260 #ifdef JMEDEBUG_RX 1261 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1262 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1263 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1264 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1265 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1266 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1267 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1268 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1269 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1270 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1271 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1272 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1273 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1274 #endif 1275 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1276 jme_intr_rx(sc); 1277 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1278 /* 1279 * Notify hardware availability of new Rx 1280 * buffers. 1281 * Reading RXCSR takes very long time under 1282 * heavy load so cache RXCSR value and writes 1283 * the ORed value with the kick command to 1284 * the RXCSR. This saves one register access 1285 * cycle. 1286 */ 1287 sc->jme_rx_cons = 0; 1288 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1289 JME_RXCSR, 1290 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1291 } 1292 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1293 jme_ifstart(&sc->jme_if); 1294 1295 goto again; 1296 1297 done: 1298 /* enable interrupts. */ 1299 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1300 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1301 return 1; 1302 } 1303 1304 1305 static int 1306 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1307 { 1308 struct jme_softc *sc = ifp->if_softc; 1309 int s, error; 1310 struct ifreq *ifr; 1311 struct ifcapreq *ifcr; 1312 1313 s = splnet(); 1314 /* 1315 * we can't support at the same time jumbo frames and 1316 * TX checksums offload/TSO 1317 */ 1318 switch(cmd) { 1319 case SIOCSIFMTU: 1320 ifr = data; 1321 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1322 (ifp->if_capenable & ( 1323 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1324 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1325 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1326 splx(s); 1327 return EINVAL; 1328 } 1329 break; 1330 case SIOCSIFCAP: 1331 ifcr = data; 1332 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1333 (ifcr->ifcr_capenable & ( 1334 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1335 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1336 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1337 splx(s); 1338 return EINVAL; 1339 } 1340 break; 1341 } 1342 1343 error = ether_ioctl(ifp, cmd, data); 1344 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1345 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1346 jme_set_filter(sc); 1347 error = 0; 1348 } else { 1349 error = jme_init(ifp, 0); 1350 } 1351 } 1352 splx(s); 1353 return error; 1354 } 1355 1356 static int 1357 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1358 { 1359 struct jme_desc *txd; 1360 struct jme_desc *desc; 1361 struct mbuf *m; 1362 struct m_tag *mtag; 1363 int error, i, prod, headdsc, nsegs; 1364 uint32_t cflags, tso_segsz; 1365 1366 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){ 1367 /* 1368 * Due to the adherence to NDIS specification JMC250 1369 * assumes upper stack computed TCP pseudo checksum 1370 * without including payload length. This breaks 1371 * checksum offload for TSO case so recompute TCP 1372 * pseudo checksum for JMC250. Hopefully this wouldn't 1373 * be much burden on modern CPUs. 1374 */ 1375 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1376 int iphl = v4 ? 1377 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1378 M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data); 1379 /* 1380 * note: we support vlan offloading, so we should never have 1381 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1382 * right. 1383 */ 1384 int hlen = ETHER_HDR_LEN + iphl; 1385 1386 if (__predict_false((*m_head)->m_len < 1387 (hlen + sizeof(struct tcphdr)))) { 1388 /* 1389 * TCP/IP headers are not in the first mbuf; we need 1390 * to do this the slow and painful way. Let's just 1391 * hope this doesn't happen very often. 1392 */ 1393 struct tcphdr th; 1394 1395 m_copydata((*m_head), hlen, sizeof(th), &th); 1396 if (v4) { 1397 struct ip ip; 1398 1399 m_copydata((*m_head), ETHER_HDR_LEN, 1400 sizeof(ip), &ip); 1401 ip.ip_len = 0; 1402 m_copyback((*m_head), 1403 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1404 sizeof(ip.ip_len), &ip.ip_len); 1405 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1406 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1407 } else { 1408 #if INET6 1409 struct ip6_hdr ip6; 1410 1411 m_copydata((*m_head), ETHER_HDR_LEN, 1412 sizeof(ip6), &ip6); 1413 ip6.ip6_plen = 0; 1414 m_copyback((*m_head), ETHER_HDR_LEN + 1415 offsetof(struct ip6_hdr, ip6_plen), 1416 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1417 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1418 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1419 #endif /* INET6 */ 1420 } 1421 m_copyback((*m_head), 1422 hlen + offsetof(struct tcphdr, th_sum), 1423 sizeof(th.th_sum), &th.th_sum); 1424 1425 hlen += th.th_off << 2; 1426 } else { 1427 /* 1428 * TCP/IP headers are in the first mbuf; we can do 1429 * this the easy way. 1430 */ 1431 struct tcphdr *th; 1432 1433 if (v4) { 1434 struct ip *ip = 1435 (void *)(mtod((*m_head), char *) + 1436 ETHER_HDR_LEN); 1437 th = (void *)(mtod((*m_head), char *) + hlen); 1438 1439 ip->ip_len = 0; 1440 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1441 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1442 } else { 1443 #if INET6 1444 struct ip6_hdr *ip6 = 1445 (void *)(mtod((*m_head), char *) + 1446 ETHER_HDR_LEN); 1447 th = (void *)(mtod((*m_head), char *) + hlen); 1448 1449 ip6->ip6_plen = 0; 1450 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1451 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1452 #endif /* INET6 */ 1453 } 1454 hlen += th->th_off << 2; 1455 } 1456 1457 } 1458 1459 prod = sc->jme_tx_prod; 1460 txd = &sc->jme_txring[prod]; 1461 1462 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1463 *m_head, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1464 if (error) { 1465 if (error == EFBIG) { 1466 log(LOG_ERR, "%s: Tx packet consumes too many " 1467 "DMA segments, dropping...\n", 1468 device_xname(sc->jme_dev)); 1469 m_freem(*m_head); 1470 m_head = NULL; 1471 } 1472 return (error); 1473 } 1474 /* 1475 * Check descriptor overrun. Leave one free descriptor. 1476 * Since we always use 64bit address mode for transmitting, 1477 * each Tx request requires one more dummy descriptor. 1478 */ 1479 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1480 #ifdef JMEDEBUG_TX 1481 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1482 #endif 1483 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1484 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1485 return (ENOBUFS); 1486 } 1487 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1488 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1489 1490 m = *m_head; 1491 cflags = 0; 1492 tso_segsz = 0; 1493 /* Configure checksum offload and TSO. */ 1494 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) { 1495 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1496 cflags |= JME_TD_TSO; 1497 } else { 1498 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1499 cflags |= JME_TD_IPCSUM; 1500 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0) 1501 cflags |= JME_TD_TCPCSUM; 1502 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0) 1503 cflags |= JME_TD_UDPCSUM; 1504 } 1505 /* Configure VLAN. */ 1506 if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) { 1507 cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); 1508 cflags |= JME_TD_VLAN_TAG; 1509 } 1510 1511 desc = &sc->jme_txring[prod]; 1512 desc->flags = htole32(cflags); 1513 desc->buflen = htole32(tso_segsz); 1514 desc->addr_hi = htole32(m->m_pkthdr.len); 1515 desc->addr_lo = 0; 1516 headdsc = prod; 1517 sc->jme_tx_cnt++; 1518 JME_DESC_INC(prod, JME_NBUFS); 1519 for (i = 0; i < nsegs; i++) { 1520 desc = &sc->jme_txring[prod]; 1521 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1522 desc->buflen = 1523 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1524 desc->addr_hi = htole32( 1525 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1526 desc->addr_lo = htole32( 1527 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1528 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1529 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1530 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1531 sc->jme_txmbuf[prod] = NULL; 1532 sc->jme_tx_cnt++; 1533 JME_DESC_INC(prod, JME_NBUFS); 1534 } 1535 1536 /* Update producer index. */ 1537 sc->jme_tx_prod = prod; 1538 #ifdef JMEDEBUG_TX 1539 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1540 #endif 1541 /* 1542 * Finally request interrupt and give the first descriptor 1543 * owenership to hardware. 1544 */ 1545 desc = &sc->jme_txring[headdsc]; 1546 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1547 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1548 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1549 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1550 1551 sc->jme_txmbuf[headdsc] = m; 1552 return (0); 1553 } 1554 1555 static void 1556 jme_txeof(struct jme_softc *sc) 1557 { 1558 struct ifnet *ifp; 1559 struct jme_desc *desc; 1560 uint32_t status; 1561 int cons, cons0, nsegs, seg; 1562 1563 ifp = &sc->jme_if; 1564 1565 #ifdef JMEDEBUG_TX 1566 printf("jme_txeof cons %d prod %d\n", 1567 sc->jme_tx_cons, sc->jme_tx_prod); 1568 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1569 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1570 "JME_TXTRHD 0x%x\n", 1571 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1572 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1573 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1574 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1575 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1576 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1577 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1578 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1579 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1580 desc = &sc->jme_txring[cons]; 1581 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1582 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1583 JME_DESC_INC(cons, JME_NBUFS); 1584 } 1585 #endif 1586 1587 cons = sc->jme_tx_cons; 1588 if (cons == sc->jme_tx_prod) 1589 return; 1590 1591 /* 1592 * Go through our Tx list and free mbufs for those 1593 * frames which have been transmitted. 1594 */ 1595 for (; cons != sc->jme_tx_prod;) { 1596 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1597 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1598 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1599 1600 desc = &sc->jme_txring[cons]; 1601 status = le32toh(desc->flags); 1602 #ifdef JMEDEBUG_TX 1603 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1604 sc->jme_txmbufm[cons]->dm_nsegs); 1605 #endif 1606 if (status & JME_TD_OWN) 1607 break; 1608 1609 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1610 ifp->if_oerrors++; 1611 else { 1612 ifp->if_opackets++; 1613 if ((status & JME_TD_COLLISION) != 0) 1614 ifp->if_collisions += 1615 le32toh(desc->buflen) & 1616 JME_TD_BUF_LEN_MASK; 1617 } 1618 /* 1619 * Only the first descriptor of multi-descriptor 1620 * transmission is updated so driver have to skip entire 1621 * chained buffers for the transmiited frame. In other 1622 * words, JME_TD_OWN bit is valid only at the first 1623 * descriptor of a multi-descriptor transmission. 1624 */ 1625 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1626 cons0 = cons; 1627 JME_DESC_INC(cons, JME_NBUFS); 1628 for (seg = 1; seg < nsegs + 1; seg++) { 1629 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1630 cons * sizeof(struct jme_desc), 1631 sizeof(struct jme_desc), 1632 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1633 sc->jme_txring[cons].flags = 0; 1634 JME_DESC_INC(cons, JME_NBUFS); 1635 } 1636 /* Reclaim transferred mbufs. */ 1637 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1638 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1639 BUS_DMASYNC_POSTWRITE); 1640 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1641 1642 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1643 m_freem(sc->jme_txmbuf[cons0]); 1644 sc->jme_txmbuf[cons0] = NULL; 1645 sc->jme_tx_cnt -= nsegs + 1; 1646 KASSERT(sc->jme_tx_cnt >= 0); 1647 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1648 } 1649 sc->jme_tx_cons = cons; 1650 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1651 if (sc->jme_tx_cnt == 0) 1652 ifp->if_timer = 0; 1653 #ifdef JMEDEBUG_TX 1654 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1655 #endif 1656 } 1657 1658 static void 1659 jme_ifstart(struct ifnet *ifp) 1660 { 1661 jme_softc_t *sc = ifp->if_softc; 1662 struct mbuf *mb_head; 1663 int enq; 1664 1665 /* 1666 * check if we can free some desc. 1667 * Clear TX interrupt status to reset TX coalescing counters. 1668 */ 1669 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1670 JME_INTR_STATUS, INTR_TXQ_COMP); 1671 jme_txeof(sc); 1672 1673 if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1674 return; 1675 for (enq = 0;; enq++) { 1676 nexttx: 1677 /* Grab a paquet for output */ 1678 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1679 if (mb_head == NULL) { 1680 #ifdef JMEDEBUG_TX 1681 printf("%s: nothing to send\n", __func__); 1682 #endif 1683 break; 1684 } 1685 /* try to add this mbuf to the TX ring */ 1686 if (jme_encap(sc, &mb_head)) { 1687 if (mb_head == NULL) { 1688 ifp->if_oerrors++; 1689 /* packet dropped, try next one */ 1690 goto nexttx; 1691 } 1692 /* resource shortage, try again later */ 1693 IF_PREPEND(&ifp->if_snd, mb_head); 1694 ifp->if_flags |= IFF_OACTIVE; 1695 break; 1696 } 1697 /* Pass packet to bpf if there is a listener */ 1698 bpf_mtap(ifp, mb_head); 1699 } 1700 #ifdef JMEDEBUG_TX 1701 printf("jme_ifstart enq %d\n", enq); 1702 #endif 1703 if (enq) { 1704 /* 1705 * Set a 5 second timer just in case we don't hear from 1706 * the card again. 1707 */ 1708 ifp->if_timer = 5; 1709 /* 1710 * Reading TXCSR takes very long time under heavy load 1711 * so cache TXCSR value and writes the ORed value with 1712 * the kick command to the TXCSR. This saves one register 1713 * access cycle. 1714 */ 1715 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1716 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1717 #ifdef JMEDEBUG_TX 1718 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1719 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1720 "JME_TXTRHD 0x%x\n", 1721 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1722 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1723 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1724 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1725 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1726 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1727 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1728 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1729 #endif 1730 } 1731 } 1732 1733 static void 1734 jme_ifwatchdog(struct ifnet *ifp) 1735 { 1736 jme_softc_t *sc = ifp->if_softc; 1737 1738 if ((ifp->if_flags & IFF_RUNNING) == 0) 1739 return; 1740 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1741 ifp->if_oerrors++; 1742 jme_init(ifp, 0); 1743 } 1744 1745 static int 1746 jme_mediachange(struct ifnet *ifp) 1747 { 1748 int error; 1749 jme_softc_t *sc = ifp->if_softc; 1750 1751 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1752 error = 0; 1753 else if (error != 0) { 1754 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1755 return error; 1756 } 1757 return 0; 1758 } 1759 1760 static void 1761 jme_ticks(void *v) 1762 { 1763 jme_softc_t *sc = v; 1764 int s = splnet(); 1765 1766 /* Tick the MII. */ 1767 mii_tick(&sc->jme_mii); 1768 1769 /* every seconds */ 1770 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1771 splx(s); 1772 } 1773 1774 static void 1775 jme_mac_config(jme_softc_t *sc) 1776 { 1777 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1778 struct mii_data *mii = &sc->jme_mii; 1779 1780 ghc = 0; 1781 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1782 rxmac &= ~RXMAC_FC_ENB; 1783 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1784 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1785 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1786 txpause &= ~TXPFC_PAUSE_ENB; 1787 1788 if (mii->mii_media_active & IFM_FDX) { 1789 ghc |= GHC_FULL_DUPLEX; 1790 rxmac &= ~RXMAC_COLL_DET_ENB; 1791 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1792 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1793 TXMAC_FRAME_BURST); 1794 /* Disable retry transmit timer/retry limit. */ 1795 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1796 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1797 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1798 } else { 1799 rxmac |= RXMAC_COLL_DET_ENB; 1800 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1801 /* Enable retry transmit timer/retry limit. */ 1802 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1803 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1804 } 1805 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1806 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1807 case IFM_10_T: 1808 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1809 break; 1810 case IFM_100_TX: 1811 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1812 break; 1813 case IFM_1000_T: 1814 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1815 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1816 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1817 break; 1818 default: 1819 break; 1820 } 1821 if ((sc->jme_flags & JME_FLAG_GIGA) && 1822 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1823 /* 1824 * Workaround occasional packet loss issue of JMC250 A2 1825 * when it runs on half-duplex media. 1826 */ 1827 #ifdef JMEDEBUG 1828 printf("JME250 A2 workaround\n"); 1829 #endif 1830 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1831 JME_GPREG1); 1832 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1833 gpreg &= ~GPREG1_HDPX_FIX; 1834 else 1835 gpreg |= GPREG1_HDPX_FIX; 1836 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1837 JME_GPREG1, gpreg); 1838 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1839 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1840 /* Extend interface FIFO depth. */ 1841 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1842 0x1B, 0x0000); 1843 } else { 1844 /* Select default interface FIFO depth. */ 1845 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1846 0x1B, 0x0004); 1847 } 1848 } 1849 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1850 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1851 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1852 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1853 } 1854 1855 static void 1856 jme_set_filter(jme_softc_t *sc) 1857 { 1858 struct ifnet *ifp = &sc->jme_if; 1859 struct ether_multistep step; 1860 struct ether_multi *enm; 1861 uint32_t hash[2] = {0, 0}; 1862 int i; 1863 uint32_t rxcfg; 1864 1865 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1866 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1867 RXMAC_ALLMULTI); 1868 /* Always accept frames destined to our station address. */ 1869 rxcfg |= RXMAC_UNICAST; 1870 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1871 rxcfg |= RXMAC_BROADCAST; 1872 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1873 if ((ifp->if_flags & IFF_PROMISC) != 0) 1874 rxcfg |= RXMAC_PROMISC; 1875 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1876 rxcfg |= RXMAC_ALLMULTI; 1877 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1878 JME_MAR0, 0xFFFFFFFF); 1879 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1880 JME_MAR1, 0xFFFFFFFF); 1881 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1882 JME_RXMAC, rxcfg); 1883 return; 1884 } 1885 /* 1886 * Set up the multicast address filter by passing all multicast 1887 * addresses through a CRC generator, and then using the low-order 1888 * 6 bits as an index into the 64 bit multicast hash table. The 1889 * high order bits select the register, while the rest of the bits 1890 * select the bit within the register. 1891 */ 1892 rxcfg |= RXMAC_MULTICAST; 1893 memset(hash, 0, sizeof(hash)); 1894 1895 ETHER_FIRST_MULTI(step, &sc->jme_ec, enm); 1896 while (enm != NULL) { 1897 #ifdef JEMDBUG 1898 printf("%s: addrs %s %s\n", __func__, 1899 ether_sprintf(enm->enm_addrlo), 1900 ether_sprintf(enm->enm_addrhi)); 1901 #endif 1902 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1903 i = ether_crc32_be(enm->enm_addrlo, 6); 1904 /* Just want the 6 least significant bits. */ 1905 i &= 0x3f; 1906 hash[i / 32] |= 1 << (i%32); 1907 } else { 1908 hash[0] = hash[1] = 0xffffffff; 1909 sc->jme_if.if_flags |= IFF_ALLMULTI; 1910 break; 1911 } 1912 ETHER_NEXT_MULTI(step, enm); 1913 } 1914 #ifdef JMEDEBUG 1915 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1916 #endif 1917 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1918 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1919 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1920 } 1921 1922 #if 0 1923 static int 1924 jme_multicast_hash(uint8_t *a) 1925 { 1926 int hash; 1927 1928 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1929 #define xor8(a,b,c,d,e,f,g,h) \ 1930 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1931 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1932 1933 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1934 DA(a,36), DA(a,42)); 1935 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1936 DA(a,37), DA(a,43)) << 1; 1937 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1938 DA(a,38), DA(a,44)) << 2; 1939 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1940 DA(a,39), DA(a,45)) << 3; 1941 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1942 DA(a,40), DA(a,46)) << 4; 1943 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1944 DA(a,41), DA(a,47)) << 5; 1945 1946 return hash; 1947 } 1948 #endif 1949 1950 static int 1951 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1952 { 1953 uint32_t reg; 1954 int i; 1955 1956 *val = 0; 1957 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1958 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1959 JME_SMBCSR); 1960 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1961 break; 1962 delay(10); 1963 } 1964 1965 if (i == 0) { 1966 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1967 return (ETIMEDOUT); 1968 } 1969 1970 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1971 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1972 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1973 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1974 delay(10); 1975 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1976 JME_SMBINTF); 1977 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1978 break; 1979 } 1980 1981 if (i == 0) { 1982 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1983 return (ETIMEDOUT); 1984 } 1985 1986 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1987 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1988 return (0); 1989 } 1990 1991 1992 static int 1993 jme_eeprom_macaddr(struct jme_softc *sc) 1994 { 1995 uint8_t eaddr[ETHER_ADDR_LEN]; 1996 uint8_t fup, reg, val; 1997 uint32_t offset; 1998 int match; 1999 2000 offset = 0; 2001 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 2002 fup != JME_EEPROM_SIG0) 2003 return (ENOENT); 2004 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 2005 fup != JME_EEPROM_SIG1) 2006 return (ENOENT); 2007 match = 0; 2008 do { 2009 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 2010 break; 2011 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 2012 == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) { 2013 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 2014 break; 2015 if (reg >= JME_PAR0 && 2016 reg < JME_PAR0 + ETHER_ADDR_LEN) { 2017 if (jme_eeprom_read_byte(sc, offset + 2, 2018 &val) != 0) 2019 break; 2020 eaddr[reg - JME_PAR0] = val; 2021 match++; 2022 } 2023 } 2024 if (fup & JME_EEPROM_DESC_END) 2025 break; 2026 2027 /* Try next eeprom descriptor. */ 2028 offset += JME_EEPROM_DESC_BYTES; 2029 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2030 2031 if (match == ETHER_ADDR_LEN) { 2032 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2033 return (0); 2034 } 2035 2036 return (ENOENT); 2037 } 2038 2039 static int 2040 jme_reg_macaddr(struct jme_softc *sc) 2041 { 2042 uint32_t par0, par1; 2043 2044 par0 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0); 2045 par1 = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1); 2046 par1 &= 0xffff; 2047 if ((par0 == 0 && par1 == 0) || 2048 (par0 == 0xffffffff && par1 == 0xffff)) { 2049 return (ENOENT); 2050 } else { 2051 sc->jme_enaddr[0] = (par0 >> 0) & 0xff; 2052 sc->jme_enaddr[1] = (par0 >> 8) & 0xff; 2053 sc->jme_enaddr[2] = (par0 >> 16) & 0xff; 2054 sc->jme_enaddr[3] = (par0 >> 24) & 0xff; 2055 sc->jme_enaddr[4] = (par1 >> 0) & 0xff; 2056 sc->jme_enaddr[5] = (par1 >> 8) & 0xff; 2057 } 2058 return (0); 2059 } 2060 2061 /* 2062 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2063 * set up in jme_pci_attach() 2064 */ 2065 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2066 { 2067 int rc; 2068 const struct sysctlnode *node; 2069 2070 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2071 0, CTLTYPE_NODE, "hw", NULL, 2072 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2073 goto err; 2074 } 2075 2076 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2077 0, CTLTYPE_NODE, "jme", 2078 SYSCTL_DESCR("jme interface controls"), 2079 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2080 goto err; 2081 } 2082 2083 jme_root_num = node->sysctl_num; 2084 return; 2085 2086 err: 2087 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2088 } 2089 2090 static int 2091 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2092 { 2093 int error, t; 2094 struct sysctlnode node; 2095 struct jme_softc *sc; 2096 uint32_t reg; 2097 2098 node = *rnode; 2099 sc = node.sysctl_data; 2100 t = sc->jme_intrxto; 2101 node.sysctl_data = &t; 2102 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2103 if (error || newp == NULL) 2104 return error; 2105 2106 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2107 return EINVAL; 2108 2109 /* 2110 * update the softc with sysctl-changed value, and mark 2111 * for hardware update 2112 */ 2113 sc->jme_intrxto = t; 2114 /* Configure Rx queue 0 packet completion coalescing. */ 2115 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2116 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2117 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2118 return 0; 2119 } 2120 2121 static int 2122 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2123 { 2124 int error, t; 2125 struct sysctlnode node; 2126 struct jme_softc *sc; 2127 uint32_t reg; 2128 2129 node = *rnode; 2130 sc = node.sysctl_data; 2131 t = sc->jme_intrxct; 2132 node.sysctl_data = &t; 2133 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2134 if (error || newp == NULL) 2135 return error; 2136 2137 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2138 return EINVAL; 2139 2140 /* 2141 * update the softc with sysctl-changed value, and mark 2142 * for hardware update 2143 */ 2144 sc->jme_intrxct = t; 2145 /* Configure Rx queue 0 packet completion coalescing. */ 2146 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2147 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2148 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2149 return 0; 2150 } 2151 2152 static int 2153 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2154 { 2155 int error, t; 2156 struct sysctlnode node; 2157 struct jme_softc *sc; 2158 uint32_t reg; 2159 2160 node = *rnode; 2161 sc = node.sysctl_data; 2162 t = sc->jme_inttxto; 2163 node.sysctl_data = &t; 2164 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2165 if (error || newp == NULL) 2166 return error; 2167 2168 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2169 return EINVAL; 2170 2171 /* 2172 * update the softc with sysctl-changed value, and mark 2173 * for hardware update 2174 */ 2175 sc->jme_inttxto = t; 2176 /* Configure Tx queue 0 packet completion coalescing. */ 2177 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2178 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2179 reg |= PCCTX_COAL_TXQ0; 2180 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2181 return 0; 2182 } 2183 2184 static int 2185 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2186 { 2187 int error, t; 2188 struct sysctlnode node; 2189 struct jme_softc *sc; 2190 uint32_t reg; 2191 2192 node = *rnode; 2193 sc = node.sysctl_data; 2194 t = sc->jme_inttxct; 2195 node.sysctl_data = &t; 2196 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2197 if (error || newp == NULL) 2198 return error; 2199 2200 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2201 return EINVAL; 2202 2203 /* 2204 * update the softc with sysctl-changed value, and mark 2205 * for hardware update 2206 */ 2207 sc->jme_inttxct = t; 2208 /* Configure Tx queue 0 packet completion coalescing. */ 2209 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2210 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2211 reg |= PCCTX_COAL_TXQ0; 2212 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2213 return 0; 2214 } 2215