1 /* $NetBSD: if_jme.c,v 1.10 2009/06/26 00:24:18 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice unmodified, this list of conditions, and the following 41 * disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 */ 58 59 60 /* 61 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast) 62 * Ethernet Controllers. 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.10 2009/06/26 00:24:18 dyoung Exp $"); 67 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/mbuf.h> 72 #include <sys/protosw.h> 73 #include <sys/socket.h> 74 #include <sys/ioctl.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 79 #include <sys/device.h> 80 #include <sys/syslog.h> 81 #include <sys/sysctl.h> 82 83 #include <net/if.h> 84 #if defined(SIOCSIFMEDIA) 85 #include <net/if_media.h> 86 #endif 87 #include <net/if_types.h> 88 #include <net/if_dl.h> 89 #include <net/route.h> 90 #include <net/netisr.h> 91 92 #include "bpfilter.h" 93 #if NBPFILTER > 0 94 #include <net/bpf.h> 95 #include <net/bpfdesc.h> 96 #endif 97 98 #include "rnd.h" 99 #if NRND > 0 100 #include <sys/rnd.h> 101 #endif 102 103 #include <netinet/in.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/ip.h> 106 107 #ifdef INET 108 #include <netinet/in_var.h> 109 #endif 110 111 #include <netinet/tcp.h> 112 113 #include <net/if_ether.h> 114 #include <uvm/uvm_extern.h> 115 #if defined(INET) 116 #include <netinet/if_inarp.h> 117 #endif 118 119 #include <sys/bus.h> 120 #include <sys/intr.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 #include <dev/pci/if_jmereg.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 struct jme_product_desc { 131 u_int32_t jme_product; 132 const char *jme_desc; 133 }; 134 135 /* number of entries in transmit and receive rings */ 136 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc)) 137 138 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 139 140 /* Water mark to kick reclaiming Tx buffers. */ 141 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10)) 142 143 144 struct jme_softc { 145 device_t jme_dev; /* base device */ 146 bus_space_tag_t jme_bt_mac; 147 bus_space_handle_t jme_bh_mac; /* Mac registers */ 148 bus_space_tag_t jme_bt_phy; 149 bus_space_handle_t jme_bh_phy; /* PHY registers */ 150 bus_space_tag_t jme_bt_misc; 151 bus_space_handle_t jme_bh_misc; /* Misc registers */ 152 bus_dma_tag_t jme_dmatag; 153 bus_dma_segment_t jme_txseg; /* transmit ring seg */ 154 bus_dmamap_t jme_txmap; /* transmit ring DMA map */ 155 struct jme_desc* jme_txring; /* transmit ring */ 156 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */ 157 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */ 158 int jme_tx_cons; /* transmit ring consumer */ 159 int jme_tx_prod; /* transmit ring producer */ 160 int jme_tx_cnt; /* transmit ring active count */ 161 bus_dma_segment_t jme_rxseg; /* receive ring seg */ 162 bus_dmamap_t jme_rxmap; /* receive ring DMA map */ 163 struct jme_desc* jme_rxring; /* receive ring */ 164 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */ 165 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */ 166 int jme_rx_cons; /* receive ring consumer */ 167 int jme_rx_prod; /* receive ring producer */ 168 void* jme_ih; /* our interrupt */ 169 struct ethercom jme_ec; 170 struct callout jme_tick_ch; /* tick callout */ 171 u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */ 172 u_int8_t jme_phyaddr; /* address of integrated phy */ 173 u_int8_t jme_chip_rev; /* chip revision */ 174 u_int8_t jme_rev; /* PCI revision */ 175 mii_data_t jme_mii; /* mii bus */ 176 u_int32_t jme_flags; /* device features, see below */ 177 uint32_t jme_txcsr; /* TX config register */ 178 uint32_t jme_rxcsr; /* RX config register */ 179 #if NRND > 0 180 rndsource_element_t rnd_source; 181 #endif 182 /* interrupt coalition parameters */ 183 struct sysctllog *jme_clog; 184 int jme_intrxto; /* interrupt RX timeout */ 185 int jme_intrxct; /* interrupt RX packets counter */ 186 int jme_inttxto; /* interrupt TX timeout */ 187 int jme_inttxct; /* interrupt TX packets counter */ 188 }; 189 190 #define JME_FLAG_FPGA 0x0001 /* FPGA version */ 191 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */ 192 193 194 #define jme_if jme_ec.ec_if 195 #define jme_bpf jme_if.if_bpf 196 197 typedef struct jme_softc jme_softc_t; 198 typedef u_long ioctl_cmd_t; 199 200 static int jme_pci_match(device_t, cfdata_t, void *); 201 static void jme_pci_attach(device_t, device_t, void *); 202 static void jme_intr_rx(jme_softc_t *); 203 static int jme_intr(void *); 204 205 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 206 static int jme_mediachange(struct ifnet *); 207 static void jme_ifwatchdog(struct ifnet *); 208 static void jme_shutdown(void *); 209 210 static void jme_txeof(struct jme_softc *); 211 static void jme_ifstart(struct ifnet *); 212 static void jme_reset(jme_softc_t *); 213 static int jme_ifinit(struct ifnet *); 214 static int jme_init(struct ifnet *, int); 215 static void jme_stop(struct ifnet *, int); 216 // static void jme_restart(void *); 217 static void jme_ticks(void *); 218 static void jme_mac_config(jme_softc_t *); 219 static void jme_set_filter(jme_softc_t *); 220 221 int jme_mii_read(device_t, int, int); 222 void jme_mii_write(device_t, int, int, int); 223 void jme_statchg(device_t); 224 225 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 226 static int jme_eeprom_macaddr(struct jme_softc *); 227 228 #define JME_TIMEOUT 1000 229 #define JME_PHY_TIMEOUT 1000 230 #define JME_EEPROM_TIMEOUT 1000 231 232 static int jme_sysctl_intrxto(SYSCTLFN_PROTO); 233 static int jme_sysctl_intrxct(SYSCTLFN_PROTO); 234 static int jme_sysctl_inttxto(SYSCTLFN_PROTO); 235 static int jme_sysctl_inttxct(SYSCTLFN_PROTO); 236 static int jme_root_num; 237 238 239 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t), 240 jme_pci_match, jme_pci_attach, NULL, NULL); 241 242 static const struct jme_product_desc jme_products[] = { 243 { PCI_PRODUCT_JMICRON_JMC250, 244 "JMicron JMC250 Gigabit Ethernet Controller" }, 245 { PCI_PRODUCT_JMICRON_JMC260, 246 "JMicron JMC260 Gigabit Ethernet Controller" }, 247 { 0, NULL }, 248 }; 249 250 static const struct jme_product_desc *jme_lookup_product(uint32_t); 251 252 static const struct jme_product_desc * 253 jme_lookup_product(uint32_t id) 254 { 255 const struct jme_product_desc *jp; 256 257 for (jp = jme_products ; jp->jme_desc != NULL; jp++) 258 if (PCI_PRODUCT(id) == jp->jme_product) 259 return jp; 260 261 return NULL; 262 } 263 264 static int 265 jme_pci_match(device_t parent, cfdata_t cf, void *aux) 266 { 267 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 268 269 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON) 270 return 0; 271 272 if (jme_lookup_product(pa->pa_id) != NULL) 273 return 1; 274 275 return 0; 276 } 277 278 static void 279 jme_pci_attach(device_t parent, device_t self, void *aux) 280 { 281 jme_softc_t *sc = device_private(self); 282 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 283 const struct jme_product_desc *jp; 284 struct ifnet * const ifp = &sc->jme_if; 285 bus_space_tag_t iot1, iot2, memt; 286 bus_space_handle_t ioh1, ioh2, memh; 287 bus_size_t size, size2; 288 pci_intr_handle_t intrhandle; 289 const char *intrstr; 290 pcireg_t csr; 291 int nsegs, i; 292 const struct sysctlnode *node; 293 int jme_nodenum; 294 295 sc->jme_dev = self; 296 aprint_normal("\n"); 297 callout_init(&sc->jme_tick_ch, 0); 298 299 jp = jme_lookup_product(pa->pa_id); 300 if (jp == NULL) 301 panic("jme_pci_attach: impossible"); 302 303 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250) 304 sc->jme_flags = JME_FLAG_GIGA; 305 306 /* 307 * Map the card space. Try Mem first. 308 */ 309 if (pci_mapreg_map(pa, JME_PCI_BAR0, 310 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 311 0, &memt, &memh, NULL, &size) == 0) { 312 sc->jme_bt_mac = memt; 313 sc->jme_bh_mac = memh; 314 sc->jme_bt_phy = memt; 315 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF, 316 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) { 317 aprint_error_dev(self, "can't subregion PHY space\n"); 318 bus_space_unmap(memt, memh, size); 319 return; 320 } 321 sc->jme_bt_misc = memt; 322 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF, 323 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 324 aprint_error_dev(self, "can't subregion misc space\n"); 325 bus_space_unmap(memt, memh, size); 326 return; 327 } 328 } else { 329 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO, 330 0, &iot1, &ioh1, NULL, &size) != 0) { 331 aprint_error_dev(self, "can't map I/O space 1\n"); 332 return; 333 } 334 sc->jme_bt_mac = iot1; 335 sc->jme_bh_mac = ioh1; 336 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO, 337 0, &iot2, &ioh2, NULL, &size2) != 0) { 338 aprint_error_dev(self, "can't map I/O space 2\n"); 339 bus_space_unmap(iot1, ioh1, size); 340 return; 341 } 342 sc->jme_bt_phy = iot2; 343 sc->jme_bh_phy = ioh2; 344 sc->jme_bt_misc = iot2; 345 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF, 346 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) { 347 aprint_error_dev(self, "can't subregion misc space\n"); 348 bus_space_unmap(iot1, ioh1, size); 349 bus_space_unmap(iot2, ioh2, size2); 350 return; 351 } 352 } 353 354 if (pci_dma64_available(pa)) 355 sc->jme_dmatag = pa->pa_dmat64; 356 else 357 sc->jme_dmatag = pa->pa_dmat; 358 359 /* Enable the device. */ 360 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 361 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 362 csr | PCI_COMMAND_MASTER_ENABLE); 363 364 aprint_normal_dev(self, "%s\n", jp->jme_desc); 365 366 sc->jme_rev = PCI_REVISION(pa->pa_class); 367 368 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE); 369 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 370 CHIPMODE_NOT_FPGA) 371 sc->jme_flags |= JME_FLAG_FPGA; 372 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 373 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: " 374 "0x%x", sc->jme_rev, sc->jme_chip_rev); 375 if (sc->jme_flags & JME_FLAG_FPGA) 376 aprint_verbose(" FPGA revision: 0x%x", 377 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); 378 aprint_verbose("\n"); 379 380 /* 381 * Save PHY address. 382 * Integrated JR0211 has fixed PHY address whereas FPGA version 383 * requires PHY probing to get correct PHY address. 384 */ 385 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 386 sc->jme_phyaddr = 387 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 388 JME_GPREG0) & GPREG0_PHY_ADDR_MASK; 389 } else 390 sc->jme_phyaddr = 0; 391 392 393 jme_reset(sc); 394 395 /* read mac addr */ 396 if (jme_eeprom_macaddr(sc)) { 397 aprint_error_dev(self, "error reading Ethernet address\n"); 398 /* return; */ 399 } 400 aprint_normal_dev(self, "Ethernet address %s\n", 401 ether_sprintf(sc->jme_enaddr)); 402 403 /* Map and establish interrupts */ 404 if (pci_intr_map(pa, &intrhandle)) { 405 aprint_error_dev(self, "couldn't map interrupt\n"); 406 return; 407 } 408 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 409 sc->jme_if.if_softc = sc; 410 sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 411 jme_intr, sc); 412 if (sc->jme_ih == NULL) { 413 aprint_error_dev(self, "couldn't establish interrupt"); 414 if (intrstr != NULL) 415 aprint_error(" at %s", intrstr); 416 aprint_error("\n"); 417 return; 418 } 419 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 420 421 /* allocate and map DMA-safe memory for transmit ring */ 422 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 423 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 424 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg, 425 nsegs, PAGE_SIZE, (void **)&sc->jme_txring, 426 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 427 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 428 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 || 429 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring, 430 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 431 aprint_error_dev(self, "can't allocate DMA memory TX ring\n"); 432 return; 433 } 434 /* allocate and map DMA-safe memory for receive ring */ 435 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 436 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 || 437 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg, 438 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring, 439 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 || 440 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0, 441 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 || 442 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring, 443 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) { 444 aprint_error_dev(self, "can't allocate DMA memory RX ring\n"); 445 return; 446 } 447 for (i = 0; i < JME_NBUFS; i++) { 448 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL; 449 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN, 450 JME_NBUFS, JME_MAX_TX_LEN, 0, BUS_DMA_NOWAIT, 451 &sc->jme_txmbufm[i]) != 0) { 452 aprint_error_dev(self, "can't allocate DMA TX map\n"); 453 return; 454 } 455 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN, 456 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT, 457 &sc->jme_rxmbufm[i]) != 0) { 458 aprint_error_dev(self, "can't allocate DMA RX map\n"); 459 return; 460 } 461 } 462 /* 463 * Add shutdown hook so that DMA is disabled prior to reboot. 464 */ 465 (void)shutdownhook_establish(jme_shutdown, ifp); 466 467 /* 468 * Initialize our media structures and probe the MII. 469 * 470 * Note that we don't care about the media instance. We 471 * are expecting to have multiple PHYs on the 10/100 cards, 472 * and on those cards we exclude the internal PHY from providing 473 * 10baseT. By ignoring the instance, it allows us to not have 474 * to specify it on the command line when switching media. 475 */ 476 sc->jme_mii.mii_ifp = ifp; 477 sc->jme_mii.mii_readreg = jme_mii_read; 478 sc->jme_mii.mii_writereg = jme_mii_write; 479 sc->jme_mii.mii_statchg = jme_statchg; 480 sc->jme_ec.ec_mii = &sc->jme_mii; 481 ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange, 482 ether_mediastatus); 483 mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY, 484 MII_OFFSET_ANY, 0); 485 if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) { 486 ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 487 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE); 488 } else 489 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO); 490 491 /* 492 * We can support 802.1Q VLAN-sized frames. 493 */ 494 sc->jme_ec.ec_capabilities |= 495 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 496 497 if (sc->jme_flags & JME_FLAG_GIGA) 498 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 499 500 501 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 502 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 503 ifp->if_ioctl = jme_ifioctl; 504 ifp->if_start = jme_ifstart; 505 ifp->if_watchdog = jme_ifwatchdog; 506 ifp->if_init = jme_ifinit; 507 ifp->if_stop = jme_stop; 508 ifp->if_timer = 0; 509 ifp->if_capabilities |= 510 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 511 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 512 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 513 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */ 514 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */ 515 IFCAP_TSOv4 | IFCAP_TSOv6; 516 IFQ_SET_READY(&ifp->if_snd); 517 if_attach(ifp); 518 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr); 519 520 #if NRND > 0 521 rnd_attach_source(&sc->rnd_source, device_xname(self), 522 RND_TYPE_NET, 0); 523 #endif 524 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT; 525 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT; 526 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT; 527 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT; 528 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 529 0, CTLTYPE_NODE, device_xname(sc->jme_dev), 530 SYSCTL_DESCR("jme per-controller controls"), 531 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE, 532 CTL_EOL) != 0) { 533 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n"); 534 return; 535 } 536 jme_nodenum = node->sysctl_num; 537 538 /* interrupt moderation sysctls */ 539 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 540 CTLFLAG_READWRITE, 541 CTLTYPE_INT, "int_rxto", 542 SYSCTL_DESCR("jme RX interrupt moderation timer"), 543 jme_sysctl_intrxto, 0, sc, 544 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 545 CTL_EOL) != 0) { 546 aprint_normal_dev(sc->jme_dev, 547 "couldn't create int_rxto sysctl node\n"); 548 } 549 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 550 CTLFLAG_READWRITE, 551 CTLTYPE_INT, "int_rxct", 552 SYSCTL_DESCR("jme RX interrupt moderation packet counter"), 553 jme_sysctl_intrxct, 0, sc, 554 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 555 CTL_EOL) != 0) { 556 aprint_normal_dev(sc->jme_dev, 557 "couldn't create int_rxct sysctl node\n"); 558 } 559 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 560 CTLFLAG_READWRITE, 561 CTLTYPE_INT, "int_txto", 562 SYSCTL_DESCR("jme TX interrupt moderation timer"), 563 jme_sysctl_inttxto, 0, sc, 564 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 565 CTL_EOL) != 0) { 566 aprint_normal_dev(sc->jme_dev, 567 "couldn't create int_txto sysctl node\n"); 568 } 569 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node, 570 CTLFLAG_READWRITE, 571 CTLTYPE_INT, "int_txct", 572 SYSCTL_DESCR("jme TX interrupt moderation packet counter"), 573 jme_sysctl_inttxct, 0, sc, 574 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE, 575 CTL_EOL) != 0) { 576 aprint_normal_dev(sc->jme_dev, 577 "couldn't create int_txct sysctl node\n"); 578 } 579 } 580 581 static void 582 jme_stop_rx(jme_softc_t *sc) 583 { 584 uint32_t reg; 585 int i; 586 587 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR); 588 if ((reg & RXCSR_RX_ENB) == 0) 589 return; 590 reg &= ~RXCSR_RX_ENB; 591 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg); 592 for (i = JME_TIMEOUT / 10; i > 0; i--) { 593 DELAY(10); 594 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 595 JME_RXCSR) & RXCSR_RX_ENB) == 0) 596 break; 597 } 598 if (i == 0) 599 aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n"); 600 601 } 602 603 static void 604 jme_stop_tx(jme_softc_t *sc) 605 { 606 uint32_t reg; 607 int i; 608 609 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR); 610 if ((reg & TXCSR_TX_ENB) == 0) 611 return; 612 reg &= ~TXCSR_TX_ENB; 613 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg); 614 for (i = JME_TIMEOUT / 10; i > 0; i--) { 615 DELAY(10); 616 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 617 JME_TXCSR) & TXCSR_TX_ENB) == 0) 618 break; 619 } 620 if (i == 0) 621 aprint_error_dev(sc->jme_dev, 622 "stopping transmitter timeout!\n"); 623 } 624 625 static void 626 jme_reset(jme_softc_t *sc) 627 { 628 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET); 629 DELAY(10); 630 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0); 631 } 632 633 static void 634 jme_shutdown(void *v) 635 { 636 637 jme_stop(v, 1); 638 } 639 640 static void 641 jme_stop(struct ifnet *ifp, int disable) 642 { 643 jme_softc_t *sc = ifp->if_softc; 644 int i; 645 /* Stop receiver, transmitter. */ 646 jme_stop_rx(sc); 647 jme_stop_tx(sc); 648 /* free receive mbufs */ 649 for (i = 0; i < JME_NBUFS; i++) { 650 if (sc->jme_rxmbuf[i]) { 651 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 652 m_freem(sc->jme_rxmbuf[i]); 653 } 654 sc->jme_rxmbuf[i] = NULL; 655 } 656 /* process completed transmits */ 657 jme_txeof(sc); 658 /* free abort pending transmits */ 659 for (i = 0; i < JME_NBUFS; i++) { 660 if (sc->jme_txmbuf[i]) { 661 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]); 662 m_freem(sc->jme_txmbuf[i]); 663 sc->jme_txmbuf[i] = NULL; 664 } 665 } 666 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 667 ifp->if_timer = 0; 668 } 669 670 #if 0 671 static void 672 jme_restart(void *v) 673 { 674 675 jme_init(v); 676 } 677 #endif 678 679 static int 680 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m) 681 { 682 int error; 683 bus_dmamap_t map; 684 int i = sc->jme_rx_prod; 685 686 if (sc->jme_rxmbuf[i] != NULL) { 687 aprint_error_dev(sc->jme_dev, 688 "mbuf already here: rxprod %d rxcons %d\n", 689 sc->jme_rx_prod, sc->jme_rx_cons); 690 if (m) 691 m_freem(m); 692 return EINVAL; 693 } 694 695 if (m == NULL) { 696 sc->jme_rxmbuf[i] = NULL; 697 MGETHDR(m, M_DONTWAIT, MT_DATA); 698 if (m == NULL) 699 return (ENOBUFS); 700 MCLGET(m, M_DONTWAIT); 701 if ((m->m_flags & M_EXT) == 0) { 702 m_freem(m); 703 return (ENOBUFS); 704 } 705 } 706 map = sc->jme_rxmbufm[i]; 707 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 708 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m, 709 BUS_DMA_READ|BUS_DMA_NOWAIT); 710 if (error) { 711 sc->jme_rxmbuf[i] = NULL; 712 aprint_error_dev(sc->jme_dev, 713 "unable to load rx DMA map %d, error = %d\n", 714 i, error); 715 m_freem(m); 716 return (error); 717 } 718 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize, 719 BUS_DMASYNC_PREREAD); 720 721 sc->jme_rxmbuf[i] = m; 722 723 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len); 724 sc->jme_rxring[i].addr_lo = 725 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr)); 726 sc->jme_rxring[i].addr_hi = 727 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr)); 728 sc->jme_rxring[i].flags = 729 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 730 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 731 i * sizeof(struct jme_desc), sizeof(struct jme_desc), 732 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 733 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS); 734 return (0); 735 } 736 737 static int 738 jme_ifinit(struct ifnet *ifp) 739 { 740 return jme_init(ifp, 1); 741 } 742 743 static int 744 jme_init(struct ifnet *ifp, int do_ifinit) 745 { 746 jme_softc_t *sc = ifp->if_softc; 747 int i, s; 748 uint8_t eaddr[ETHER_ADDR_LEN]; 749 uint32_t reg; 750 751 s = splnet(); 752 /* cancel any pending IO */ 753 jme_stop(ifp, 1); 754 jme_reset(sc); 755 if ((sc->jme_if.if_flags & IFF_UP) == 0) { 756 splx(s); 757 return 0; 758 } 759 /* allocate receive ring */ 760 sc->jme_rx_prod = 0; 761 for (i = 0; i < JME_NBUFS; i++) { 762 if (jme_add_rxbuf(sc, NULL) < 0) { 763 aprint_error_dev(sc->jme_dev, 764 "can't allocate rx mbuf\n"); 765 for (i--; i >= 0; i--) { 766 bus_dmamap_unload(sc->jme_dmatag, 767 sc->jme_rxmbufm[i]); 768 m_freem(sc->jme_rxmbuf[i]); 769 sc->jme_rxmbuf[i] = NULL; 770 } 771 splx(s); 772 return ENOMEM; 773 } 774 } 775 /* init TX ring */ 776 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc)); 777 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 778 0, JME_NBUFS * sizeof(struct jme_desc), 779 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 780 for (i = 0; i < JME_NBUFS; i++) 781 sc->jme_txmbuf[i] = NULL; 782 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0; 783 784 /* Reprogram the station address. */ 785 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 786 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0, 787 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 788 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 789 JME_PAR1, eaddr[5] << 8 | eaddr[4]); 790 791 /* 792 * Configure Tx queue. 793 * Tx priority queue weight value : 0 794 * Tx FIFO threshold for processing next packet : 16QW 795 * Maximum Tx DMA length : 512 796 * Allow Tx DMA burst. 797 */ 798 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 799 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 800 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 801 sc->jme_txcsr |= TXCSR_DMA_SIZE_512; 802 sc->jme_txcsr |= TXCSR_DMA_BURST; 803 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 804 JME_TXCSR, sc->jme_txcsr); 805 806 /* Set Tx descriptor counter. */ 807 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 808 JME_TXQDC, JME_NBUFS); 809 810 /* Set Tx ring address to the hardware. */ 811 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI, 812 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr)); 813 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO, 814 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr)); 815 816 /* Configure TxMAC parameters. */ 817 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, 818 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB | 819 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB); 820 821 /* 822 * Configure Rx queue. 823 * FIFO full threshold for transmitting Tx pause packet : 128T 824 * FIFO threshold for processing next packet : 128QW 825 * Rx queue 0 select 826 * Max Rx DMA length : 128 827 * Rx descriptor retry : 32 828 * Rx descriptor retry time gap : 256ns 829 * Don't receive runt/bad frame. 830 */ 831 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 832 /* 833 * Since Rx FIFO size is 4K bytes, receiving frames larger 834 * than 4K bytes will suffer from Rx FIFO overruns. So 835 * decrease FIFO threshold to reduce the FIFO overruns for 836 * frames larger than 4000 bytes. 837 * For best performance of standard MTU sized frames use 838 * maximum allowable FIFO threshold, 128QW. 839 */ 840 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 841 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 842 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 843 else 844 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 845 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 846 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 847 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 848 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 849 JME_RXCSR, sc->jme_rxcsr); 850 851 /* Set Rx descriptor counter. */ 852 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 853 JME_RXQDC, JME_NBUFS); 854 855 /* Set Rx ring address to the hardware. */ 856 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI, 857 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr)); 858 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO, 859 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr)); 860 861 /* Clear receive filter. */ 862 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0); 863 /* Set up the receive filter. */ 864 jme_set_filter(sc); 865 866 /* 867 * Disable all WOL bits as WOL can interfere normal Rx 868 * operation. Also clear WOL detection status bits. 869 */ 870 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS); 871 reg &= ~PMCS_WOL_ENB_MASK; 872 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg); 873 874 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 875 /* 876 * Pad 10bytes right before received frame. This will greatly 877 * help Rx performance on strict-alignment architectures as 878 * it does not need to copy the frame to align the payload. 879 */ 880 reg |= RXMAC_PAD_10BYTES; 881 if ((ifp->if_capenable & 882 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx| 883 IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0) 884 reg |= RXMAC_CSUM_ENB; 885 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */ 886 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg); 887 888 /* Configure general purpose reg0 */ 889 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0); 890 reg &= ~GPREG0_PCC_UNIT_MASK; 891 /* Set PCC timer resolution to micro-seconds unit. */ 892 reg |= GPREG0_PCC_UNIT_US; 893 /* 894 * Disable all shadow register posting as we have to read 895 * JME_INTR_STATUS register in jme_int_task. Also it seems 896 * that it's hard to synchronize interrupt status between 897 * hardware and software with shadow posting due to 898 * requirements of bus_dmamap_sync(9). 899 */ 900 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 901 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 902 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 903 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 904 /* Disable posting of DW0. */ 905 reg &= ~GPREG0_POST_DW0_ENB; 906 /* Clear PME message. */ 907 reg &= ~GPREG0_PME_ENB; 908 /* Set PHY address. */ 909 reg &= ~GPREG0_PHY_ADDR_MASK; 910 reg |= sc->jme_phyaddr; 911 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg); 912 913 /* Configure Tx queue 0 packet completion coalescing. */ 914 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 915 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 916 reg |= PCCTX_COAL_TXQ0; 917 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 918 919 /* Configure Rx queue 0 packet completion coalescing. */ 920 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 921 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 922 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 923 924 /* Disable Timers */ 925 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0); 926 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0); 927 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0); 928 929 /* Configure retry transmit period, retry limit value. */ 930 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 931 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 932 TXTRHD_RT_PERIOD_MASK) | 933 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 934 TXTRHD_RT_LIMIT_SHIFT)); 935 936 /* Disable RSS. */ 937 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 938 JME_RSSC, RSSC_DIS_RSS); 939 940 /* Initialize the interrupt mask. */ 941 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 942 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 943 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 944 JME_INTR_STATUS, 0xFFFFFFFF); 945 946 /* set media, if not already handling a media change */ 947 if (do_ifinit) { 948 int error; 949 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 950 error = 0; 951 else if (error != 0) { 952 aprint_error_dev(sc->jme_dev, "could not set media\n"); 953 return error; 954 } 955 } 956 957 /* Program MAC with resolved speed/duplex/flow-control. */ 958 jme_mac_config(sc); 959 960 /* Start receiver/transmitter. */ 961 sc->jme_rx_cons = 0; 962 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, 963 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 964 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 965 sc->jme_txcsr | TXCSR_TX_ENB); 966 967 /* start ticks calls */ 968 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 969 sc->jme_if.if_flags |= IFF_RUNNING; 970 sc->jme_if.if_flags &= ~IFF_OACTIVE; 971 splx(s); 972 return 0; 973 } 974 975 976 int 977 jme_mii_read(device_t self, int phy, int reg) 978 { 979 struct jme_softc *sc = device_private(self); 980 int val, i; 981 982 /* For FPGA version, PHY address 0 should be ignored. */ 983 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 984 if (phy == 0) 985 return (0); 986 } else { 987 if (sc->jme_phyaddr != phy) 988 return (0); 989 } 990 991 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 992 SMI_OP_READ | SMI_OP_EXECUTE | 993 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 994 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 995 delay(10); 996 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 997 JME_SMI)) & SMI_OP_EXECUTE) == 0) 998 break; 999 } 1000 1001 if (i == 0) { 1002 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg); 1003 return (0); 1004 } 1005 1006 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 1007 } 1008 1009 void 1010 jme_mii_write(device_t self, int phy, int reg, int val) 1011 { 1012 struct jme_softc *sc = device_private(self); 1013 int i; 1014 1015 /* For FPGA version, PHY address 0 should be ignored. */ 1016 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 1017 if (phy == 0) 1018 return; 1019 } else { 1020 if (sc->jme_phyaddr != phy) 1021 return; 1022 } 1023 1024 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI, 1025 SMI_OP_WRITE | SMI_OP_EXECUTE | 1026 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 1027 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 1028 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) { 1029 delay(10); 1030 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, 1031 JME_SMI)) & SMI_OP_EXECUTE) == 0) 1032 break; 1033 } 1034 1035 if (i == 0) 1036 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg); 1037 1038 return; 1039 } 1040 1041 void 1042 jme_statchg(device_t self) 1043 { 1044 jme_softc_t *sc = device_private(self); 1045 struct ifnet *ifp = &sc->jme_if; 1046 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) 1047 jme_init(ifp, 0); 1048 } 1049 1050 static void 1051 jme_intr_rx(jme_softc_t *sc) { 1052 struct mbuf *m, *mhead; 1053 struct ifnet *ifp = &sc->jme_if; 1054 uint32_t flags, buflen; 1055 int i, ipackets, nsegs, seg, error; 1056 struct jme_desc *desc; 1057 1058 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0, 1059 sizeof(struct jme_desc) * JME_NBUFS, 1060 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1061 #ifdef JMEDEBUG_RX 1062 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n", 1063 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags)); 1064 #endif 1065 ipackets = 0; 1066 while((le32toh(sc->jme_rxring[ sc->jme_rx_cons].flags) & JME_RD_OWN) 1067 == 0) { 1068 i = sc->jme_rx_cons; 1069 desc = &sc->jme_rxring[i]; 1070 #ifdef JMEDEBUG_RX 1071 printf("rxintr i %d flags 0x%x buflen 0x%x\n", 1072 i, le32toh(desc->flags), le32toh(desc->buflen)); 1073 #endif 1074 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 1075 break; 1076 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmbufm[i], 0, 1077 sc->jme_rxmbufm[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); 1078 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]); 1079 1080 buflen = le32toh(desc->buflen); 1081 nsegs = JME_RX_NSEGS(buflen); 1082 flags = le32toh(desc->flags); 1083 if ((buflen & JME_RX_ERR_STAT) != 0 || 1084 JME_RX_BYTES(buflen) < sizeof(struct ether_header) || 1085 JME_RX_BYTES(buflen) > 1086 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) { 1087 #ifdef JMEDEBUG_RX 1088 printf("rx error flags 0x%x buflen 0x%x\n", 1089 flags, buflen); 1090 #endif 1091 ifp->if_ierrors++; 1092 /* reuse the mbufs */ 1093 for (seg = 0; seg < nsegs; seg++) { 1094 m = sc->jme_rxmbuf[i]; 1095 sc->jme_rxmbuf[i] = NULL; 1096 if ((error = jme_add_rxbuf(sc, m)) != 0) 1097 aprint_error_dev(sc->jme_dev, 1098 "can't reuse mbuf: %d\n", error); 1099 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1100 i = sc->jme_rx_cons; 1101 } 1102 continue; 1103 } 1104 /* receive this packet */ 1105 mhead = m = sc->jme_rxmbuf[i]; 1106 sc->jme_rxmbuf[i] = NULL; 1107 /* add a new buffer to chain */ 1108 if (jme_add_rxbuf(sc, NULL) == ENOBUFS) { 1109 for (seg = 0; seg < nsegs; seg++) { 1110 m = sc->jme_rxmbuf[i]; 1111 sc->jme_rxmbuf[i] = NULL; 1112 if ((error = jme_add_rxbuf(sc, m)) != 0) 1113 aprint_error_dev(sc->jme_dev, 1114 "can't reuse mbuf: %d\n", error); 1115 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1116 i = sc->jme_rx_cons; 1117 } 1118 ifp->if_ierrors++; 1119 continue; 1120 } 1121 1122 /* build mbuf chain: head, then remaining segments */ 1123 m->m_pkthdr.rcvif = ifp; 1124 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES; 1125 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) : 1126 m->m_pkthdr.len; 1127 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES; 1128 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1129 for (seg = 1; seg < nsegs; seg++) { 1130 i = sc->jme_rx_cons; 1131 m = sc->jme_rxmbuf[i]; 1132 sc->jme_rxmbuf[i] = NULL; 1133 (void)jme_add_rxbuf(sc, NULL); 1134 m->m_flags &= ~M_PKTHDR; 1135 m_cat(mhead, m); 1136 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS); 1137 } 1138 /* and adjust last mbuf's size */ 1139 if (nsegs > 1) { 1140 m->m_len = 1141 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1)); 1142 } 1143 ifp->if_ipackets++; 1144 ipackets++; 1145 #if NBPFILTER > 0 1146 if (ifp->if_bpf) 1147 bpf_mtap(ifp->if_bpf, mhead); 1148 #endif /* NBPFILTER > 0 */ 1149 1150 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) && 1151 (flags & JME_RD_IPV4)) { 1152 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1153 if (!(flags & JME_RD_IPCSUM)) 1154 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1155 } 1156 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) && 1157 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) { 1158 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1159 if (!(flags & JME_RD_TCPCSUM)) 1160 mhead->m_pkthdr.csum_flags |= 1161 M_CSUM_TCP_UDP_BAD; 1162 } 1163 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) && 1164 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) { 1165 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1166 if (!(flags & JME_RD_UDPCSUM)) 1167 mhead->m_pkthdr.csum_flags |= 1168 M_CSUM_TCP_UDP_BAD; 1169 } 1170 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) && 1171 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) { 1172 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6; 1173 if (!(flags & JME_RD_TCPCSUM)) 1174 mhead->m_pkthdr.csum_flags |= 1175 M_CSUM_TCP_UDP_BAD; 1176 } 1177 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) && 1178 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) { 1179 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6; 1180 if (!(flags & JME_RD_UDPCSUM)) 1181 mhead->m_pkthdr.csum_flags |= 1182 M_CSUM_TCP_UDP_BAD; 1183 } 1184 if (flags & JME_RD_VLAN_TAG) { 1185 /* pass to vlan_input() */ 1186 VLAN_INPUT_TAG(ifp, mhead, 1187 (flags & JME_RD_VLAN_MASK), continue); 1188 } 1189 (*ifp->if_input)(ifp, mhead); 1190 } 1191 #if NRND > 0 1192 if (ipackets && RND_ENABLED(&sc->rnd_source)) 1193 rnd_add_uint32(&sc->rnd_source, ipackets); 1194 #endif /* NRND > 0 */ 1195 1196 } 1197 1198 static int 1199 jme_intr(void *v) 1200 { 1201 jme_softc_t *sc = v; 1202 uint32_t istatus; 1203 1204 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1205 JME_INTR_STATUS); 1206 if (istatus == 0 || istatus == 0xFFFFFFFF) 1207 return 0; 1208 /* Disable interrupts. */ 1209 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1210 JME_INTR_MASK_CLR, 0xFFFFFFFF); 1211 again: 1212 /* and update istatus */ 1213 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1214 JME_INTR_STATUS); 1215 if ((istatus & JME_INTRS_CHECK) == 0) 1216 goto done; 1217 /* Reset PCC counter/timer and Ack interrupts. */ 1218 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1219 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 1220 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1221 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 1222 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1223 JME_INTR_STATUS, istatus); 1224 1225 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0) 1226 goto done; 1227 #ifdef JMEDEBUG_RX 1228 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus, 1229 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR), 1230 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO), 1231 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI), 1232 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC), 1233 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA), 1234 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC)); 1235 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n", 1236 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0), 1237 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1), 1238 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0), 1239 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1), 1240 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC)); 1241 #endif 1242 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 1243 jme_intr_rx(sc); 1244 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) { 1245 /* 1246 * Notify hardware availability of new Rx 1247 * buffers. 1248 * Reading RXCSR takes very long time under 1249 * heavy load so cache RXCSR value and writes 1250 * the ORed value with the kick command to 1251 * the RXCSR. This saves one register access 1252 * cycle. 1253 */ 1254 sc->jme_rx_cons = 0; 1255 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1256 JME_RXCSR, 1257 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START); 1258 } 1259 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 1260 jme_ifstart(&sc->jme_if); 1261 1262 goto again; 1263 1264 done: 1265 /* enable interrupts. */ 1266 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1267 JME_INTR_MASK_SET, JME_INTRS_ENABLE); 1268 return 1; 1269 } 1270 1271 1272 static int 1273 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1274 { 1275 struct jme_softc *sc = ifp->if_softc; 1276 int s, error; 1277 struct ifreq *ifr; 1278 struct ifcapreq *ifcr; 1279 1280 s = splnet(); 1281 /* 1282 * we can't support at the same time jumbo frames and 1283 * TX checksums offload/TSO 1284 */ 1285 switch(cmd) { 1286 case SIOCSIFMTU: 1287 ifr = data; 1288 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE && 1289 (ifp->if_capenable & ( 1290 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1291 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1292 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1293 splx(s); 1294 return EINVAL; 1295 } 1296 break; 1297 case SIOCSIFCAP: 1298 ifcr = data; 1299 if (ifp->if_mtu > JME_TX_FIFO_SIZE && 1300 (ifcr->ifcr_capenable & ( 1301 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx| 1302 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx| 1303 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) { 1304 splx(s); 1305 return EINVAL; 1306 } 1307 break; 1308 } 1309 1310 error = ether_ioctl(ifp, cmd, data); 1311 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) { 1312 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1313 jme_set_filter(sc); 1314 error = 0; 1315 } else { 1316 error = jme_init(ifp, 0); 1317 } 1318 } 1319 splx(s); 1320 return error; 1321 } 1322 1323 static int 1324 jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1325 { 1326 struct jme_desc *txd; 1327 struct jme_desc *desc; 1328 struct mbuf *m; 1329 struct m_tag *mtag; 1330 int error, i, prod, headdsc, nsegs; 1331 uint32_t cflags, tso_segsz; 1332 1333 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){ 1334 /* 1335 * Due to the adherence to NDIS specification JMC250 1336 * assumes upper stack computed TCP pseudo checksum 1337 * without including payload length. This breaks 1338 * checksum offload for TSO case so recompute TCP 1339 * pseudo checksum for JMC250. Hopefully this wouldn't 1340 * be much burden on modern CPUs. 1341 */ 1342 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1343 int iphl = v4 ? 1344 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) : 1345 M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data); 1346 /* 1347 * note: we support vlan offloading, so we should never have 1348 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always 1349 * right. 1350 */ 1351 int hlen = ETHER_HDR_LEN + iphl; 1352 1353 if (__predict_false((*m_head)->m_len < 1354 (hlen + sizeof(struct tcphdr)))) { 1355 /* 1356 * TCP/IP headers are not in the first mbuf; we need 1357 * to do this the slow and painful way. Let's just 1358 * hope this doesn't happen very often. 1359 */ 1360 struct tcphdr th; 1361 1362 m_copydata((*m_head), hlen, sizeof(th), &th); 1363 if (v4) { 1364 struct ip ip; 1365 1366 m_copydata((*m_head), ETHER_HDR_LEN, 1367 sizeof(ip), &ip); 1368 ip.ip_len = 0; 1369 m_copyback((*m_head), 1370 ETHER_HDR_LEN + offsetof(struct ip, ip_len), 1371 sizeof(ip.ip_len), &ip.ip_len); 1372 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1373 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1374 } else { 1375 #if INET6 1376 struct ip6_hdr ip6; 1377 1378 m_copydata((*m_head), ETHER_HDR_LEN, 1379 sizeof(ip6), &ip6); 1380 ip6.ip6_plen = 0; 1381 m_copyback((*m_head), ETHER_HDR_LEN + 1382 offsetof(struct ip6_hdr, ip6_plen), 1383 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1384 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1385 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1386 #endif /* INET6 */ 1387 } 1388 m_copyback((*m_head), 1389 hlen + offsetof(struct tcphdr, th_sum), 1390 sizeof(th.th_sum), &th.th_sum); 1391 1392 hlen += th.th_off << 2; 1393 } else { 1394 /* 1395 * TCP/IP headers are in the first mbuf; we can do 1396 * this the easy way. 1397 */ 1398 struct tcphdr *th; 1399 1400 if (v4) { 1401 struct ip *ip = 1402 (void *)(mtod((*m_head), char *) + 1403 ETHER_HDR_LEN); 1404 th = (void *)(mtod((*m_head), char *) + hlen); 1405 1406 ip->ip_len = 0; 1407 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1408 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1409 } else { 1410 #if INET6 1411 struct ip6_hdr *ip6 = 1412 (void *)(mtod((*m_head), char *) + 1413 ETHER_HDR_LEN); 1414 th = (void *)(mtod((*m_head), char *) + hlen); 1415 1416 ip6->ip6_plen = 0; 1417 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1418 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1419 #endif /* INET6 */ 1420 } 1421 hlen += th->th_off << 2; 1422 } 1423 1424 } 1425 1426 prod = sc->jme_tx_prod; 1427 txd = &sc->jme_txring[prod]; 1428 1429 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod], 1430 *m_head, BUS_DMA_WRITE); 1431 if (error) { 1432 if (error == EFBIG) { 1433 log(LOG_ERR, "%s: Tx packet consumes too many " 1434 "DMA segments, dropping...\n", 1435 device_xname(sc->jme_dev)); 1436 m_freem(*m_head); 1437 m_head = NULL; 1438 } 1439 return (error); 1440 } 1441 /* 1442 * Check descriptor overrun. Leave one free descriptor. 1443 * Since we always use 64bit address mode for transmitting, 1444 * each Tx request requires one more dummy descriptor. 1445 */ 1446 nsegs = sc->jme_txmbufm[prod]->dm_nsegs; 1447 #ifdef JMEDEBUG_TX 1448 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt); 1449 #endif 1450 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) { 1451 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]); 1452 return (ENOBUFS); 1453 } 1454 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod], 1455 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE); 1456 1457 m = *m_head; 1458 cflags = 0; 1459 tso_segsz = 0; 1460 /* Configure checksum offload and TSO. */ 1461 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) { 1462 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT; 1463 cflags |= JME_TD_TSO; 1464 } else { 1465 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) 1466 cflags |= JME_TD_IPCSUM; 1467 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0) 1468 cflags |= JME_TD_TCPCSUM; 1469 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0) 1470 cflags |= JME_TD_UDPCSUM; 1471 } 1472 /* Configure VLAN. */ 1473 if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) { 1474 cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); 1475 cflags |= JME_TD_VLAN_TAG; 1476 } 1477 1478 desc = &sc->jme_txring[prod]; 1479 desc->flags = htole32(cflags); 1480 desc->buflen = htole32(tso_segsz); 1481 desc->addr_hi = htole32(m->m_pkthdr.len); 1482 desc->addr_lo = 0; 1483 headdsc = prod; 1484 sc->jme_tx_cnt++; 1485 JME_DESC_INC(prod, JME_NBUFS); 1486 for (i = 0; i < nsegs; i++) { 1487 desc = &sc->jme_txring[prod]; 1488 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1489 desc->buflen = 1490 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len); 1491 desc->addr_hi = htole32( 1492 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1493 desc->addr_lo = htole32( 1494 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr)); 1495 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1496 prod * sizeof(struct jme_desc), sizeof(struct jme_desc), 1497 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1498 sc->jme_txmbuf[prod] = NULL; 1499 sc->jme_tx_cnt++; 1500 JME_DESC_INC(prod, JME_NBUFS); 1501 } 1502 1503 /* Update producer index. */ 1504 sc->jme_tx_prod = prod; 1505 #ifdef JMEDEBUG_TX 1506 printf("jme_encap prod now %d\n", sc->jme_tx_prod); 1507 #endif 1508 /* 1509 * Finally request interrupt and give the first descriptor 1510 * owenership to hardware. 1511 */ 1512 desc = &sc->jme_txring[headdsc]; 1513 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1514 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1515 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc), 1516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1517 1518 sc->jme_txmbuf[headdsc] = m; 1519 return (0); 1520 } 1521 1522 static void 1523 jme_txeof(struct jme_softc *sc) 1524 { 1525 struct ifnet *ifp; 1526 struct jme_desc *desc; 1527 uint32_t status; 1528 int cons, cons0, nsegs, seg; 1529 1530 ifp = &sc->jme_if; 1531 1532 #ifdef JMEDEBUG_TX 1533 printf("jme_txeof cons %d prod %d\n", 1534 sc->jme_tx_cons, sc->jme_tx_prod); 1535 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1536 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1537 "JME_TXTRHD 0x%x\n", 1538 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1539 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1540 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1541 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1542 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1543 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1544 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1545 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1546 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) { 1547 desc = &sc->jme_txring[cons]; 1548 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons, 1549 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo); 1550 JME_DESC_INC(cons, JME_NBUFS); 1551 } 1552 #endif 1553 1554 cons = sc->jme_tx_cons; 1555 if (cons == sc->jme_tx_prod) 1556 return; 1557 1558 /* 1559 * Go through our Tx list and free mbufs for those 1560 * frames which have been transmitted. 1561 */ 1562 for (; cons != sc->jme_tx_prod;) { 1563 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1564 cons * sizeof(struct jme_desc), sizeof(struct jme_desc), 1565 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1566 1567 desc = &sc->jme_txring[cons]; 1568 status = le32toh(desc->flags); 1569 #ifdef JMEDEBUG_TX 1570 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status, 1571 sc->jme_txmbufm[cons]->dm_nsegs); 1572 #endif 1573 if (status & JME_TD_OWN) 1574 break; 1575 1576 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 1577 ifp->if_oerrors++; 1578 else { 1579 ifp->if_opackets++; 1580 if ((status & JME_TD_COLLISION) != 0) 1581 ifp->if_collisions += 1582 le32toh(desc->buflen) & 1583 JME_TD_BUF_LEN_MASK; 1584 } 1585 /* 1586 * Only the first descriptor of multi-descriptor 1587 * transmission is updated so driver have to skip entire 1588 * chained buffers for the transmiited frame. In other 1589 * words, JME_TD_OWN bit is valid only at the first 1590 * descriptor of a multi-descriptor transmission. 1591 */ 1592 nsegs = sc->jme_txmbufm[cons]->dm_nsegs; 1593 cons0 = cons; 1594 JME_DESC_INC(cons, JME_NBUFS); 1595 for (seg = 1; seg < nsegs + 1; seg++) { 1596 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap, 1597 cons * sizeof(struct jme_desc), 1598 sizeof(struct jme_desc), 1599 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1600 sc->jme_txring[cons].flags = 0; 1601 JME_DESC_INC(cons, JME_NBUFS); 1602 } 1603 /* Reclaim transferred mbufs. */ 1604 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0], 1605 0, sc->jme_txmbufm[cons0]->dm_mapsize, 1606 BUS_DMASYNC_POSTWRITE); 1607 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]); 1608 1609 KASSERT(sc->jme_txmbuf[cons0] != NULL); 1610 m_freem(sc->jme_txmbuf[cons0]); 1611 sc->jme_txmbuf[cons0] = NULL; 1612 sc->jme_tx_cnt -= nsegs + 1; 1613 KASSERT(sc->jme_tx_cnt >= 0); 1614 sc->jme_if.if_flags &= ~IFF_OACTIVE; 1615 } 1616 sc->jme_tx_cons = cons; 1617 /* Unarm watchog timer when there is no pending descriptors in queue. */ 1618 if (sc->jme_tx_cnt == 0) 1619 ifp->if_timer = 0; 1620 #ifdef JMEDEBUG_TX 1621 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt); 1622 #endif 1623 } 1624 1625 static void 1626 jme_ifstart(struct ifnet *ifp) 1627 { 1628 jme_softc_t *sc = ifp->if_softc; 1629 struct mbuf *mb_head; 1630 int enq; 1631 1632 /* 1633 * check if we can free some desc. 1634 * Clear TX interrupt status to reset TX coalescing counters. 1635 */ 1636 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1637 JME_INTR_STATUS, INTR_TXQ_COMP); 1638 jme_txeof(sc); 1639 1640 if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1641 return; 1642 for (enq = 0;; enq++) { 1643 nexttx: 1644 /* Grab a paquet for output */ 1645 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1646 if (mb_head == NULL) { 1647 #ifdef JMEDEBUG_TX 1648 printf("%s: nothing to send\n", __func__); 1649 #endif 1650 break; 1651 } 1652 /* try to add this mbuf to the TX ring */ 1653 if (jme_encap(sc, &mb_head)) { 1654 if (mb_head == NULL) { 1655 ifp->if_oerrors++; 1656 /* packet dropped, try next one */ 1657 goto nexttx; 1658 } 1659 /* resource shortage, try again later */ 1660 IF_PREPEND(&ifp->if_snd, mb_head); 1661 ifp->if_flags |= IFF_OACTIVE; 1662 break; 1663 } 1664 #if NBPFILTER > 0 1665 /* Pass packet to bpf if there is a listener */ 1666 if (ifp->if_bpf) 1667 bpf_mtap(ifp->if_bpf, mb_head); 1668 #endif 1669 } 1670 #ifdef JMEDEBUG_TX 1671 printf("jme_ifstart enq %d\n", enq); 1672 #endif 1673 if (enq) { 1674 /* 1675 * Set a 5 second timer just in case we don't hear from 1676 * the card again. 1677 */ 1678 ifp->if_timer = 5; 1679 /* 1680 * Reading TXCSR takes very long time under heavy load 1681 * so cache TXCSR value and writes the ORed value with 1682 * the kick command to the TXCSR. This saves one register 1683 * access cycle. 1684 */ 1685 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, 1686 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1687 #ifdef JMEDEBUG_TX 1688 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x " 1689 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x " 1690 "JME_TXTRHD 0x%x\n", 1691 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR), 1692 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO), 1693 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI), 1694 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC), 1695 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA), 1696 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC), 1697 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC), 1698 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)); 1699 #endif 1700 } 1701 } 1702 1703 static void 1704 jme_ifwatchdog(struct ifnet *ifp) 1705 { 1706 jme_softc_t *sc = ifp->if_softc; 1707 1708 if ((ifp->if_flags & IFF_RUNNING) == 0) 1709 return; 1710 printf("%s: device timeout\n", device_xname(sc->jme_dev)); 1711 ifp->if_oerrors++; 1712 jme_init(ifp, 0); 1713 } 1714 1715 static int 1716 jme_mediachange(struct ifnet *ifp) 1717 { 1718 int error; 1719 jme_softc_t *sc = ifp->if_softc; 1720 1721 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO) 1722 error = 0; 1723 else if (error != 0) { 1724 aprint_error_dev(sc->jme_dev, "could not set media\n"); 1725 return error; 1726 } 1727 return 0; 1728 } 1729 1730 static void 1731 jme_ticks(void *v) 1732 { 1733 jme_softc_t *sc = v; 1734 int s = splnet(); 1735 1736 /* Tick the MII. */ 1737 mii_tick(&sc->jme_mii); 1738 1739 /* every seconds */ 1740 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc); 1741 splx(s); 1742 } 1743 1744 static void 1745 jme_mac_config(jme_softc_t *sc) 1746 { 1747 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1748 struct mii_data *mii = &sc->jme_mii; 1749 1750 ghc = 0; 1751 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1752 rxmac &= ~RXMAC_FC_ENB; 1753 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC); 1754 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1755 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC); 1756 txpause &= ~TXPFC_PAUSE_ENB; 1757 1758 if (mii->mii_media_active & IFM_FDX) { 1759 ghc |= GHC_FULL_DUPLEX; 1760 rxmac &= ~RXMAC_COLL_DET_ENB; 1761 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1762 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1763 TXMAC_FRAME_BURST); 1764 /* Disable retry transmit timer/retry limit. */ 1765 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1766 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) 1767 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 1768 } else { 1769 rxmac |= RXMAC_COLL_DET_ENB; 1770 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 1771 /* Enable retry transmit timer/retry limit. */ 1772 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD, 1773 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 1774 } 1775 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 1776 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1777 case IFM_10_T: 1778 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100; 1779 break; 1780 case IFM_100_TX: 1781 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100; 1782 break; 1783 case IFM_1000_T: 1784 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000; 1785 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 1786 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 1787 break; 1788 default: 1789 break; 1790 } 1791 if ((sc->jme_flags & JME_FLAG_GIGA) && 1792 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 1793 /* 1794 * Workaround occasional packet loss issue of JMC250 A2 1795 * when it runs on half-duplex media. 1796 */ 1797 #ifdef JMEDEBUG 1798 printf("JME250 A2 workaround\n"); 1799 #endif 1800 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, 1801 JME_GPREG1); 1802 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1803 gpreg &= ~GPREG1_HDPX_FIX; 1804 else 1805 gpreg |= GPREG1_HDPX_FIX; 1806 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, 1807 JME_GPREG1, gpreg); 1808 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 1809 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 1810 /* Extend interface FIFO depth. */ 1811 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1812 0x1B, 0x0000); 1813 } else { 1814 /* Select default interface FIFO depth. */ 1815 jme_mii_write(sc->jme_dev, sc->jme_phyaddr, 1816 0x1B, 0x0004); 1817 } 1818 } 1819 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc); 1820 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac); 1821 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac); 1822 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause); 1823 } 1824 1825 static void 1826 jme_set_filter(jme_softc_t *sc) 1827 { 1828 struct ifnet *ifp = &sc->jme_if; 1829 struct ether_multistep step; 1830 struct ether_multi *enm; 1831 uint32_t hash[2] = {0, 0}; 1832 int i; 1833 uint32_t rxcfg; 1834 1835 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC); 1836 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 1837 RXMAC_ALLMULTI); 1838 /* Always accept frames destined to our station address. */ 1839 rxcfg |= RXMAC_UNICAST; 1840 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1841 rxcfg |= RXMAC_BROADCAST; 1842 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1843 if ((ifp->if_flags & IFF_PROMISC) != 0) 1844 rxcfg |= RXMAC_PROMISC; 1845 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1846 rxcfg |= RXMAC_ALLMULTI; 1847 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1848 JME_MAR0, 0xFFFFFFFF); 1849 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1850 JME_MAR1, 0xFFFFFFFF); 1851 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, 1852 JME_RXMAC, rxcfg); 1853 return; 1854 } 1855 /* 1856 * Set up the multicast address filter by passing all multicast 1857 * addresses through a CRC generator, and then using the low-order 1858 * 6 bits as an index into the 64 bit multicast hash table. The 1859 * high order bits select the register, while the rest of the bits 1860 * select the bit within the register. 1861 */ 1862 rxcfg |= RXMAC_MULTICAST; 1863 memset(hash, 0, sizeof(hash)); 1864 1865 ETHER_FIRST_MULTI(step, &sc->jme_ec, enm); 1866 while (enm != NULL) { 1867 #ifdef JEMDBUG 1868 printf("%s: addrs %s %s\n", __func__, 1869 ether_sprintf(enm->enm_addrlo), 1870 ether_sprintf(enm->enm_addrhi)); 1871 #endif 1872 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1873 i = ether_crc32_be(enm->enm_addrlo, 6); 1874 /* Just want the 6 least significant bits. */ 1875 i &= 0x3f; 1876 hash[i / 32] |= 1 << (i%32); 1877 } else { 1878 hash[0] = hash[1] = 0xffffffff; 1879 sc->jme_if.if_flags |= IFF_ALLMULTI; 1880 break; 1881 } 1882 ETHER_NEXT_MULTI(step, enm); 1883 } 1884 #ifdef JMEDEBUG 1885 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1886 #endif 1887 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]); 1888 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]); 1889 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg); 1890 } 1891 1892 #if 0 1893 static int 1894 jme_multicast_hash(uint8_t *a) 1895 { 1896 int hash; 1897 1898 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1899 #define xor8(a,b,c,d,e,f,g,h) \ 1900 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1901 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1902 1903 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1904 DA(a,36), DA(a,42)); 1905 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1906 DA(a,37), DA(a,43)) << 1; 1907 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1908 DA(a,38), DA(a,44)) << 2; 1909 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1910 DA(a,39), DA(a,45)) << 3; 1911 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1912 DA(a,40), DA(a,46)) << 4; 1913 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1914 DA(a,41), DA(a,47)) << 5; 1915 1916 return hash; 1917 } 1918 #endif 1919 1920 static int 1921 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 1922 { 1923 uint32_t reg; 1924 int i; 1925 1926 *val = 0; 1927 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1928 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1929 JME_SMBCSR); 1930 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 1931 break; 1932 delay(10); 1933 } 1934 1935 if (i == 0) { 1936 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n"); 1937 return (ETIMEDOUT); 1938 } 1939 1940 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 1941 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy, 1942 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 1943 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) { 1944 delay(10); 1945 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, 1946 JME_SMBINTF); 1947 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 1948 break; 1949 } 1950 1951 if (i == 0) { 1952 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n"); 1953 return (ETIMEDOUT); 1954 } 1955 1956 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF); 1957 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 1958 return (0); 1959 } 1960 1961 1962 static int 1963 jme_eeprom_macaddr(struct jme_softc *sc) 1964 { 1965 uint8_t eaddr[ETHER_ADDR_LEN]; 1966 uint8_t fup, reg, val; 1967 uint32_t offset; 1968 int match; 1969 1970 offset = 0; 1971 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1972 fup != JME_EEPROM_SIG0) 1973 return (ENOENT); 1974 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 1975 fup != JME_EEPROM_SIG1) 1976 return (ENOENT); 1977 match = 0; 1978 do { 1979 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 1980 break; 1981 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) 1982 == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) { 1983 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 1984 break; 1985 if (reg >= JME_PAR0 && 1986 reg < JME_PAR0 + ETHER_ADDR_LEN) { 1987 if (jme_eeprom_read_byte(sc, offset + 2, 1988 &val) != 0) 1989 break; 1990 eaddr[reg - JME_PAR0] = val; 1991 match++; 1992 } 1993 } 1994 if (fup & JME_EEPROM_DESC_END) 1995 break; 1996 1997 /* Try next eeprom descriptor. */ 1998 offset += JME_EEPROM_DESC_BYTES; 1999 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 2000 2001 if (match == ETHER_ADDR_LEN) { 2002 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN); 2003 return (0); 2004 } 2005 2006 return (ENOENT); 2007 } 2008 2009 /* 2010 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be 2011 * set up in jme_pci_attach() 2012 */ 2013 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup") 2014 { 2015 int rc; 2016 const struct sysctlnode *node; 2017 2018 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2019 0, CTLTYPE_NODE, "hw", NULL, 2020 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2021 goto err; 2022 } 2023 2024 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2025 0, CTLTYPE_NODE, "jme", 2026 SYSCTL_DESCR("jme interface controls"), 2027 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2028 goto err; 2029 } 2030 2031 jme_root_num = node->sysctl_num; 2032 return; 2033 2034 err: 2035 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2036 } 2037 2038 static int 2039 jme_sysctl_intrxto(SYSCTLFN_ARGS) 2040 { 2041 int error, t; 2042 struct sysctlnode node; 2043 struct jme_softc *sc; 2044 uint32_t reg; 2045 2046 node = *rnode; 2047 sc = node.sysctl_data; 2048 t = sc->jme_intrxto; 2049 node.sysctl_data = &t; 2050 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2051 if (error || newp == NULL) 2052 return error; 2053 2054 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX) 2055 return EINVAL; 2056 2057 /* 2058 * update the softc with sysctl-changed value, and mark 2059 * for hardware update 2060 */ 2061 sc->jme_intrxto = t; 2062 /* Configure Rx queue 0 packet completion coalescing. */ 2063 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2064 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2065 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2066 return 0; 2067 } 2068 2069 static int 2070 jme_sysctl_intrxct(SYSCTLFN_ARGS) 2071 { 2072 int error, t; 2073 struct sysctlnode node; 2074 struct jme_softc *sc; 2075 uint32_t reg; 2076 2077 node = *rnode; 2078 sc = node.sysctl_data; 2079 t = sc->jme_intrxct; 2080 node.sysctl_data = &t; 2081 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2082 if (error || newp == NULL) 2083 return error; 2084 2085 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX) 2086 return EINVAL; 2087 2088 /* 2089 * update the softc with sysctl-changed value, and mark 2090 * for hardware update 2091 */ 2092 sc->jme_intrxct = t; 2093 /* Configure Rx queue 0 packet completion coalescing. */ 2094 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK; 2095 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK; 2096 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg); 2097 return 0; 2098 } 2099 2100 static int 2101 jme_sysctl_inttxto(SYSCTLFN_ARGS) 2102 { 2103 int error, t; 2104 struct sysctlnode node; 2105 struct jme_softc *sc; 2106 uint32_t reg; 2107 2108 node = *rnode; 2109 sc = node.sysctl_data; 2110 t = sc->jme_inttxto; 2111 node.sysctl_data = &t; 2112 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2113 if (error || newp == NULL) 2114 return error; 2115 2116 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX) 2117 return EINVAL; 2118 2119 /* 2120 * update the softc with sysctl-changed value, and mark 2121 * for hardware update 2122 */ 2123 sc->jme_inttxto = t; 2124 /* Configure Tx queue 0 packet completion coalescing. */ 2125 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2126 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2127 reg |= PCCTX_COAL_TXQ0; 2128 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2129 return 0; 2130 } 2131 2132 static int 2133 jme_sysctl_inttxct(SYSCTLFN_ARGS) 2134 { 2135 int error, t; 2136 struct sysctlnode node; 2137 struct jme_softc *sc; 2138 uint32_t reg; 2139 2140 node = *rnode; 2141 sc = node.sysctl_data; 2142 t = sc->jme_inttxct; 2143 node.sysctl_data = &t; 2144 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2145 if (error || newp == NULL) 2146 return error; 2147 2148 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX) 2149 return EINVAL; 2150 2151 /* 2152 * update the softc with sysctl-changed value, and mark 2153 * for hardware update 2154 */ 2155 sc->jme_inttxct = t; 2156 /* Configure Tx queue 0 packet completion coalescing. */ 2157 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK; 2158 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK; 2159 reg |= PCCTX_COAL_TXQ0; 2160 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg); 2161 return 0; 2162 } 2163