1 /* $NetBSD: if_ixlvar.h,v 1.7 2020/09/08 10:05:47 yamaguchi Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_PCI_IF_IXLVAR_H_ 30 #define _DEV_PCI_IF_IXLVAR_H_ 31 32 enum i40e_filter_pctype { 33 /* Note: Values 0-28 are reserved for future use. 34 * Value 29, 30, 32 are not supported on XL710 and X710. 35 */ 36 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 37 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 38 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 39 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 40 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 41 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 42 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 43 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 44 /* Note: Values 37-38 are reserved for future use. 45 * Value 39, 40, 42 are not supported on XL710 and X710. 46 */ 47 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 48 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 49 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 50 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 51 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 52 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 53 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 54 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 55 /* Note: Value 47 is reserved for future use */ 56 I40E_FILTER_PCTYPE_FCOE_OX = 48, 57 I40E_FILTER_PCTYPE_FCOE_RX = 49, 58 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 59 /* Note: Values 51-62 are reserved for future use */ 60 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 61 }; 62 63 #define IXL_BIT_ULL(a) (1ULL << (a)) 64 #define IXL_RSS_HENA_DEFAULT_BASE \ 65 (IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 66 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 67 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 68 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 69 IXL_BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 70 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 71 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 72 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 73 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 74 IXL_BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 75 IXL_BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 76 #define IXL_RSS_HENA_DEFAULT_XL710 IXL_RSS_HENA_DEFAULT_BASE 77 #define IXL_RSS_HENA_DEFAULT_X722 (IXL_RSS_HENA_DEFAULT_XL710 | \ 78 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 79 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 80 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 81 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 82 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 83 IXL_BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK)) 84 85 #define IXL_RSS_VSI_LUT_SIZE 64 86 #define IXL_RSS_KEY_SIZE_REG 13 87 #define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * sizeof(uint32_t)) 88 89 enum i40e_reset_type { 90 I40E_RESET_POR = 0, 91 I40E_RESET_CORER = 1, 92 I40E_RESET_GLOBR = 2, 93 I40E_RESET_EMPR = 3, 94 }; 95 96 struct ixl_aq_desc { 97 uint16_t iaq_flags; 98 #define IXL_AQ_DD (1U << 0) 99 #define IXL_AQ_CMP (1U << 1) 100 #define IXL_AQ_ERR (1U << 2) 101 #define IXL_AQ_VFE (1U << 3) 102 #define IXL_AQ_LB (1U << 9) 103 #define IXL_AQ_RD (1U << 10) 104 #define IXL_AQ_VFC (1U << 11) 105 #define IXL_AQ_BUF (1U << 12) 106 #define IXL_AQ_SI (1U << 13) 107 #define IXL_AQ_EI (1U << 14) 108 #define IXL_AQ_FE (1U << 15) 109 110 #define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 111 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 112 "\003ERR" "\002CMP" "\001DD" 113 114 uint16_t iaq_opcode; 115 116 uint16_t iaq_datalen; 117 uint16_t iaq_retval; 118 119 uint64_t iaq_cookie; 120 121 uint32_t iaq_param[4]; 122 /* iaq_data_hi iaq_param[2] */ 123 /* iaq_data_lo iaq_param[3] */ 124 } __packed __aligned(16); 125 126 /* aq commands */ 127 #define IXL_AQ_OP_GET_VERSION 0x0001 128 #define IXL_AQ_OP_DRIVER_VERSION 0x0002 129 #define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 130 #define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 131 #define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 132 #define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 133 #define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 134 #define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 135 #define IXL_AQ_OP_LIST_DEV_CAP 0x000b 136 #define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 137 #define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 138 #define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 139 #define IXL_AQ_OP_RX_CTL_REG_READ 0x0206 140 #define IXL_AQ_OP_RX_CTL_REG_WRITE 0x0207 141 #define IXL_AQ_OP_ADD_VSI 0x0210 142 #define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 143 #define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 144 #define IXL_AQ_OP_ADD_VEB 0x0230 145 #define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 146 #define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 147 #define IXL_AQ_OP_ADD_MACVLAN 0x0250 148 #define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 149 #define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 150 #define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 151 #define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 152 #define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 153 #define IXL_AQ_OP_PHY_RESTART_AN 0x0605 154 #define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 155 #define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 156 #define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 157 #define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 158 #define IXL_AQ_OP_NVM_READ 0x0701 159 #define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 160 #define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 161 #define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 162 #define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 163 #define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 164 #define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 165 #define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 166 #define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 167 #define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 168 #define IXL_AQ_OP_RSS_SET_KEY 0x0b02 169 #define IXL_AQ_OP_RSS_SET_LUT 0x0b03 170 #define IXL_AQ_OP_RSS_GET_KEY 0x0b04 171 #define IXL_AQ_OP_RSS_GET_LUT 0x0b05 172 173 static inline void 174 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 175 { 176 uint64_t val; 177 178 if (sizeof(addr) > 4) { 179 val = (intptr_t)addr; 180 iaq->iaq_param[2] = htole32(val >> 32); 181 } else { 182 iaq->iaq_param[2] = htole32(0); 183 } 184 185 iaq->iaq_param[3] = htole32(addr); 186 } 187 188 static inline bool 189 ixl_aq_has_dva(struct ixl_aq_desc *iaq) 190 { 191 uint64_t val; 192 193 if (sizeof(bus_addr_t) > 4) { 194 val = le32toh(iaq->iaq_param[2]); 195 val = val << 32; 196 } else { 197 val = 0; 198 } 199 val |= htole32(iaq->iaq_param[3]); 200 201 return !(val == 0); 202 } 203 204 struct ixl_aq_mac_addresses { 205 uint8_t pf_lan[ETHER_ADDR_LEN]; 206 uint8_t pf_san[ETHER_ADDR_LEN]; 207 uint8_t port[ETHER_ADDR_LEN]; 208 uint8_t pf_wol[ETHER_ADDR_LEN]; 209 } __packed; 210 211 #define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 212 #define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 213 #define IXL_AQ_MAC_PORT_VALID (1U << 6) 214 #define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 215 216 struct ixl_aq_capability { 217 uint16_t cap_id; 218 #define IXL_AQ_CAP_SWITCH_MODE 0x0001 219 #define IXL_AQ_CAP_MNG_MODE 0x0002 220 #define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 221 #define IXL_AQ_CAP_OS2BMC_CAP 0x0004 222 #define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 223 #define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 224 #define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 225 #define IXL_AQ_CAP_SRIOV 0x0012 226 #define IXL_AQ_CAP_VF 0x0013 227 #define IXL_AQ_CAP_VMDQ 0x0014 228 #define IXL_AQ_CAP_8021QBG 0x0015 229 #define IXL_AQ_CAP_8021QBR 0x0016 230 #define IXL_AQ_CAP_VSI 0x0017 231 #define IXL_AQ_CAP_DCB 0x0018 232 #define IXL_AQ_CAP_FCOE 0x0021 233 #define IXL_AQ_CAP_ISCSI 0x0022 234 #define IXL_AQ_CAP_RSS 0x0040 235 #define IXL_AQ_CAP_RXQ 0x0041 236 #define IXL_AQ_CAP_TXQ 0x0042 237 #define IXL_AQ_CAP_MSIX 0x0043 238 #define IXL_AQ_CAP_VF_MSIX 0x0044 239 #define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 240 #define IXL_AQ_CAP_1588 0x0046 241 #define IXL_AQ_CAP_IWARP 0x0051 242 #define IXL_AQ_CAP_LED 0x0061 243 #define IXL_AQ_CAP_SDP 0x0062 244 #define IXL_AQ_CAP_MDIO 0x0063 245 #define IXL_AQ_CAP_WSR_PROT 0x0064 246 #define IXL_AQ_CAP_NVM_MGMT 0x0080 247 #define IXL_AQ_CAP_FLEX10 0x00F1 248 #define IXL_AQ_CAP_CEM 0x00F2 249 uint8_t major_rev; 250 uint8_t minor_rev; 251 uint32_t number; 252 uint32_t logical_id; 253 uint32_t phys_id; 254 uint8_t _reserved[16]; 255 } __packed __aligned(4); 256 257 #define IXL_LLDP_SHUTDOWN 0x1 258 259 struct ixl_aq_switch_config { 260 uint16_t num_reported; 261 uint16_t num_total; 262 uint8_t _reserved[12]; 263 } __packed __aligned(4); 264 265 struct ixl_aq_switch_config_element { 266 uint8_t type; 267 #define IXL_AQ_SW_ELEM_TYPE_MAC 1 268 #define IXL_AQ_SW_ELEM_TYPE_PF 2 269 #define IXL_AQ_SW_ELEM_TYPE_VF 3 270 #define IXL_AQ_SW_ELEM_TYPE_EMP 4 271 #define IXL_AQ_SW_ELEM_TYPE_BMC 5 272 #define IXL_AQ_SW_ELEM_TYPE_PV 16 273 #define IXL_AQ_SW_ELEM_TYPE_VEB 17 274 #define IXL_AQ_SW_ELEM_TYPE_PA 18 275 #define IXL_AQ_SW_ELEM_TYPE_VSI 19 276 uint8_t revision; 277 #define IXL_AQ_SW_ELEM_REV_1 1 278 uint16_t seid; 279 280 uint16_t uplink_seid; 281 uint16_t downlink_seid; 282 283 uint8_t _reserved[3]; 284 uint8_t connection_type; 285 #define IXL_AQ_CONN_TYPE_REGULAR 0x1 286 #define IXL_AQ_CONN_TYPE_DEFAULT 0x2 287 #define IXL_AQ_CONN_TYPE_CASCADED 0x3 288 289 uint16_t scheduler_id; 290 uint16_t element_info; 291 } __packed __aligned(4); 292 293 #define IXL_PHY_TYPE_SGMII 0x00 294 #define IXL_PHY_TYPE_1000BASE_KX 0x01 295 #define IXL_PHY_TYPE_10GBASE_KX4 0x02 296 #define IXL_PHY_TYPE_10GBASE_KR 0x03 297 #define IXL_PHY_TYPE_40GBASE_KR4 0x04 298 #define IXL_PHY_TYPE_XAUI 0x05 299 #define IXL_PHY_TYPE_XFI 0x06 300 #define IXL_PHY_TYPE_SFI 0x07 301 #define IXL_PHY_TYPE_XLAUI 0x08 302 #define IXL_PHY_TYPE_XLPPI 0x09 303 #define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 304 #define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 305 #define IXL_PHY_TYPE_10GBASE_AOC 0x0c 306 #define IXL_PHY_TYPE_40GBASE_AOC 0x0d 307 #define IXL_PHY_TYPE_100BASE_TX 0x11 308 #define IXL_PHY_TYPE_1000BASE_T 0x12 309 #define IXL_PHY_TYPE_10GBASE_T 0x13 310 #define IXL_PHY_TYPE_10GBASE_SR 0x14 311 #define IXL_PHY_TYPE_10GBASE_LR 0x15 312 #define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 313 #define IXL_PHY_TYPE_10GBASE_CR1 0x17 314 #define IXL_PHY_TYPE_40GBASE_CR4 0x18 315 #define IXL_PHY_TYPE_40GBASE_SR4 0x19 316 #define IXL_PHY_TYPE_40GBASE_LR4 0x1a 317 #define IXL_PHY_TYPE_1000BASE_SX 0x1b 318 #define IXL_PHY_TYPE_1000BASE_LX 0x1c 319 #define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 320 #define IXL_PHY_TYPE_20GBASE_KR2 0x1e 321 322 #define IXL_PHY_TYPE_25GBASE_KR 0x1f 323 #define IXL_PHY_TYPE_25GBASE_CR 0x20 324 #define IXL_PHY_TYPE_25GBASE_SR 0x21 325 #define IXL_PHY_TYPE_25GBASE_LR 0x22 326 #define IXL_PHY_TYPE_25GBASE_AOC 0x23 327 #define IXL_PHY_TYPE_25GBASE_ACC 0x24 328 329 #define IXL_PHY_LINK_SPEED_100MB (1 << 1) 330 #define IXL_PHY_LINK_SPEED_1000MB (1 << 2) 331 #define IXL_PHY_LINK_SPEED_10GB (1 << 3) 332 #define IXL_PHY_LINK_SPEED_40GB (1 << 4) 333 #define IXL_PHY_LINK_SPEED_20GB (1 << 5) 334 #define IXL_PHY_LINK_SPEED_25GB (1 << 6) 335 336 #define IXL_PHY_ABILITY_PAUSE_TX (1 << 0) 337 #define IXL_PHY_ABILITY_PAUSE_RX (1 << 1) 338 #define IXL_PHY_ABILITY_LOWPOW (1 << 2) 339 #define IXL_PHY_ABILITY_LINKUP (1 << 3) 340 #define IXL_PHY_ABILITY_AUTONEGO (1 << 4) 341 #define IXL_PHY_ABILITY_MODQUAL (1 << 5) 342 343 struct ixl_aq_module_desc { 344 uint8_t oui[3]; 345 uint8_t _reserved1; 346 uint8_t part_number[16]; 347 uint8_t revision[4]; 348 uint8_t _reserved2[8]; 349 } __packed __aligned(4); 350 351 struct ixl_aq_phy_abilities { 352 uint32_t phy_type; 353 354 uint8_t link_speed; 355 uint8_t abilities; 356 uint16_t eee_capability; 357 358 uint32_t eeer_val; 359 360 uint8_t d3_lpan; 361 uint8_t phy_type_ext; 362 #define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 363 #define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 364 #define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 365 #define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 366 uint8_t fec_cfg_curr_mod_ext_info; 367 #define IXL_AQ_ENABLE_FEC_KR 0x01 368 #define IXL_AQ_ENABLE_FEC_RS 0x02 369 #define IXL_AQ_REQUEST_FEC_KR 0x04 370 #define IXL_AQ_REQUEST_FEC_RS 0x08 371 #define IXL_AQ_ENABLE_FEC_AUTO 0x10 372 #define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 373 #define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 374 uint8_t ext_comp_code; 375 376 uint8_t phy_id[4]; 377 378 uint8_t module_type[3]; 379 #define IXL_SFF8024_ID_SFP 0x03 380 #define IXL_SFF8024_ID_QSFP 0x0c 381 #define IXL_SFF8024_ID_QSFP_PLUS 0x0d 382 #define IXL_SFF8024_ID_QSFP28 0x11 383 uint8_t qualified_module_count; 384 #define IXL_AQ_PHY_MAX_QMS 16 385 struct ixl_aq_module_desc 386 qualified_module[IXL_AQ_PHY_MAX_QMS]; 387 } __packed __aligned(4); 388 389 struct ixl_aq_phy_param { 390 uint32_t phy_types; 391 uint8_t link_speed; 392 uint8_t abilities; 393 #define IXL_AQ_PHY_ABILITY_AUTO_LINK (1 << 5) 394 uint16_t eee_capability; 395 uint32_t eeer_val; 396 uint8_t d3_lpan; 397 uint8_t phy_type_ext; 398 uint8_t fec_cfg; 399 uint8_t config; 400 } __packed __aligned(4); 401 402 struct ixl_aq_link_param { 403 uint8_t notify; 404 #define IXL_AQ_LINK_NOTIFY 0x03 405 uint8_t _reserved1; 406 uint8_t phy; 407 uint8_t speed; 408 uint8_t status; 409 uint8_t _reserved2[11]; 410 } __packed __aligned(4); 411 412 struct ixl_aq_vsi_param { 413 uint16_t uplink_seid; 414 uint8_t connect_type; 415 #define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 416 #define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 417 #define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 418 uint8_t _reserved1; 419 420 uint8_t vf_id; 421 uint8_t _reserved2; 422 uint16_t vsi_flags; 423 #define IXL_AQ_VSI_TYPE_SHIFT 0x0 424 #define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 425 #define IXL_AQ_VSI_TYPE_VF 0x0 426 #define IXL_AQ_VSI_TYPE_VMDQ2 0x1 427 #define IXL_AQ_VSI_TYPE_PF 0x2 428 #define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 429 #define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 430 431 uint32_t addr_hi; 432 uint32_t addr_lo; 433 } __packed __aligned(16); 434 435 struct ixl_aq_add_macvlan { 436 uint16_t num_addrs; 437 uint16_t seid0; 438 uint16_t seid1; 439 uint16_t seid2; 440 uint32_t addr_hi; 441 uint32_t addr_lo; 442 } __packed __aligned(16); 443 444 struct ixl_aq_add_macvlan_elem { 445 uint8_t macaddr[6]; 446 uint16_t vlan; 447 uint16_t flags; 448 #define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 449 #define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 450 uint16_t queue; 451 uint32_t _reserved; 452 } __packed __aligned(16); 453 454 struct ixl_aq_remove_macvlan { 455 uint16_t num_addrs; 456 uint16_t seid0; 457 uint16_t seid1; 458 uint16_t seid2; 459 uint32_t addr_hi; 460 uint32_t addr_lo; 461 } __packed __aligned(16); 462 463 struct ixl_aq_remove_macvlan_elem { 464 uint8_t macaddr[6]; 465 uint16_t vlan; 466 uint8_t flags; 467 #define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 468 #define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 469 uint8_t _reserved[7]; 470 } __packed __aligned(16); 471 472 struct ixl_aq_vsi_reply { 473 uint16_t seid; 474 uint16_t vsi_number; 475 476 uint16_t vsis_used; 477 uint16_t vsis_free; 478 479 uint32_t addr_hi; 480 uint32_t addr_lo; 481 } __packed __aligned(16); 482 483 struct ixl_aq_vsi_data { 484 /* first 96 byte are written by SW */ 485 uint16_t valid_sections; 486 #define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 487 #define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 488 #define IXL_AQ_VSI_VALID_VLAN (1 << 2) 489 #define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 490 #define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 491 #define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 492 #define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 493 #define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 494 #define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 495 #define IXL_AQ_VSI_VALID_SCHED (1 << 9) 496 /* switch section */ 497 uint16_t switch_id; 498 #define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 499 #define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 500 #define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 501 #define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 502 503 uint8_t _reserved1[2]; 504 /* security section */ 505 uint8_t sec_flags; 506 #define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 507 #define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 508 #define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 509 uint8_t _reserved2; 510 511 /* vlan section */ 512 uint16_t pvid; 513 uint16_t fcoe_pvid; 514 515 uint8_t port_vlan_flags; 516 #define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 517 #define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 518 #define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 519 #define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 520 #define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 521 #define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 522 #define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 523 #define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 524 #define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 525 #define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 526 #define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 527 #define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 528 uint8_t _reserved3[3]; 529 530 /* ingress egress up section */ 531 uint32_t ingress_table; 532 #define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 533 #define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 534 uint32_t egress_table; 535 536 /* cascaded pv section */ 537 uint16_t cas_pv_tag; 538 uint8_t cas_pv_flags; 539 #define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 540 #define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 541 #define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 542 #define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 543 #define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 544 #define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 545 #define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 546 #define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 547 (1 << 6) 548 uint8_t _reserved4; 549 550 /* queue mapping section */ 551 uint16_t mapping_flags; 552 #define IXL_AQ_VSI_QUE_MAP_MASK 0x1 553 #define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 554 #define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 555 uint16_t queue_mapping[16]; 556 #define IXL_AQ_VSI_QUEUE_SHIFT 0x0 557 #define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 558 uint16_t tc_mapping[8]; 559 #define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 560 #define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 561 #define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 562 #define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 563 564 /* queueing option section */ 565 uint8_t queueing_opt_flags; 566 #define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 567 #define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 568 #define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 569 #define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 570 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 571 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 572 uint8_t _reserved5[3]; 573 574 /* scheduler section */ 575 uint8_t up_enable_bits; 576 uint8_t _reserved6; 577 578 /* outer up section */ 579 uint32_t outer_up_table; /* same as ingress/egress tables */ 580 uint8_t _reserved7[8]; 581 582 /* last 32 bytes are written by FW */ 583 uint16_t qs_handle[8]; 584 #define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 585 uint16_t stat_counter_idx; 586 uint16_t sched_id; 587 588 uint8_t _reserved8[12]; 589 } __packed __aligned(8); 590 591 CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 592 593 struct ixl_aq_vsi_promisc_param { 594 uint16_t flags; 595 uint16_t valid_flags; 596 #define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 597 #define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 598 #define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 599 #define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 600 #define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 601 #define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 602 603 uint16_t seid; 604 #define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 605 uint16_t vlan; 606 #define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 607 uint32_t reserved[2]; 608 } __packed __aligned(8); 609 610 struct ixl_aq_veb_param { 611 uint16_t uplink_seid; 612 uint16_t downlink_seid; 613 uint16_t veb_flags; 614 #define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 615 #define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 616 #define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 617 #define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 618 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 619 #define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 620 #define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 621 #define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 622 uint8_t enable_tcs; 623 uint8_t _reserved[9]; 624 } __packed __aligned(16); 625 626 struct ixl_aq_veb_reply { 627 uint16_t _reserved1; 628 uint16_t _reserved2; 629 uint16_t _reserved3; 630 uint16_t switch_seid; 631 uint16_t veb_seid; 632 #define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 633 #define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 634 #define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 635 #define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 636 uint16_t statistic_index; 637 uint16_t vebs_used; 638 uint16_t vebs_free; 639 } __packed __aligned(16); 640 641 /* GET PHY ABILITIES param[0] */ 642 #define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 643 #define IXL_AQ_PHY_REPORT_INIT (1 << 1) 644 645 struct ixl_aq_phy_reg_access { 646 uint8_t phy_iface; 647 #define IXL_AQ_PHY_IF_INTERNAL 0 648 #define IXL_AQ_PHY_IF_EXTERNAL 1 649 #define IXL_AQ_PHY_IF_MODULE 2 650 uint8_t dev_addr; 651 uint16_t recall; 652 #define IXL_AQ_PHY_QSFP_DEV_ADDR 0 653 #define IXL_AQ_PHY_QSFP_LAST 1 654 uint32_t reg; 655 uint32_t val; 656 uint32_t _reserved2; 657 } __packed __aligned(16); 658 659 /* RESTART_AN param[0] */ 660 #define IXL_AQ_PHY_RESTART_AN (1 << 1) 661 #define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 662 663 struct ixl_aq_link_status { /* this occupies the iaq_param space */ 664 uint16_t command_flags; /* only field set on command */ 665 #define IXL_AQ_LSE_MASK 0x3 666 #define IXL_AQ_LSE_NOP 0x0 667 #define IXL_AQ_LSE_DISABLE 0x2 668 #define IXL_AQ_LSE_ENABLE 0x3 669 #define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 670 uint8_t phy_type; 671 uint8_t link_speed; 672 #define IXL_AQ_LINK_SPEED_100MB (1 << 1) 673 #define IXL_AQ_LINK_SPEED_1000MB (1 << 2) 674 #define IXL_AQ_LINK_SPEED_10GB (1 << 3) 675 #define IXL_AQ_LINK_SPEED_40GB (1 << 4) 676 #define IXL_AQ_LINK_SPEED_25GB (1 << 6) 677 uint8_t link_info; 678 #define IXL_AQ_LINK_UP_FUNCTION 0x01 679 #define IXL_AQ_LINK_FAULT 0x02 680 #define IXL_AQ_LINK_FAULT_TX 0x04 681 #define IXL_AQ_LINK_FAULT_RX 0x08 682 #define IXL_AQ_LINK_FAULT_REMOTE 0x10 683 #define IXL_AQ_LINK_UP_PORT 0x20 684 #define IXL_AQ_MEDIA_AVAILABLE 0x40 685 #define IXL_AQ_SIGNAL_DETECT 0x80 686 uint8_t an_info; 687 #define IXL_AQ_AN_COMPLETED 0x01 688 #define IXL_AQ_LP_AN_ABILITY 0x02 689 #define IXL_AQ_PD_FAULT 0x04 690 #define IXL_AQ_FEC_EN 0x08 691 #define IXL_AQ_PHY_LOW_POWER 0x10 692 #define IXL_AQ_LINK_PAUSE_TX 0x20 693 #define IXL_AQ_LINK_PAUSE_RX 0x40 694 #define IXL_AQ_QUALIFIED_MODULE 0x80 695 696 uint8_t ext_info; 697 #define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 698 #define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 699 #define IXL_AQ_LINK_TX_SHIFT 0x02 700 #define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 701 #define IXL_AQ_LINK_TX_ACTIVE 0x00 702 #define IXL_AQ_LINK_TX_DRAINED 0x01 703 #define IXL_AQ_LINK_TX_FLUSHED 0x03 704 #define IXL_AQ_LINK_FORCED_40G 0x10 705 /* 25G Error Codes */ 706 #define IXL_AQ_25G_NO_ERR 0X00 707 #define IXL_AQ_25G_NOT_PRESENT 0X01 708 #define IXL_AQ_25G_NVM_CRC_ERR 0X02 709 #define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 710 #define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 711 #define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 712 uint8_t loopback; 713 uint16_t max_frame_size; 714 715 uint8_t config; 716 #define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 717 #define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 718 #define IXL_AQ_CONFIG_CRC_ENA 0x04 719 #define IXL_AQ_CONFIG_PACING_MASK 0x78 720 uint8_t power_desc; 721 #define IXL_AQ_LINK_POWER_CLASS_1 0x00 722 #define IXL_AQ_LINK_POWER_CLASS_2 0x01 723 #define IXL_AQ_LINK_POWER_CLASS_3 0x02 724 #define IXL_AQ_LINK_POWER_CLASS_4 0x03 725 #define IXL_AQ_PWR_CLASS_MASK 0x03 726 727 uint8_t reserved[4]; 728 } __packed __aligned(4); 729 730 /* event mask command flags for param[2] */ 731 #define IXL_AQ_PHY_EV_MASK 0x3ff 732 #define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 733 #define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 734 #define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 735 #define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 736 #define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 737 #define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 738 #define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 739 #define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 740 #define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 741 742 struct ixl_aq_req_resource_param { 743 uint16_t resource_id; 744 #define IXL_AQ_RESOURCE_ID_NVM 0x0001 745 #define IXL_AQ_RESOURCE_ID_SDP 0x0002 746 747 uint16_t access_type; 748 #define IXL_AQ_RESOURCE_ACCES_READ 0x01 749 #define IXL_AQ_RESOURCE_ACCES_WRITE 0x02 750 751 uint16_t timeout; 752 uint32_t resource_num; 753 uint32_t reserved; 754 } __packed __aligned(8); 755 756 struct ixl_aq_rel_resource_param { 757 uint16_t resource_id; 758 /* defined in ixl_aq_req_resource_param */ 759 uint16_t _reserved1[3]; 760 uint32_t resource_num; 761 uint32_t _reserved2; 762 } __packed __aligned(8); 763 764 struct ixl_aq_nvm_param { 765 uint8_t command_flags; 766 #define IXL_AQ_NVM_LAST_CMD (1 << 0) 767 #define IXL_AQ_NVM_FLASH_ONLY (1 << 7) 768 uint8_t module_pointer; 769 uint16_t length; 770 uint32_t offset; 771 uint32_t addr_hi; 772 uint32_t addr_lo; 773 } __packed __aligned(4); 774 775 struct ixl_aq_rss_key_param { 776 uint16_t vsi_id; 777 #define IXL_AQ_RSSKEY_VSI_VALID (0x01 << 15) 778 #define IXL_AQ_RSSKEY_VSI_ID_SHIFT 0 779 #define IXL_AQ_RSSKEY_VSI_ID_MASK (0x3FF << IXL_RSSKEY_VSI_ID_SHIFT) 780 781 uint8_t reserved[6]; 782 uint32_t addr_hi; 783 uint32_t addr_lo; 784 } __packed __aligned(8); 785 786 struct ixl_aq_rss_key_data { 787 uint8_t standard_rss_key[0x28]; 788 uint8_t extended_hash_key[0xc]; 789 } __packed __aligned(8); 790 791 struct ixl_aq_rss_lut_param { 792 uint16_t vsi_id; 793 #define IXL_AQ_RSSLUT_VSI_VALID (0x01 << 15) 794 #define IXL_AQ_RSSLUT_VSI_ID_SHIFT 0 795 #define IXL_AQ_RSSLUT_VSI_ID_MASK (0x03FF << IXL_AQ_RSSLUT_VSI_ID_SHIFT) 796 797 uint16_t flags; 798 #define IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT 0 799 #define IXL_AQ_RSSLUT_TABLE_TYPE_MASK (0x01 << IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT) 800 #define IXL_AQ_RSSLUT_TABLE_TYPE_VSI 0 801 #define IXL_AQ_RSSLUT_TABLE_TYPE_PF 1 802 uint8_t reserved[4]; 803 uint32_t addr_hi; 804 uint32_t addr_lo; 805 } __packed __aligned(8); 806 807 /* aq response codes */ 808 #define IXL_AQ_RC_OK 0 /* success */ 809 #define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 810 #define IXL_AQ_RC_ENOENT 2 /* No such element */ 811 #define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 812 #define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 813 #define IXL_AQ_RC_EIO 5 /* I/O error */ 814 #define IXL_AQ_RC_ENXIO 6 /* No such resource */ 815 #define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 816 #define IXL_AQ_RC_EAGAIN 8 /* Try again */ 817 #define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 818 #define IXL_AQ_RC_EACCES 10 /* Permission denied */ 819 #define IXL_AQ_RC_EFAULT 11 /* Bad address */ 820 #define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 821 #define IXL_AQ_RC_EEXIST 13 /* object already exists */ 822 #define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 823 #define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 824 #define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 825 #define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 826 #define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 827 #define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 828 #define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 829 #define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 830 #define IXL_AQ_RC_EFBIG 22 /* file too large */ 831 832 struct ixl_tx_desc { 833 uint64_t addr; 834 uint64_t cmd; 835 #define IXL_TX_DESC_DTYPE_SHIFT 0 836 #define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 837 #define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 838 #define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 839 #define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 840 #define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 841 #define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 842 #define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 843 #define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 844 #define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 845 #define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 846 #define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 847 848 #define IXL_TX_DESC_CMD_SHIFT 4 849 #define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 850 #define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 851 #define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 852 #define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 853 #define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 854 #define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 855 #define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 856 #define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 857 #define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 858 #define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 859 #define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 860 #define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 861 #define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 862 #define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 863 #define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 864 #define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 865 #define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 866 867 #define IXL_TX_DESC_MACLEN_SHIFT 16 868 #define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 869 #define IXL_TX_DESC_IPLEN_SHIFT 23 870 #define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 871 #define IXL_TX_DESC_L4LEN_SHIFT 30 872 #define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 873 #define IXL_TX_DESC_FCLEN_SHIFT 30 874 #define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 875 876 #define IXL_TX_DESC_BSIZE_SHIFT 34 877 #define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 878 #define IXL_TX_DESC_BSIZE_MASK \ 879 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 880 #define IXL_TX_DESC_L2TAG1_SHIFT 48 881 } __packed __aligned(16); 882 883 struct ixl_rx_rd_desc_16 { 884 uint64_t paddr; /* packet addr */ 885 uint64_t haddr; /* header addr */ 886 } __packed __aligned(16); 887 888 struct ixl_rx_rd_desc_32 { 889 uint64_t paddr; /* packet addr */ 890 uint64_t haddr; /* header addr */ 891 uint64_t _reserved1; 892 uint64_t _reserved2; 893 } __packed __aligned(16); 894 895 struct ixl_rx_wb_desc_16 { 896 uint64_t qword0; 897 #define IXL_RX_DESC_L2TAG1_SHIFT 16 898 #define IXL_RX_DESC_L2TAG1_MASK (0xffffULL << IXL_RX_DESC_L2TAG1_SHIFT) 899 uint64_t qword1; 900 #define IXL_RX_DESC_DD (1 << 0) 901 #define IXL_RX_DESC_EOP (1 << 1) 902 #define IXL_RX_DESC_L2TAG1P (1 << 2) 903 #define IXL_RX_DESC_L3L4P (1 << 3) 904 #define IXL_RX_DESC_CRCP (1 << 4) 905 #define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 906 #define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 907 #define IXL_RX_DESC_UMB_SHIFT 9 908 #define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 909 #define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 910 #define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 911 #define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 912 #define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 913 #define IXL_RX_DESC_FLM (1 << 11) 914 #define IXL_RX_DESC_FLTSTAT_SHIFT 12 915 #define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 916 #define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 917 #define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 918 #define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 919 #define IXL_RX_DESC_LPBK (1 << 14) 920 #define IXL_RX_DESC_IPV6EXTADD (1 << 15) 921 #define IXL_RX_DESC_INT_UDP_0 (1 << 18) 922 923 #define IXL_RX_DESC_RXE (1 << 19) 924 #define IXL_RX_DESC_HBO (1 << 21) 925 #define IXL_RX_DESC_IPE (1 << 22) 926 #define IXL_RX_DESC_L4E (1 << 23) 927 #define IXL_RX_DESC_EIPE (1 << 24) 928 #define IXL_RX_DESC_OVERSIZE (1 << 25) 929 930 #define IXL_RX_DESC_PTYPE_SHIFT 30 931 #define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 932 933 #define IXL_RX_DESC_PLEN_SHIFT 38 934 #define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 935 #define IXL_RX_DESC_HLEN_SHIFT 42 936 #define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 937 } __packed __aligned(16); 938 939 enum ixl_rx_desc_ptype { 940 IXL_RX_DESC_PTYPE_IPV4FRAG = 22, 941 IXL_RX_DESC_PTYPE_IPV4 = 23, 942 IXL_RX_DESC_PTYPE_UDPV4 = 24, 943 IXL_RX_DESC_PTYPE_TCPV4 = 26, 944 IXL_RX_DESC_PTYPE_SCTPV4 = 27, 945 IXL_RX_DESC_PTYPE_ICMPV4 = 28, 946 947 IXL_RX_DESC_PTYPE_IPV6FRAG = 88, 948 IXL_RX_DESC_PTYPE_IPV6 = 89, 949 IXL_RX_DESC_PTYPE_UDPV6 = 90, 950 IXL_RX_DESC_PTYPE_TCPV6 = 92, 951 IXL_RX_DESC_PTYPE_SCTPV6 = 93, 952 IXL_RX_DESC_PTYPE_ICMPV6 = 94, 953 }; 954 955 struct ixl_rx_wb_desc_32 { 956 uint64_t qword0; 957 uint64_t qword1; 958 uint64_t qword2; 959 uint64_t qword3; 960 } __packed __aligned(16); 961 962 enum i40e_mac_type { 963 I40E_MAC_XL710, 964 I40E_MAC_X722, 965 I40E_MAC_X722_VF, 966 I40E_MAC_VF, 967 I40E_MAC_GENERIC 968 }; 969 970 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 971 #define I40E_SR_BOOT_CONFIG_PTR 0x17 972 #define I40E_NVM_OEM_VER_OFF 0x83 973 #define I40E_SR_NVM_EETRACK_LO 0x2D 974 #define I40E_SR_NVM_EETRACK_HI 0x2E 975 976 #define IXL_NVM_VERSION_LO_SHIFT 0 977 #define IXL_NVM_VERSION_LO_MASK (0xffUL << IXL_NVM_VERSION_LO_SHIFT) 978 #define IXL_NVM_VERSION_HI_SHIFT 12 979 #define IXL_NVM_VERSION_HI_MASK (0xfUL << IXL_NVM_VERSION_HI_SHIFT) 980 #define IXL_NVM_OEMVERSION_SHIFT 24 981 #define IXL_NVM_OEMVERSION_MASK (0xffUL << IXL_NVM_OEMVERSION_SHIFT) 982 #define IXL_NVM_OEMBUILD_SHIFT 8 983 #define IXL_NVM_OEMBUILD_MASK (0xffffUL << IXL_NVM_OEMBUILD_SHIFT) 984 #define IXL_NVM_OEMPATCH_SHIFT 0 985 #define IXL_NVM_OEMPATCH_MASK (0xff << IXL_NVM_OEMPATCH_SHIFT) 986 987 struct ixl_aq_buf { 988 SIMPLEQ_ENTRY(ixl_aq_buf) 989 aqb_entry; 990 void *aqb_data; 991 bus_dmamap_t aqb_map; 992 bus_dma_segment_t aqb_seg; 993 size_t aqb_size; 994 int aqb_nsegs; 995 }; 996 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 997 998 #define IXL_AQB_MAP(_aqb) ((_aqb)->aqb_map) 999 #define IXL_AQB_DVA(_aqb) ((_aqb)->aqb_map->dm_segs[0].ds_addr) 1000 #define IXL_AQB_KVA(_aqb) ((void *)(_aqb)->aqb_data) 1001 #define IXL_AQB_LEN(_aqb) ((_aqb)->aqb_size) 1002 1003 static inline unsigned int 1004 ixl_rxr_unrefreshed(unsigned int prod, unsigned int cons, unsigned int ndescs) 1005 { 1006 unsigned int num; 1007 1008 if (prod < cons) 1009 num = cons - prod; 1010 else 1011 num = (ndescs - prod) + cons; 1012 1013 if (__predict_true(num > 0)) { 1014 /* device cannot receive packets if all descripter is filled */ 1015 num -= 1; 1016 } 1017 1018 return num; 1019 } 1020 1021 struct ixl_dmamem { 1022 bus_dmamap_t ixm_map; 1023 bus_dma_segment_t ixm_seg; 1024 int ixm_nsegs; 1025 size_t ixm_size; 1026 void *ixm_kva; 1027 }; 1028 1029 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 1030 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 1031 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 1032 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 1033 1034 static inline uint32_t 1035 ixl_dmamem_hi(struct ixl_dmamem *ixm) 1036 { 1037 uint32_t retval; 1038 uint64_t val; 1039 1040 if (sizeof(IXL_DMA_DVA(ixm)) > 4) { 1041 val = (intptr_t)IXL_DMA_DVA(ixm); 1042 retval = val >> 32; 1043 } else { 1044 retval = 0; 1045 } 1046 1047 return retval; 1048 } 1049 1050 static inline uint32_t 1051 ixl_dmamem_lo(struct ixl_dmamem *ixm) 1052 { 1053 1054 return (uint32_t)IXL_DMA_DVA(ixm); 1055 } 1056 1057 struct i40e_eth_stats { 1058 uint64_t rx_bytes; 1059 uint64_t rx_unicast; 1060 uint64_t rx_multicast; 1061 uint64_t rx_broadcast; 1062 uint64_t rx_discards; 1063 uint64_t rx_unknown_protocol; 1064 1065 uint64_t tx_bytes; 1066 uint64_t tx_unicast; 1067 uint64_t tx_multicast; 1068 uint64_t tx_broadcast; 1069 uint64_t tx_discards; 1070 uint64_t tx_errors; 1071 } __packed; 1072 #endif 1073