1 /* $NetBSD: if_ixlvar.h,v 1.6 2020/02/12 06:37:21 yamaguchi Exp $ */ 2 3 /* 4 * Copyright (c) 2019 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_PCI_IF_IXLVAR_H_ 30 #define _DEV_PCI_IF_IXLVAR_H_ 31 32 enum i40e_filter_pctype { 33 /* Note: Values 0-28 are reserved for future use. 34 * Value 29, 30, 32 are not supported on XL710 and X710. 35 */ 36 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 37 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 38 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 39 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 40 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 41 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 42 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 43 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 44 /* Note: Values 37-38 are reserved for future use. 45 * Value 39, 40, 42 are not supported on XL710 and X710. 46 */ 47 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 48 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 49 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 50 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 51 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 52 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 53 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 54 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 55 /* Note: Value 47 is reserved for future use */ 56 I40E_FILTER_PCTYPE_FCOE_OX = 48, 57 I40E_FILTER_PCTYPE_FCOE_RX = 49, 58 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 59 /* Note: Values 51-62 are reserved for future use */ 60 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 61 }; 62 63 enum i40e_reset_type { 64 I40E_RESET_POR = 0, 65 I40E_RESET_CORER = 1, 66 I40E_RESET_GLOBR = 2, 67 I40E_RESET_EMPR = 3, 68 }; 69 70 struct ixl_aq_desc { 71 uint16_t iaq_flags; 72 #define IXL_AQ_DD (1U << 0) 73 #define IXL_AQ_CMP (1U << 1) 74 #define IXL_AQ_ERR (1U << 2) 75 #define IXL_AQ_VFE (1U << 3) 76 #define IXL_AQ_LB (1U << 9) 77 #define IXL_AQ_RD (1U << 10) 78 #define IXL_AQ_VFC (1U << 11) 79 #define IXL_AQ_BUF (1U << 12) 80 #define IXL_AQ_SI (1U << 13) 81 #define IXL_AQ_EI (1U << 14) 82 #define IXL_AQ_FE (1U << 15) 83 84 #define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 85 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 86 "\003ERR" "\002CMP" "\001DD" 87 88 uint16_t iaq_opcode; 89 90 uint16_t iaq_datalen; 91 uint16_t iaq_retval; 92 93 uint64_t iaq_cookie; 94 95 uint32_t iaq_param[4]; 96 /* iaq_data_hi iaq_param[2] */ 97 /* iaq_data_lo iaq_param[3] */ 98 } __packed __aligned(16); 99 100 /* aq commands */ 101 #define IXL_AQ_OP_GET_VERSION 0x0001 102 #define IXL_AQ_OP_DRIVER_VERSION 0x0002 103 #define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 104 #define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 105 #define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 106 #define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 107 #define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 108 #define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 109 #define IXL_AQ_OP_LIST_DEV_CAP 0x000b 110 #define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 111 #define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 112 #define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 113 #define IXL_AQ_OP_RX_CTL_REG_READ 0x0206 114 #define IXL_AQ_OP_RX_CTL_REG_WRITE 0x0207 115 #define IXL_AQ_OP_ADD_VSI 0x0210 116 #define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 117 #define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 118 #define IXL_AQ_OP_ADD_VEB 0x0230 119 #define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 120 #define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 121 #define IXL_AQ_OP_ADD_MACVLAN 0x0250 122 #define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 123 #define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 124 #define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 125 #define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 126 #define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 127 #define IXL_AQ_OP_PHY_RESTART_AN 0x0605 128 #define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 129 #define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 130 #define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 131 #define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 132 #define IXL_AQ_OP_NVM_READ 0x0701 133 #define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 134 #define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 135 #define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 136 #define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 137 #define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 138 #define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 139 #define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 140 #define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 141 #define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 142 #define IXL_AQ_OP_RSS_SET_KEY 0x0b02 143 #define IXL_AQ_OP_RSS_SET_LUT 0x0b03 144 #define IXL_AQ_OP_RSS_GET_KEY 0x0b04 145 #define IXL_AQ_OP_RSS_GET_LUT 0x0b05 146 147 struct ixl_aq_mac_addresses { 148 uint8_t pf_lan[ETHER_ADDR_LEN]; 149 uint8_t pf_san[ETHER_ADDR_LEN]; 150 uint8_t port[ETHER_ADDR_LEN]; 151 uint8_t pf_wol[ETHER_ADDR_LEN]; 152 } __packed; 153 154 #define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 155 #define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 156 #define IXL_AQ_MAC_PORT_VALID (1U << 6) 157 #define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 158 159 struct ixl_aq_capability { 160 uint16_t cap_id; 161 #define IXL_AQ_CAP_SWITCH_MODE 0x0001 162 #define IXL_AQ_CAP_MNG_MODE 0x0002 163 #define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 164 #define IXL_AQ_CAP_OS2BMC_CAP 0x0004 165 #define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 166 #define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 167 #define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 168 #define IXL_AQ_CAP_SRIOV 0x0012 169 #define IXL_AQ_CAP_VF 0x0013 170 #define IXL_AQ_CAP_VMDQ 0x0014 171 #define IXL_AQ_CAP_8021QBG 0x0015 172 #define IXL_AQ_CAP_8021QBR 0x0016 173 #define IXL_AQ_CAP_VSI 0x0017 174 #define IXL_AQ_CAP_DCB 0x0018 175 #define IXL_AQ_CAP_FCOE 0x0021 176 #define IXL_AQ_CAP_ISCSI 0x0022 177 #define IXL_AQ_CAP_RSS 0x0040 178 #define IXL_AQ_CAP_RXQ 0x0041 179 #define IXL_AQ_CAP_TXQ 0x0042 180 #define IXL_AQ_CAP_MSIX 0x0043 181 #define IXL_AQ_CAP_VF_MSIX 0x0044 182 #define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 183 #define IXL_AQ_CAP_1588 0x0046 184 #define IXL_AQ_CAP_IWARP 0x0051 185 #define IXL_AQ_CAP_LED 0x0061 186 #define IXL_AQ_CAP_SDP 0x0062 187 #define IXL_AQ_CAP_MDIO 0x0063 188 #define IXL_AQ_CAP_WSR_PROT 0x0064 189 #define IXL_AQ_CAP_NVM_MGMT 0x0080 190 #define IXL_AQ_CAP_FLEX10 0x00F1 191 #define IXL_AQ_CAP_CEM 0x00F2 192 uint8_t major_rev; 193 uint8_t minor_rev; 194 uint32_t number; 195 uint32_t logical_id; 196 uint32_t phys_id; 197 uint8_t _reserved[16]; 198 } __packed __aligned(4); 199 200 #define IXL_LLDP_SHUTDOWN 0x1 201 202 struct ixl_aq_switch_config { 203 uint16_t num_reported; 204 uint16_t num_total; 205 uint8_t _reserved[12]; 206 } __packed __aligned(4); 207 208 struct ixl_aq_switch_config_element { 209 uint8_t type; 210 #define IXL_AQ_SW_ELEM_TYPE_MAC 1 211 #define IXL_AQ_SW_ELEM_TYPE_PF 2 212 #define IXL_AQ_SW_ELEM_TYPE_VF 3 213 #define IXL_AQ_SW_ELEM_TYPE_EMP 4 214 #define IXL_AQ_SW_ELEM_TYPE_BMC 5 215 #define IXL_AQ_SW_ELEM_TYPE_PV 16 216 #define IXL_AQ_SW_ELEM_TYPE_VEB 17 217 #define IXL_AQ_SW_ELEM_TYPE_PA 18 218 #define IXL_AQ_SW_ELEM_TYPE_VSI 19 219 uint8_t revision; 220 #define IXL_AQ_SW_ELEM_REV_1 1 221 uint16_t seid; 222 223 uint16_t uplink_seid; 224 uint16_t downlink_seid; 225 226 uint8_t _reserved[3]; 227 uint8_t connection_type; 228 #define IXL_AQ_CONN_TYPE_REGULAR 0x1 229 #define IXL_AQ_CONN_TYPE_DEFAULT 0x2 230 #define IXL_AQ_CONN_TYPE_CASCADED 0x3 231 232 uint16_t scheduler_id; 233 uint16_t element_info; 234 } __packed __aligned(4); 235 236 #define IXL_PHY_TYPE_SGMII 0x00 237 #define IXL_PHY_TYPE_1000BASE_KX 0x01 238 #define IXL_PHY_TYPE_10GBASE_KX4 0x02 239 #define IXL_PHY_TYPE_10GBASE_KR 0x03 240 #define IXL_PHY_TYPE_40GBASE_KR4 0x04 241 #define IXL_PHY_TYPE_XAUI 0x05 242 #define IXL_PHY_TYPE_XFI 0x06 243 #define IXL_PHY_TYPE_SFI 0x07 244 #define IXL_PHY_TYPE_XLAUI 0x08 245 #define IXL_PHY_TYPE_XLPPI 0x09 246 #define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 247 #define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 248 #define IXL_PHY_TYPE_10GBASE_AOC 0x0c 249 #define IXL_PHY_TYPE_40GBASE_AOC 0x0d 250 #define IXL_PHY_TYPE_100BASE_TX 0x11 251 #define IXL_PHY_TYPE_1000BASE_T 0x12 252 #define IXL_PHY_TYPE_10GBASE_T 0x13 253 #define IXL_PHY_TYPE_10GBASE_SR 0x14 254 #define IXL_PHY_TYPE_10GBASE_LR 0x15 255 #define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 256 #define IXL_PHY_TYPE_10GBASE_CR1 0x17 257 #define IXL_PHY_TYPE_40GBASE_CR4 0x18 258 #define IXL_PHY_TYPE_40GBASE_SR4 0x19 259 #define IXL_PHY_TYPE_40GBASE_LR4 0x1a 260 #define IXL_PHY_TYPE_1000BASE_SX 0x1b 261 #define IXL_PHY_TYPE_1000BASE_LX 0x1c 262 #define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 263 #define IXL_PHY_TYPE_20GBASE_KR2 0x1e 264 265 #define IXL_PHY_TYPE_25GBASE_KR 0x1f 266 #define IXL_PHY_TYPE_25GBASE_CR 0x20 267 #define IXL_PHY_TYPE_25GBASE_SR 0x21 268 #define IXL_PHY_TYPE_25GBASE_LR 0x22 269 #define IXL_PHY_TYPE_25GBASE_AOC 0x23 270 #define IXL_PHY_TYPE_25GBASE_ACC 0x24 271 272 #define IXL_PHY_LINK_SPEED_100MB (1 << 1) 273 #define IXL_PHY_LINK_SPEED_1000MB (1 << 2) 274 #define IXL_PHY_LINK_SPEED_10GB (1 << 3) 275 #define IXL_PHY_LINK_SPEED_40GB (1 << 4) 276 #define IXL_PHY_LINK_SPEED_20GB (1 << 5) 277 #define IXL_PHY_LINK_SPEED_25GB (1 << 6) 278 279 #define IXL_PHY_ABILITY_PAUSE_TX (1 << 0) 280 #define IXL_PHY_ABILITY_PAUSE_RX (1 << 1) 281 #define IXL_PHY_ABILITY_LOWPOW (1 << 2) 282 #define IXL_PHY_ABILITY_LINKUP (1 << 3) 283 #define IXL_PHY_ABILITY_AUTONEGO (1 << 4) 284 #define IXL_PHY_ABILITY_MODQUAL (1 << 5) 285 286 struct ixl_aq_module_desc { 287 uint8_t oui[3]; 288 uint8_t _reserved1; 289 uint8_t part_number[16]; 290 uint8_t revision[4]; 291 uint8_t _reserved2[8]; 292 } __packed __aligned(4); 293 294 struct ixl_aq_phy_abilities { 295 uint32_t phy_type; 296 297 uint8_t link_speed; 298 uint8_t abilities; 299 uint16_t eee_capability; 300 301 uint32_t eeer_val; 302 303 uint8_t d3_lpan; 304 uint8_t phy_type_ext; 305 #define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 306 #define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 307 #define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 308 #define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 309 uint8_t fec_cfg_curr_mod_ext_info; 310 #define IXL_AQ_ENABLE_FEC_KR 0x01 311 #define IXL_AQ_ENABLE_FEC_RS 0x02 312 #define IXL_AQ_REQUEST_FEC_KR 0x04 313 #define IXL_AQ_REQUEST_FEC_RS 0x08 314 #define IXL_AQ_ENABLE_FEC_AUTO 0x10 315 #define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 316 #define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 317 uint8_t ext_comp_code; 318 319 uint8_t phy_id[4]; 320 321 uint8_t module_type[3]; 322 #define IXL_SFF8024_ID_SFP 0x03 323 #define IXL_SFF8024_ID_QSFP 0x0c 324 #define IXL_SFF8024_ID_QSFP_PLUS 0x0d 325 #define IXL_SFF8024_ID_QSFP28 0x11 326 uint8_t qualified_module_count; 327 #define IXL_AQ_PHY_MAX_QMS 16 328 struct ixl_aq_module_desc 329 qualified_module[IXL_AQ_PHY_MAX_QMS]; 330 } __packed __aligned(4); 331 332 struct ixl_aq_phy_param { 333 uint32_t phy_types; 334 uint8_t link_speed; 335 uint8_t abilities; 336 #define IXL_AQ_PHY_ABILITY_AUTO_LINK (1 << 5) 337 uint16_t eee_capability; 338 uint32_t eeer_val; 339 uint8_t d3_lpan; 340 uint8_t phy_type_ext; 341 uint8_t fec_cfg; 342 uint8_t config; 343 } __packed __aligned(4); 344 345 struct ixl_aq_link_param { 346 uint8_t notify; 347 #define IXL_AQ_LINK_NOTIFY 0x03 348 uint8_t _reserved1; 349 uint8_t phy; 350 uint8_t speed; 351 uint8_t status; 352 uint8_t _reserved2[11]; 353 } __packed __aligned(4); 354 355 struct ixl_aq_vsi_param { 356 uint16_t uplink_seid; 357 uint8_t connect_type; 358 #define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 359 #define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 360 #define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 361 uint8_t _reserved1; 362 363 uint8_t vf_id; 364 uint8_t _reserved2; 365 uint16_t vsi_flags; 366 #define IXL_AQ_VSI_TYPE_SHIFT 0x0 367 #define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 368 #define IXL_AQ_VSI_TYPE_VF 0x0 369 #define IXL_AQ_VSI_TYPE_VMDQ2 0x1 370 #define IXL_AQ_VSI_TYPE_PF 0x2 371 #define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 372 #define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 373 374 uint32_t addr_hi; 375 uint32_t addr_lo; 376 } __packed __aligned(16); 377 378 struct ixl_aq_add_macvlan { 379 uint16_t num_addrs; 380 uint16_t seid0; 381 uint16_t seid1; 382 uint16_t seid2; 383 uint32_t addr_hi; 384 uint32_t addr_lo; 385 } __packed __aligned(16); 386 387 struct ixl_aq_add_macvlan_elem { 388 uint8_t macaddr[6]; 389 uint16_t vlan; 390 uint16_t flags; 391 #define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 392 #define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 393 uint16_t queue; 394 uint32_t _reserved; 395 } __packed __aligned(16); 396 397 struct ixl_aq_remove_macvlan { 398 uint16_t num_addrs; 399 uint16_t seid0; 400 uint16_t seid1; 401 uint16_t seid2; 402 uint32_t addr_hi; 403 uint32_t addr_lo; 404 } __packed __aligned(16); 405 406 struct ixl_aq_remove_macvlan_elem { 407 uint8_t macaddr[6]; 408 uint16_t vlan; 409 uint8_t flags; 410 #define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 411 #define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 412 uint8_t _reserved[7]; 413 } __packed __aligned(16); 414 415 struct ixl_aq_vsi_reply { 416 uint16_t seid; 417 uint16_t vsi_number; 418 419 uint16_t vsis_used; 420 uint16_t vsis_free; 421 422 uint32_t addr_hi; 423 uint32_t addr_lo; 424 } __packed __aligned(16); 425 426 struct ixl_aq_vsi_data { 427 /* first 96 byte are written by SW */ 428 uint16_t valid_sections; 429 #define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 430 #define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 431 #define IXL_AQ_VSI_VALID_VLAN (1 << 2) 432 #define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 433 #define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 434 #define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 435 #define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 436 #define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 437 #define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 438 #define IXL_AQ_VSI_VALID_SCHED (1 << 9) 439 /* switch section */ 440 uint16_t switch_id; 441 #define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 442 #define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 443 #define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 444 #define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 445 446 uint8_t _reserved1[2]; 447 /* security section */ 448 uint8_t sec_flags; 449 #define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 450 #define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 451 #define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 452 uint8_t _reserved2; 453 454 /* vlan section */ 455 uint16_t pvid; 456 uint16_t fcoe_pvid; 457 458 uint8_t port_vlan_flags; 459 #define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 460 #define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 461 #define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 462 #define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 463 #define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 464 #define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 465 #define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 466 #define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 467 #define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 468 #define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 469 #define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 470 #define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 471 uint8_t _reserved3[3]; 472 473 /* ingress egress up section */ 474 uint32_t ingress_table; 475 #define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 476 #define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 477 uint32_t egress_table; 478 479 /* cascaded pv section */ 480 uint16_t cas_pv_tag; 481 uint8_t cas_pv_flags; 482 #define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 483 #define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 484 #define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 485 #define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 486 #define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 487 #define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 488 #define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 489 #define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 490 (1 << 6) 491 uint8_t _reserved4; 492 493 /* queue mapping section */ 494 uint16_t mapping_flags; 495 #define IXL_AQ_VSI_QUE_MAP_MASK 0x1 496 #define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 497 #define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 498 uint16_t queue_mapping[16]; 499 #define IXL_AQ_VSI_QUEUE_SHIFT 0x0 500 #define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 501 uint16_t tc_mapping[8]; 502 #define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 503 #define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 504 #define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 505 #define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 506 507 /* queueing option section */ 508 uint8_t queueing_opt_flags; 509 #define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 510 #define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 511 #define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 512 #define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 513 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 514 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 515 uint8_t _reserved5[3]; 516 517 /* scheduler section */ 518 uint8_t up_enable_bits; 519 uint8_t _reserved6; 520 521 /* outer up section */ 522 uint32_t outer_up_table; /* same as ingress/egress tables */ 523 uint8_t _reserved7[8]; 524 525 /* last 32 bytes are written by FW */ 526 uint16_t qs_handle[8]; 527 #define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 528 uint16_t stat_counter_idx; 529 uint16_t sched_id; 530 531 uint8_t _reserved8[12]; 532 } __packed __aligned(8); 533 534 CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 535 536 struct ixl_aq_vsi_promisc_param { 537 uint16_t flags; 538 uint16_t valid_flags; 539 #define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 540 #define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 541 #define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 542 #define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 543 #define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 544 #define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 545 546 uint16_t seid; 547 #define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 548 uint16_t vlan; 549 #define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 550 uint32_t reserved[2]; 551 } __packed __aligned(8); 552 553 struct ixl_aq_veb_param { 554 uint16_t uplink_seid; 555 uint16_t downlink_seid; 556 uint16_t veb_flags; 557 #define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 558 #define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 559 #define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 560 #define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 561 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 562 #define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 563 #define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 564 #define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 565 uint8_t enable_tcs; 566 uint8_t _reserved[9]; 567 } __packed __aligned(16); 568 569 struct ixl_aq_veb_reply { 570 uint16_t _reserved1; 571 uint16_t _reserved2; 572 uint16_t _reserved3; 573 uint16_t switch_seid; 574 uint16_t veb_seid; 575 #define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 576 #define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 577 #define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 578 #define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 579 uint16_t statistic_index; 580 uint16_t vebs_used; 581 uint16_t vebs_free; 582 } __packed __aligned(16); 583 584 /* GET PHY ABILITIES param[0] */ 585 #define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 586 #define IXL_AQ_PHY_REPORT_INIT (1 << 1) 587 588 struct ixl_aq_phy_reg_access { 589 uint8_t phy_iface; 590 #define IXL_AQ_PHY_IF_INTERNAL 0 591 #define IXL_AQ_PHY_IF_EXTERNAL 1 592 #define IXL_AQ_PHY_IF_MODULE 2 593 uint8_t dev_addr; 594 uint16_t recall; 595 #define IXL_AQ_PHY_QSFP_DEV_ADDR 0 596 #define IXL_AQ_PHY_QSFP_LAST 1 597 uint32_t reg; 598 uint32_t val; 599 uint32_t _reserved2; 600 } __packed __aligned(16); 601 602 /* RESTART_AN param[0] */ 603 #define IXL_AQ_PHY_RESTART_AN (1 << 1) 604 #define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 605 606 struct ixl_aq_link_status { /* this occupies the iaq_param space */ 607 uint16_t command_flags; /* only field set on command */ 608 #define IXL_AQ_LSE_MASK 0x3 609 #define IXL_AQ_LSE_NOP 0x0 610 #define IXL_AQ_LSE_DISABLE 0x2 611 #define IXL_AQ_LSE_ENABLE 0x3 612 #define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 613 uint8_t phy_type; 614 uint8_t link_speed; 615 #define IXL_AQ_LINK_SPEED_100MB (1 << 1) 616 #define IXL_AQ_LINK_SPEED_1000MB (1 << 2) 617 #define IXL_AQ_LINK_SPEED_10GB (1 << 3) 618 #define IXL_AQ_LINK_SPEED_40GB (1 << 4) 619 #define IXL_AQ_LINK_SPEED_25GB (1 << 6) 620 uint8_t link_info; 621 #define IXL_AQ_LINK_UP_FUNCTION 0x01 622 #define IXL_AQ_LINK_FAULT 0x02 623 #define IXL_AQ_LINK_FAULT_TX 0x04 624 #define IXL_AQ_LINK_FAULT_RX 0x08 625 #define IXL_AQ_LINK_FAULT_REMOTE 0x10 626 #define IXL_AQ_LINK_UP_PORT 0x20 627 #define IXL_AQ_MEDIA_AVAILABLE 0x40 628 #define IXL_AQ_SIGNAL_DETECT 0x80 629 uint8_t an_info; 630 #define IXL_AQ_AN_COMPLETED 0x01 631 #define IXL_AQ_LP_AN_ABILITY 0x02 632 #define IXL_AQ_PD_FAULT 0x04 633 #define IXL_AQ_FEC_EN 0x08 634 #define IXL_AQ_PHY_LOW_POWER 0x10 635 #define IXL_AQ_LINK_PAUSE_TX 0x20 636 #define IXL_AQ_LINK_PAUSE_RX 0x40 637 #define IXL_AQ_QUALIFIED_MODULE 0x80 638 639 uint8_t ext_info; 640 #define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 641 #define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 642 #define IXL_AQ_LINK_TX_SHIFT 0x02 643 #define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 644 #define IXL_AQ_LINK_TX_ACTIVE 0x00 645 #define IXL_AQ_LINK_TX_DRAINED 0x01 646 #define IXL_AQ_LINK_TX_FLUSHED 0x03 647 #define IXL_AQ_LINK_FORCED_40G 0x10 648 /* 25G Error Codes */ 649 #define IXL_AQ_25G_NO_ERR 0X00 650 #define IXL_AQ_25G_NOT_PRESENT 0X01 651 #define IXL_AQ_25G_NVM_CRC_ERR 0X02 652 #define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 653 #define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 654 #define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 655 uint8_t loopback; 656 uint16_t max_frame_size; 657 658 uint8_t config; 659 #define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 660 #define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 661 #define IXL_AQ_CONFIG_CRC_ENA 0x04 662 #define IXL_AQ_CONFIG_PACING_MASK 0x78 663 uint8_t power_desc; 664 #define IXL_AQ_LINK_POWER_CLASS_1 0x00 665 #define IXL_AQ_LINK_POWER_CLASS_2 0x01 666 #define IXL_AQ_LINK_POWER_CLASS_3 0x02 667 #define IXL_AQ_LINK_POWER_CLASS_4 0x03 668 #define IXL_AQ_PWR_CLASS_MASK 0x03 669 670 uint8_t reserved[4]; 671 } __packed __aligned(4); 672 673 /* event mask command flags for param[2] */ 674 #define IXL_AQ_PHY_EV_MASK 0x3ff 675 #define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 676 #define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 677 #define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 678 #define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 679 #define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 680 #define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 681 #define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 682 #define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 683 #define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 684 685 struct ixl_aq_req_resource_param { 686 uint16_t resource_id; 687 #define IXL_AQ_RESOURCE_ID_NVM 0x0001 688 #define IXL_AQ_RESOURCE_ID_SDP 0x0002 689 690 uint16_t access_type; 691 #define IXL_AQ_RESOURCE_ACCES_READ 0x01 692 #define IXL_AQ_RESOURCE_ACCES_WRITE 0x02 693 694 uint16_t timeout; 695 uint32_t resource_num; 696 uint32_t reserved; 697 } __packed __aligned(8); 698 699 struct ixl_aq_rel_resource_param { 700 uint16_t resource_id; 701 /* defined in ixl_aq_req_resource_param */ 702 uint16_t _reserved1[3]; 703 uint32_t resource_num; 704 uint32_t _reserved2; 705 } __packed __aligned(8); 706 707 struct ixl_aq_nvm_param { 708 uint8_t command_flags; 709 #define IXL_AQ_NVM_LAST_CMD (1 << 0) 710 #define IXL_AQ_NVM_FLASH_ONLY (1 << 7) 711 uint8_t module_pointer; 712 uint16_t length; 713 uint32_t offset; 714 uint32_t addr_hi; 715 uint32_t addr_lo; 716 } __packed __aligned(4); 717 718 struct ixl_aq_rss_key_param { 719 uint16_t vsi_id; 720 #define IXL_AQ_RSSKEY_VSI_VALID (0x01 << 15) 721 #define IXL_AQ_RSSKEY_VSI_ID_SHIFT 0 722 #define IXL_AQ_RSSKEY_VSI_ID_MASK (0x3FF << IXL_RSSKEY_VSI_ID_SHIFT) 723 724 uint8_t reserved[6]; 725 uint32_t addr_hi; 726 uint32_t addr_lo; 727 } __packed __aligned(8); 728 729 struct ixl_aq_rss_key_data { 730 uint8_t standard_rss_key[0x28]; 731 uint8_t extended_hash_key[0xc]; 732 } __packed __aligned(8); 733 734 struct ixl_aq_rss_lut_param { 735 uint16_t vsi_id; 736 #define IXL_AQ_RSSLUT_VSI_VALID (0x01 << 15) 737 #define IXL_AQ_RSSLUT_VSI_ID_SHIFT 0 738 #define IXL_AQ_RSSLUT_VSI_ID_MASK (0x03FF << IXL_AQ_RSSLUT_VSI_ID_SHIFT) 739 740 uint16_t flags; 741 #define IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT 0 742 #define IXL_AQ_RSSLUT_TABLE_TYPE_MASK (0x01 << IXL_AQ_RSSLUT_TABLE_TYPE_SHIFT) 743 #define IXL_AQ_RSSLUT_TABLE_TYPE_VSI 0 744 #define IXL_AQ_RSSLUT_TABLE_TYPE_PF 1 745 uint8_t reserved[4]; 746 uint32_t addr_hi; 747 uint32_t addr_lo; 748 } __packed __aligned(8); 749 750 /* aq response codes */ 751 #define IXL_AQ_RC_OK 0 /* success */ 752 #define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 753 #define IXL_AQ_RC_ENOENT 2 /* No such element */ 754 #define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 755 #define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 756 #define IXL_AQ_RC_EIO 5 /* I/O error */ 757 #define IXL_AQ_RC_ENXIO 6 /* No such resource */ 758 #define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 759 #define IXL_AQ_RC_EAGAIN 8 /* Try again */ 760 #define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 761 #define IXL_AQ_RC_EACCES 10 /* Permission denied */ 762 #define IXL_AQ_RC_EFAULT 11 /* Bad address */ 763 #define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 764 #define IXL_AQ_RC_EEXIST 13 /* object already exists */ 765 #define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 766 #define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 767 #define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 768 #define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 769 #define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 770 #define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 771 #define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 772 #define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 773 #define IXL_AQ_RC_EFBIG 22 /* file too large */ 774 775 struct ixl_tx_desc { 776 uint64_t addr; 777 uint64_t cmd; 778 #define IXL_TX_DESC_DTYPE_SHIFT 0 779 #define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 780 #define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 781 #define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 782 #define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 783 #define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 784 #define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 785 #define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 786 #define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 787 #define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 788 #define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 789 #define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 790 791 #define IXL_TX_DESC_CMD_SHIFT 4 792 #define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 793 #define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 794 #define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 795 #define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 796 #define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 797 #define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 798 #define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 799 #define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 800 #define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 801 #define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 802 #define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 803 #define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 804 #define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 805 #define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 806 #define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 807 #define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 808 #define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 809 810 #define IXL_TX_DESC_MACLEN_SHIFT 16 811 #define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 812 #define IXL_TX_DESC_IPLEN_SHIFT 23 813 #define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 814 #define IXL_TX_DESC_L4LEN_SHIFT 30 815 #define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 816 #define IXL_TX_DESC_FCLEN_SHIFT 30 817 #define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 818 819 #define IXL_TX_DESC_BSIZE_SHIFT 34 820 #define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 821 #define IXL_TX_DESC_BSIZE_MASK \ 822 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 823 #define IXL_TX_DESC_L2TAG1_SHIFT 48 824 } __packed __aligned(16); 825 826 struct ixl_rx_rd_desc_16 { 827 uint64_t paddr; /* packet addr */ 828 uint64_t haddr; /* header addr */ 829 } __packed __aligned(16); 830 831 struct ixl_rx_rd_desc_32 { 832 uint64_t paddr; /* packet addr */ 833 uint64_t haddr; /* header addr */ 834 uint64_t _reserved1; 835 uint64_t _reserved2; 836 } __packed __aligned(16); 837 838 struct ixl_rx_wb_desc_16 { 839 uint64_t qword0; 840 #define IXL_RX_DESC_L2TAG1_SHIFT 16 841 #define IXL_RX_DESC_L2TAG1_MASK (0xffffULL << IXL_RX_DESC_L2TAG1_SHIFT) 842 uint64_t qword1; 843 #define IXL_RX_DESC_DD (1 << 0) 844 #define IXL_RX_DESC_EOP (1 << 1) 845 #define IXL_RX_DESC_L2TAG1P (1 << 2) 846 #define IXL_RX_DESC_L3L4P (1 << 3) 847 #define IXL_RX_DESC_CRCP (1 << 4) 848 #define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 849 #define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 850 #define IXL_RX_DESC_UMB_SHIFT 9 851 #define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 852 #define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 853 #define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 854 #define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 855 #define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 856 #define IXL_RX_DESC_FLM (1 << 11) 857 #define IXL_RX_DESC_FLTSTAT_SHIFT 12 858 #define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 859 #define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 860 #define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 861 #define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 862 #define IXL_RX_DESC_LPBK (1 << 14) 863 #define IXL_RX_DESC_IPV6EXTADD (1 << 15) 864 #define IXL_RX_DESC_INT_UDP_0 (1 << 18) 865 866 #define IXL_RX_DESC_RXE (1 << 19) 867 #define IXL_RX_DESC_HBO (1 << 21) 868 #define IXL_RX_DESC_IPE (1 << 22) 869 #define IXL_RX_DESC_L4E (1 << 23) 870 #define IXL_RX_DESC_EIPE (1 << 24) 871 #define IXL_RX_DESC_OVERSIZE (1 << 25) 872 873 #define IXL_RX_DESC_PTYPE_SHIFT 30 874 #define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 875 876 #define IXL_RX_DESC_PLEN_SHIFT 38 877 #define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 878 #define IXL_RX_DESC_HLEN_SHIFT 42 879 #define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 880 } __packed __aligned(16); 881 882 enum ixl_rx_desc_ptype { 883 IXL_RX_DESC_PTYPE_IPV4FRAG = 22, 884 IXL_RX_DESC_PTYPE_IPV4 = 23, 885 IXL_RX_DESC_PTYPE_UDPV4 = 24, 886 IXL_RX_DESC_PTYPE_TCPV4 = 26, 887 IXL_RX_DESC_PTYPE_SCTPV4 = 27, 888 IXL_RX_DESC_PTYPE_ICMPV4 = 28, 889 890 IXL_RX_DESC_PTYPE_IPV6FRAG = 88, 891 IXL_RX_DESC_PTYPE_IPV6 = 89, 892 IXL_RX_DESC_PTYPE_UDPV6 = 90, 893 IXL_RX_DESC_PTYPE_TCPV6 = 92, 894 IXL_RX_DESC_PTYPE_SCTPV6 = 93, 895 IXL_RX_DESC_PTYPE_ICMPV6 = 94, 896 }; 897 898 struct ixl_rx_wb_desc_32 { 899 uint64_t qword0; 900 uint64_t qword1; 901 uint64_t qword2; 902 uint64_t qword3; 903 } __packed __aligned(16); 904 905 enum i40e_mac_type { 906 I40E_MAC_XL710, 907 I40E_MAC_X722, 908 I40E_MAC_X722_VF, 909 I40E_MAC_VF, 910 I40E_MAC_GENERIC 911 }; 912 913 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 914 #define I40E_SR_BOOT_CONFIG_PTR 0x17 915 #define I40E_NVM_OEM_VER_OFF 0x83 916 #define I40E_SR_NVM_EETRACK_LO 0x2D 917 #define I40E_SR_NVM_EETRACK_HI 0x2E 918 919 #define IXL_NVM_VERSION_LO_SHIFT 0 920 #define IXL_NVM_VERSION_LO_MASK (0xffUL << IXL_NVM_VERSION_LO_SHIFT) 921 #define IXL_NVM_VERSION_HI_SHIFT 12 922 #define IXL_NVM_VERSION_HI_MASK (0xfUL << IXL_NVM_VERSION_HI_SHIFT) 923 #define IXL_NVM_OEMVERSION_SHIFT 24 924 #define IXL_NVM_OEMVERSION_MASK (0xffUL << IXL_NVM_OEMVERSION_SHIFT) 925 #define IXL_NVM_OEMBUILD_SHIFT 8 926 #define IXL_NVM_OEMBUILD_MASK (0xffffUL << IXL_NVM_OEMBUILD_SHIFT) 927 #define IXL_NVM_OEMPATCH_SHIFT 0 928 #define IXL_NVM_OEMPATCH_MASK (0xff << IXL_NVM_OEMPATCH_SHIFT) 929 #endif 930