1 /* $NetBSD: if_iwnreg.h,v 1.13 2013/07/28 11:46:24 prlw1 Exp $ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.43 2011/09/01 18:49:56 kettenis Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/endian.h> 22 23 /* XXX Added for NetBSD */ 24 #define IEEE80211_TKIP_MICLEN 8 25 26 #define IWN_TX_RING_COUNT 256 27 #define IWN_TX_RING_LOMARK 192 28 #define IWN_TX_RING_HIMARK 224 29 #define IWN_RX_RING_COUNT_LOG 6 30 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31 32 #define IWN4965_NTXQUEUES 16 33 #define IWN5000_NTXQUEUES 20 34 35 #define IWN4965_NDMACHNLS 7 36 #define IWN5000_NDMACHNLS 8 37 38 #define IWN_SRVC_DMACHNL 9 39 40 #define IWN_ICT_SIZE 4096 41 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 42 43 /* Maximum number of DMA segments for TX. */ 44 #define IWN_MAX_SCATTER 20 45 46 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 47 #define IWN_RBUF_SIZE (4 * 1024) 48 49 #if defined(__LP64__) 50 /* HW supports 36-bit DMA addresses. */ 51 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 52 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 53 #else 54 #define IWN_LOADDR(paddr) (paddr) 55 #define IWN_HIADDR(paddr) (0) 56 #endif 57 58 /* Base Address Register. */ 59 #define IWN_PCI_BAR0 PCI_MAPREG_START 60 61 /* 62 * Control and status registers. 63 */ 64 #define IWN_HW_IF_CONFIG 0x000 65 #define IWN_INT_COALESCING 0x004 66 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 67 #define IWN_INT 0x008 68 #define IWN_INT_MASK 0x00c 69 #define IWN_FH_INT 0x010 70 #define IWN_RESET 0x020 71 #define IWN_GP_CNTRL 0x024 72 #define IWN_HW_REV 0x028 73 #define IWN_EEPROM 0x02c 74 #define IWN_EEPROM_GP 0x030 75 #define IWN_OTP_GP 0x034 76 #define IWN_GIO 0x03c 77 #define IWN_GP_DRIVER 0x050 78 #define IWN_UCODE_GP1_CLR 0x05c 79 #define IWN_LED 0x094 80 #define IWN_DRAM_INT_TBL 0x0a0 81 #define IWN_SHADOW_REG_CTRL 0x0a8 82 #define IWN_GIO_CHICKEN 0x100 83 #define IWN_ANA_PLL 0x20c 84 #define IWN_HW_REV_WA 0x22c 85 #define IWN_DBG_HPET_MEM 0x240 86 #define IWN_DBG_LINK_PWR_MGMT 0x250 87 #define IWN_MEM_RADDR 0x40c 88 #define IWN_MEM_WADDR 0x410 89 #define IWN_MEM_WDATA 0x418 90 #define IWN_MEM_RDATA 0x41c 91 #define IWN_PRPH_WADDR 0x444 92 #define IWN_PRPH_RADDR 0x448 93 #define IWN_PRPH_WDATA 0x44c 94 #define IWN_PRPH_RDATA 0x450 95 #define IWN_HBUS_TARG_WRPTR 0x460 96 97 /* 98 * Flow-Handler registers. 99 */ 100 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 101 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 102 #define IWN_FH_KW_ADDR 0x197c 103 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 104 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 105 #define IWN_FH_STATUS_WPTR 0x1bc0 106 #define IWN_FH_RX_BASE 0x1bc4 107 #define IWN_FH_RX_WPTR 0x1bc8 108 #define IWN_FH_RX_CONFIG 0x1c00 109 #define IWN_FH_RX_STATUS 0x1c44 110 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 111 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 112 #define IWN_FH_TX_CHICKEN 0x1e98 113 #define IWN_FH_TX_STATUS 0x1eb0 114 115 /* 116 * TX scheduler registers. 117 */ 118 #define IWN_SCHED_BASE 0xa02c00 119 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 120 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 121 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 122 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 123 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 124 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 125 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 126 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 127 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 128 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 129 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 130 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 131 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 132 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 133 134 /* 135 * Offsets in TX scheduler's SRAM. 136 */ 137 #define IWN4965_SCHED_CTX_OFF 0x380 138 #define IWN4965_SCHED_CTX_LEN 416 139 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 140 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 141 #define IWN5000_SCHED_CTX_OFF 0x600 142 #define IWN5000_SCHED_CTX_LEN 520 143 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 144 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 145 146 /* 147 * NIC internal memory offsets. 148 */ 149 #define IWN_APMG_CLK_CTRL 0x3000 150 #define IWN_APMG_CLK_EN 0x3004 151 #define IWN_APMG_CLK_DIS 0x3008 152 #define IWN_APMG_PS 0x300c 153 #define IWN_APMG_DIGITAL_SVR 0x3058 154 #define IWN_APMG_ANALOG_SVR 0x306c 155 #define IWN_APMG_PCI_STT 0x3010 156 #define IWN_BSM_WR_CTRL 0x3400 157 #define IWN_BSM_WR_MEM_SRC 0x3404 158 #define IWN_BSM_WR_MEM_DST 0x3408 159 #define IWN_BSM_WR_DWCOUNT 0x340c 160 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 161 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 162 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 163 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 164 #define IWN_BSM_SRAM_BASE 0x3800 165 166 /* Possible flags for register IWN_HW_IF_CONFIG. */ 167 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 168 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 169 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 170 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 171 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 172 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 173 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 174 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 175 176 /* Possible values for register IWN_INT_PERIODIC. */ 177 #define IWN_INT_PERIODIC_DIS 0x00 178 #define IWN_INT_PERIODIC_ENA 0xff 179 180 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 181 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 182 183 /* Possible values for IWN_BSM_WR_MEM_DST. */ 184 #define IWN_FW_TEXT_BASE 0x00000000 185 #define IWN_FW_DATA_BASE 0x00800000 186 187 /* Possible flags for register IWN_RESET. */ 188 #define IWN_RESET_NEVO (1 << 0) 189 #define IWN_RESET_SW (1 << 7) 190 #define IWN_RESET_MASTER_DISABLED (1 << 8) 191 #define IWN_RESET_STOP_MASTER (1 << 9) 192 #define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 193 194 /* Possible flags for register IWN_GP_CNTRL. */ 195 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 196 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 197 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 198 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 199 #define IWN_GP_CNTRL_SLEEP (1 << 4) 200 #define IWN_GP_CNTRL_RFKILL (1 << 27) 201 202 /* Possible flags for register IWN_HW_REV. */ 203 #define IWN_HW_REV_TYPE_SHIFT 4 204 #define IWN_HW_REV_TYPE_MASK 0x000000f0 205 #define IWN_HW_REV_TYPE_4965 0 206 #define IWN_HW_REV_TYPE_5300 2 207 #define IWN_HW_REV_TYPE_5350 3 208 #define IWN_HW_REV_TYPE_5150 4 209 #define IWN_HW_REV_TYPE_5100 5 210 #define IWN_HW_REV_TYPE_1000 6 211 #define IWN_HW_REV_TYPE_6000 7 212 #define IWN_HW_REV_TYPE_6050 8 213 #define IWN_HW_REV_TYPE_6005 11 214 /* Types 6030 and 6035 also return 11 */ 215 216 /* Possible flags for register IWN_GIO_CHICKEN. */ 217 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 218 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 219 220 /* Possible flags for register IWN_GIO. */ 221 #define IWN_GIO_L0S_ENA (1 << 1) 222 223 /* Possible flags for register IWN_GP_DRIVER. */ 224 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 225 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 226 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 227 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 228 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 229 230 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 231 #define IWN_UCODE_GP1_RFKILL (1 << 1) 232 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 233 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 234 235 /* Possible flags/values for register IWN_LED. */ 236 #define IWN_LED_BSM_CTRL (1 << 5) 237 #define IWN_LED_OFF 0x00000038 238 #define IWN_LED_ON 0x00000078 239 240 /* Possible flags for register IWN_DRAM_INT_TBL. */ 241 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 242 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 243 244 /* Possible values for register IWN_ANA_PLL. */ 245 #define IWN_ANA_PLL_INIT 0x00880300 246 247 /* Possible flags for register IWN_FH_RX_STATUS. */ 248 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 249 250 /* Possible flags for register IWN_BSM_WR_CTRL. */ 251 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 252 #define IWN_BSM_WR_CTRL_START (1 << 31) 253 254 /* Possible flags for register IWN_INT. */ 255 #define IWN_INT_ALIVE (1 << 0) 256 #define IWN_INT_WAKEUP (1 << 1) 257 #define IWN_INT_SW_RX (1 << 3) 258 #define IWN_INT_CT_REACHED (1 << 6) 259 #define IWN_INT_RF_TOGGLED (1 << 7) 260 #define IWN_INT_SW_ERR (1 << 25) 261 #define IWN_INT_SCHED (1 << 26) 262 #define IWN_INT_FH_TX (1 << 27) 263 #define IWN_INT_RX_PERIODIC (1 << 28) 264 #define IWN_INT_HW_ERR (1 << 29) 265 #define IWN_INT_FH_RX (1 << 31) 266 267 /* Shortcut. */ 268 #define IWN_INT_MASK_DEF \ 269 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 270 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 271 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 272 273 /* Possible flags for register IWN_FH_INT. */ 274 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 275 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 276 #define IWN_FH_INT_HI_PRIOR (1 << 30) 277 /* Shortcuts for the above. */ 278 #define IWN_FH_INT_TX \ 279 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 280 #define IWN_FH_INT_RX \ 281 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 282 283 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 284 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 285 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 286 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 287 288 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 289 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 290 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 291 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 292 293 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 294 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 295 296 /* Possible flags for register IWN_FH_TX_STATUS. */ 297 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 298 299 /* Possible flags for register IWN_FH_RX_CONFIG. */ 300 #define IWN_FH_RX_CONFIG_ENA (1 << 31) 301 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 302 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 303 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 304 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 305 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 306 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 307 308 /* Possible flags for register IWN_FH_TX_CONFIG. */ 309 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 310 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 311 312 /* Possible flags for register IWN_EEPROM. */ 313 #define IWN_EEPROM_READ_VALID (1 << 0) 314 #define IWN_EEPROM_CMD (1 << 1) 315 316 /* Possible flags for register IWN_EEPROM_GP. */ 317 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 318 319 /* Possible flags for register IWN_OTP_GP. */ 320 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 321 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 322 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 323 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 324 325 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 326 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 327 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 328 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 329 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 330 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 331 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 332 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 333 334 /* Possible flags for registers IWN_APMG_CLK_*. */ 335 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 336 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 337 338 /* Possible flags for register IWN_APMG_PS. */ 339 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 340 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 341 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 342 #define IWN_APMG_PS_PWR_SRC_VAUX 2 343 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 344 #define IWN_APMG_PS_RESET_REQ (1 << 26) 345 346 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 347 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 348 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 349 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 350 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 351 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 352 353 /* Possible flags for IWN_APMG_PCI_STT. */ 354 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 355 356 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 357 #define IWN_FW_UPDATED (1 << 31) 358 359 #define IWN_SCHED_WINSZ 64 360 #define IWN_SCHED_LIMIT 64 361 #define IWN4965_SCHED_COUNT 512 362 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 363 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 364 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 365 366 struct iwn_tx_desc { 367 uint8_t reserved1[3]; 368 uint8_t nsegs; 369 struct { 370 uint32_t addr; 371 uint16_t len; 372 } __packed segs[IWN_MAX_SCATTER]; 373 /* Pad to 128 bytes. */ 374 uint32_t reserved2; 375 } __packed; 376 377 struct iwn_rx_status { 378 uint16_t closed_count; 379 uint16_t closed_rx_count; 380 uint16_t finished_count; 381 uint16_t finished_rx_count; 382 uint32_t reserved[2]; 383 } __packed; 384 385 struct iwn_rx_desc { 386 uint32_t len; 387 uint8_t type; 388 #define IWN_UC_READY 1 389 #define IWN_ADD_NODE_DONE 24 390 #define IWN_TX_DONE 28 391 #define IWN5000_CALIBRATION_RESULT 102 392 #define IWN5000_CALIBRATION_DONE 103 393 #define IWN_START_SCAN 130 394 #define IWN_STOP_SCAN 132 395 #define IWN_RX_STATISTICS 156 396 #define IWN_BEACON_STATISTICS 157 397 #define IWN_STATE_CHANGED 161 398 #define IWN_BEACON_MISSED 162 399 #define IWN_RX_PHY 192 400 #define IWN_MPDU_RX_DONE 193 401 #define IWN_RX_DONE 195 402 #define IWN_RX_COMPRESSED_BA 197 403 404 uint8_t flags; 405 uint8_t idx; 406 uint8_t qid; 407 } __packed; 408 409 /* Possible RX status flags. */ 410 #define IWN_RX_NO_CRC_ERR (1 << 0) 411 #define IWN_RX_NO_OVFL_ERR (1 << 1) 412 /* Shortcut for the above. */ 413 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 414 #define IWN_RX_MPDU_MIC_OK (1 << 6) 415 #define IWN_RX_CIPHER_MASK (7 << 8) 416 #define IWN_RX_CIPHER_CCMP (2 << 8) 417 #define IWN_RX_MPDU_DEC (1 << 11) 418 #define IWN_RX_DECRYPT_MASK (3 << 11) 419 #define IWN_RX_DECRYPT_OK (3 << 11) 420 421 struct iwn_tx_cmd { 422 uint8_t code; 423 #define IWN_CMD_RXON 16 424 #define IWN_CMD_RXON_ASSOC 17 425 #define IWN_CMD_EDCA_PARAMS 19 426 #define IWN_CMD_TIMING 20 427 #define IWN_CMD_ADD_NODE 24 428 #define IWN_CMD_TX_DATA 28 429 #define IWN_CMD_SET_LED 72 430 #define IWN_CMD_LINK_QUALITY 78 431 #define IWN5000_CMD_WIMAX_COEX 90 432 #define IWN5000_CMD_CALIB_CONFIG 101 433 #define IWN_CMD_SET_POWER_MODE 119 434 #define IWN_CMD_SCAN 128 435 #define IWN_CMD_TXPOWER_DBM 149 436 #define IWN_CMD_TXPOWER 151 437 #define IWN5000_CMD_TX_ANT_CONFIG 152 438 #define IWN_CMD_BT_COEX 155 439 #define IWN_CMD_GET_STATISTICS 156 440 #define IWN_CMD_SET_CRITICAL_TEMP 164 441 #define IWN_CMD_SET_SENSITIVITY 168 442 #define IWN_CMD_PHY_CALIB 176 443 #define IWN_CMD_BT_COEX_PRIO_TABLE 204 444 445 uint8_t flags; 446 uint8_t idx; 447 uint8_t qid; 448 uint8_t data[136]; 449 } __packed; 450 451 /* Antenna flags, used in various commands. */ 452 #define IWN_ANT_A (1 << 0) 453 #define IWN_ANT_B (1 << 1) 454 #define IWN_ANT_C (1 << 2) 455 /* Shortcuts. */ 456 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 457 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 458 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 459 460 /* Structure for command IWN_CMD_RXON. */ 461 struct iwn_rxon { 462 uint8_t myaddr[IEEE80211_ADDR_LEN]; 463 uint16_t reserved1; 464 uint8_t bssid[IEEE80211_ADDR_LEN]; 465 uint16_t reserved2; 466 uint8_t wlap[IEEE80211_ADDR_LEN]; 467 uint16_t reserved3; 468 uint8_t mode; 469 #define IWN_MODE_HOSTAP 1 470 #define IWN_MODE_STA 3 471 #define IWN_MODE_IBSS 4 472 #define IWN_MODE_MONITOR 6 473 474 uint8_t air; 475 uint16_t rxchain; 476 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 477 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 478 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 479 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 480 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 481 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 482 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 483 484 uint8_t ofdm_mask; 485 uint8_t cck_mask; 486 uint16_t associd; 487 uint32_t flags; 488 #define IWN_RXON_24GHZ (1 << 0) 489 #define IWN_RXON_CCK (1 << 1) 490 #define IWN_RXON_AUTO (1 << 2) 491 #define IWN_RXON_SHSLOT (1 << 4) 492 #define IWN_RXON_SHPREAMBLE (1 << 5) 493 #define IWN_RXON_NODIVERSITY (1 << 7) 494 #define IWN_RXON_ANTENNA_A (1 << 8) 495 #define IWN_RXON_ANTENNA_B (1 << 9) 496 #define IWN_RXON_TSF (1 << 15) 497 #define IWN_RXON_CTS_TO_SELF (1 << 30) 498 499 uint32_t filter; 500 #define IWN_FILTER_PROMISC (1 << 0) 501 #define IWN_FILTER_CTL (1 << 1) 502 #define IWN_FILTER_MULTICAST (1 << 2) 503 #define IWN_FILTER_NODECRYPT (1 << 3) 504 #define IWN_FILTER_BSS (1 << 5) 505 #define IWN_FILTER_BEACON (1 << 6) 506 507 uint8_t chan; 508 uint8_t reserved4; 509 uint8_t ht_single_mask; 510 uint8_t ht_dual_mask; 511 /* The following fields are for >=5000 Series only. */ 512 uint8_t ht_triple_mask; 513 uint8_t reserved5; 514 uint16_t acquisition; 515 uint16_t reserved6; 516 } __packed; 517 518 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 519 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 520 521 /* Structure for command IWN_CMD_ASSOCIATE. */ 522 struct iwn_assoc { 523 uint32_t flags; 524 uint32_t filter; 525 uint8_t ofdm_mask; 526 uint8_t cck_mask; 527 uint16_t reserved; 528 } __packed; 529 530 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 531 struct iwn_edca_params { 532 uint32_t flags; 533 #define IWN_EDCA_UPDATE (1 << 0) 534 #define IWN_EDCA_TXOP (1 << 4) 535 536 struct { 537 uint16_t cwmin; 538 uint16_t cwmax; 539 uint8_t aifsn; 540 uint8_t reserved; 541 uint16_t txoplimit; 542 } __packed ac[WME_NUM_AC]; 543 } __packed; 544 545 /* Structure for command IWN_CMD_TIMING. */ 546 struct iwn_cmd_timing { 547 uint64_t tstamp; 548 uint16_t bintval; 549 uint16_t atim; 550 uint32_t binitval; 551 uint16_t lintval; 552 uint16_t reserved; 553 } __packed; 554 555 /* Structure for command IWN_CMD_ADD_NODE. */ 556 struct iwn_node_info { 557 uint8_t control; 558 #define IWN_NODE_UPDATE (1 << 0) 559 560 uint8_t reserved1[3]; 561 562 uint8_t macaddr[IEEE80211_ADDR_LEN]; 563 uint16_t reserved2; 564 uint8_t id; 565 #define IWN_ID_BSS 0 566 #define IWN5000_ID_BROADCAST 15 567 #define IWN4965_ID_BROADCAST 31 568 569 uint8_t flags; 570 #define IWN_FLAG_SET_KEY (1 << 0) 571 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 572 #define IWN_FLAG_SET_TXRATE (1 << 2) 573 #define IWN_FLAG_SET_ADDBA (1 << 3) 574 #define IWN_FLAG_SET_DELBA (1 << 4) 575 576 uint16_t reserved3; 577 uint16_t kflags; 578 #define IWN_KFLAG_CCMP (1 << 1) 579 #define IWN_KFLAG_MAP (1 << 3) 580 #define IWN_KFLAG_KID(kid) ((kid) << 8) 581 #define IWN_KFLAG_INVALID (1 << 11) 582 #define IWN_KFLAG_GROUP (1 << 14) 583 584 uint8_t tsc2; /* TKIP TSC2 */ 585 uint8_t reserved4; 586 uint16_t ttak[5]; 587 uint8_t kid; 588 uint8_t reserved5; 589 uint8_t key[16]; 590 /* The following 3 fields are for 5000 Series only. */ 591 uint64_t tsc; 592 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 593 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 594 595 uint32_t htflags; 596 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 597 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 598 599 uint32_t mask; 600 uint16_t disable_tid; 601 uint16_t reserved6; 602 uint8_t addba_tid; 603 uint8_t delba_tid; 604 uint16_t addba_ssn; 605 uint32_t reserved7; 606 } __packed; 607 608 struct iwn4965_node_info { 609 uint8_t control; 610 uint8_t reserved1[3]; 611 uint8_t macaddr[IEEE80211_ADDR_LEN]; 612 uint16_t reserved2; 613 uint8_t id; 614 uint8_t flags; 615 uint16_t reserved3; 616 uint16_t kflags; 617 uint8_t tsc2; /* TKIP TSC2 */ 618 uint8_t reserved4; 619 uint16_t ttak[5]; 620 uint8_t kid; 621 uint8_t reserved5; 622 uint8_t key[16]; 623 uint32_t htflags; 624 uint32_t mask; 625 uint16_t disable_tid; 626 uint16_t reserved6; 627 uint8_t addba_tid; 628 uint8_t delba_tid; 629 uint16_t addba_ssn; 630 uint32_t reserved7; 631 } __packed; 632 633 #define IWN_RFLAG_CCK (1 << 1) 634 #define IWN_RFLAG_ANT(x) ((x) << 6) 635 636 /* Structure for command IWN_CMD_TX_DATA. */ 637 struct iwn_cmd_data { 638 uint16_t len; 639 uint16_t lnext; 640 uint32_t flags; 641 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 642 #define IWN_TX_NEED_RTS (1 << 1) 643 #define IWN_TX_NEED_CTS (1 << 2) 644 #define IWN_TX_NEED_ACK (1 << 3) 645 #define IWN_TX_LINKQ (1 << 4) 646 #define IWN_TX_IMM_BA (1 << 6) 647 #define IWN_TX_FULL_TXOP (1 << 7) 648 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 649 #define IWN_TX_AUTO_SEQ (1 << 13) 650 #define IWN_TX_MORE_FRAG (1 << 14) 651 #define IWN_TX_INSERT_TSTAMP (1 << 16) 652 #define IWN_TX_NEED_PADDING (1 << 20) 653 654 uint32_t scratch; 655 uint8_t plcp; 656 uint8_t rflags; 657 uint16_t xrflags; 658 659 uint8_t id; 660 uint8_t security; 661 #define IWN_CIPHER_WEP40 1 662 #define IWN_CIPHER_CCMP 2 663 #define IWN_CIPHER_TKIP 3 664 #define IWN_CIPHER_WEP104 9 665 666 uint8_t linkq; 667 uint8_t reserved2; 668 uint8_t key[16]; 669 uint16_t fnext; 670 uint16_t reserved3; 671 uint32_t lifetime; 672 #define IWN_LIFETIME_INFINITE 0xffffffff 673 674 uint32_t loaddr; 675 uint8_t hiaddr; 676 uint8_t rts_ntries; 677 uint8_t data_ntries; 678 uint8_t tid; 679 uint16_t timeout; 680 uint16_t txop; 681 } __packed; 682 683 /* Structure for command IWN_CMD_LINK_QUALITY. */ 684 #define IWN_MAX_TX_RETRIES 16 685 struct iwn_cmd_link_quality { 686 uint8_t id; 687 uint8_t reserved1; 688 uint16_t ctl; 689 uint8_t flags; 690 uint8_t mimo; 691 uint8_t antmsk_1stream; 692 uint8_t antmsk_2stream; 693 uint8_t ridx[WME_NUM_AC]; 694 uint16_t ampdu_limit; 695 uint8_t ampdu_threshold; 696 uint8_t ampdu_max; 697 uint32_t reserved2; 698 struct { 699 uint8_t plcp; 700 uint8_t rflags; 701 uint16_t xrflags; 702 } __packed retry[IWN_MAX_TX_RETRIES]; 703 uint32_t reserved3; 704 } __packed; 705 706 /* Structure for command IWN_CMD_SET_LED. */ 707 struct iwn_cmd_led { 708 uint32_t unit; /* multiplier (in usecs) */ 709 uint8_t which; 710 #define IWN_LED_ACTIVITY 1 711 #define IWN_LED_LINK 2 712 713 uint8_t off; 714 uint8_t on; 715 uint8_t reserved; 716 } __packed; 717 718 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 719 struct iwn5000_wimax_coex { 720 uint32_t flags; 721 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 722 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 723 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 724 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 725 726 struct iwn5000_wimax_event { 727 uint8_t request; 728 uint8_t window; 729 uint8_t reserved; 730 uint8_t flags; 731 } __packed events[16]; 732 } __packed; 733 734 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 735 struct iwn5000_calib_elem { 736 uint32_t enable; 737 uint32_t start; 738 #define IWN5000_CALIB_DC (1 << 1) 739 uint32_t send; 740 uint32_t apply; 741 uint32_t reserved; 742 } __packed; 743 744 struct iwn5000_calib_status { 745 struct iwn5000_calib_elem once; 746 struct iwn5000_calib_elem perd; 747 uint32_t flags; 748 } __packed; 749 750 struct iwn5000_calib_config { 751 struct iwn5000_calib_status ucode; 752 struct iwn5000_calib_status driver; 753 uint32_t reserved; 754 } __packed; 755 756 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 757 struct iwn_pmgt_cmd { 758 uint16_t flags; 759 #define IWN_PS_ALLOW_SLEEP (1 << 0) 760 #define IWN_PS_NOTIFY (1 << 1) 761 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 762 #define IWN_PS_PCI_PMGT (1 << 3) 763 #define IWN_PS_FAST_PD (1 << 4) 764 765 uint8_t keepalive; 766 uint8_t debug; 767 uint32_t rxtimeout; 768 uint32_t txtimeout; 769 uint32_t intval[5]; 770 uint32_t beacons; 771 } __packed; 772 773 /* Structures for command IWN_CMD_SCAN. */ 774 struct iwn_scan_essid { 775 uint8_t id; 776 uint8_t len; 777 uint8_t data[IEEE80211_NWID_LEN]; 778 } __packed; 779 780 struct iwn_scan_hdr { 781 uint16_t len; 782 uint8_t reserved1; 783 uint8_t nchan; 784 uint16_t quiet_time; 785 uint16_t quiet_threshold; 786 uint16_t crc_threshold; 787 uint16_t rxchain; 788 uint32_t max_svc; /* background scans */ 789 uint32_t pause_svc; /* background scans */ 790 uint32_t flags; 791 uint32_t filter; 792 793 /* Followed by a struct iwn_cmd_data. */ 794 /* Followed by an array of 20 structs iwn_scan_essid. */ 795 /* Followed by probe request body. */ 796 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 797 } __packed; 798 799 struct iwn_scan_chan { 800 uint32_t flags; 801 #define IWN_CHAN_ACTIVE (1 << 0) 802 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 803 804 uint16_t chan; 805 uint8_t rf_gain; 806 uint8_t dsp_gain; 807 uint16_t active; /* msecs */ 808 uint16_t passive; /* msecs */ 809 } __packed; 810 811 /* Maximum size of a scan command. */ 812 #define IWN_SCAN_MAXSZ (MCLBYTES - 4) 813 814 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 815 #define IWN_RIDX_MAX 32 816 struct iwn4965_cmd_txpower { 817 uint8_t band; 818 uint8_t reserved1; 819 uint8_t chan; 820 uint8_t reserved2; 821 struct { 822 uint8_t rf_gain[2]; 823 uint8_t dsp_gain[2]; 824 } __packed power[IWN_RIDX_MAX + 1]; 825 } __packed; 826 827 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 828 struct iwn5000_cmd_txpower { 829 int8_t global_limit; /* in half-dBm */ 830 #define IWN5000_TXPOWER_AUTO 0x7f 831 #define IWN5000_TXPOWER_MAX_DBM 16 832 833 uint8_t flags; 834 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 835 836 int8_t srv_limit; /* in half-dBm */ 837 uint8_t reserved; 838 } __packed; 839 840 /* Structure for command IWN_CMD_BT_COEX. */ 841 struct iwn_bluetooth { 842 uint8_t flags; 843 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 844 #define IWN_BT_COEX_BT_PRIO (1 << 1) 845 #define IWN_BT_COEX_2_WIRE (1 << 2) 846 #define IWN_BT_COEX_ENABLE IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO 847 uint8_t lead_time; 848 #define IWN_BT_LEAD_TIME_DEF 30 849 uint8_t max_kill; 850 #define IWN_BT_MAX_KILL_DEF 5 851 uint8_t bt3_timer_t7_value; 852 #define IWN_BT_BT3_T7_DEF 1 853 uint32_t kill_ack_mask; 854 #define IWN_BT_KILL_ACK_MASK_DEF htole32(0xffff0000) 855 uint32_t kill_cts_mask; 856 #define IWN_BT_KILL_CTS_MASK_DEF htole32(0xffff0000) 857 } __packed; 858 859 struct iwn_bt_basic { 860 struct iwn_bluetooth bt; 861 uint8_t bt3_prio_sample_time; 862 #define IWN_BT_BT3_PRIO_SAMPLE_DEF 2 863 uint8_t bt3_timer_t2_value; 864 #define IWN_BT_BT3_T2_DEF 12 865 uint16_t bt4_reaction_time; /* unused */ 866 uint32_t bt3_lookup_table[12]; 867 uint8_t reduce_txpower; /* bit 0 */ 868 uint8_t reserved; 869 uint16_t valid; 870 #define IWN_BT_VALID_ENABLE_FLAGS htole16(1 << 0) 871 #define IWN_BT_VALID_BOOST htole16(1 << 1) 872 #define IWN_BT_VALID_MAX_KILL htole16(1 << 2) 873 #define IWN_BT_VALID_3W_TIMERS htole16(1 << 3) 874 #define IWN_BT_VALID_KILL_ACK_MASK htole16(1 << 4) 875 #define IWN_BT_VALID_KILL_CTS_MASK htole16(1 << 5) 876 #define IWN_BT_VALID_REDUCED_TX_PWR htole16(1 << 6) 877 #define IWN_BT_VALID_3W_LUT htole16(1 << 7) 878 #define IWN_BT_ALL_VALID_MASK (IWN_BT_VALID_ENABLE_FLAGS | \ 879 IWN_BT_VALID_BOOST | \ 880 IWN_BT_VALID_MAX_KILL | \ 881 IWN_BT_VALID_3W_TIMERS | \ 882 IWN_BT_VALID_KILL_ACK_MASK | \ 883 IWN_BT_VALID_KILL_CTS_MASK | \ 884 IWN_BT_VALID_REDUCED_TX_PWR | \ 885 IWN_BT_VALID_3W_LUT) 886 } __packed; 887 888 struct iwn_bt_adv1 { 889 struct iwn_bt_basic basic; 890 uint8_t prio_boost; 891 #define IWN_BT_PRIO_BOOST_DEF 0xf0 892 /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 893 uint8_t tx_prio_boost; 894 uint16_t rx_prio_boost; 895 } __packed; 896 897 struct iwn_bt_adv2 { 898 struct iwn_bt_basic basic; 899 uint32_t prio_boost; 900 #define IWN_BT_PRIO_BOOST_DEF32 0xf0f0f0 901 uint8_t reserved; 902 /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 903 uint8_t tx_prio_boost; 904 uint16_t rx_prio_boost; 905 } __packed; 906 907 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 908 struct iwn_critical_temp { 909 uint32_t reserved; 910 uint32_t tempM; 911 uint32_t tempR; 912 /* degK <-> degC conversion macros. */ 913 #define IWN_CTOK(c) ((c) + 273) 914 #define IWN_KTOC(k) ((k) - 273) 915 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 916 } __packed; 917 918 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 919 struct iwn_sensitivity_cmd { 920 uint16_t which; 921 #define IWN_SENSITIVITY_DEFAULTTBL 0 922 #define IWN_SENSITIVITY_WORKTBL 1 923 924 uint16_t energy_cck; 925 uint16_t energy_ofdm; 926 uint16_t corr_ofdm_x1; 927 uint16_t corr_ofdm_mrc_x1; 928 uint16_t corr_cck_mrc_x4; 929 uint16_t corr_ofdm_x4; 930 uint16_t corr_ofdm_mrc_x4; 931 uint16_t corr_barker; 932 uint16_t corr_barker_mrc; 933 uint16_t corr_cck_x4; 934 uint16_t energy_ofdm_th; 935 } __packed; 936 937 struct iwn_enhanced_sensitivity_cmd { 938 uint16_t which; 939 uint16_t energy_cck; 940 uint16_t energy_ofdm; 941 uint16_t corr_ofdm_x1; 942 uint16_t corr_ofdm_mrc_x1; 943 uint16_t corr_cck_mrc_x4; 944 uint16_t corr_ofdm_x4; 945 uint16_t corr_ofdm_mrc_x4; 946 uint16_t corr_barker; 947 uint16_t corr_barker_mrc; 948 uint16_t corr_cck_x4; 949 uint16_t energy_ofdm_th; 950 /* "Enhanced" part. */ 951 uint16_t ina_det_ofdm; 952 uint16_t ina_det_cck; 953 uint16_t corr_11_9_en; 954 uint16_t ofdm_det_slope_mrc; 955 uint16_t ofdm_det_icept_mrc; 956 uint16_t ofdm_det_slope; 957 uint16_t ofdm_det_icept; 958 uint16_t cck_det_slope_mrc; 959 uint16_t cck_det_icept_mrc; 960 uint16_t cck_det_slope; 961 uint16_t cck_det_icept; 962 uint16_t reserved; 963 } __packed; 964 965 /* Structures for command IWN_CMD_PHY_CALIB. */ 966 struct iwn_phy_calib { 967 uint8_t code; 968 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 969 #define IWN5000_PHY_CALIB_DC 8 970 #define IWN5000_PHY_CALIB_LO 9 971 #define IWN5000_PHY_CALIB_TX_IQ 11 972 #define IWN5000_PHY_CALIB_CRYSTAL 15 973 #define IWN5000_PHY_CALIB_BASE_BAND 16 974 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 975 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18 976 977 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 978 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 979 980 uint8_t group; 981 uint8_t ngroups; 982 uint8_t isvalid; 983 } __packed; 984 985 struct iwn5000_phy_calib_crystal { 986 uint8_t code; 987 uint8_t group; 988 uint8_t ngroups; 989 uint8_t isvalid; 990 991 uint8_t cap_pin[2]; 992 uint8_t reserved[2]; 993 } __packed; 994 995 struct iwn5000_phy_calib_temp_offset { 996 uint8_t code; 997 uint8_t group; 998 uint8_t ngroups; 999 uint8_t isvalid; 1000 int16_t offset; 1001 #define IWN_DEFAULT_TEMP_OFFSET 2700 1002 1003 uint16_t reserved; 1004 } __packed; 1005 1006 struct iwn_phy_calib_gain { 1007 uint8_t code; 1008 uint8_t group; 1009 uint8_t ngroups; 1010 uint8_t isvalid; 1011 1012 int8_t gain[3]; 1013 uint8_t reserved; 1014 } __packed; 1015 1016 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1017 struct iwn_spectrum_cmd { 1018 uint16_t len; 1019 uint8_t token; 1020 uint8_t id; 1021 uint8_t origin; 1022 uint8_t periodic; 1023 uint16_t timeout; 1024 uint32_t start; 1025 uint32_t reserved1; 1026 uint32_t flags; 1027 uint32_t filter; 1028 uint16_t nchan; 1029 uint16_t reserved2; 1030 struct { 1031 uint32_t duration; 1032 uint8_t chan; 1033 uint8_t type; 1034 #define IWN_MEASUREMENT_BASIC (1 << 0) 1035 #define IWN_MEASUREMENT_CCA (1 << 1) 1036 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1037 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1038 #define IWN_MEASUREMENT_FRAME (1 << 4) 1039 #define IWN_MEASUREMENT_IDLE (1 << 7) 1040 1041 uint16_t reserved; 1042 } __packed chan[10]; 1043 } __packed; 1044 1045 /* Structure for IWN_UC_READY notification. */ 1046 #define IWN_NATTEN_GROUPS 5 1047 struct iwn_ucode_info { 1048 uint8_t minor; 1049 uint8_t major; 1050 uint16_t reserved1; 1051 uint8_t revision[8]; 1052 uint8_t type; 1053 uint8_t subtype; 1054 #define IWN_UCODE_RUNTIME 0 1055 #define IWN_UCODE_INIT 9 1056 1057 uint16_t reserved2; 1058 uint32_t logptr; 1059 uint32_t errptr; 1060 uint32_t tstamp; 1061 uint32_t valid; 1062 1063 /* The following fields are for UCODE_INIT only. */ 1064 int32_t volt; 1065 struct { 1066 int32_t chan20MHz; 1067 int32_t chan40MHz; 1068 } __packed temp[4]; 1069 int32_t atten[IWN_NATTEN_GROUPS][2]; 1070 } __packed; 1071 1072 /* Structures for IWN_TX_DONE notification. */ 1073 struct iwn4965_tx_stat { 1074 uint8_t nframes; 1075 uint8_t btkillcnt; 1076 uint8_t rtsfailcnt; 1077 uint8_t ackfailcnt; 1078 uint8_t rate; 1079 uint8_t rflags; 1080 uint16_t xrflags; 1081 uint16_t duration; 1082 uint16_t reserved; 1083 uint32_t power[2]; 1084 uint32_t status; 1085 } __packed; 1086 1087 struct iwn5000_tx_stat { 1088 uint8_t nframes; 1089 uint8_t btkillcnt; 1090 uint8_t rtsfailcnt; 1091 uint8_t ackfailcnt; 1092 uint8_t rate; 1093 uint8_t rflags; 1094 uint16_t xrflags; 1095 uint16_t duration; 1096 uint16_t reserved; 1097 uint32_t power[2]; 1098 uint32_t info; 1099 uint16_t seq; 1100 uint16_t len; 1101 uint8_t tlc; 1102 uint8_t ratid; 1103 uint8_t fc[2]; 1104 uint16_t status; 1105 uint16_t sequence; 1106 } __packed; 1107 1108 /* Structure for IWN_BEACON_MISSED notification. */ 1109 struct iwn_beacon_missed { 1110 uint32_t consecutive; 1111 uint32_t total; 1112 uint32_t expected; 1113 uint32_t received; 1114 } __packed; 1115 1116 /* Structure for IWN_MPDU_RX_DONE notification. */ 1117 struct iwn_rx_mpdu { 1118 uint16_t len; 1119 uint16_t reserved; 1120 } __packed; 1121 1122 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1123 struct iwn4965_rx_phystat { 1124 uint16_t antenna; 1125 uint16_t agc; 1126 uint8_t rssi[6]; 1127 } __packed; 1128 1129 struct iwn5000_rx_phystat { 1130 uint32_t reserved1; 1131 uint32_t agc; 1132 uint16_t rssi[3]; 1133 } __packed; 1134 1135 struct iwn_rx_stat { 1136 uint8_t phy_len; 1137 uint8_t cfg_phy_len; 1138 #define IWN_STAT_MAXLEN 20 1139 1140 uint8_t id; 1141 uint8_t reserved1; 1142 uint64_t tstamp; 1143 uint32_t beacon; 1144 uint16_t flags; 1145 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1146 1147 uint16_t chan; 1148 uint8_t phybuf[32]; 1149 uint8_t rate; 1150 uint8_t rflags; 1151 uint16_t xrflags; 1152 uint16_t len; 1153 uint16_t reserve3; 1154 } __packed; 1155 1156 #define IWN_RSSI_TO_DBM 44 1157 1158 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1159 struct iwn_compressed_ba { 1160 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1161 uint16_t reserved; 1162 uint8_t id; 1163 uint8_t tid; 1164 uint16_t seq; 1165 uint64_t bitmap; 1166 uint16_t qid; 1167 uint16_t ssn; 1168 } __packed; 1169 1170 /* Structure for IWN_START_SCAN notification. */ 1171 struct iwn_start_scan { 1172 uint64_t tstamp; 1173 uint32_t tbeacon; 1174 uint8_t chan; 1175 uint8_t band; 1176 uint16_t reserved; 1177 uint32_t status; 1178 } __packed; 1179 1180 /* Structure for IWN_STOP_SCAN notification. */ 1181 struct iwn_stop_scan { 1182 uint8_t nchan; 1183 uint8_t status; 1184 uint8_t reserved; 1185 uint8_t chan; 1186 uint64_t tsf; 1187 } __packed; 1188 1189 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1190 struct iwn_spectrum_notif { 1191 uint8_t id; 1192 uint8_t token; 1193 uint8_t idx; 1194 uint8_t state; 1195 #define IWN_MEASUREMENT_START 0 1196 #define IWN_MEASUREMENT_STOP 1 1197 1198 uint32_t start; 1199 uint8_t band; 1200 uint8_t chan; 1201 uint8_t type; 1202 uint8_t reserved1; 1203 uint32_t cca_ofdm; 1204 uint32_t cca_cck; 1205 uint32_t cca_time; 1206 uint8_t basic; 1207 uint8_t reserved2[3]; 1208 uint32_t ofdm[8]; 1209 uint32_t cck[8]; 1210 uint32_t stop; 1211 uint32_t status; 1212 #define IWN_MEASUREMENT_OK 0 1213 #define IWN_MEASUREMENT_CONCURRENT 1 1214 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1215 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1216 #define IWN_MEASUREMENT_STOPPED 6 1217 #define IWN_MEASUREMENT_TIMEOUT 7 1218 #define IWN_MEASUREMENT_FAILED 8 1219 } __packed; 1220 1221 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1222 struct iwn_rx_phy_stats { 1223 uint32_t ina; 1224 uint32_t fina; 1225 uint32_t bad_plcp; 1226 uint32_t bad_crc32; 1227 uint32_t overrun; 1228 uint32_t eoverrun; 1229 uint32_t good_crc32; 1230 uint32_t fa; 1231 uint32_t bad_fina_sync; 1232 uint32_t sfd_timeout; 1233 uint32_t fina_timeout; 1234 uint32_t no_rts_ack; 1235 uint32_t rxe_limit; 1236 uint32_t ack; 1237 uint32_t cts; 1238 uint32_t ba_resp; 1239 uint32_t dsp_kill; 1240 uint32_t bad_mh; 1241 uint32_t rssi_sum; 1242 uint32_t reserved; 1243 } __packed; 1244 1245 struct iwn_rx_general_stats { 1246 uint32_t bad_cts; 1247 uint32_t bad_ack; 1248 uint32_t not_bss; 1249 uint32_t filtered; 1250 uint32_t bad_chan; 1251 uint32_t beacons; 1252 uint32_t missed_beacons; 1253 uint32_t adc_saturated; /* time in 0.8us */ 1254 uint32_t ina_searched; /* time in 0.8us */ 1255 uint32_t noise[3]; 1256 uint32_t flags; 1257 uint32_t load; 1258 uint32_t fa; 1259 uint32_t rssi[3]; 1260 uint32_t energy[3]; 1261 } __packed; 1262 1263 struct iwn_rx_ht_phy_stats { 1264 uint32_t bad_plcp; 1265 uint32_t overrun; 1266 uint32_t eoverrun; 1267 uint32_t good_crc32; 1268 uint32_t bad_crc32; 1269 uint32_t bad_mh; 1270 uint32_t good_ampdu_crc32; 1271 uint32_t ampdu; 1272 uint32_t fragment; 1273 uint32_t reserved; 1274 } __packed; 1275 1276 struct iwn_rx_stats { 1277 struct iwn_rx_phy_stats ofdm; 1278 struct iwn_rx_phy_stats cck; 1279 struct iwn_rx_general_stats general; 1280 struct iwn_rx_ht_phy_stats ht; 1281 } __packed; 1282 1283 struct iwn_tx_stats { 1284 uint32_t preamble; 1285 uint32_t rx_detected; 1286 uint32_t bt_defer; 1287 uint32_t bt_kill; 1288 uint32_t short_len; 1289 uint32_t cts_timeout; 1290 uint32_t ack_timeout; 1291 uint32_t exp_ack; 1292 uint32_t ack; 1293 uint32_t msdu; 1294 uint32_t busrt_err1; 1295 uint32_t burst_err2; 1296 uint32_t cts_collision; 1297 uint32_t ack_collision; 1298 uint32_t ba_timeout; 1299 uint32_t ba_resched; 1300 uint32_t query_ampdu; 1301 uint32_t query; 1302 uint32_t query_ampdu_frag; 1303 uint32_t query_mismatch; 1304 uint32_t not_ready; 1305 uint32_t underrun; 1306 uint32_t bt_ht_kill; 1307 uint32_t rx_ba_resp; 1308 uint32_t reserved[2]; 1309 } __packed; 1310 1311 struct iwn_general_stats { 1312 uint32_t temp; 1313 uint32_t temp_m; 1314 uint32_t burst_check; 1315 uint32_t burst; 1316 uint32_t reserved1[4]; 1317 uint32_t sleep; 1318 uint32_t slot_out; 1319 uint32_t slot_idle; 1320 uint32_t ttl_tstamp; 1321 uint32_t tx_ant_a; 1322 uint32_t tx_ant_b; 1323 uint32_t exec; 1324 uint32_t probe; 1325 uint32_t reserved2[2]; 1326 uint32_t rx_enabled; 1327 uint32_t reserved3[3]; 1328 } __packed; 1329 1330 struct iwn_stats { 1331 uint32_t flags; 1332 struct iwn_rx_stats rx; 1333 struct iwn_tx_stats tx; 1334 struct iwn_general_stats general; 1335 } __packed; 1336 1337 1338 /* Firmware error dump. */ 1339 struct iwn_fw_dump { 1340 uint32_t valid; 1341 uint32_t id; 1342 uint32_t pc; 1343 uint32_t branch_link[2]; 1344 uint32_t interrupt_link[2]; 1345 uint32_t error_data[2]; 1346 uint32_t src_line; 1347 uint32_t tsf; 1348 uint32_t time[2]; 1349 } __packed; 1350 1351 /* TLV firmware header. */ 1352 struct iwn_fw_tlv_hdr { 1353 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1354 uint32_t signature; 1355 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1356 1357 uint8_t descr[64]; 1358 uint32_t rev; 1359 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1360 1361 uint32_t build; 1362 uint64_t altmask; 1363 } __packed; 1364 1365 /* TLV header. */ 1366 struct iwn_fw_tlv { 1367 uint16_t type; 1368 #define IWN_FW_TLV_MAIN_TEXT 1 1369 #define IWN_FW_TLV_MAIN_DATA 2 1370 #define IWN_FW_TLV_INIT_TEXT 3 1371 #define IWN_FW_TLV_INIT_DATA 4 1372 #define IWN_FW_TLV_BOOT_TEXT 5 1373 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1374 1375 uint16_t alt; 1376 uint32_t len; 1377 } __packed; 1378 1379 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1380 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1381 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1382 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1383 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1384 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1385 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1386 1387 /* 1388 * Offsets into EEPROM. 1389 */ 1390 #define IWN_EEPROM_MAC 0x015 1391 #define IWN_EEPROM_SKU_CAP 0x045 1392 #define IWN_EEPROM_RFCFG 0x048 1393 #define IWN4965_EEPROM_DOMAIN 0x060 1394 #define IWN4965_EEPROM_BAND1 0x063 1395 #define IWN5000_EEPROM_REG 0x066 1396 #define IWN5000_EEPROM_CAL 0x067 1397 #define IWN4965_EEPROM_BAND2 0x072 1398 #define IWN4965_EEPROM_BAND3 0x080 1399 #define IWN4965_EEPROM_BAND4 0x08d 1400 #define IWN4965_EEPROM_BAND5 0x099 1401 #define IWN4965_EEPROM_BAND6 0x0a0 1402 #define IWN4965_EEPROM_BAND7 0x0a8 1403 #define IWN4965_EEPROM_MAXPOW 0x0e8 1404 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1405 #define IWN4965_EEPROM_BANDS 0x0ea 1406 /* Indirect offsets. */ 1407 #define IWN5000_EEPROM_DOMAIN 0x001 1408 #define IWN5000_EEPROM_BAND1 0x004 1409 #define IWN5000_EEPROM_BAND2 0x013 1410 #define IWN5000_EEPROM_BAND3 0x021 1411 #define IWN5000_EEPROM_BAND4 0x02e 1412 #define IWN5000_EEPROM_BAND5 0x03a 1413 #define IWN5000_EEPROM_BAND6 0x041 1414 #define IWN5000_EEPROM_BAND7 0x049 1415 #define IWN6000_EEPROM_ENHINFO 0x054 1416 #define IWN5000_EEPROM_CRYSTAL 0x128 1417 #define IWN5000_EEPROM_TEMP 0x12a 1418 #define IWN5000_EEPROM_VOLT 0x12b 1419 1420 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1421 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1422 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1423 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1424 1425 /* Possible flags for IWN_EEPROM_RFCFG. */ 1426 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1427 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1428 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1429 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1430 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1431 1432 struct iwn_eeprom_chan { 1433 uint8_t flags; 1434 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1435 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1436 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1437 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1438 1439 int8_t maxpwr; 1440 } __packed; 1441 1442 struct iwn_eeprom_enhinfo { 1443 uint16_t chan; 1444 int8_t chain[3]; /* max power in half-dBm */ 1445 uint8_t reserved; 1446 int8_t mimo2; /* max power in half-dBm */ 1447 int8_t mimo3; /* max power in half-dBm */ 1448 } __packed; 1449 1450 struct iwn5000_eeprom_calib_hdr { 1451 uint8_t version; 1452 uint8_t pa_type; 1453 uint16_t volt; 1454 } __packed; 1455 1456 #define IWN_NSAMPLES 3 1457 struct iwn4965_eeprom_chan_samples { 1458 uint8_t num; 1459 struct { 1460 uint8_t temp; 1461 uint8_t gain; 1462 uint8_t power; 1463 int8_t pa_det; 1464 } samples[2][IWN_NSAMPLES]; 1465 } __packed; 1466 1467 #define IWN_NBANDS 8 1468 struct iwn4965_eeprom_band { 1469 uint8_t lo; /* low channel number */ 1470 uint8_t hi; /* high channel number */ 1471 struct iwn4965_eeprom_chan_samples chans[2]; 1472 } __packed; 1473 1474 /* 1475 * Offsets of channels descriptions in EEPROM. 1476 */ 1477 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1478 IWN4965_EEPROM_BAND1, 1479 IWN4965_EEPROM_BAND2, 1480 IWN4965_EEPROM_BAND3, 1481 IWN4965_EEPROM_BAND4, 1482 IWN4965_EEPROM_BAND5, 1483 IWN4965_EEPROM_BAND6, 1484 IWN4965_EEPROM_BAND7 1485 }; 1486 1487 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1488 IWN5000_EEPROM_BAND1, 1489 IWN5000_EEPROM_BAND2, 1490 IWN5000_EEPROM_BAND3, 1491 IWN5000_EEPROM_BAND4, 1492 IWN5000_EEPROM_BAND5, 1493 IWN5000_EEPROM_BAND6, 1494 IWN5000_EEPROM_BAND7 1495 }; 1496 1497 #define IWN_CHAN_BANDS_COUNT 7 1498 #define IWN_MAX_CHAN_PER_BAND 14 1499 static const struct iwn_chan_band { 1500 uint8_t nchan; 1501 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1502 } iwn_bands[] = { 1503 /* 20MHz channels, 2GHz band. */ 1504 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1505 /* 20MHz channels, 5GHz band. */ 1506 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1507 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1508 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1509 { 6, { 145, 149, 153, 157, 161, 165 } }, 1510 /* 40MHz channels (primary channels), 2GHz band. */ 1511 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1512 /* 40MHz channels (primary channels), 5GHz band. */ 1513 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1514 }; 1515 1516 #define IWN1000_OTP_NBLOCKS 3 1517 #define IWN6000_OTP_NBLOCKS 4 1518 #define IWN6050_OTP_NBLOCKS 7 1519 1520 /* HW rate indices. */ 1521 #define IWN_RIDX_CCK1 0 1522 #define IWN_RIDX_OFDM6 4 1523 1524 static const struct iwn_rate { 1525 uint8_t rate; 1526 uint8_t plcp; 1527 uint8_t flags; 1528 } iwn_rates[IWN_RIDX_MAX + 1] = { 1529 { 2, 10, IWN_RFLAG_CCK }, 1530 { 4, 20, IWN_RFLAG_CCK }, 1531 { 11, 55, IWN_RFLAG_CCK }, 1532 { 22, 110, IWN_RFLAG_CCK }, 1533 { 12, 0xd, 0 }, 1534 { 18, 0xf, 0 }, 1535 { 24, 0x5, 0 }, 1536 { 36, 0x7, 0 }, 1537 { 48, 0x9, 0 }, 1538 { 72, 0xb, 0 }, 1539 { 96, 0x1, 0 }, 1540 { 108, 0x3, 0 }, 1541 { 120, 0x3, 0 } 1542 }; 1543 1544 #define IWN4965_MAX_PWR_INDEX 107 1545 1546 /* 1547 * RF Tx gain values from highest to lowest power (values obtained from 1548 * the reference driver.) 1549 */ 1550 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1551 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1552 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1553 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1554 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1555 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1556 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1557 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1558 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1561 }; 1562 1563 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1564 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1565 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1566 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1567 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1568 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1569 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1570 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1571 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1572 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1573 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1574 }; 1575 1576 /* 1577 * DSP pre-DAC gain values from highest to lowest power (values obtained 1578 * from the reference driver.) 1579 */ 1580 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1581 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1582 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1583 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1584 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1585 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1586 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1587 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1588 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1589 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1590 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1591 }; 1592 1593 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1594 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1595 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1596 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1597 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1598 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1599 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1600 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1601 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1602 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1603 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1604 }; 1605 1606 /* 1607 * Power saving settings (values obtained from the reference driver.) 1608 */ 1609 #define IWN_NDTIMRANGES 3 1610 #define IWN_NPOWERLEVELS 6 1611 static const struct iwn_pmgt { 1612 uint32_t rxtimeout; 1613 uint32_t txtimeout; 1614 uint32_t intval[5]; 1615 int skip_dtim; 1616 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1617 /* DTIM <= 2 */ 1618 { 1619 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1620 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1621 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1622 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1623 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1624 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1625 }, 1626 /* 3 <= DTIM <= 10 */ 1627 { 1628 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1629 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1630 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1631 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1632 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1633 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1634 }, 1635 /* DTIM >= 11 */ 1636 { 1637 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1638 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1639 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1640 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1641 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1642 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1643 } 1644 }; 1645 1646 struct iwn_sensitivity_limits { 1647 uint32_t min_ofdm_x1; 1648 uint32_t max_ofdm_x1; 1649 uint32_t min_ofdm_mrc_x1; 1650 uint32_t max_ofdm_mrc_x1; 1651 uint32_t min_ofdm_x4; 1652 uint32_t max_ofdm_x4; 1653 uint32_t min_ofdm_mrc_x4; 1654 uint32_t max_ofdm_mrc_x4; 1655 uint32_t min_cck_x4; 1656 uint32_t max_cck_x4; 1657 uint32_t min_cck_mrc_x4; 1658 uint32_t max_cck_mrc_x4; 1659 uint32_t min_energy_cck; 1660 uint32_t energy_cck; 1661 uint32_t energy_ofdm; 1662 }; 1663 1664 /* 1665 * RX sensitivity limits (values obtained from the reference driver.) 1666 */ 1667 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1668 105, 140, 1669 220, 270, 1670 85, 120, 1671 170, 210, 1672 125, 200, 1673 200, 400, 1674 97, 1675 100, 1676 100 1677 }; 1678 1679 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1680 120, 120, /* min = max for performance bug in DSP. */ 1681 240, 240, /* min = max for performance bug in DSP. */ 1682 90, 120, 1683 170, 210, 1684 125, 200, 1685 170, 400, 1686 95, 1687 95, 1688 95 1689 }; 1690 1691 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1692 105, 105, /* min = max for performance bug in DSP. */ 1693 220, 220, /* min = max for performance bug in DSP. */ 1694 90, 120, 1695 170, 210, 1696 125, 200, 1697 170, 400, 1698 95, 1699 95, 1700 95 1701 }; 1702 1703 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1704 120, 155, 1705 240, 290, 1706 90, 120, 1707 170, 210, 1708 125, 200, 1709 170, 400, 1710 95, 1711 95, 1712 95 1713 }; 1714 1715 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1716 105, 110, 1717 192, 232, 1718 80, 145, 1719 128, 232, 1720 125, 175, 1721 160, 310, 1722 97, 1723 97, 1724 100 1725 }; 1726 1727 /* Map TID to TX scheduler's FIFO. */ 1728 static const uint8_t iwn_tid2fifo[] = { 1729 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1730 }; 1731 1732 /* WiFi/WiMAX coexist event priority table for 6050. */ 1733 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1734 { 0x04, 0x03, 0x00, 0x00 }, 1735 { 0x04, 0x03, 0x00, 0x03 }, 1736 { 0x04, 0x03, 0x00, 0x03 }, 1737 { 0x04, 0x03, 0x00, 0x03 }, 1738 { 0x04, 0x03, 0x00, 0x00 }, 1739 { 0x04, 0x03, 0x00, 0x07 }, 1740 { 0x04, 0x03, 0x00, 0x00 }, 1741 { 0x04, 0x03, 0x00, 0x03 }, 1742 { 0x04, 0x03, 0x00, 0x03 }, 1743 { 0x04, 0x03, 0x00, 0x00 }, 1744 { 0x06, 0x03, 0x00, 0x07 }, 1745 { 0x04, 0x03, 0x00, 0x00 }, 1746 { 0x06, 0x06, 0x00, 0x03 }, 1747 { 0x04, 0x03, 0x00, 0x07 }, 1748 { 0x04, 0x03, 0x00, 0x00 }, 1749 { 0x04, 0x03, 0x00, 0x00 } 1750 }; 1751 1752 /* Firmware errors. */ 1753 static const char * const iwn_fw_errmsg[] = { 1754 "OK", 1755 "FAIL", 1756 "BAD_PARAM", 1757 "BAD_CHECKSUM", 1758 "NMI_INTERRUPT_WDG", 1759 "SYSASSERT", 1760 "FATAL_ERROR", 1761 "BAD_COMMAND", 1762 "HW_ERROR_TUNE_LOCK", 1763 "HW_ERROR_TEMPERATURE", 1764 "ILLEGAL_CHAN_FREQ", 1765 "VCC_NOT_STABLE", 1766 "FH_ERROR", 1767 "NMI_INTERRUPT_HOST", 1768 "NMI_INTERRUPT_ACTION_PT", 1769 "NMI_INTERRUPT_UNKNOWN", 1770 "UCODE_VERSION_MISMATCH", 1771 "HW_ERROR_ABS_LOCK", 1772 "HW_ERROR_CAL_LOCK_FAIL", 1773 "NMI_INTERRUPT_INST_ACTION_PT", 1774 "NMI_INTERRUPT_DATA_ACTION_PT", 1775 "NMI_TRM_HW_ER", 1776 "NMI_INTERRUPT_TRM", 1777 "NMI_INTERRUPT_BREAKPOINT" 1778 "DEBUG_0", 1779 "DEBUG_1", 1780 "DEBUG_2", 1781 "DEBUG_3", 1782 "ADVANCED_SYSASSERT" 1783 }; 1784 1785 /* Find least significant bit that is set. */ 1786 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1787 1788 #define IWN_READ(sc, reg) \ 1789 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1790 1791 #define IWN_WRITE(sc, reg, val) \ 1792 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1793 1794 #define IWN_WRITE_1(sc, reg, val) \ 1795 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1796 1797 #define IWN_SETBITS(sc, reg, mask) \ 1798 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1799 1800 #define IWN_CLRBITS(sc, reg, mask) \ 1801 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1802 1803 #define IWN_BARRIER_WRITE(sc) \ 1804 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1805 BUS_SPACE_BARRIER_WRITE) 1806 1807 #define IWN_BARRIER_READ_WRITE(sc) \ 1808 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1809 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1810 1811