1 /* $NetBSD: if_ipw.c,v 1.74 2021/06/16 00:21:18 riastradh Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.74 2021/06/16 00:21:18 riastradh Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40 #include <sys/param.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/conf.h> 49 #include <sys/proc.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #include <net/bpf.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_radiotap.h> 69 70 #include <netinet/in.h> 71 #include <netinet/in_systm.h> 72 #include <netinet/in_var.h> 73 #include <netinet/ip.h> 74 75 #include <dev/firmload.h> 76 77 #include <dev/pci/if_ipwreg.h> 78 #include <dev/pci/if_ipwvar.h> 79 80 #ifdef IPW_DEBUG 81 #define DPRINTF(x) if (ipw_debug > 0) printf x 82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 83 int ipw_debug = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n, x) 87 #endif 88 89 /* Permit loading the Intel firmware */ 90 static int ipw_accept_eula; 91 92 static int ipw_dma_alloc(struct ipw_softc *); 93 static void ipw_release(struct ipw_softc *); 94 static int ipw_match(device_t, cfdata_t, void *); 95 static void ipw_attach(device_t, device_t, void *); 96 static int ipw_detach(device_t, int); 97 98 static int ipw_media_change(struct ifnet *); 99 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 105 struct ipw_soft_bd *, struct ipw_soft_buf *); 106 static void ipw_rx_intr(struct ipw_softc *); 107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 108 static void ipw_tx_intr(struct ipw_softc *); 109 static int ipw_intr(void *); 110 static void ipw_softintr(void *); 111 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 112 static int ipw_tx_start(struct ifnet *, struct mbuf *, 113 struct ieee80211_node *); 114 static void ipw_start(struct ifnet *); 115 static void ipw_watchdog(struct ifnet *); 116 static int ipw_ioctl(struct ifnet *, u_long, void *); 117 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 118 static int ipw_get_radio(struct ipw_softc *, int *); 119 static void ipw_stop_master(struct ipw_softc *); 120 static int ipw_reset(struct ipw_softc *); 121 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 122 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 123 static int ipw_cache_firmware(struct ipw_softc *); 124 static void ipw_free_firmware(struct ipw_softc *); 125 static int ipw_config(struct ipw_softc *); 126 static int ipw_init(struct ifnet *); 127 static void ipw_stop(struct ifnet *, int); 128 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 129 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 130 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 131 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 132 bus_size_t); 133 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 134 bus_size_t); 135 136 static inline uint8_t 137 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 138 { 139 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 140 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 141 } 142 143 static inline uint32_t 144 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 145 { 146 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 147 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 148 } 149 150 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 151 ipw_detach, NULL); 152 153 static int 154 ipw_match(device_t parent, cfdata_t match, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 159 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 160 return 1; 161 162 return 0; 163 } 164 165 /* Base Address Register */ 166 #define IPW_PCI_BAR0 0x10 167 168 static void 169 ipw_attach(device_t parent, device_t self, void *aux) 170 { 171 struct ipw_softc *sc = device_private(self); 172 struct ieee80211com *ic = &sc->sc_ic; 173 struct ifnet *ifp = &sc->sc_if; 174 struct pci_attach_args *pa = aux; 175 const char *intrstr; 176 bus_space_tag_t memt; 177 bus_space_handle_t memh; 178 bus_addr_t base; 179 pci_intr_handle_t ih; 180 uint32_t data; 181 uint16_t val; 182 int i, error; 183 char intrbuf[PCI_INTRSTR_LEN]; 184 185 sc->sc_dev = self; 186 sc->sc_pct = pa->pa_pc; 187 sc->sc_pcitag = pa->pa_tag; 188 189 pci_aprint_devinfo(pa, NULL); 190 191 /* enable bus-mastering */ 192 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 193 data |= PCI_COMMAND_MASTER_ENABLE; 194 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 195 196 /* map the register window */ 197 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 198 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 199 if (error != 0) { 200 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 201 return; 202 } 203 204 sc->sc_st = memt; 205 sc->sc_sh = memh; 206 sc->sc_dmat = pa->pa_dmat; 207 sc->sc_fwname = "ipw2100-1.2.fw"; 208 209 /* disable interrupts */ 210 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 211 212 if (pci_intr_map(pa, &ih) != 0) { 213 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 214 goto fail; 215 } 216 217 sc->sc_soft_ih = softint_establish(SOFTINT_NET, ipw_softintr, sc); 218 if (sc->sc_soft_ih == NULL) { 219 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 220 goto fail; 221 } 222 223 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 224 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, ih, IPL_NET, ipw_intr, 225 sc, device_xname(self)); 226 if (sc->sc_ih == NULL) { 227 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 228 if (intrstr != NULL) 229 aprint_error(" at %s", intrstr); 230 aprint_error("\n"); 231 goto fail; 232 } 233 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 234 235 if (ipw_reset(sc) != 0) { 236 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 237 goto fail; 238 } 239 240 if (ipw_dma_alloc(sc) != 0) { 241 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 242 goto fail; 243 } 244 245 ifp->if_softc = sc; 246 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 247 ifp->if_init = ipw_init; 248 ifp->if_stop = ipw_stop; 249 ifp->if_ioctl = ipw_ioctl; 250 ifp->if_start = ipw_start; 251 ifp->if_watchdog = ipw_watchdog; 252 IFQ_SET_READY(&ifp->if_snd); 253 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 254 255 ic->ic_ifp = ifp; 256 ic->ic_phytype = IEEE80211_T_DS; 257 ic->ic_opmode = IEEE80211_M_STA; 258 ic->ic_state = IEEE80211_S_INIT; 259 260 /* set device capabilities */ 261 ic->ic_caps = 262 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 263 | IEEE80211_C_TXPMGT /* tx power management */ 264 | IEEE80211_C_IBSS /* ibss mode */ 265 | IEEE80211_C_MONITOR /* monitor mode */ 266 ; 267 268 /* read MAC address from EEPROM */ 269 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 270 ic->ic_myaddr[0] = val >> 8; 271 ic->ic_myaddr[1] = val & 0xff; 272 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 273 ic->ic_myaddr[2] = val >> 8; 274 ic->ic_myaddr[3] = val & 0xff; 275 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 276 ic->ic_myaddr[4] = val >> 8; 277 ic->ic_myaddr[5] = val & 0xff; 278 279 /* set supported .11b rates */ 280 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 281 282 /* set supported .11b channels (read from EEPROM) */ 283 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 284 val = 0x7ff; /* default to channels 1-11 */ 285 val <<= 1; 286 for (i = 1; i < 16; i++) { 287 if (val & (1 << i)) { 288 ic->ic_channels[i].ic_freq = 289 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 290 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 291 } 292 } 293 294 /* check support for radio transmitter switch in EEPROM */ 295 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 296 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 297 298 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 299 ether_sprintf(ic->ic_myaddr)); 300 301 if_initialize(ifp); 302 ieee80211_ifattach(ic); 303 /* Use common softint-based if_input */ 304 ifp->if_percpuq = if_percpuq_create(ifp); 305 if_register(ifp); 306 307 /* override state transition machine */ 308 sc->sc_newstate = ic->ic_newstate; 309 ic->ic_newstate = ipw_newstate; 310 311 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 312 313 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 314 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 315 316 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 317 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 318 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 319 320 sc->sc_txtap_len = sizeof sc->sc_txtapu; 321 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 322 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 323 324 /* 325 * Add a few sysctl knobs. 326 * XXX: Not yet 327 */ 328 sc->dwelltime = 100; 329 330 if (pmf_device_register(self, NULL, NULL)) 331 pmf_class_network_register(self, ifp); 332 else 333 aprint_error_dev(self, "couldn't establish power handler\n"); 334 335 ieee80211_announce(ic); 336 337 return; 338 339 fail: ipw_detach(self, 0); 340 } 341 342 static int 343 ipw_detach(device_t self, int flags) 344 { 345 struct ipw_softc *sc = device_private(self); 346 struct ifnet *ifp = &sc->sc_if; 347 348 if (ifp->if_softc) { 349 ipw_stop(ifp, 1); 350 ipw_free_firmware(sc); 351 352 bpf_detach(ifp); 353 ieee80211_ifdetach(&sc->sc_ic); 354 if_detach(ifp); 355 356 ipw_release(sc); 357 } 358 359 if (sc->sc_ih != NULL) { 360 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 361 sc->sc_ih = NULL; 362 } 363 364 if (sc->sc_soft_ih != NULL) { 365 softint_disestablish(sc->sc_soft_ih); 366 sc->sc_soft_ih = NULL; 367 } 368 369 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 370 371 return 0; 372 } 373 374 static int 375 ipw_dma_alloc(struct ipw_softc *sc) 376 { 377 struct ipw_soft_bd *sbd; 378 struct ipw_soft_hdr *shdr; 379 struct ipw_soft_buf *sbuf; 380 int error, i, nsegs; 381 382 /* 383 * Allocate and map tx ring. 384 */ 385 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 386 BUS_DMA_NOWAIT, &sc->tbd_map); 387 if (error != 0) { 388 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 389 goto fail; 390 } 391 392 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 393 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 394 if (error != 0) { 395 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 396 goto fail; 397 } 398 399 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 400 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 401 if (error != 0) { 402 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 403 goto fail; 404 } 405 406 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 407 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 408 if (error != 0) { 409 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 410 goto fail; 411 } 412 413 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 414 415 /* 416 * Allocate and map rx ring. 417 */ 418 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 419 BUS_DMA_NOWAIT, &sc->rbd_map); 420 if (error != 0) { 421 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 422 goto fail; 423 } 424 425 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 426 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 427 if (error != 0) { 428 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 429 goto fail; 430 } 431 432 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 433 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 434 if (error != 0) { 435 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 436 goto fail; 437 } 438 439 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 440 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 441 if (error != 0) { 442 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 443 goto fail; 444 } 445 446 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 447 448 /* 449 * Allocate and map status ring. 450 */ 451 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 452 0, BUS_DMA_NOWAIT, &sc->status_map); 453 if (error != 0) { 454 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 455 goto fail; 456 } 457 458 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 459 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 460 if (error != 0) { 461 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 462 goto fail; 463 } 464 465 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 466 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 467 if (error != 0) { 468 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 469 goto fail; 470 } 471 472 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 473 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 474 if (error != 0) { 475 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 476 goto fail; 477 } 478 479 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 480 481 /* 482 * Allocate command DMA map. 483 */ 484 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 485 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 486 if (error != 0) { 487 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 488 goto fail; 489 } 490 491 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 492 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 493 if (error != 0) { 494 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 495 goto fail; 496 } 497 498 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 499 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 500 if (error != 0) { 501 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 502 goto fail; 503 } 504 505 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 506 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 507 if (error != 0) { 508 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 509 return error; 510 } 511 512 /* 513 * Allocate and map hdr list. 514 */ 515 516 error = bus_dmamap_create(sc->sc_dmat, 517 IPW_NDATA * sizeof(struct ipw_hdr), 1, 518 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 519 &sc->hdr_map); 520 if (error != 0) { 521 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 522 goto fail; 523 } 524 525 error = bus_dmamem_alloc(sc->sc_dmat, 526 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 527 1, &nsegs, BUS_DMA_NOWAIT); 528 if (error != 0) { 529 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 530 goto fail; 531 } 532 533 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 534 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 535 BUS_DMA_NOWAIT); 536 if (error != 0) { 537 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 538 goto fail; 539 } 540 541 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 542 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 543 if (error != 0) { 544 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 545 goto fail; 546 } 547 548 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 549 550 /* 551 * Create DMA hdrs tailq. 552 */ 553 TAILQ_INIT(&sc->sc_free_shdr); 554 for (i = 0; i < IPW_NDATA; i++) { 555 shdr = &sc->shdr_list[i]; 556 shdr->hdr = sc->hdr_list + i; 557 shdr->offset = sizeof(struct ipw_hdr) * i; 558 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 559 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 560 } 561 562 /* 563 * Allocate tx buffers DMA maps. 564 */ 565 TAILQ_INIT(&sc->sc_free_sbuf); 566 for (i = 0; i < IPW_NDATA; i++) { 567 sbuf = &sc->tx_sbuf_list[i]; 568 569 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 570 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 571 if (error != 0) { 572 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 573 goto fail; 574 } 575 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 576 } 577 578 /* 579 * Initialize tx ring. 580 */ 581 for (i = 0; i < IPW_NTBD; i++) { 582 sbd = &sc->stbd_list[i]; 583 sbd->bd = &sc->tbd_list[i]; 584 sbd->type = IPW_SBD_TYPE_NOASSOC; 585 } 586 587 /* 588 * Pre-allocate rx buffers and DMA maps 589 */ 590 for (i = 0; i < IPW_NRBD; i++) { 591 sbd = &sc->srbd_list[i]; 592 sbuf = &sc->rx_sbuf_list[i]; 593 sbd->bd = &sc->rbd_list[i]; 594 595 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 596 if (sbuf->m == NULL) { 597 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 598 error = ENOMEM; 599 goto fail; 600 } 601 602 MCLGET(sbuf->m, M_DONTWAIT); 603 if (!(sbuf->m->m_flags & M_EXT)) { 604 m_freem(sbuf->m); 605 sbuf->m = NULL; 606 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 607 error = ENOMEM; 608 goto fail; 609 } 610 611 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 612 613 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 614 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 615 if (error != 0) { 616 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 617 m_freem(sbuf->m); 618 sbuf->m = NULL; 619 goto fail; 620 } 621 622 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 623 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 624 if (error != 0) { 625 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 626 sbuf->map = NULL; 627 m_freem(sbuf->m); 628 sbuf->m = NULL; 629 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 630 goto fail; 631 } 632 633 sbd->type = IPW_SBD_TYPE_DATA; 634 sbd->priv = sbuf; 635 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 636 sbd->bd->len = htole32(MCLBYTES); 637 638 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 639 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 640 641 } 642 643 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 644 BUS_DMASYNC_PREREAD); 645 646 return 0; 647 648 fail: ipw_release(sc); 649 return error; 650 } 651 652 static void 653 ipw_release(struct ipw_softc *sc) 654 { 655 struct ipw_soft_buf *sbuf; 656 int i; 657 658 if (sc->tbd_map != NULL) { 659 if (sc->tbd_list != NULL) { 660 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 661 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 662 IPW_TBD_SZ); 663 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 664 } 665 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 666 } 667 668 if (sc->rbd_map != NULL) { 669 if (sc->rbd_list != NULL) { 670 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 671 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 672 IPW_RBD_SZ); 673 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 674 } 675 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 676 } 677 678 if (sc->status_map != NULL) { 679 if (sc->status_list != NULL) { 680 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 681 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 682 IPW_RBD_SZ); 683 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 684 } 685 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 686 } 687 688 for (i = 0; i < IPW_NTBD; i++) 689 ipw_release_sbd(sc, &sc->stbd_list[i]); 690 691 if (sc->cmd_map != NULL) 692 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 693 694 if (sc->hdr_list != NULL) { 695 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 696 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 697 IPW_NDATA * sizeof(struct ipw_hdr)); 698 } 699 if (sc->hdr_map != NULL) { 700 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 701 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 702 } 703 704 for (i = 0; i < IPW_NDATA; i++) 705 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 706 707 for (i = 0; i < IPW_NRBD; i++) { 708 sbuf = &sc->rx_sbuf_list[i]; 709 if (sbuf->map != NULL) { 710 if (sbuf->m != NULL) { 711 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 712 m_freem(sbuf->m); 713 } 714 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 715 } 716 } 717 718 } 719 720 static int 721 ipw_media_change(struct ifnet *ifp) 722 { 723 int error; 724 725 error = ieee80211_media_change(ifp); 726 if (error != ENETRESET) 727 return error; 728 729 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 730 ipw_init(ifp); 731 732 return 0; 733 } 734 735 /* 736 * The firmware automatically adapts the transmit speed. We report the current 737 * transmit speed here. 738 */ 739 static void 740 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 741 { 742 #define N(a) (sizeof (a) / sizeof (a[0])) 743 struct ipw_softc *sc = ifp->if_softc; 744 struct ieee80211com *ic = &sc->sc_ic; 745 static const struct { 746 uint32_t val; 747 int rate; 748 } rates[] = { 749 { IPW_RATE_DS1, 2 }, 750 { IPW_RATE_DS2, 4 }, 751 { IPW_RATE_DS5, 11 }, 752 { IPW_RATE_DS11, 22 }, 753 }; 754 uint32_t val; 755 int rate, i; 756 757 imr->ifm_status = IFM_AVALID; 758 imr->ifm_active = IFM_IEEE80211; 759 if (ic->ic_state == IEEE80211_S_RUN) 760 imr->ifm_status |= IFM_ACTIVE; 761 762 /* read current transmission rate from adapter */ 763 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 764 765 /* convert ipw rate to 802.11 rate */ 766 for (i = 0; i < N(rates) && rates[i].val != val; i++); 767 rate = (i < N(rates)) ? rates[i].rate : 0; 768 769 imr->ifm_active |= IFM_IEEE80211_11B; 770 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 771 switch (ic->ic_opmode) { 772 case IEEE80211_M_STA: 773 break; 774 775 case IEEE80211_M_IBSS: 776 imr->ifm_active |= IFM_IEEE80211_ADHOC; 777 break; 778 779 case IEEE80211_M_MONITOR: 780 imr->ifm_active |= IFM_IEEE80211_MONITOR; 781 break; 782 783 case IEEE80211_M_AHDEMO: 784 case IEEE80211_M_HOSTAP: 785 /* should not get there */ 786 break; 787 } 788 #undef N 789 } 790 791 static int 792 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 793 int arg) 794 { 795 struct ifnet *ifp = ic->ic_ifp; 796 struct ipw_softc *sc = ifp->if_softc; 797 struct ieee80211_node *ni; 798 uint8_t macaddr[IEEE80211_ADDR_LEN]; 799 uint32_t len; 800 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 801 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 802 803 switch (nstate) { 804 case IEEE80211_S_INIT: 805 break; 806 default: 807 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 808 KASSERT(ic->ic_curchan != NULL); 809 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 810 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 811 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 812 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 813 break; 814 } 815 816 switch (nstate) { 817 case IEEE80211_S_RUN: 818 DELAY(200); /* firmware needs a short delay here */ 819 820 len = IEEE80211_ADDR_LEN; 821 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 822 823 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 824 if (ni == NULL) 825 break; 826 827 ieee80211_ref_node(ni); 828 ieee80211_sta_join(ic, ni); 829 ieee80211_node_authorize(ni); 830 831 if (ic->ic_opmode == IEEE80211_M_STA) 832 ieee80211_notify_node_join(ic, ni, 1); 833 break; 834 835 case IEEE80211_S_INIT: 836 case IEEE80211_S_SCAN: 837 case IEEE80211_S_AUTH: 838 case IEEE80211_S_ASSOC: 839 break; 840 } 841 842 ic->ic_state = nstate; 843 return 0; 844 } 845 846 /* 847 * Read 16 bits at address 'addr' from the serial EEPROM. 848 */ 849 static uint16_t 850 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 851 { 852 uint32_t tmp; 853 uint16_t val; 854 int n; 855 856 /* clock C once before the first command */ 857 IPW_EEPROM_CTL(sc, 0); 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 859 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 860 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 861 862 /* write start bit (1) */ 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 865 866 /* write READ opcode (10) */ 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 871 872 /* write address A7-A0 */ 873 for (n = 7; n >= 0; n--) { 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 875 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 876 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 877 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 878 } 879 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 881 882 /* read data Q15-Q0 */ 883 val = 0; 884 for (n = 15; n >= 0; n--) { 885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 886 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 887 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 888 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 889 } 890 891 IPW_EEPROM_CTL(sc, 0); 892 893 /* clear Chip Select and clock C */ 894 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 895 IPW_EEPROM_CTL(sc, 0); 896 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 897 898 return le16toh(val); 899 } 900 901 static void 902 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 903 { 904 905 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 906 BUS_DMASYNC_POSTREAD); 907 908 #ifdef IPW_DEBUG 909 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 910 911 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 912 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 913 le32toh(cmd->status))); 914 #endif 915 916 wakeup(&sc->cmd); 917 } 918 919 static void 920 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 921 { 922 struct ieee80211com *ic = &sc->sc_ic; 923 struct ifnet *ifp = sc->sc_ic.ic_ifp; 924 uint32_t state; 925 int s; 926 927 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 928 BUS_DMASYNC_POSTREAD); 929 930 state = le32toh(*mtod(sbuf->m, uint32_t *)); 931 932 DPRINTFN(2, ("entering state %u\n", state)); 933 934 s = splnet(); 935 936 switch (state) { 937 case IPW_STATE_ASSOCIATED: 938 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 939 break; 940 941 case IPW_STATE_SCANNING: 942 /* don't leave run state on background scan */ 943 if (ic->ic_state != IEEE80211_S_RUN) 944 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 945 946 ic->ic_flags |= IEEE80211_F_SCAN; 947 break; 948 949 case IPW_STATE_SCAN_COMPLETE: 950 ieee80211_notify_scan_done(ic); 951 ic->ic_flags &= ~IEEE80211_F_SCAN; 952 break; 953 954 case IPW_STATE_ASSOCIATION_LOST: 955 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 956 break; 957 958 case IPW_STATE_RADIO_DISABLED: 959 ic->ic_ifp->if_flags &= ~IFF_UP; 960 ipw_stop(ifp, 1); 961 break; 962 } 963 964 splx(s); 965 } 966 967 /* 968 * XXX: Hack to set the current channel to the value advertised in beacons or 969 * probe responses. Only used during AP detection. 970 */ 971 static void 972 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 973 { 974 struct ieee80211_frame *wh; 975 uint8_t subtype; 976 uint8_t *frm, *efrm; 977 978 wh = mtod(m, struct ieee80211_frame *); 979 980 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 981 return; 982 983 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 984 985 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 986 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 987 return; 988 989 frm = (uint8_t *)(wh + 1); 990 efrm = mtod(m, uint8_t *) + m->m_len; 991 992 frm += 12; /* skip tstamp, bintval and capinfo fields */ 993 while (frm + 2 < efrm) { 994 if (*frm == IEEE80211_ELEMID_DSPARMS) { 995 #if IEEE80211_CHAN_MAX < 255 996 if (frm[2] <= IEEE80211_CHAN_MAX) 997 #endif 998 ic->ic_curchan = &ic->ic_channels[frm[2]]; 999 } 1000 1001 frm += frm[1] + 2; 1002 } 1003 } 1004 1005 static void 1006 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1007 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1008 { 1009 struct ieee80211com *ic = &sc->sc_ic; 1010 struct ifnet *ifp = &sc->sc_if; 1011 struct mbuf *mnew, *m; 1012 struct ieee80211_frame *wh; 1013 struct ieee80211_node *ni; 1014 int error, s; 1015 1016 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1017 status->rssi)); 1018 1019 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1020 le32toh(status->len) > MCLBYTES) 1021 return; 1022 1023 /* 1024 * Try to allocate a new mbuf for this ring element and load it before 1025 * processing the current mbuf. If the ring element cannot be loaded, 1026 * drop the received packet and reuse the old mbuf. In the unlikely 1027 * case that the old mbuf can't be reloaded either, explicitly panic. 1028 */ 1029 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1030 if (mnew == NULL) { 1031 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1032 if_statinc(ifp, if_ierrors); 1033 return; 1034 } 1035 1036 MCLGET(mnew, M_DONTWAIT); 1037 if (!(mnew->m_flags & M_EXT)) { 1038 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1039 m_freem(mnew); 1040 if_statinc(ifp, if_ierrors); 1041 return; 1042 } 1043 1044 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1045 1046 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1047 BUS_DMASYNC_POSTREAD); 1048 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1049 1050 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1051 BUS_DMA_READ | BUS_DMA_NOWAIT); 1052 if (error != 0) { 1053 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1054 m_freem(mnew); 1055 1056 /* try to reload the old mbuf */ 1057 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1058 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1059 if (error != 0) { 1060 /* very unlikely that it will fail... */ 1061 panic("%s: unable to remap rx buf", 1062 device_xname(sc->sc_dev)); 1063 } 1064 if_statinc(ifp, if_ierrors); 1065 return; 1066 } 1067 1068 /* 1069 * New mbuf successfully loaded, update Rx ring and continue 1070 * processing. 1071 */ 1072 m = sbuf->m; 1073 sbuf->m = mnew; 1074 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1075 1076 /* finalize mbuf */ 1077 m_set_rcvif(m, ifp); 1078 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1079 1080 s = splnet(); 1081 1082 if (sc->sc_drvbpf != NULL) { 1083 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1084 1085 tap->wr_antsignal = status->rssi; 1086 1087 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 1088 } 1089 1090 if (ic->ic_state == IEEE80211_S_SCAN) 1091 ipw_fix_channel(ic, m); 1092 1093 wh = mtod(m, struct ieee80211_frame *); 1094 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1095 1096 /* send the frame to the 802.11 layer */ 1097 ieee80211_input(ic, m, ni, status->rssi, 0); 1098 1099 /* node is no longer needed */ 1100 ieee80211_free_node(ni); 1101 1102 splx(s); 1103 1104 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1105 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1106 } 1107 1108 static void 1109 ipw_rx_intr(struct ipw_softc *sc) 1110 { 1111 struct ipw_status *status; 1112 struct ipw_soft_bd *sbd; 1113 struct ipw_soft_buf *sbuf; 1114 uint32_t r, i; 1115 1116 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1117 return; 1118 1119 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1120 1121 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1122 1123 /* firmware was killed, stop processing received frames */ 1124 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1125 return; 1126 1127 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1128 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1129 BUS_DMASYNC_POSTREAD); 1130 1131 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1132 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1133 BUS_DMASYNC_POSTREAD); 1134 1135 status = &sc->status_list[i]; 1136 sbd = &sc->srbd_list[i]; 1137 sbuf = sbd->priv; 1138 1139 switch (le16toh(status->code) & 0xf) { 1140 case IPW_STATUS_CODE_COMMAND: 1141 ipw_command_intr(sc, sbuf); 1142 break; 1143 1144 case IPW_STATUS_CODE_NEWSTATE: 1145 ipw_newstate_intr(sc, sbuf); 1146 break; 1147 1148 case IPW_STATUS_CODE_DATA_802_3: 1149 case IPW_STATUS_CODE_DATA_802_11: 1150 ipw_data_intr(sc, status, sbd, sbuf); 1151 break; 1152 1153 case IPW_STATUS_CODE_NOTIFICATION: 1154 DPRINTFN(2, ("received notification\n")); 1155 break; 1156 1157 default: 1158 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1159 le16toh(status->code)); 1160 } 1161 1162 sbd->bd->flags = 0; 1163 1164 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1165 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1166 BUS_DMASYNC_PREREAD); 1167 1168 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1169 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1170 BUS_DMASYNC_PREREAD); 1171 } 1172 1173 /* Tell the firmware what we have processed */ 1174 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1175 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1176 } 1177 1178 static void 1179 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1180 { 1181 struct ipw_soft_hdr *shdr; 1182 struct ipw_soft_buf *sbuf; 1183 1184 switch (sbd->type) { 1185 case IPW_SBD_TYPE_COMMAND: 1186 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1187 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1188 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1189 break; 1190 1191 case IPW_SBD_TYPE_HEADER: 1192 shdr = sbd->priv; 1193 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1194 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1195 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1196 break; 1197 1198 case IPW_SBD_TYPE_DATA: 1199 sbuf = sbd->priv; 1200 1201 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1202 0, sbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1203 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1204 m_freem(sbuf->m); 1205 if (sbuf->ni != NULL) 1206 ieee80211_free_node(sbuf->ni); 1207 /* kill watchdog timer */ 1208 sc->sc_tx_timer = 0; 1209 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1210 break; 1211 } 1212 sbd->type = IPW_SBD_TYPE_NOASSOC; 1213 } 1214 1215 static void 1216 ipw_tx_intr(struct ipw_softc *sc) 1217 { 1218 struct ifnet *ifp = &sc->sc_if; 1219 struct ipw_soft_bd *sbd; 1220 uint32_t r, i; 1221 int s; 1222 1223 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1224 return; 1225 1226 s = splnet(); 1227 1228 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1229 1230 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1231 sbd = &sc->stbd_list[i]; 1232 1233 if (sbd->type == IPW_SBD_TYPE_DATA) 1234 if_statinc(ifp, if_opackets); 1235 1236 ipw_release_sbd(sc, sbd); 1237 sc->txfree++; 1238 } 1239 1240 /* remember what the firmware has processed */ 1241 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1242 1243 /* Call start() since some buffer descriptors have been released */ 1244 ifp->if_flags &= ~IFF_OACTIVE; 1245 ipw_start(ifp); /* in softint */ 1246 1247 splx(s); 1248 } 1249 1250 static int 1251 ipw_intr(void *arg) 1252 { 1253 struct ipw_softc *sc = arg; 1254 uint32_t r; 1255 1256 r = CSR_READ_4(sc, IPW_CSR_INTR); 1257 if (r == 0 || r == 0xffffffff) 1258 return 0; 1259 1260 /* Disable interrupts */ 1261 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1262 1263 softint_schedule(sc->sc_soft_ih); 1264 return 1; 1265 } 1266 1267 static void 1268 ipw_softintr(void *arg) 1269 { 1270 struct ipw_softc *sc = arg; 1271 uint32_t r; 1272 int s; 1273 1274 r = CSR_READ_4(sc, IPW_CSR_INTR); 1275 if (r == 0 || r == 0xffffffff) 1276 goto out; 1277 1278 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1279 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1280 s = splnet(); 1281 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1282 ipw_stop(&sc->sc_if, 1); 1283 splx(s); 1284 } 1285 1286 if (r & IPW_INTR_FW_INIT_DONE) { 1287 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1288 wakeup(sc); 1289 } 1290 1291 if (r & IPW_INTR_RX_TRANSFER) 1292 ipw_rx_intr(sc); 1293 1294 if (r & IPW_INTR_TX_TRANSFER) 1295 ipw_tx_intr(sc); 1296 1297 /* Acknowledge all interrupts */ 1298 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1299 1300 out: 1301 /* Re-enable interrupts */ 1302 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1303 } 1304 1305 /* 1306 * Send a command to the firmware and wait for the acknowledgement. 1307 */ 1308 static int 1309 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1310 { 1311 struct ipw_soft_bd *sbd; 1312 1313 sbd = &sc->stbd_list[sc->txcur]; 1314 1315 sc->cmd.type = htole32(type); 1316 sc->cmd.subtype = 0; 1317 sc->cmd.len = htole32(len); 1318 sc->cmd.seq = 0; 1319 1320 (void)memcpy(sc->cmd.data, data, len); 1321 1322 sbd->type = IPW_SBD_TYPE_COMMAND; 1323 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1324 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1325 sbd->bd->nfrag = 1; 1326 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1327 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1328 1329 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1330 BUS_DMASYNC_PREWRITE); 1331 1332 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1333 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1334 BUS_DMASYNC_PREWRITE); 1335 1336 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1337 1338 /* kick firmware */ 1339 sc->txfree--; 1340 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1341 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1342 1343 /* Wait at most one second for command to complete */ 1344 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1345 } 1346 1347 static int 1348 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1349 { 1350 struct ipw_softc *sc = ifp->if_softc; 1351 struct ieee80211com *ic = &sc->sc_ic; 1352 struct ieee80211_frame *wh; 1353 struct ipw_soft_bd *sbd; 1354 struct ipw_soft_hdr *shdr; 1355 struct ipw_soft_buf *sbuf; 1356 struct ieee80211_key *k; 1357 struct mbuf *mnew; 1358 int error, i; 1359 1360 wh = mtod(m0, struct ieee80211_frame *); 1361 1362 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1363 k = ieee80211_crypto_encap(ic, ni, m0); 1364 if (k == NULL) { 1365 m_freem(m0); 1366 return ENOBUFS; 1367 } 1368 1369 /* packet header may have moved, reset our local pointer */ 1370 wh = mtod(m0, struct ieee80211_frame *); 1371 } 1372 1373 if (sc->sc_drvbpf != NULL) { 1374 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1375 1376 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1377 } 1378 1379 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1380 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1381 KASSERT(shdr != NULL && sbuf != NULL); 1382 1383 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1384 shdr->hdr->subtype = 0; 1385 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1386 shdr->hdr->encrypt = 0; 1387 shdr->hdr->keyidx = 0; 1388 shdr->hdr->keysz = 0; 1389 shdr->hdr->fragmentsz = 0; 1390 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1391 if (ic->ic_opmode == IEEE80211_M_STA) 1392 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1393 else 1394 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1395 1396 /* trim IEEE802.11 header */ 1397 m_adj(m0, sizeof (struct ieee80211_frame)); 1398 1399 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1400 BUS_DMA_NOWAIT); 1401 if (error != 0 && error != EFBIG) { 1402 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1403 error); 1404 m_freem(m0); 1405 return error; 1406 } 1407 1408 if (error != 0) { 1409 /* too many fragments, linearize */ 1410 1411 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1412 if (mnew == NULL) { 1413 m_freem(m0); 1414 return ENOMEM; 1415 } 1416 1417 m_copy_pkthdr(mnew, m0); 1418 1419 /* If the data won't fit in the header, get a cluster */ 1420 if (m0->m_pkthdr.len > MHLEN) { 1421 MCLGET(mnew, M_DONTWAIT); 1422 if (!(mnew->m_flags & M_EXT)) { 1423 m_freem(m0); 1424 m_freem(mnew); 1425 return ENOMEM; 1426 } 1427 } 1428 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1429 m_freem(m0); 1430 mnew->m_len = mnew->m_pkthdr.len; 1431 m0 = mnew; 1432 1433 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1434 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1435 if (error != 0) { 1436 aprint_error_dev(sc->sc_dev, 1437 "could not map mbuf (error %d)\n", error); 1438 m_freem(m0); 1439 return error; 1440 } 1441 } 1442 1443 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1444 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1445 1446 sbd = &sc->stbd_list[sc->txcur]; 1447 sbd->type = IPW_SBD_TYPE_HEADER; 1448 sbd->priv = shdr; 1449 sbd->bd->physaddr = htole32(shdr->addr); 1450 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1451 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1452 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1453 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1454 1455 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1456 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1457 shdr->hdr->encrypt)); 1458 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1459 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1460 1461 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1462 sc->txcur * sizeof (struct ipw_bd), 1463 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1464 1465 sc->txfree--; 1466 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1467 1468 sbuf->m = m0; 1469 sbuf->ni = ni; 1470 1471 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1472 sbd = &sc->stbd_list[sc->txcur]; 1473 1474 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1475 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1476 sbd->bd->nfrag = 0; 1477 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1478 if (i == sbuf->map->dm_nsegs - 1) { 1479 sbd->type = IPW_SBD_TYPE_DATA; 1480 sbd->priv = sbuf; 1481 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1482 } else { 1483 sbd->type = IPW_SBD_TYPE_NOASSOC; 1484 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1485 } 1486 1487 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1488 (int)sbuf->map->dm_segs[i].ds_len)); 1489 1490 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1491 sc->txcur * sizeof (struct ipw_bd), 1492 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1493 1494 sc->txfree--; 1495 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1496 } 1497 1498 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1499 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1500 1501 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1502 BUS_DMASYNC_PREWRITE); 1503 1504 /* Inform firmware about this new packet */ 1505 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1506 1507 return 0; 1508 } 1509 1510 static void 1511 ipw_start(struct ifnet *ifp) 1512 { 1513 struct ipw_softc *sc = ifp->if_softc; 1514 struct ieee80211com *ic = &sc->sc_ic; 1515 struct mbuf *m0; 1516 struct ether_header *eh; 1517 struct ieee80211_node *ni; 1518 1519 if (ic->ic_state != IEEE80211_S_RUN) 1520 return; 1521 1522 for (;;) { 1523 IF_DEQUEUE(&ifp->if_snd, m0); 1524 if (m0 == NULL) 1525 break; 1526 1527 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1528 IF_PREPEND(&ifp->if_snd, m0); 1529 ifp->if_flags |= IFF_OACTIVE; 1530 break; 1531 } 1532 1533 if (m0->m_len < sizeof (struct ether_header) && 1534 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1535 continue; 1536 1537 eh = mtod(m0, struct ether_header *); 1538 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1539 if (ni == NULL) { 1540 m_freem(m0); 1541 continue; 1542 } 1543 1544 bpf_mtap(ifp, m0, BPF_D_OUT); 1545 1546 m0 = ieee80211_encap(ic, m0, ni); 1547 if (m0 == NULL) { 1548 ieee80211_free_node(ni); 1549 continue; 1550 } 1551 1552 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1553 1554 if (ipw_tx_start(ifp, m0, ni) != 0) { 1555 ieee80211_free_node(ni); 1556 if_statinc(ifp, if_oerrors); 1557 break; 1558 } 1559 1560 /* start watchdog timer */ 1561 sc->sc_tx_timer = 5; 1562 ifp->if_timer = 1; 1563 } 1564 } 1565 1566 static void 1567 ipw_watchdog(struct ifnet *ifp) 1568 { 1569 struct ipw_softc *sc = ifp->if_softc; 1570 1571 ifp->if_timer = 0; 1572 1573 if (sc->sc_tx_timer > 0) { 1574 if (--sc->sc_tx_timer == 0) { 1575 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1576 if_statinc(ifp, if_oerrors); 1577 ifp->if_flags &= ~IFF_UP; 1578 ipw_stop(ifp, 1); 1579 return; 1580 } 1581 ifp->if_timer = 1; 1582 } 1583 1584 ieee80211_watchdog(&sc->sc_ic); 1585 } 1586 1587 static int 1588 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1589 { 1590 uint32_t addr, size, data, i; 1591 int error; 1592 1593 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1594 return ENOTTY; 1595 1596 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1597 1598 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1599 if ((error = copyout(&size, tbl, sizeof(size))) != 0) 1600 return error; 1601 1602 for (i = 1, ++tbl; i < size; i++, tbl++) { 1603 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1604 data = MEM_READ_4(sc, addr); 1605 if ((error = copyout(&data, tbl, sizeof(data))) != 0) 1606 return error; 1607 } 1608 return 0; 1609 } 1610 1611 static int 1612 ipw_get_radio(struct ipw_softc *sc, int *ret) 1613 { 1614 uint32_t addr, data; 1615 1616 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1617 return ENOTTY; 1618 1619 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1620 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) 1621 data = -1; 1622 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1623 data = 0; 1624 else 1625 data = 1; 1626 1627 return copyout(&data, ret, sizeof(data)); 1628 } 1629 1630 static int 1631 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1632 { 1633 #define IS_RUNNING(ifp) \ 1634 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1635 1636 struct ipw_softc *sc = ifp->if_softc; 1637 struct ieee80211com *ic = &sc->sc_ic; 1638 struct ifreq *ifr = (struct ifreq *)data; 1639 int s, error = 0; 1640 1641 s = splnet(); 1642 1643 switch (cmd) { 1644 case SIOCSIFFLAGS: 1645 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1646 break; 1647 if (ifp->if_flags & IFF_UP) { 1648 if (!(ifp->if_flags & IFF_RUNNING)) 1649 ipw_init(ifp); 1650 } else { 1651 if (ifp->if_flags & IFF_RUNNING) 1652 ipw_stop(ifp, 1); 1653 } 1654 break; 1655 1656 case SIOCADDMULTI: 1657 case SIOCDELMULTI: 1658 /* XXX no h/w multicast filter? --dyoung */ 1659 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1660 /* setup multicast filter, etc */ 1661 error = 0; 1662 } 1663 break; 1664 1665 case SIOCGTABLE1: 1666 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1667 break; 1668 1669 case SIOCGRADIO: 1670 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1671 break; 1672 1673 case SIOCSIFMEDIA: 1674 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1675 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1676 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1677 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1678 else 1679 sc->sc_fwname = "ipw2100-1.2.fw"; 1680 1681 ipw_free_firmware(sc); 1682 /* FALLTHROUGH */ 1683 default: 1684 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1685 if (error != ENETRESET) 1686 break; 1687 1688 if (error == ENETRESET) { 1689 if (IS_RUNNING(ifp) && 1690 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1691 ipw_init(ifp); 1692 error = 0; 1693 } 1694 1695 } 1696 1697 splx(s); 1698 return error; 1699 #undef IS_RUNNING 1700 } 1701 1702 static uint32_t 1703 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1704 { 1705 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1706 } 1707 1708 static void 1709 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1710 { 1711 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1712 } 1713 1714 static int 1715 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1716 { 1717 uint32_t addr, info; 1718 uint16_t count, size; 1719 uint32_t total; 1720 1721 /* addr[4] + count[2] + size[2] */ 1722 addr = MEM_READ_4(sc, sc->table2_base + off); 1723 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1724 1725 count = info >> 16; 1726 size = info & 0xffff; 1727 total = count * size; 1728 1729 if (total > *len) { 1730 *len = total; 1731 return EINVAL; 1732 } 1733 1734 *len = total; 1735 ipw_read_mem_1(sc, addr, buf, total); 1736 1737 return 0; 1738 } 1739 1740 static void 1741 ipw_stop_master(struct ipw_softc *sc) 1742 { 1743 int ntries; 1744 1745 /* disable interrupts */ 1746 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1747 1748 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1749 for (ntries = 0; ntries < 50; ntries++) { 1750 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1751 break; 1752 DELAY(10); 1753 } 1754 if (ntries == 50) 1755 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1756 1757 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1758 IPW_RST_PRINCETON_RESET); 1759 1760 sc->flags &= ~IPW_FLAG_FW_INITED; 1761 } 1762 1763 static int 1764 ipw_reset(struct ipw_softc *sc) 1765 { 1766 int ntries; 1767 1768 ipw_stop_master(sc); 1769 1770 /* move adapter to D0 state */ 1771 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1772 IPW_CTL_INIT); 1773 1774 /* wait for clock stabilization */ 1775 for (ntries = 0; ntries < 1000; ntries++) { 1776 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1777 break; 1778 DELAY(200); 1779 } 1780 if (ntries == 1000) 1781 return EIO; 1782 1783 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1784 IPW_RST_SW_RESET); 1785 1786 DELAY(10); 1787 1788 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1789 IPW_CTL_INIT); 1790 1791 return 0; 1792 } 1793 1794 /* 1795 * Upload the microcode to the device. 1796 */ 1797 static int 1798 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1799 { 1800 int ntries; 1801 1802 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1803 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1804 1805 MEM_WRITE_2(sc, 0x220000, 0x0703); 1806 MEM_WRITE_2(sc, 0x220000, 0x0707); 1807 1808 MEM_WRITE_1(sc, 0x210014, 0x72); 1809 MEM_WRITE_1(sc, 0x210014, 0x72); 1810 1811 MEM_WRITE_1(sc, 0x210000, 0x40); 1812 MEM_WRITE_1(sc, 0x210000, 0x00); 1813 MEM_WRITE_1(sc, 0x210000, 0x40); 1814 1815 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1816 1817 MEM_WRITE_1(sc, 0x210000, 0x00); 1818 MEM_WRITE_1(sc, 0x210000, 0x00); 1819 MEM_WRITE_1(sc, 0x210000, 0x80); 1820 1821 MEM_WRITE_2(sc, 0x220000, 0x0703); 1822 MEM_WRITE_2(sc, 0x220000, 0x0707); 1823 1824 MEM_WRITE_1(sc, 0x210014, 0x72); 1825 MEM_WRITE_1(sc, 0x210014, 0x72); 1826 1827 MEM_WRITE_1(sc, 0x210000, 0x00); 1828 MEM_WRITE_1(sc, 0x210000, 0x80); 1829 1830 for (ntries = 0; ntries < 10; ntries++) { 1831 if (MEM_READ_1(sc, 0x210000) & 1) 1832 break; 1833 DELAY(10); 1834 } 1835 if (ntries == 10) { 1836 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1837 return EIO; 1838 } 1839 1840 MEM_WRITE_4(sc, 0x3000e0, 0); 1841 1842 return 0; 1843 } 1844 1845 /* set of macros to handle unaligned little endian data in firmware image */ 1846 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1847 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1848 static int 1849 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1850 { 1851 u_char *p, *end; 1852 uint32_t dst; 1853 uint16_t len; 1854 int error; 1855 1856 p = fw; 1857 end = fw + size; 1858 while (p < end) { 1859 dst = GETLE32(p); p += 4; 1860 len = GETLE16(p); p += 2; 1861 1862 ipw_write_mem_1(sc, dst, p, len); 1863 p += len; 1864 } 1865 1866 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1867 IPW_IO_LED_OFF); 1868 1869 /* enable interrupts */ 1870 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1871 1872 /* kick the firmware */ 1873 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1874 1875 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1876 IPW_CTL_ALLOW_STANDBY); 1877 1878 /* wait at most one second for firmware initialization to complete */ 1879 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1880 aprint_error_dev(sc->sc_dev, 1881 "timeout waiting for firmware initialization " 1882 "to complete\n"); 1883 return error; 1884 } 1885 1886 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1887 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1888 1889 return 0; 1890 } 1891 1892 /* 1893 * Store firmware into kernel memory so we can download it when we need to, 1894 * e.g when the adapter wakes up from suspend mode. 1895 */ 1896 static int 1897 ipw_cache_firmware(struct ipw_softc *sc) 1898 { 1899 struct ipw_firmware *fw = &sc->fw; 1900 struct ipw_firmware_hdr hdr; 1901 firmware_handle_t fwh; 1902 off_t fwsz, p; 1903 int error; 1904 1905 ipw_free_firmware(sc); 1906 1907 if (ipw_accept_eula == 0) { 1908 aprint_error_dev(sc->sc_dev, 1909 "EULA not accepted; please see the ipw(4) man page.\n"); 1910 return EPERM; 1911 } 1912 1913 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1914 goto fail0; 1915 1916 fwsz = firmware_get_size(fwh); 1917 1918 if (fwsz < sizeof(hdr)) 1919 goto fail2; 1920 1921 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1922 goto fail2; 1923 1924 fw->main_size = le32toh(hdr.main_size); 1925 fw->ucode_size = le32toh(hdr.ucode_size); 1926 1927 fw->main = firmware_malloc(fw->main_size); 1928 if (fw->main == NULL) { 1929 error = ENOMEM; 1930 goto fail1; 1931 } 1932 1933 fw->ucode = firmware_malloc(fw->ucode_size); 1934 if (fw->ucode == NULL) { 1935 error = ENOMEM; 1936 goto fail2; 1937 } 1938 1939 p = sizeof(hdr); 1940 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1941 goto fail3; 1942 1943 p += fw->main_size; 1944 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1945 goto fail3; 1946 1947 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1948 fw->ucode_size)); 1949 1950 sc->flags |= IPW_FLAG_FW_CACHED; 1951 1952 firmware_close(fwh); 1953 1954 return 0; 1955 1956 fail3: firmware_free(fw->ucode, fw->ucode_size); 1957 fail2: firmware_free(fw->main, fw->main_size); 1958 fail1: firmware_close(fwh); 1959 fail0: 1960 return error; 1961 } 1962 1963 static void 1964 ipw_free_firmware(struct ipw_softc *sc) 1965 { 1966 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1967 return; 1968 1969 firmware_free(sc->fw.main, sc->fw.main_size); 1970 firmware_free(sc->fw.ucode, sc->fw.ucode_size); 1971 1972 sc->flags &= ~IPW_FLAG_FW_CACHED; 1973 } 1974 1975 static int 1976 ipw_config(struct ipw_softc *sc) 1977 { 1978 struct ieee80211com *ic = &sc->sc_ic; 1979 struct ifnet *ifp = &sc->sc_if; 1980 struct ipw_security security; 1981 struct ieee80211_key *k; 1982 struct ipw_wep_key wepkey; 1983 struct ipw_scan_options options; 1984 struct ipw_configuration config; 1985 uint32_t data; 1986 int error, i; 1987 1988 switch (ic->ic_opmode) { 1989 case IEEE80211_M_STA: 1990 case IEEE80211_M_HOSTAP: 1991 data = htole32(IPW_MODE_BSS); 1992 break; 1993 1994 case IEEE80211_M_IBSS: 1995 case IEEE80211_M_AHDEMO: 1996 data = htole32(IPW_MODE_IBSS); 1997 break; 1998 1999 case IEEE80211_M_MONITOR: 2000 data = htole32(IPW_MODE_MONITOR); 2001 break; 2002 } 2003 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2004 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2005 if (error != 0) 2006 return error; 2007 2008 if (ic->ic_opmode == IEEE80211_M_IBSS || 2009 ic->ic_opmode == IEEE80211_M_MONITOR) { 2010 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2011 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2012 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2013 if (error != 0) 2014 return error; 2015 } 2016 2017 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2018 DPRINTF(("Enabling adapter\n")); 2019 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2020 } 2021 2022 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2023 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2024 IEEE80211_ADDR_LEN); 2025 if (error != 0) 2026 return error; 2027 2028 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2029 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2030 2031 if (ic->ic_opmode == IEEE80211_M_IBSS) 2032 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2033 if (ifp->if_flags & IFF_PROMISC) 2034 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2035 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2036 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2037 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2038 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2039 if (error != 0) 2040 return error; 2041 2042 data = htole32(0x3); /* 1, 2 */ 2043 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2044 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2045 if (error != 0) 2046 return error; 2047 2048 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2049 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2050 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2051 if (error != 0) 2052 return error; 2053 2054 data = htole32(IPW_POWER_MODE_CAM); 2055 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2056 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2057 if (error != 0) 2058 return error; 2059 2060 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2061 data = htole32(32); /* default value */ 2062 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2063 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2064 sizeof data); 2065 if (error != 0) 2066 return error; 2067 } 2068 2069 data = htole32(ic->ic_rtsthreshold); 2070 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2071 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2072 if (error != 0) 2073 return error; 2074 2075 data = htole32(ic->ic_fragthreshold); 2076 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2077 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2078 if (error != 0) 2079 return error; 2080 2081 #ifdef IPW_DEBUG 2082 if (ipw_debug > 0) { 2083 printf("Setting ESSID to "); 2084 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2085 printf("\n"); 2086 } 2087 #endif 2088 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2089 ic->ic_des_esslen); 2090 if (error != 0) 2091 return error; 2092 2093 /* no mandatory BSSID */ 2094 DPRINTF(("Setting mandatory BSSID to null\n")); 2095 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2096 if (error != 0) 2097 return error; 2098 2099 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2100 DPRINTF(("Setting desired BSSID to %s\n", 2101 ether_sprintf(ic->ic_des_bssid))); 2102 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2103 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2104 if (error != 0) 2105 return error; 2106 } 2107 2108 (void)memset(&security, 0, sizeof(security)); 2109 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2110 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2111 security.ciphers = htole32(IPW_CIPHER_NONE); 2112 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2113 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2114 sizeof security); 2115 if (error != 0) 2116 return error; 2117 2118 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2119 k = ic->ic_crypto.cs_nw_keys; 2120 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2121 if (k->wk_keylen == 0) 2122 continue; 2123 2124 wepkey.idx = i; 2125 wepkey.len = k->wk_keylen; 2126 memset(wepkey.key, 0, sizeof(wepkey.key)); 2127 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2128 DPRINTF(("Setting wep key index %u len %u\n", 2129 wepkey.idx, wepkey.len)); 2130 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2131 sizeof wepkey); 2132 if (error != 0) 2133 return error; 2134 } 2135 2136 data = htole32(ic->ic_crypto.cs_def_txkey); 2137 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2138 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2139 sizeof data); 2140 if (error != 0) 2141 return error; 2142 } 2143 2144 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2145 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2146 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2147 if (error != 0) 2148 return error; 2149 2150 #if 0 2151 struct ipw_wpa_ie ie; 2152 2153 memset(&ie, 0 sizeof(ie)); 2154 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2155 DPRINTF(("Setting wpa ie\n")); 2156 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2157 if (error != 0) 2158 return error; 2159 #endif 2160 2161 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2162 data = htole32(ic->ic_bintval); 2163 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2164 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2165 sizeof data); 2166 if (error != 0) 2167 return error; 2168 } 2169 2170 options.flags = 0; 2171 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2172 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2173 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2174 if (error != 0) 2175 return error; 2176 2177 /* finally, enable adapter (start scanning for an access point) */ 2178 DPRINTF(("Enabling adapter\n")); 2179 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2180 } 2181 2182 static int 2183 ipw_init(struct ifnet *ifp) 2184 { 2185 struct ipw_softc *sc = ifp->if_softc; 2186 struct ipw_firmware *fw = &sc->fw; 2187 2188 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2189 if (ipw_cache_firmware(sc) != 0) { 2190 aprint_error_dev(sc->sc_dev, 2191 "could not cache the firmware (%s)\n", 2192 sc->sc_fwname); 2193 goto fail; 2194 } 2195 } 2196 2197 ipw_stop(ifp, 0); 2198 2199 if (ipw_reset(sc) != 0) { 2200 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2201 goto fail; 2202 } 2203 2204 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2205 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2206 goto fail; 2207 } 2208 2209 ipw_stop_master(sc); 2210 2211 /* 2212 * Setup tx, rx and status rings. 2213 */ 2214 sc->txold = IPW_NTBD - 1; 2215 sc->txcur = 0; 2216 sc->txfree = IPW_NTBD - 2; 2217 sc->rxcur = IPW_NRBD - 1; 2218 2219 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2220 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2221 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2222 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2223 2224 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2225 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2226 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2227 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2228 2229 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2230 2231 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2232 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2233 goto fail; 2234 } 2235 2236 sc->flags |= IPW_FLAG_FW_INITED; 2237 2238 /* retrieve information tables base addresses */ 2239 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2240 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2241 2242 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2243 2244 if (ipw_config(sc) != 0) { 2245 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2246 goto fail; 2247 } 2248 2249 ifp->if_flags &= ~IFF_OACTIVE; 2250 ifp->if_flags |= IFF_RUNNING; 2251 2252 return 0; 2253 2254 fail: ifp->if_flags &= ~IFF_UP; 2255 ipw_stop(ifp, 0); 2256 2257 return EIO; 2258 } 2259 2260 static void 2261 ipw_stop(struct ifnet *ifp, int disable) 2262 { 2263 struct ipw_softc *sc = ifp->if_softc; 2264 struct ieee80211com *ic = &sc->sc_ic; 2265 int i; 2266 2267 ipw_stop_master(sc); 2268 2269 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2270 2271 /* 2272 * Release tx buffers. 2273 */ 2274 for (i = 0; i < IPW_NTBD; i++) 2275 ipw_release_sbd(sc, &sc->stbd_list[i]); 2276 2277 sc->sc_tx_timer = 0; 2278 ifp->if_timer = 0; 2279 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2280 2281 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2282 } 2283 2284 static void 2285 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2286 bus_size_t count) 2287 { 2288 for (; count > 0; offset++, datap++, count--) { 2289 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2290 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2291 } 2292 } 2293 2294 static void 2295 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2296 bus_size_t count) 2297 { 2298 for (; count > 0; offset++, datap++, count--) { 2299 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2300 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2301 } 2302 } 2303 2304 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2305 { 2306 const struct sysctlnode *rnode; 2307 const struct sysctlnode *cnode; 2308 2309 sysctl_createv(NULL, 0, NULL, &rnode, 2310 CTLFLAG_PERMANENT, 2311 CTLTYPE_NODE, "ipw", 2312 NULL, 2313 NULL, 0, 2314 NULL, 0, 2315 CTL_HW, CTL_CREATE, CTL_EOL); 2316 2317 sysctl_createv(NULL, 0, &rnode, &cnode, 2318 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2319 CTLTYPE_INT, "accept_eula", 2320 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2321 NULL, 0, 2322 &ipw_accept_eula, sizeof(ipw_accept_eula), 2323 CTL_CREATE, CTL_EOL); 2324 } 2325