1 /* $NetBSD: if_ipw.c,v 1.49 2009/09/05 14:09:55 tsutsui Exp $ */ 2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4 /*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.49 2009/09/05 14:09:55 tsutsui Exp $"); 33 34 /*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/conf.h> 50 51 #include <sys/bus.h> 52 #include <machine/endian.h> 53 #include <sys/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcidevs.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 77 #include <dev/firmload.h> 78 79 #include <dev/pci/if_ipwreg.h> 80 #include <dev/pci/if_ipwvar.h> 81 82 #ifdef IPW_DEBUG 83 #define DPRINTF(x) if (ipw_debug > 0) printf x 84 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 85 int ipw_debug = 0; 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 /* Permit loading the Intel firmware */ 92 static int ipw_accept_eula; 93 94 static int ipw_dma_alloc(struct ipw_softc *); 95 static void ipw_release(struct ipw_softc *); 96 static int ipw_match(device_t, cfdata_t, void *); 97 static void ipw_attach(device_t, device_t, void *); 98 static int ipw_detach(device_t, int); 99 100 static int ipw_media_change(struct ifnet *); 101 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 102 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 103 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 104 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 105 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 106 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 107 struct ipw_soft_bd *, struct ipw_soft_buf *); 108 static void ipw_rx_intr(struct ipw_softc *); 109 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 110 static void ipw_tx_intr(struct ipw_softc *); 111 static int ipw_intr(void *); 112 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 113 static int ipw_tx_start(struct ifnet *, struct mbuf *, 114 struct ieee80211_node *); 115 static void ipw_start(struct ifnet *); 116 static void ipw_watchdog(struct ifnet *); 117 static int ipw_ioctl(struct ifnet *, u_long, void *); 118 static int ipw_get_table1(struct ipw_softc *, uint32_t *); 119 static int ipw_get_radio(struct ipw_softc *, int *); 120 static void ipw_stop_master(struct ipw_softc *); 121 static int ipw_reset(struct ipw_softc *); 122 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 123 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 124 static int ipw_cache_firmware(struct ipw_softc *); 125 static void ipw_free_firmware(struct ipw_softc *); 126 static int ipw_config(struct ipw_softc *); 127 static int ipw_init(struct ifnet *); 128 static void ipw_stop(struct ifnet *, int); 129 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 130 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 131 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 132 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 135 bus_size_t); 136 137 /* 138 * Supported rates for 802.11b mode (in 500Kbps unit). 139 */ 140 static const struct ieee80211_rateset ipw_rateset_11b = 141 { 4, { 2, 4, 11, 22 } }; 142 143 static inline uint8_t 144 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 145 { 146 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 147 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 148 } 149 150 static inline uint32_t 151 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 152 { 153 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 154 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 155 } 156 157 CFATTACH_DECL(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 158 ipw_detach, NULL); 159 160 static int 161 ipw_match(device_t parent, cfdata_t match, void *aux) 162 { 163 struct pci_attach_args *pa = aux; 164 165 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 166 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 167 return 1; 168 169 return 0; 170 } 171 172 /* Base Address Register */ 173 #define IPW_PCI_BAR0 0x10 174 175 static void 176 ipw_attach(device_t parent, device_t self, void *aux) 177 { 178 struct ipw_softc *sc = device_private(self); 179 struct ieee80211com *ic = &sc->sc_ic; 180 struct ifnet *ifp = &sc->sc_if; 181 struct pci_attach_args *pa = aux; 182 const char *intrstr; 183 char devinfo[256]; 184 bus_space_tag_t memt; 185 bus_space_handle_t memh; 186 bus_addr_t base; 187 pci_intr_handle_t ih; 188 uint32_t data; 189 uint16_t val; 190 int i, revision, error; 191 192 sc->sc_pct = pa->pa_pc; 193 sc->sc_pcitag = pa->pa_tag; 194 195 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 196 revision = PCI_REVISION(pa->pa_class); 197 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 198 199 /* enable bus-mastering */ 200 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 201 data |= PCI_COMMAND_MASTER_ENABLE; 202 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 203 204 /* map the register window */ 205 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 206 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 207 if (error != 0) { 208 aprint_error_dev(&sc->sc_dev, "could not map memory space\n"); 209 return; 210 } 211 212 sc->sc_st = memt; 213 sc->sc_sh = memh; 214 sc->sc_dmat = pa->pa_dmat; 215 sc->sc_fwname = "ipw2100-1.2.fw"; 216 217 /* disable interrupts */ 218 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 219 220 if (pci_intr_map(pa, &ih) != 0) { 221 aprint_error_dev(&sc->sc_dev, "could not map interrupt\n"); 222 return; 223 } 224 225 intrstr = pci_intr_string(sc->sc_pct, ih); 226 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc); 227 if (sc->sc_ih == NULL) { 228 aprint_error_dev(&sc->sc_dev, "could not establish interrupt"); 229 if (intrstr != NULL) 230 aprint_error(" at %s", intrstr); 231 aprint_error("\n"); 232 return; 233 } 234 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 235 236 if (ipw_reset(sc) != 0) { 237 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 238 goto fail; 239 } 240 241 if (ipw_dma_alloc(sc) != 0) { 242 aprint_error_dev(&sc->sc_dev, "could not allocate DMA resources\n"); 243 goto fail; 244 } 245 246 ifp->if_softc = sc; 247 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 248 ifp->if_init = ipw_init; 249 ifp->if_stop = ipw_stop; 250 ifp->if_ioctl = ipw_ioctl; 251 ifp->if_start = ipw_start; 252 ifp->if_watchdog = ipw_watchdog; 253 IFQ_SET_READY(&ifp->if_snd); 254 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 255 256 ic->ic_ifp = ifp; 257 ic->ic_phytype = IEEE80211_T_DS; 258 ic->ic_opmode = IEEE80211_M_STA; 259 ic->ic_state = IEEE80211_S_INIT; 260 261 /* set device capabilities */ 262 ic->ic_caps = 263 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 264 | IEEE80211_C_TXPMGT /* tx power management */ 265 | IEEE80211_C_IBSS /* ibss mode */ 266 | IEEE80211_C_MONITOR /* monitor mode */ 267 ; 268 269 /* read MAC address from EEPROM */ 270 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 271 ic->ic_myaddr[0] = val >> 8; 272 ic->ic_myaddr[1] = val & 0xff; 273 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 274 ic->ic_myaddr[2] = val >> 8; 275 ic->ic_myaddr[3] = val & 0xff; 276 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 277 ic->ic_myaddr[4] = val >> 8; 278 ic->ic_myaddr[5] = val & 0xff; 279 280 /* set supported .11b rates */ 281 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 282 283 /* set supported .11b channels (read from EEPROM) */ 284 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 285 val = 0x7ff; /* default to channels 1-11 */ 286 val <<= 1; 287 for (i = 1; i < 16; i++) { 288 if (val & (1 << i)) { 289 ic->ic_channels[i].ic_freq = 290 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 291 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 292 } 293 } 294 295 /* check support for radio transmitter switch in EEPROM */ 296 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 297 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 298 299 aprint_normal_dev(&sc->sc_dev, "802.11 address %s\n", 300 ether_sprintf(ic->ic_myaddr)); 301 302 if_attach(ifp); 303 ieee80211_ifattach(ic); 304 305 /* override state transition machine */ 306 sc->sc_newstate = ic->ic_newstate; 307 ic->ic_newstate = ipw_newstate; 308 309 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 310 311 #if NBPFILTER > 0 312 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 313 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 314 315 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 316 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 317 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 318 319 sc->sc_txtap_len = sizeof sc->sc_txtapu; 320 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 321 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 322 #endif 323 324 /* 325 * Add a few sysctl knobs. 326 * XXX: Not yet 327 */ 328 sc->dwelltime = 100; 329 330 if (pmf_device_register(self, NULL, NULL)) 331 pmf_class_network_register(self, ifp); 332 else 333 aprint_error_dev(self, "couldn't establish power handler\n"); 334 335 ieee80211_announce(ic); 336 337 return; 338 339 fail: ipw_detach(self, 0); 340 } 341 342 static int 343 ipw_detach(struct device* self, int flags) 344 { 345 struct ipw_softc *sc = device_private(self); 346 struct ifnet *ifp = &sc->sc_if; 347 348 if (ifp->if_softc) { 349 ipw_stop(ifp, 1); 350 ipw_free_firmware(sc); 351 352 #if NBPFILTER > 0 353 bpfdetach(ifp); 354 #endif 355 ieee80211_ifdetach(&sc->sc_ic); 356 if_detach(ifp); 357 358 ipw_release(sc); 359 } 360 361 if (sc->sc_ih != NULL) { 362 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 363 sc->sc_ih = NULL; 364 } 365 366 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 367 368 return 0; 369 } 370 371 static int 372 ipw_dma_alloc(struct ipw_softc *sc) 373 { 374 struct ipw_soft_bd *sbd; 375 struct ipw_soft_hdr *shdr; 376 struct ipw_soft_buf *sbuf; 377 int error, i, nsegs; 378 379 /* 380 * Allocate and map tx ring. 381 */ 382 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 383 BUS_DMA_NOWAIT, &sc->tbd_map); 384 if (error != 0) { 385 aprint_error_dev(&sc->sc_dev, "could not create tbd dma map\n"); 386 goto fail; 387 } 388 389 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 390 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 391 if (error != 0) { 392 aprint_error_dev(&sc->sc_dev, "could not allocate tbd dma memory\n"); 393 goto fail; 394 } 395 396 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 397 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 398 if (error != 0) { 399 aprint_error_dev(&sc->sc_dev, "could not map tbd dma memory\n"); 400 goto fail; 401 } 402 403 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 404 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 405 if (error != 0) { 406 aprint_error_dev(&sc->sc_dev, "could not load tbd dma memory\n"); 407 goto fail; 408 } 409 410 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 411 412 /* 413 * Allocate and map rx ring. 414 */ 415 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 416 BUS_DMA_NOWAIT, &sc->rbd_map); 417 if (error != 0) { 418 aprint_error_dev(&sc->sc_dev, "could not create rbd dma map\n"); 419 goto fail; 420 } 421 422 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 423 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 424 if (error != 0) { 425 aprint_error_dev(&sc->sc_dev, "could not allocate rbd dma memory\n"); 426 goto fail; 427 } 428 429 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 430 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 431 if (error != 0) { 432 aprint_error_dev(&sc->sc_dev, "could not map rbd dma memory\n"); 433 goto fail; 434 } 435 436 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 437 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 438 if (error != 0) { 439 aprint_error_dev(&sc->sc_dev, "could not load rbd dma memory\n"); 440 goto fail; 441 } 442 443 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 444 445 /* 446 * Allocate and map status ring. 447 */ 448 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 449 0, BUS_DMA_NOWAIT, &sc->status_map); 450 if (error != 0) { 451 aprint_error_dev(&sc->sc_dev, "could not create status dma map\n"); 452 goto fail; 453 } 454 455 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 456 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 457 if (error != 0) { 458 aprint_error_dev(&sc->sc_dev, "could not allocate status dma memory\n"); 459 goto fail; 460 } 461 462 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 463 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 464 if (error != 0) { 465 aprint_error_dev(&sc->sc_dev, "could not map status dma memory\n"); 466 goto fail; 467 } 468 469 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 470 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 471 if (error != 0) { 472 aprint_error_dev(&sc->sc_dev, "could not load status dma memory\n"); 473 goto fail; 474 } 475 476 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 477 478 /* 479 * Allocate command DMA map. 480 */ 481 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 482 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 483 if (error != 0) { 484 aprint_error_dev(&sc->sc_dev, "could not create cmd dma map\n"); 485 goto fail; 486 } 487 488 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 489 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 490 if (error != 0) { 491 aprint_error_dev(&sc->sc_dev, "could not allocate cmd dma memory\n"); 492 goto fail; 493 } 494 495 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 496 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 497 if (error != 0) { 498 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 499 goto fail; 500 } 501 502 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 503 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 504 if (error != 0) { 505 aprint_error_dev(&sc->sc_dev, "could not map cmd dma memory\n"); 506 return error; 507 } 508 509 /* 510 * Allocate and map hdr list. 511 */ 512 513 error = bus_dmamap_create(sc->sc_dmat, 514 IPW_NDATA * sizeof(struct ipw_hdr), 1, 515 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 516 &sc->hdr_map); 517 if (error != 0) { 518 aprint_error_dev(&sc->sc_dev, "could not create hdr dma map\n"); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(sc->sc_dmat, 523 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 524 1, &nsegs, BUS_DMA_NOWAIT); 525 if (error != 0) { 526 aprint_error_dev(&sc->sc_dev, "could not allocate hdr memory\n"); 527 goto fail; 528 } 529 530 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 531 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 532 BUS_DMA_NOWAIT); 533 if (error != 0) { 534 aprint_error_dev(&sc->sc_dev, "could not map hdr memory\n"); 535 goto fail; 536 } 537 538 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 539 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 540 if (error != 0) { 541 aprint_error_dev(&sc->sc_dev, "could not load hdr memory\n"); 542 goto fail; 543 } 544 545 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 546 547 /* 548 * Create DMA hdrs tailq. 549 */ 550 TAILQ_INIT(&sc->sc_free_shdr); 551 for (i = 0; i < IPW_NDATA; i++) { 552 shdr = &sc->shdr_list[i]; 553 shdr->hdr = sc->hdr_list + i; 554 shdr->offset = sizeof(struct ipw_hdr) * i; 555 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 556 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 557 } 558 559 /* 560 * Allocate tx buffers DMA maps. 561 */ 562 TAILQ_INIT(&sc->sc_free_sbuf); 563 for (i = 0; i < IPW_NDATA; i++) { 564 sbuf = &sc->tx_sbuf_list[i]; 565 566 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 567 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 568 if (error != 0) { 569 aprint_error_dev(&sc->sc_dev, "could not create txbuf dma map\n"); 570 goto fail; 571 } 572 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 573 } 574 575 /* 576 * Initialize tx ring. 577 */ 578 for (i = 0; i < IPW_NTBD; i++) { 579 sbd = &sc->stbd_list[i]; 580 sbd->bd = &sc->tbd_list[i]; 581 sbd->type = IPW_SBD_TYPE_NOASSOC; 582 } 583 584 /* 585 * Pre-allocate rx buffers and DMA maps 586 */ 587 for (i = 0; i < IPW_NRBD; i++) { 588 sbd = &sc->srbd_list[i]; 589 sbuf = &sc->rx_sbuf_list[i]; 590 sbd->bd = &sc->rbd_list[i]; 591 592 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 593 if (sbuf->m == NULL) { 594 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 595 error = ENOMEM; 596 goto fail; 597 } 598 599 MCLGET(sbuf->m, M_DONTWAIT); 600 if (!(sbuf->m->m_flags & M_EXT)) { 601 m_freem(sbuf->m); 602 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 603 error = ENOMEM; 604 goto fail; 605 } 606 607 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 608 609 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 610 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 611 if (error != 0) { 612 aprint_error_dev(&sc->sc_dev, "could not create rxbuf dma map\n"); 613 m_freem(sbuf->m); 614 goto fail; 615 } 616 617 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 618 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 619 if (error != 0) { 620 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 621 m_freem(sbuf->m); 622 aprint_error_dev(&sc->sc_dev, "could not map rxbuf dma memory\n"); 623 goto fail; 624 } 625 626 sbd->type = IPW_SBD_TYPE_DATA; 627 sbd->priv = sbuf; 628 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 629 sbd->bd->len = htole32(MCLBYTES); 630 631 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 632 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 633 634 } 635 636 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 637 BUS_DMASYNC_PREREAD); 638 639 return 0; 640 641 fail: ipw_release(sc); 642 return error; 643 } 644 645 static void 646 ipw_release(struct ipw_softc *sc) 647 { 648 struct ipw_soft_buf *sbuf; 649 int i; 650 651 if (sc->tbd_map != NULL) { 652 if (sc->tbd_list != NULL) { 653 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 654 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 655 IPW_TBD_SZ); 656 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 657 } 658 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 659 } 660 661 if (sc->rbd_map != NULL) { 662 if (sc->rbd_list != NULL) { 663 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 664 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 665 IPW_RBD_SZ); 666 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 667 } 668 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 669 } 670 671 if (sc->status_map != NULL) { 672 if (sc->status_list != NULL) { 673 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 674 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 675 IPW_RBD_SZ); 676 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 677 } 678 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 679 } 680 681 for (i = 0; i < IPW_NTBD; i++) 682 ipw_release_sbd(sc, &sc->stbd_list[i]); 683 684 if (sc->cmd_map != NULL) 685 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 686 687 if (sc->hdr_list != NULL) { 688 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 689 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 690 IPW_NDATA * sizeof(struct ipw_hdr)); 691 } 692 if (sc->hdr_map != NULL) { 693 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 694 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 695 } 696 697 for (i = 0; i < IPW_NDATA; i++) 698 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 699 700 for (i = 0; i < IPW_NRBD; i++) { 701 sbuf = &sc->rx_sbuf_list[i]; 702 if (sbuf->map != NULL) { 703 if (sbuf->m != NULL) { 704 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 705 m_freem(sbuf->m); 706 } 707 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 708 } 709 } 710 711 } 712 713 static int 714 ipw_media_change(struct ifnet *ifp) 715 { 716 int error; 717 718 error = ieee80211_media_change(ifp); 719 if (error != ENETRESET) 720 return error; 721 722 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 723 ipw_init(ifp); 724 725 return 0; 726 } 727 728 /* 729 * The firmware automatically adapts the transmit speed. We report the current 730 * transmit speed here. 731 */ 732 static void 733 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 734 { 735 #define N(a) (sizeof (a) / sizeof (a[0])) 736 struct ipw_softc *sc = ifp->if_softc; 737 struct ieee80211com *ic = &sc->sc_ic; 738 static const struct { 739 uint32_t val; 740 int rate; 741 } rates[] = { 742 { IPW_RATE_DS1, 2 }, 743 { IPW_RATE_DS2, 4 }, 744 { IPW_RATE_DS5, 11 }, 745 { IPW_RATE_DS11, 22 }, 746 }; 747 uint32_t val; 748 int rate, i; 749 750 imr->ifm_status = IFM_AVALID; 751 imr->ifm_active = IFM_IEEE80211; 752 if (ic->ic_state == IEEE80211_S_RUN) 753 imr->ifm_status |= IFM_ACTIVE; 754 755 /* read current transmission rate from adapter */ 756 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 757 758 /* convert ipw rate to 802.11 rate */ 759 for (i = 0; i < N(rates) && rates[i].val != val; i++); 760 rate = (i < N(rates)) ? rates[i].rate : 0; 761 762 imr->ifm_active |= IFM_IEEE80211_11B; 763 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 764 switch (ic->ic_opmode) { 765 case IEEE80211_M_STA: 766 break; 767 768 case IEEE80211_M_IBSS: 769 imr->ifm_active |= IFM_IEEE80211_ADHOC; 770 break; 771 772 case IEEE80211_M_MONITOR: 773 imr->ifm_active |= IFM_IEEE80211_MONITOR; 774 break; 775 776 case IEEE80211_M_AHDEMO: 777 case IEEE80211_M_HOSTAP: 778 /* should not get there */ 779 break; 780 } 781 #undef N 782 } 783 784 static int 785 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 786 int arg) 787 { 788 struct ifnet *ifp = ic->ic_ifp; 789 struct ipw_softc *sc = ifp->if_softc; 790 struct ieee80211_node *ni; 791 uint8_t macaddr[IEEE80211_ADDR_LEN]; 792 uint32_t len; 793 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 794 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 795 796 switch (nstate) { 797 case IEEE80211_S_INIT: 798 break; 799 default: 800 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 801 KASSERT(ic->ic_curchan != NULL); 802 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 803 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 804 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 805 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 806 break; 807 } 808 809 switch (nstate) { 810 case IEEE80211_S_RUN: 811 DELAY(200); /* firmware needs a short delay here */ 812 813 len = IEEE80211_ADDR_LEN; 814 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 815 816 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 817 if (ni == NULL) 818 break; 819 820 ieee80211_ref_node(ni); 821 ieee80211_sta_join(ic, ni); 822 ieee80211_node_authorize(ni); 823 824 if (ic->ic_opmode == IEEE80211_M_STA) 825 ieee80211_notify_node_join(ic, ni, 1); 826 break; 827 828 case IEEE80211_S_INIT: 829 case IEEE80211_S_SCAN: 830 case IEEE80211_S_AUTH: 831 case IEEE80211_S_ASSOC: 832 break; 833 } 834 835 ic->ic_state = nstate; 836 return 0; 837 } 838 839 /* 840 * Read 16 bits at address 'addr' from the serial EEPROM. 841 */ 842 static uint16_t 843 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 844 { 845 uint32_t tmp; 846 uint16_t val; 847 int n; 848 849 /* clock C once before the first command */ 850 IPW_EEPROM_CTL(sc, 0); 851 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 852 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 854 855 /* write start bit (1) */ 856 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 858 859 /* write READ opcode (10) */ 860 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 864 865 /* write address A7-A0 */ 866 for (n = 7; n >= 0; n--) { 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 868 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 870 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 871 } 872 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 874 875 /* read data Q15-Q0 */ 876 val = 0; 877 for (n = 15; n >= 0; n--) { 878 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 880 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 881 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 882 } 883 884 IPW_EEPROM_CTL(sc, 0); 885 886 /* clear Chip Select and clock C */ 887 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 888 IPW_EEPROM_CTL(sc, 0); 889 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 890 891 return le16toh(val); 892 } 893 894 static void 895 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 896 { 897 struct ipw_cmd *cmd; 898 899 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 900 BUS_DMASYNC_POSTREAD); 901 902 cmd = mtod(sbuf->m, struct ipw_cmd *); 903 904 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 905 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 906 le32toh(cmd->status))); 907 908 wakeup(&sc->cmd); 909 } 910 911 static void 912 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 913 { 914 struct ieee80211com *ic = &sc->sc_ic; 915 struct ifnet *ifp = sc->sc_ic.ic_ifp; 916 uint32_t state; 917 918 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 919 BUS_DMASYNC_POSTREAD); 920 921 state = le32toh(*mtod(sbuf->m, uint32_t *)); 922 923 DPRINTFN(2, ("entering state %u\n", state)); 924 925 switch (state) { 926 case IPW_STATE_ASSOCIATED: 927 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 928 break; 929 930 case IPW_STATE_SCANNING: 931 /* don't leave run state on background scan */ 932 if (ic->ic_state != IEEE80211_S_RUN) 933 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 934 935 ic->ic_flags |= IEEE80211_F_SCAN; 936 break; 937 938 case IPW_STATE_SCAN_COMPLETE: 939 ieee80211_notify_scan_done(ic); 940 ic->ic_flags &= ~IEEE80211_F_SCAN; 941 break; 942 943 case IPW_STATE_ASSOCIATION_LOST: 944 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 945 break; 946 947 case IPW_STATE_RADIO_DISABLED: 948 ic->ic_ifp->if_flags &= ~IFF_UP; 949 ipw_stop(ifp, 1); 950 break; 951 } 952 } 953 954 /* 955 * XXX: Hack to set the current channel to the value advertised in beacons or 956 * probe responses. Only used during AP detection. 957 */ 958 static void 959 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 960 { 961 struct ieee80211_frame *wh; 962 uint8_t subtype; 963 uint8_t *frm, *efrm; 964 965 wh = mtod(m, struct ieee80211_frame *); 966 967 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 968 return; 969 970 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 971 972 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 973 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 974 return; 975 976 frm = (uint8_t *)(wh + 1); 977 efrm = mtod(m, uint8_t *) + m->m_len; 978 979 frm += 12; /* skip tstamp, bintval and capinfo fields */ 980 while (frm < efrm) { 981 if (*frm == IEEE80211_ELEMID_DSPARMS) 982 #if IEEE80211_CHAN_MAX < 255 983 if (frm[2] <= IEEE80211_CHAN_MAX) 984 #endif 985 ic->ic_curchan = &ic->ic_channels[frm[2]]; 986 987 frm += frm[1] + 2; 988 } 989 } 990 991 static void 992 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 993 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 994 { 995 struct ieee80211com *ic = &sc->sc_ic; 996 struct ifnet *ifp = &sc->sc_if; 997 struct mbuf *mnew, *m; 998 struct ieee80211_frame *wh; 999 struct ieee80211_node *ni; 1000 int error; 1001 1002 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1003 status->rssi)); 1004 1005 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1006 le32toh(status->len) > MCLBYTES) 1007 return; 1008 1009 /* 1010 * Try to allocate a new mbuf for this ring element and load it before 1011 * processing the current mbuf. If the ring element cannot be loaded, 1012 * drop the received packet and reuse the old mbuf. In the unlikely 1013 * case that the old mbuf can't be reloaded either, explicitly panic. 1014 */ 1015 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1016 if (mnew == NULL) { 1017 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf\n"); 1018 ifp->if_ierrors++; 1019 return; 1020 } 1021 1022 MCLGET(mnew, M_DONTWAIT); 1023 if (!(mnew->m_flags & M_EXT)) { 1024 aprint_error_dev(&sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1025 m_freem(mnew); 1026 ifp->if_ierrors++; 1027 return; 1028 } 1029 1030 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1031 1032 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1033 BUS_DMASYNC_POSTREAD); 1034 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1035 1036 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1037 BUS_DMA_READ | BUS_DMA_NOWAIT); 1038 if (error != 0) { 1039 aprint_error_dev(&sc->sc_dev, "could not load rx buf DMA map\n"); 1040 m_freem(mnew); 1041 1042 /* try to reload the old mbuf */ 1043 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1044 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1045 if (error != 0) { 1046 /* very unlikely that it will fail... */ 1047 panic("%s: unable to remap rx buf", 1048 device_xname(&sc->sc_dev)); 1049 } 1050 ifp->if_ierrors++; 1051 return; 1052 } 1053 1054 /* 1055 * New mbuf successfully loaded, update Rx ring and continue 1056 * processing. 1057 */ 1058 m = sbuf->m; 1059 sbuf->m = mnew; 1060 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1061 1062 /* finalize mbuf */ 1063 m->m_pkthdr.rcvif = ifp; 1064 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1065 1066 #if NBPFILTER > 0 1067 if (sc->sc_drvbpf != NULL) { 1068 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1069 1070 tap->wr_antsignal = status->rssi; 1071 1072 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1073 } 1074 #endif 1075 1076 if (ic->ic_state == IEEE80211_S_SCAN) 1077 ipw_fix_channel(ic, m); 1078 1079 wh = mtod(m, struct ieee80211_frame *); 1080 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1081 1082 /* send the frame to the 802.11 layer */ 1083 ieee80211_input(ic, m, ni, status->rssi, 0); 1084 1085 /* node is no longer needed */ 1086 ieee80211_free_node(ni); 1087 1088 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1089 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1090 } 1091 1092 static void 1093 ipw_rx_intr(struct ipw_softc *sc) 1094 { 1095 struct ipw_status *status; 1096 struct ipw_soft_bd *sbd; 1097 struct ipw_soft_buf *sbuf; 1098 uint32_t r, i; 1099 1100 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1101 return; 1102 1103 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1104 1105 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1106 1107 /* firmware was killed, stop processing received frames */ 1108 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1109 return; 1110 1111 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1112 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1113 BUS_DMASYNC_POSTREAD); 1114 1115 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1116 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1117 BUS_DMASYNC_POSTREAD); 1118 1119 status = &sc->status_list[i]; 1120 sbd = &sc->srbd_list[i]; 1121 sbuf = sbd->priv; 1122 1123 switch (le16toh(status->code) & 0xf) { 1124 case IPW_STATUS_CODE_COMMAND: 1125 ipw_command_intr(sc, sbuf); 1126 break; 1127 1128 case IPW_STATUS_CODE_NEWSTATE: 1129 ipw_newstate_intr(sc, sbuf); 1130 break; 1131 1132 case IPW_STATUS_CODE_DATA_802_3: 1133 case IPW_STATUS_CODE_DATA_802_11: 1134 ipw_data_intr(sc, status, sbd, sbuf); 1135 break; 1136 1137 case IPW_STATUS_CODE_NOTIFICATION: 1138 DPRINTFN(2, ("received notification\n")); 1139 break; 1140 1141 default: 1142 aprint_error_dev(&sc->sc_dev, "unknown status code %u\n", 1143 le16toh(status->code)); 1144 } 1145 1146 sbd->bd->flags = 0; 1147 1148 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1149 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1150 BUS_DMASYNC_PREREAD); 1151 1152 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1153 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1154 BUS_DMASYNC_PREREAD); 1155 } 1156 1157 /* Tell the firmware what we have processed */ 1158 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1159 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1160 } 1161 1162 static void 1163 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1164 { 1165 struct ieee80211com *ic; 1166 struct ipw_soft_hdr *shdr; 1167 struct ipw_soft_buf *sbuf; 1168 1169 switch (sbd->type) { 1170 case IPW_SBD_TYPE_COMMAND: 1171 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1172 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1173 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1174 break; 1175 1176 case IPW_SBD_TYPE_HEADER: 1177 shdr = sbd->priv; 1178 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1179 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1180 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1181 break; 1182 1183 case IPW_SBD_TYPE_DATA: 1184 ic = &sc->sc_ic; 1185 sbuf = sbd->priv; 1186 1187 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1188 0, MCLBYTES, BUS_DMASYNC_POSTWRITE); 1189 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1190 m_freem(sbuf->m); 1191 if (sbuf->ni != NULL) 1192 ieee80211_free_node(sbuf->ni); 1193 /* kill watchdog timer */ 1194 sc->sc_tx_timer = 0; 1195 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1196 break; 1197 } 1198 sbd->type = IPW_SBD_TYPE_NOASSOC; 1199 } 1200 1201 static void 1202 ipw_tx_intr(struct ipw_softc *sc) 1203 { 1204 struct ifnet *ifp = &sc->sc_if; 1205 struct ipw_soft_bd *sbd; 1206 uint32_t r, i; 1207 1208 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1209 return; 1210 1211 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1212 1213 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1214 sbd = &sc->stbd_list[i]; 1215 1216 if (sbd->type == IPW_SBD_TYPE_DATA) 1217 ifp->if_opackets++; 1218 1219 ipw_release_sbd(sc, sbd); 1220 sc->txfree++; 1221 } 1222 1223 /* remember what the firmware has processed */ 1224 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1225 1226 /* Call start() since some buffer descriptors have been released */ 1227 ifp->if_flags &= ~IFF_OACTIVE; 1228 (*ifp->if_start)(ifp); 1229 } 1230 1231 static int 1232 ipw_intr(void *arg) 1233 { 1234 struct ipw_softc *sc = arg; 1235 uint32_t r; 1236 1237 r = CSR_READ_4(sc, IPW_CSR_INTR); 1238 if (r == 0 || r == 0xffffffff) 1239 return 0; 1240 1241 /* Disable interrupts */ 1242 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1243 1244 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1245 aprint_error_dev(&sc->sc_dev, "fatal error\n"); 1246 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1247 ipw_stop(&sc->sc_if, 1); 1248 } 1249 1250 if (r & IPW_INTR_FW_INIT_DONE) { 1251 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1252 wakeup(sc); 1253 } 1254 1255 if (r & IPW_INTR_RX_TRANSFER) 1256 ipw_rx_intr(sc); 1257 1258 if (r & IPW_INTR_TX_TRANSFER) 1259 ipw_tx_intr(sc); 1260 1261 /* Acknowledge all interrupts */ 1262 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1263 1264 /* Re-enable interrupts */ 1265 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1266 1267 return 0; 1268 } 1269 1270 /* 1271 * Send a command to the firmware and wait for the acknowledgement. 1272 */ 1273 static int 1274 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1275 { 1276 struct ipw_soft_bd *sbd; 1277 1278 sbd = &sc->stbd_list[sc->txcur]; 1279 1280 sc->cmd.type = htole32(type); 1281 sc->cmd.subtype = 0; 1282 sc->cmd.len = htole32(len); 1283 sc->cmd.seq = 0; 1284 1285 (void)memcpy(sc->cmd.data, data, len); 1286 1287 sbd->type = IPW_SBD_TYPE_COMMAND; 1288 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1289 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1290 sbd->bd->nfrag = 1; 1291 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1292 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1293 1294 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1295 BUS_DMASYNC_PREWRITE); 1296 1297 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1298 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1299 BUS_DMASYNC_PREWRITE); 1300 1301 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1302 1303 /* kick firmware */ 1304 sc->txfree--; 1305 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1306 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1307 1308 /* Wait at most one second for command to complete */ 1309 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1310 } 1311 1312 static int 1313 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1314 { 1315 struct ipw_softc *sc = ifp->if_softc; 1316 struct ieee80211com *ic = &sc->sc_ic; 1317 struct ieee80211_frame *wh; 1318 struct ipw_soft_bd *sbd; 1319 struct ipw_soft_hdr *shdr; 1320 struct ipw_soft_buf *sbuf; 1321 struct ieee80211_key *k; 1322 struct mbuf *mnew; 1323 int error, i; 1324 1325 wh = mtod(m0, struct ieee80211_frame *); 1326 1327 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1328 k = ieee80211_crypto_encap(ic, ni, m0); 1329 if (k == NULL) { 1330 m_freem(m0); 1331 return ENOBUFS; 1332 } 1333 1334 /* packet header may have moved, reset our local pointer */ 1335 wh = mtod(m0, struct ieee80211_frame *); 1336 } 1337 1338 #if NBPFILTER > 0 1339 if (sc->sc_drvbpf != NULL) { 1340 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1341 1342 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1343 } 1344 #endif 1345 1346 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1347 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1348 KASSERT(shdr != NULL && sbuf != NULL); 1349 1350 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1351 shdr->hdr->subtype = 0; 1352 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1353 shdr->hdr->encrypt = 0; 1354 shdr->hdr->keyidx = 0; 1355 shdr->hdr->keysz = 0; 1356 shdr->hdr->fragmentsz = 0; 1357 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1358 if (ic->ic_opmode == IEEE80211_M_STA) 1359 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1360 else 1361 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1362 1363 /* trim IEEE802.11 header */ 1364 m_adj(m0, sizeof (struct ieee80211_frame)); 1365 1366 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT); 1367 if (error != 0 && error != EFBIG) { 1368 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", 1369 error); 1370 m_freem(m0); 1371 return error; 1372 } 1373 1374 if (error != 0) { 1375 /* too many fragments, linearize */ 1376 1377 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1378 if (mnew == NULL) { 1379 m_freem(m0); 1380 return ENOMEM; 1381 } 1382 1383 M_COPY_PKTHDR(mnew, m0); 1384 1385 /* If the data won't fit in the header, get a cluster */ 1386 if (m0->m_pkthdr.len > MHLEN) { 1387 MCLGET(mnew, M_DONTWAIT); 1388 if (!(mnew->m_flags & M_EXT)) { 1389 m_freem(m0); 1390 m_freem(mnew); 1391 return ENOMEM; 1392 } 1393 } 1394 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1395 m_freem(m0); 1396 mnew->m_len = mnew->m_pkthdr.len; 1397 m0 = mnew; 1398 1399 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1400 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1401 if (error != 0) { 1402 aprint_error_dev(&sc->sc_dev, "could not map mbuf (error %d)\n", error); 1403 m_freem(m0); 1404 return error; 1405 } 1406 } 1407 1408 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1409 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1410 1411 sbd = &sc->stbd_list[sc->txcur]; 1412 sbd->type = IPW_SBD_TYPE_HEADER; 1413 sbd->priv = shdr; 1414 sbd->bd->physaddr = htole32(shdr->addr); 1415 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1416 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1417 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1418 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1419 1420 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1421 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1422 shdr->hdr->encrypt)); 1423 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1424 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1425 1426 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1427 sc->txcur * sizeof (struct ipw_bd), 1428 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1429 1430 sc->txfree--; 1431 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1432 1433 sbuf->m = m0; 1434 sbuf->ni = ni; 1435 1436 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1437 sbd = &sc->stbd_list[sc->txcur]; 1438 1439 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1440 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1441 sbd->bd->nfrag = 0; 1442 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1443 if (i == sbuf->map->dm_nsegs - 1) { 1444 sbd->type = IPW_SBD_TYPE_DATA; 1445 sbd->priv = sbuf; 1446 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1447 } else { 1448 sbd->type = IPW_SBD_TYPE_NOASSOC; 1449 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1450 } 1451 1452 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1453 (int)sbuf->map->dm_segs[i].ds_len)); 1454 1455 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1456 sc->txcur * sizeof (struct ipw_bd), 1457 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1458 1459 sc->txfree--; 1460 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1461 } 1462 1463 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1464 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1465 1466 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES, 1467 BUS_DMASYNC_PREWRITE); 1468 1469 /* Inform firmware about this new packet */ 1470 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1471 1472 return 0; 1473 } 1474 1475 static void 1476 ipw_start(struct ifnet *ifp) 1477 { 1478 struct ipw_softc *sc = ifp->if_softc; 1479 struct ieee80211com *ic = &sc->sc_ic; 1480 struct mbuf *m0; 1481 struct ether_header *eh; 1482 struct ieee80211_node *ni; 1483 1484 1485 if (ic->ic_state != IEEE80211_S_RUN) 1486 return; 1487 1488 for (;;) { 1489 IF_DEQUEUE(&ifp->if_snd, m0); 1490 if (m0 == NULL) 1491 break; 1492 1493 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1494 IF_PREPEND(&ifp->if_snd, m0); 1495 ifp->if_flags |= IFF_OACTIVE; 1496 break; 1497 } 1498 1499 if (m0->m_len < sizeof (struct ether_header) && 1500 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1501 continue; 1502 1503 eh = mtod(m0, struct ether_header *); 1504 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1505 if (ni == NULL) { 1506 m_freem(m0); 1507 continue; 1508 } 1509 1510 #if NBPFILTER > 0 1511 if (ifp->if_bpf != NULL) 1512 bpf_mtap(ifp->if_bpf, m0); 1513 #endif 1514 1515 m0 = ieee80211_encap(ic, m0, ni); 1516 if (m0 == NULL) { 1517 ieee80211_free_node(ni); 1518 continue; 1519 } 1520 1521 #if NBPFILTER > 0 1522 if (ic->ic_rawbpf != NULL) 1523 bpf_mtap(ic->ic_rawbpf, m0); 1524 #endif 1525 1526 if (ipw_tx_start(ifp, m0, ni) != 0) { 1527 ieee80211_free_node(ni); 1528 ifp->if_oerrors++; 1529 break; 1530 } 1531 1532 /* start watchdog timer */ 1533 sc->sc_tx_timer = 5; 1534 ifp->if_timer = 1; 1535 } 1536 } 1537 1538 static void 1539 ipw_watchdog(struct ifnet *ifp) 1540 { 1541 struct ipw_softc *sc = ifp->if_softc; 1542 1543 ifp->if_timer = 0; 1544 1545 if (sc->sc_tx_timer > 0) { 1546 if (--sc->sc_tx_timer == 0) { 1547 aprint_error_dev(&sc->sc_dev, "device timeout\n"); 1548 ifp->if_oerrors++; 1549 ifp->if_flags &= ~IFF_UP; 1550 ipw_stop(ifp, 1); 1551 return; 1552 } 1553 ifp->if_timer = 1; 1554 } 1555 1556 ieee80211_watchdog(&sc->sc_ic); 1557 } 1558 1559 static int 1560 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1561 { 1562 uint32_t addr, size, i; 1563 1564 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1565 return ENOTTY; 1566 1567 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1568 1569 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1570 if (suword(tbl, size) != 0) 1571 return EFAULT; 1572 1573 for (i = 1, ++tbl; i < size; i++, tbl++) { 1574 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1575 if (suword(tbl, MEM_READ_4(sc, addr)) != 0) 1576 return EFAULT; 1577 } 1578 return 0; 1579 } 1580 1581 static int 1582 ipw_get_radio(struct ipw_softc *sc, int *ret) 1583 { 1584 uint32_t addr; 1585 1586 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1587 return ENOTTY; 1588 1589 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1590 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) { 1591 suword(ret, -1); 1592 return 0; 1593 } 1594 1595 if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1596 suword(ret, 0); 1597 else 1598 suword(ret, 1); 1599 1600 return 0; 1601 } 1602 1603 static int 1604 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1605 { 1606 #define IS_RUNNING(ifp) \ 1607 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1608 1609 struct ipw_softc *sc = ifp->if_softc; 1610 struct ieee80211com *ic = &sc->sc_ic; 1611 struct ifreq *ifr = (struct ifreq *)data; 1612 int s, error = 0; 1613 1614 s = splnet(); 1615 1616 switch (cmd) { 1617 case SIOCSIFFLAGS: 1618 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1619 break; 1620 if (ifp->if_flags & IFF_UP) { 1621 if (!(ifp->if_flags & IFF_RUNNING)) 1622 ipw_init(ifp); 1623 } else { 1624 if (ifp->if_flags & IFF_RUNNING) 1625 ipw_stop(ifp, 1); 1626 } 1627 break; 1628 1629 case SIOCADDMULTI: 1630 case SIOCDELMULTI: 1631 /* XXX no h/w multicast filter? --dyoung */ 1632 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1633 /* setup multicast filter, etc */ 1634 error = 0; 1635 } 1636 break; 1637 1638 case SIOCGTABLE1: 1639 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1640 break; 1641 1642 case SIOCGRADIO: 1643 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1644 break; 1645 1646 case SIOCSIFMEDIA: 1647 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1648 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1649 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1650 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1651 else 1652 sc->sc_fwname = "ipw2100-1.2.fw"; 1653 1654 ipw_free_firmware(sc); 1655 /* FALLTRHOUGH */ 1656 default: 1657 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1658 if (error != ENETRESET) 1659 break; 1660 1661 if (error == ENETRESET) { 1662 if (IS_RUNNING(ifp) && 1663 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1664 ipw_init(ifp); 1665 error = 0; 1666 } 1667 1668 } 1669 1670 splx(s); 1671 return error; 1672 #undef IS_RUNNING 1673 } 1674 1675 static uint32_t 1676 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1677 { 1678 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1679 } 1680 1681 static void 1682 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1683 { 1684 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1685 } 1686 1687 static int 1688 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1689 { 1690 uint32_t addr, info; 1691 uint16_t count, size; 1692 uint32_t total; 1693 1694 /* addr[4] + count[2] + size[2] */ 1695 addr = MEM_READ_4(sc, sc->table2_base + off); 1696 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1697 1698 count = info >> 16; 1699 size = info & 0xffff; 1700 total = count * size; 1701 1702 if (total > *len) { 1703 *len = total; 1704 return EINVAL; 1705 } 1706 1707 *len = total; 1708 ipw_read_mem_1(sc, addr, buf, total); 1709 1710 return 0; 1711 } 1712 1713 static void 1714 ipw_stop_master(struct ipw_softc *sc) 1715 { 1716 int ntries; 1717 1718 /* disable interrupts */ 1719 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1720 1721 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1722 for (ntries = 0; ntries < 50; ntries++) { 1723 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1724 break; 1725 DELAY(10); 1726 } 1727 if (ntries == 50) 1728 aprint_error_dev(&sc->sc_dev, "timeout waiting for master\n"); 1729 1730 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1731 IPW_RST_PRINCETON_RESET); 1732 1733 sc->flags &= ~IPW_FLAG_FW_INITED; 1734 } 1735 1736 static int 1737 ipw_reset(struct ipw_softc *sc) 1738 { 1739 int ntries; 1740 1741 ipw_stop_master(sc); 1742 1743 /* move adapter to D0 state */ 1744 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1745 IPW_CTL_INIT); 1746 1747 /* wait for clock stabilization */ 1748 for (ntries = 0; ntries < 1000; ntries++) { 1749 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1750 break; 1751 DELAY(200); 1752 } 1753 if (ntries == 1000) 1754 return EIO; 1755 1756 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1757 IPW_RST_SW_RESET); 1758 1759 DELAY(10); 1760 1761 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1762 IPW_CTL_INIT); 1763 1764 return 0; 1765 } 1766 1767 /* 1768 * Upload the microcode to the device. 1769 */ 1770 static int 1771 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1772 { 1773 int ntries; 1774 1775 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1776 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1777 1778 MEM_WRITE_2(sc, 0x220000, 0x0703); 1779 MEM_WRITE_2(sc, 0x220000, 0x0707); 1780 1781 MEM_WRITE_1(sc, 0x210014, 0x72); 1782 MEM_WRITE_1(sc, 0x210014, 0x72); 1783 1784 MEM_WRITE_1(sc, 0x210000, 0x40); 1785 MEM_WRITE_1(sc, 0x210000, 0x00); 1786 MEM_WRITE_1(sc, 0x210000, 0x40); 1787 1788 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1789 1790 MEM_WRITE_1(sc, 0x210000, 0x00); 1791 MEM_WRITE_1(sc, 0x210000, 0x00); 1792 MEM_WRITE_1(sc, 0x210000, 0x80); 1793 1794 MEM_WRITE_2(sc, 0x220000, 0x0703); 1795 MEM_WRITE_2(sc, 0x220000, 0x0707); 1796 1797 MEM_WRITE_1(sc, 0x210014, 0x72); 1798 MEM_WRITE_1(sc, 0x210014, 0x72); 1799 1800 MEM_WRITE_1(sc, 0x210000, 0x00); 1801 MEM_WRITE_1(sc, 0x210000, 0x80); 1802 1803 for (ntries = 0; ntries < 10; ntries++) { 1804 if (MEM_READ_1(sc, 0x210000) & 1) 1805 break; 1806 DELAY(10); 1807 } 1808 if (ntries == 10) { 1809 aprint_error_dev(&sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1810 return EIO; 1811 } 1812 1813 MEM_WRITE_4(sc, 0x3000e0, 0); 1814 1815 return 0; 1816 } 1817 1818 /* set of macros to handle unaligned little endian data in firmware image */ 1819 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1820 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1821 static int 1822 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1823 { 1824 u_char *p, *end; 1825 uint32_t dst; 1826 uint16_t len; 1827 int error; 1828 1829 p = fw; 1830 end = fw + size; 1831 while (p < end) { 1832 dst = GETLE32(p); p += 4; 1833 len = GETLE16(p); p += 2; 1834 1835 ipw_write_mem_1(sc, dst, p, len); 1836 p += len; 1837 } 1838 1839 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1840 IPW_IO_LED_OFF); 1841 1842 /* enable interrupts */ 1843 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1844 1845 /* kick the firmware */ 1846 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1847 1848 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1849 IPW_CTL_ALLOW_STANDBY); 1850 1851 /* wait at most one second for firmware initialization to complete */ 1852 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1853 aprint_error_dev(&sc->sc_dev, "timeout waiting for firmware initialization " 1854 "to complete\n"); 1855 return error; 1856 } 1857 1858 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1859 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1860 1861 return 0; 1862 } 1863 1864 /* 1865 * Store firmware into kernel memory so we can download it when we need to, 1866 * e.g when the adapter wakes up from suspend mode. 1867 */ 1868 static int 1869 ipw_cache_firmware(struct ipw_softc *sc) 1870 { 1871 struct ipw_firmware *fw = &sc->fw; 1872 struct ipw_firmware_hdr hdr; 1873 firmware_handle_t fwh; 1874 off_t fwsz, p; 1875 int error; 1876 1877 ipw_free_firmware(sc); 1878 1879 if (ipw_accept_eula == 0) { 1880 aprint_error_dev(&sc->sc_dev, 1881 "EULA not accepted; please see the ipw(4) man page.\n"); 1882 return EPERM; 1883 } 1884 1885 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1886 goto fail0; 1887 1888 fwsz = firmware_get_size(fwh); 1889 1890 if (fwsz < sizeof(hdr)) 1891 goto fail2; 1892 1893 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1894 goto fail2; 1895 1896 fw->main_size = le32toh(hdr.main_size); 1897 fw->ucode_size = le32toh(hdr.ucode_size); 1898 1899 fw->main = firmware_malloc(fw->main_size); 1900 if (fw->main == NULL) { 1901 error = ENOMEM; 1902 goto fail1; 1903 } 1904 1905 fw->ucode = firmware_malloc(fw->ucode_size); 1906 if (fw->ucode == NULL) { 1907 error = ENOMEM; 1908 goto fail2; 1909 } 1910 1911 p = sizeof(hdr); 1912 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1913 goto fail3; 1914 1915 p += fw->main_size; 1916 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1917 goto fail3; 1918 1919 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1920 fw->ucode_size)); 1921 1922 sc->flags |= IPW_FLAG_FW_CACHED; 1923 1924 firmware_close(fwh); 1925 1926 return 0; 1927 1928 fail3: firmware_free(fw->ucode, 0); 1929 fail2: firmware_free(fw->main, 0); 1930 fail1: firmware_close(fwh); 1931 fail0: 1932 return error; 1933 } 1934 1935 static void 1936 ipw_free_firmware(struct ipw_softc *sc) 1937 { 1938 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1939 return; 1940 1941 firmware_free(sc->fw.main, 0); 1942 firmware_free(sc->fw.ucode, 0); 1943 1944 sc->flags &= ~IPW_FLAG_FW_CACHED; 1945 } 1946 1947 static int 1948 ipw_config(struct ipw_softc *sc) 1949 { 1950 struct ieee80211com *ic = &sc->sc_ic; 1951 struct ifnet *ifp = &sc->sc_if; 1952 struct ipw_security security; 1953 struct ieee80211_key *k; 1954 struct ipw_wep_key wepkey; 1955 struct ipw_scan_options options; 1956 struct ipw_configuration config; 1957 uint32_t data; 1958 int error, i; 1959 1960 switch (ic->ic_opmode) { 1961 case IEEE80211_M_STA: 1962 case IEEE80211_M_HOSTAP: 1963 data = htole32(IPW_MODE_BSS); 1964 break; 1965 1966 case IEEE80211_M_IBSS: 1967 case IEEE80211_M_AHDEMO: 1968 data = htole32(IPW_MODE_IBSS); 1969 break; 1970 1971 case IEEE80211_M_MONITOR: 1972 data = htole32(IPW_MODE_MONITOR); 1973 break; 1974 } 1975 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1976 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1977 if (error != 0) 1978 return error; 1979 1980 if (ic->ic_opmode == IEEE80211_M_IBSS || 1981 ic->ic_opmode == IEEE80211_M_MONITOR) { 1982 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1983 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1984 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1985 if (error != 0) 1986 return error; 1987 } 1988 1989 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1990 DPRINTF(("Enabling adapter\n")); 1991 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1992 } 1993 1994 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 1995 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1996 IEEE80211_ADDR_LEN); 1997 if (error != 0) 1998 return error; 1999 2000 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2001 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2002 2003 if (ic->ic_opmode == IEEE80211_M_IBSS) 2004 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2005 if (ifp->if_flags & IFF_PROMISC) 2006 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2007 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2008 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2009 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2010 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2011 if (error != 0) 2012 return error; 2013 2014 data = htole32(0x3); /* 1, 2 */ 2015 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2016 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2017 if (error != 0) 2018 return error; 2019 2020 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2021 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2022 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2023 if (error != 0) 2024 return error; 2025 2026 data = htole32(IPW_POWER_MODE_CAM); 2027 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2028 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2029 if (error != 0) 2030 return error; 2031 2032 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2033 data = htole32(32); /* default value */ 2034 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2035 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2036 sizeof data); 2037 if (error != 0) 2038 return error; 2039 } 2040 2041 data = htole32(ic->ic_rtsthreshold); 2042 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2043 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2044 if (error != 0) 2045 return error; 2046 2047 data = htole32(ic->ic_fragthreshold); 2048 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2049 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2050 if (error != 0) 2051 return error; 2052 2053 #ifdef IPW_DEBUG 2054 if (ipw_debug > 0) { 2055 printf("Setting ESSID to "); 2056 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2057 printf("\n"); 2058 } 2059 #endif 2060 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2061 ic->ic_des_esslen); 2062 if (error != 0) 2063 return error; 2064 2065 /* no mandatory BSSID */ 2066 DPRINTF(("Setting mandatory BSSID to null\n")); 2067 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2068 if (error != 0) 2069 return error; 2070 2071 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2072 DPRINTF(("Setting desired BSSID to %s\n", 2073 ether_sprintf(ic->ic_des_bssid))); 2074 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2075 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2076 if (error != 0) 2077 return error; 2078 } 2079 2080 (void)memset(&security, 0, sizeof(security)); 2081 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2082 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2083 security.ciphers = htole32(IPW_CIPHER_NONE); 2084 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2085 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2086 sizeof security); 2087 if (error != 0) 2088 return error; 2089 2090 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2091 k = ic->ic_crypto.cs_nw_keys; 2092 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2093 if (k->wk_keylen == 0) 2094 continue; 2095 2096 wepkey.idx = i; 2097 wepkey.len = k->wk_keylen; 2098 memset(wepkey.key, 0, sizeof(wepkey.key)); 2099 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2100 DPRINTF(("Setting wep key index %u len %u\n", 2101 wepkey.idx, wepkey.len)); 2102 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2103 sizeof wepkey); 2104 if (error != 0) 2105 return error; 2106 } 2107 2108 data = htole32(ic->ic_crypto.cs_def_txkey); 2109 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2110 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2111 sizeof data); 2112 if (error != 0) 2113 return error; 2114 } 2115 2116 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2117 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2118 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2119 if (error != 0) 2120 return error; 2121 2122 #if 0 2123 struct ipw_wpa_ie ie; 2124 2125 memset(&ie, 0 sizeof(ie)); 2126 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2127 DPRINTF(("Setting wpa ie\n")); 2128 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2129 if (error != 0) 2130 return error; 2131 #endif 2132 2133 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2134 data = htole32(ic->ic_bintval); 2135 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2136 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2137 sizeof data); 2138 if (error != 0) 2139 return error; 2140 } 2141 2142 options.flags = 0; 2143 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2144 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2145 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2146 if (error != 0) 2147 return error; 2148 2149 /* finally, enable adapter (start scanning for an access point) */ 2150 DPRINTF(("Enabling adapter\n")); 2151 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2152 } 2153 2154 static int 2155 ipw_init(struct ifnet *ifp) 2156 { 2157 struct ipw_softc *sc = ifp->if_softc; 2158 struct ipw_firmware *fw = &sc->fw; 2159 2160 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2161 if (ipw_cache_firmware(sc) != 0) { 2162 aprint_error_dev(&sc->sc_dev, "could not cache the firmware (%s)\n", 2163 sc->sc_fwname); 2164 goto fail; 2165 } 2166 } 2167 2168 ipw_stop(ifp, 0); 2169 2170 if (ipw_reset(sc) != 0) { 2171 aprint_error_dev(&sc->sc_dev, "could not reset adapter\n"); 2172 goto fail; 2173 } 2174 2175 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2176 aprint_error_dev(&sc->sc_dev, "could not load microcode\n"); 2177 goto fail; 2178 } 2179 2180 ipw_stop_master(sc); 2181 2182 /* 2183 * Setup tx, rx and status rings. 2184 */ 2185 sc->txold = IPW_NTBD - 1; 2186 sc->txcur = 0; 2187 sc->txfree = IPW_NTBD - 2; 2188 sc->rxcur = IPW_NRBD - 1; 2189 2190 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2191 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2192 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2193 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2194 2195 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2196 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2197 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2198 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2199 2200 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2201 2202 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2203 aprint_error_dev(&sc->sc_dev, "could not load firmware\n"); 2204 goto fail; 2205 } 2206 2207 sc->flags |= IPW_FLAG_FW_INITED; 2208 2209 /* retrieve information tables base addresses */ 2210 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2211 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2212 2213 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2214 2215 if (ipw_config(sc) != 0) { 2216 aprint_error_dev(&sc->sc_dev, "device configuration failed\n"); 2217 goto fail; 2218 } 2219 2220 ifp->if_flags &= ~IFF_OACTIVE; 2221 ifp->if_flags |= IFF_RUNNING; 2222 2223 return 0; 2224 2225 fail: ifp->if_flags &= ~IFF_UP; 2226 ipw_stop(ifp, 0); 2227 2228 return EIO; 2229 } 2230 2231 static void 2232 ipw_stop(struct ifnet *ifp, int disable) 2233 { 2234 struct ipw_softc *sc = ifp->if_softc; 2235 struct ieee80211com *ic = &sc->sc_ic; 2236 int i; 2237 2238 ipw_stop_master(sc); 2239 2240 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2241 2242 /* 2243 * Release tx buffers. 2244 */ 2245 for (i = 0; i < IPW_NTBD; i++) 2246 ipw_release_sbd(sc, &sc->stbd_list[i]); 2247 2248 sc->sc_tx_timer = 0; 2249 ifp->if_timer = 0; 2250 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2251 2252 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2253 } 2254 2255 static void 2256 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2257 bus_size_t count) 2258 { 2259 for (; count > 0; offset++, datap++, count--) { 2260 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2261 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2262 } 2263 } 2264 2265 static void 2266 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2267 bus_size_t count) 2268 { 2269 for (; count > 0; offset++, datap++, count--) { 2270 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2271 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2272 } 2273 } 2274 2275 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2276 { 2277 const struct sysctlnode *rnode; 2278 const struct sysctlnode *cnode; 2279 2280 sysctl_createv(NULL, 0, NULL, &rnode, 2281 CTLFLAG_PERMANENT, 2282 CTLTYPE_NODE, "hw", 2283 NULL, 2284 NULL, 0, 2285 NULL, 0, 2286 CTL_HW, CTL_EOL); 2287 2288 sysctl_createv(NULL, 0, &rnode, &rnode, 2289 CTLFLAG_PERMANENT, 2290 CTLTYPE_NODE, "ipw", 2291 NULL, 2292 NULL, 0, 2293 NULL, 0, 2294 CTL_CREATE, CTL_EOL); 2295 2296 sysctl_createv(NULL, 0, &rnode, &cnode, 2297 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2298 CTLTYPE_INT, "accept_eula", 2299 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2300 NULL, 0, 2301 &ipw_accept_eula, sizeof(ipw_accept_eula), 2302 CTL_CREATE, CTL_EOL); 2303 } 2304