1 /* $NetBSD: if_fxp_pci.c,v 1.50 2006/10/12 01:31:29 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.50 2006/10/12 01:31:29 christos Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 94 }; 95 96 static int fxp_pci_match(struct device *, struct cfdata *, void *); 97 static void fxp_pci_attach(struct device *, struct device *, void *); 98 99 static int fxp_pci_enable(struct fxp_softc *); 100 static void fxp_pci_disable(struct fxp_softc *); 101 102 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 103 static void fxp_pci_powerhook(int why, void *arg); 104 105 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 106 fxp_pci_match, fxp_pci_attach, NULL, NULL); 107 108 static const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 135 "Intel PRO/100 VE (LOM) Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 137 "Intel PRO/100 VE Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 139 "Intel PRO/100 VE Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 141 "Intel PRO/100 VM Network Controller" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 143 "Intel PRO/100 VM Network Controller" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 145 "Intel PRO/100 VM Network Controller" }, 146 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 147 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 148 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 149 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 150 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 151 "Intel PRO/100 VM (MOB) Network Controller" }, 152 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 153 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 154 { PCI_PRODUCT_INTEL_PRO_100_M, 155 "Intel PRO/100 M Network Controller" }, 156 { PCI_PRODUCT_INTEL_82801EB_LAN, 157 "Intel 82801EB/ER (ICH5) Network Controller" }, 158 { PCI_PRODUCT_INTEL_82801FB_LAN, 159 "Intel 82562EZ (ICH6)" }, 160 { PCI_PRODUCT_INTEL_82801G_LAN, 161 "Intel 82801GB/GR (ICH7) Network Controller" }, 162 { 0, 163 NULL }, 164 }; 165 166 static const struct fxp_pci_product * 167 fxp_pci_lookup(const struct pci_attach_args *pa) 168 { 169 const struct fxp_pci_product *fpp; 170 171 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 172 return (NULL); 173 174 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 175 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 176 return (fpp); 177 178 return (NULL); 179 } 180 181 static int 182 fxp_pci_match(struct device *parent __unused, struct cfdata *match __unused, 183 void *aux) 184 { 185 struct pci_attach_args *pa = aux; 186 187 if (fxp_pci_lookup(pa) != NULL) 188 return (1); 189 190 return (0); 191 } 192 193 /* 194 * Restore PCI configuration registers that may have been clobbered. 195 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 196 * ethernet, after an APM suspend/resume, as well as after an ACPI 197 * D3->D0 transition. We call this function from a power hook after 198 * APM resume events, as well as after the ACPI D3->D0 transition. 199 */ 200 static void 201 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 202 { 203 pcireg_t reg; 204 205 #if 0 206 /* 207 * Check to see if the command register is blank -- if so, then 208 * we'll assume that all the clobberable-registers have been 209 * clobbered. 210 */ 211 212 /* 213 * In general, the above metric is accurate. Unfortunately, 214 * it is inaccurate across a hibernation. Ideally APM/ACPI 215 * code should take note of hibernation events and execute 216 * a hibernation wakeup hook, but at present a hibernation wake 217 * is indistinguishable from a suspend wake. 218 */ 219 220 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 221 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 222 return; 223 #else 224 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 225 #endif 226 227 pci_conf_write(psc->psc_pc, psc->psc_tag, 228 PCI_COMMAND_STATUS_REG, 229 (reg & 0xffff0000) | 230 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 231 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 232 psc->psc_regs[PCI_BHLC_REG>>2]); 233 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 234 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 235 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 236 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 237 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 238 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 239 } 240 241 242 /* 243 * Power handler routine. Called when the system is transitioning into/out 244 * of power save modes. We restore the (bashed) PCI configuration registers 245 * on a resume. 246 */ 247 static void 248 fxp_pci_powerhook(int why, void *arg) 249 { 250 struct fxp_pci_softc *psc = arg; 251 252 switch (why) { 253 case PWR_SUSPEND: 254 pci_conf_capture(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 255 break; 256 case PWR_RESUME: 257 pci_conf_restore(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 258 fxp_pci_confreg_restore(psc); 259 break; 260 } 261 262 return; 263 } 264 265 static void 266 fxp_pci_attach(struct device *parent __unused, struct device *self, void *aux) 267 { 268 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 269 struct fxp_softc *sc = (struct fxp_softc *)self; 270 struct pci_attach_args *pa = aux; 271 pci_chipset_tag_t pc = pa->pa_pc; 272 pci_intr_handle_t ih; 273 const struct fxp_pci_product *fpp; 274 const char *intrstr = NULL; 275 bus_space_tag_t iot, memt; 276 bus_space_handle_t ioh, memh; 277 int ioh_valid, memh_valid; 278 bus_addr_t addr; 279 bus_size_t size; 280 int flags; 281 int error; 282 283 aprint_naive(": Ethernet controller\n"); 284 285 /* 286 * Map control/status registers. 287 */ 288 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 289 PCI_MAPREG_TYPE_IO, 0, 290 &iot, &ioh, NULL, NULL) == 0); 291 292 /* 293 * Version 2.1 of the PCI spec, page 196, "Address Maps": 294 * 295 * Prefetchable 296 * 297 * Set to one if there are no side effects on reads, the 298 * device returns all bytes regardless of the byte enables, 299 * and host bridges can merge processor writes into this 300 * range without causing errors. Bit must be set to zero 301 * otherwise. 302 * 303 * The 82557 incorrectly sets the "prefetchable" bit, resulting 304 * in errors on systems which will do merged reads and writes. 305 * These errors manifest themselves as all-bits-set when reading 306 * from the EEPROM or other < 4 byte registers. 307 * 308 * We must work around this problem by always forcing the mapping 309 * for memory space to be uncacheable. On systems which cannot 310 * create an uncacheable mapping (because the firmware mapped it 311 * into only cacheable/prefetchable space due to the "prefetchable" 312 * bit), we can fall back onto i/o mapped access. 313 */ 314 memh_valid = 0; 315 memt = pa->pa_memt; 316 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 317 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 318 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 319 &addr, &size, &flags) == 0) { 320 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 321 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 322 memh_valid = 1; 323 } 324 325 if (memh_valid) { 326 sc->sc_st = memt; 327 sc->sc_sh = memh; 328 } else if (ioh_valid) { 329 sc->sc_st = iot; 330 sc->sc_sh = ioh; 331 } else { 332 aprint_error(": unable to map device registers\n"); 333 return; 334 } 335 336 sc->sc_dmat = pa->pa_dmat; 337 338 fpp = fxp_pci_lookup(pa); 339 if (fpp == NULL) { 340 printf("\n"); 341 panic("fxp_pci_attach: impossible"); 342 } 343 344 sc->sc_rev = PCI_REVISION(pa->pa_class); 345 346 switch (fpp->fpp_prodid) { 347 case PCI_PRODUCT_INTEL_82557: 348 case PCI_PRODUCT_INTEL_82559ER: 349 case PCI_PRODUCT_INTEL_IN_BUSINESS: 350 { 351 const char *chipname = NULL; 352 353 if (sc->sc_rev >= FXP_REV_82558_A4) { 354 chipname = "i82558 Ethernet"; 355 /* 356 * Enable the MWI command for memory writes. 357 */ 358 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 359 sc->sc_flags |= FXPF_MWI; 360 } 361 if (sc->sc_rev >= FXP_REV_82559_A0) 362 chipname = "i82559 Ethernet"; 363 if (sc->sc_rev >= FXP_REV_82559S_A) 364 chipname = "i82559S Ethernet"; 365 if (sc->sc_rev >= FXP_REV_82550) 366 chipname = "i82550 Ethernet"; 367 368 /* 369 * Mark all i82559 and i82550 revisions as having 370 * the "resume bug". See i82557.c for details. 371 */ 372 if (sc->sc_rev >= FXP_REV_82559_A0) 373 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 374 375 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 376 fpp->fpp_name, sc->sc_rev); 377 break; 378 } 379 380 case PCI_PRODUCT_INTEL_82801BA_LAN: 381 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 382 383 /* 384 * The 82801BA Ethernet has a bug which requires us to send a 385 * NOP before a CU_RESUME if we're in 10baseT mode. 386 */ 387 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 388 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 389 break; 390 391 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 392 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 393 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 394 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 395 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 396 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 397 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 398 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 399 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 400 401 /* 402 * ICH3 chips apparently have problems with the enhanced 403 * features, so just treat them as an i82557. It also 404 * has the resume bug that the ICH2 has. 405 */ 406 sc->sc_rev = 1; 407 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 408 break; 409 case PCI_PRODUCT_INTEL_82801E_LAN_1: 410 case PCI_PRODUCT_INTEL_82801E_LAN_2: 411 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 412 413 /* 414 * XXX We have to read the C-ICH's developer's manual 415 * in detail 416 */ 417 break; 418 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 419 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 420 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 421 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 422 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 423 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 424 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 425 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 426 case PCI_PRODUCT_INTEL_82801EB_LAN: 427 case PCI_PRODUCT_INTEL_82801FB_LAN: 428 case PCI_PRODUCT_INTEL_82801G_LAN: 429 default: 430 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 431 432 /* 433 * No particular quirks. 434 */ 435 break; 436 } 437 438 /* Make sure bus-mastering is enabled. */ 439 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 440 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 441 PCI_COMMAND_MASTER_ENABLE); 442 443 /* 444 * Under some circumstances (such as APM suspend/resume 445 * cycles, and across ACPI power state changes), the 446 * i82257-family can lose the contents of critical PCI 447 * configuration registers, causing the card to be 448 * non-responsive and useless. This occurs on the Sony VAIO 449 * Z505-series, among others. Preserve them here so they can 450 * be later restored (by fxp_pci_confreg_restore()). 451 */ 452 psc->psc_pc = pc; 453 psc->psc_tag = pa->pa_tag; 454 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 455 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 456 psc->psc_regs[PCI_BHLC_REG>>2] = 457 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 458 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 459 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 460 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 461 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 462 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 463 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 464 465 /* power up chip */ 466 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 467 pci_activate_null))) { 468 case EOPNOTSUPP: 469 break; 470 case 0: 471 sc->sc_enable = fxp_pci_enable; 472 sc->sc_disable = fxp_pci_disable; 473 break; 474 default: 475 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 476 error); 477 return; 478 } 479 480 /* Restore PCI configuration registers. */ 481 fxp_pci_confreg_restore(psc); 482 483 sc->sc_enabled = 1; 484 485 /* 486 * Map and establish our interrupt. 487 */ 488 if (pci_intr_map(pa, &ih)) { 489 aprint_error("%s: couldn't map interrupt\n", 490 sc->sc_dev.dv_xname); 491 return; 492 } 493 intrstr = pci_intr_string(pc, ih); 494 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 495 if (sc->sc_ih == NULL) { 496 aprint_error("%s: couldn't establish interrupt", 497 sc->sc_dev.dv_xname); 498 if (intrstr != NULL) 499 aprint_normal(" at %s", intrstr); 500 aprint_normal("\n"); 501 return; 502 } 503 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 504 505 /* Finish off the attach. */ 506 fxp_attach(sc); 507 if (sc->sc_disable != NULL) 508 fxp_disable(sc); 509 510 /* Add a suspend hook to restore PCI config state */ 511 psc->psc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 512 fxp_pci_powerhook, psc); 513 if (psc->psc_powerhook == NULL) 514 aprint_error( 515 "%s: WARNING: unable to establish pci power hook\n", 516 sc->sc_dev.dv_xname); 517 } 518 519 static int 520 fxp_pci_enable(struct fxp_softc *sc) 521 { 522 struct fxp_pci_softc *psc = (void *) sc; 523 524 #if 0 525 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 526 #endif 527 528 /* Bring the device into D0 power state. */ 529 pci_conf_write(psc->psc_pc, psc->psc_tag, 530 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 531 532 /* Now restore the configuration registers. */ 533 fxp_pci_confreg_restore(psc); 534 535 return (0); 536 } 537 538 static void 539 fxp_pci_disable(struct fxp_softc *sc) 540 { 541 struct fxp_pci_softc *psc = (void *) sc; 542 543 /* 544 * for some 82558_A4 and 82558_B0, entering D3 state makes 545 * media detection disordered. 546 */ 547 if (sc->sc_rev <= FXP_REV_82558_B0) 548 return; 549 550 #if 0 551 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 552 #endif 553 554 /* Put the device into D3 state. */ 555 pci_conf_write(psc->psc_pc, psc->psc_tag, 556 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 557 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 558 } 559