1 /* $NetBSD: if_fxp_pci.c,v 1.49 2006/09/27 21:46:15 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.49 2006/09/27 21:46:15 cube Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 94 }; 95 96 static int fxp_pci_match(struct device *, struct cfdata *, void *); 97 static void fxp_pci_attach(struct device *, struct device *, void *); 98 99 static int fxp_pci_enable(struct fxp_softc *); 100 static void fxp_pci_disable(struct fxp_softc *); 101 102 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 103 static void fxp_pci_powerhook(int why, void *arg); 104 105 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 106 fxp_pci_match, fxp_pci_attach, NULL, NULL); 107 108 static const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 135 "Intel PRO/100 VE (LOM) Network Controller" }, 136 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 137 "Intel PRO/100 VE Network Controller" }, 138 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 139 "Intel PRO/100 VE Network Controller" }, 140 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 141 "Intel PRO/100 VM Network Controller" }, 142 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 143 "Intel PRO/100 VM Network Controller" }, 144 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 145 "Intel PRO/100 VM Network Controller" }, 146 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 147 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 148 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 149 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 150 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 151 "Intel PRO/100 VM (MOB) Network Controller" }, 152 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 153 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 154 { PCI_PRODUCT_INTEL_PRO_100_M, 155 "Intel PRO/100 M Network Controller" }, 156 { PCI_PRODUCT_INTEL_82801EB_LAN, 157 "Intel 82801EB/ER (ICH5) Network Controller" }, 158 { PCI_PRODUCT_INTEL_82801FB_LAN, 159 "Intel 82562EZ (ICH6)" }, 160 { PCI_PRODUCT_INTEL_82801G_LAN, 161 "Intel 82801GB/GR (ICH7) Network Controller" }, 162 { 0, 163 NULL }, 164 }; 165 166 static const struct fxp_pci_product * 167 fxp_pci_lookup(const struct pci_attach_args *pa) 168 { 169 const struct fxp_pci_product *fpp; 170 171 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 172 return (NULL); 173 174 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 175 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 176 return (fpp); 177 178 return (NULL); 179 } 180 181 static int 182 fxp_pci_match(struct device *parent, struct cfdata *match, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 186 if (fxp_pci_lookup(pa) != NULL) 187 return (1); 188 189 return (0); 190 } 191 192 /* 193 * Restore PCI configuration registers that may have been clobbered. 194 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 195 * ethernet, after an APM suspend/resume, as well as after an ACPI 196 * D3->D0 transition. We call this function from a power hook after 197 * APM resume events, as well as after the ACPI D3->D0 transition. 198 */ 199 static void 200 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 201 { 202 pcireg_t reg; 203 204 #if 0 205 /* 206 * Check to see if the command register is blank -- if so, then 207 * we'll assume that all the clobberable-registers have been 208 * clobbered. 209 */ 210 211 /* 212 * In general, the above metric is accurate. Unfortunately, 213 * it is inaccurate across a hibernation. Ideally APM/ACPI 214 * code should take note of hibernation events and execute 215 * a hibernation wakeup hook, but at present a hibernation wake 216 * is indistinguishable from a suspend wake. 217 */ 218 219 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 220 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 221 return; 222 #else 223 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 224 #endif 225 226 pci_conf_write(psc->psc_pc, psc->psc_tag, 227 PCI_COMMAND_STATUS_REG, 228 (reg & 0xffff0000) | 229 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 230 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 231 psc->psc_regs[PCI_BHLC_REG>>2]); 232 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 233 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 234 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 235 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 236 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 237 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 238 } 239 240 241 /* 242 * Power handler routine. Called when the system is transitioning into/out 243 * of power save modes. We restore the (bashed) PCI configuration registers 244 * on a resume. 245 */ 246 static void 247 fxp_pci_powerhook(int why, void *arg) 248 { 249 struct fxp_pci_softc *psc = arg; 250 251 switch (why) { 252 case PWR_SUSPEND: 253 pci_conf_capture(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 254 break; 255 case PWR_RESUME: 256 pci_conf_restore(psc->psc_pc, psc->psc_tag, &psc->psc_pciconf); 257 fxp_pci_confreg_restore(psc); 258 break; 259 } 260 261 return; 262 } 263 264 static void 265 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 266 { 267 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 268 struct fxp_softc *sc = (struct fxp_softc *)self; 269 struct pci_attach_args *pa = aux; 270 pci_chipset_tag_t pc = pa->pa_pc; 271 pci_intr_handle_t ih; 272 const struct fxp_pci_product *fpp; 273 const char *intrstr = NULL; 274 bus_space_tag_t iot, memt; 275 bus_space_handle_t ioh, memh; 276 int ioh_valid, memh_valid; 277 bus_addr_t addr; 278 bus_size_t size; 279 int flags; 280 int error; 281 282 aprint_naive(": Ethernet controller\n"); 283 284 /* 285 * Map control/status registers. 286 */ 287 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 288 PCI_MAPREG_TYPE_IO, 0, 289 &iot, &ioh, NULL, NULL) == 0); 290 291 /* 292 * Version 2.1 of the PCI spec, page 196, "Address Maps": 293 * 294 * Prefetchable 295 * 296 * Set to one if there are no side effects on reads, the 297 * device returns all bytes regardless of the byte enables, 298 * and host bridges can merge processor writes into this 299 * range without causing errors. Bit must be set to zero 300 * otherwise. 301 * 302 * The 82557 incorrectly sets the "prefetchable" bit, resulting 303 * in errors on systems which will do merged reads and writes. 304 * These errors manifest themselves as all-bits-set when reading 305 * from the EEPROM or other < 4 byte registers. 306 * 307 * We must work around this problem by always forcing the mapping 308 * for memory space to be uncacheable. On systems which cannot 309 * create an uncacheable mapping (because the firmware mapped it 310 * into only cacheable/prefetchable space due to the "prefetchable" 311 * bit), we can fall back onto i/o mapped access. 312 */ 313 memh_valid = 0; 314 memt = pa->pa_memt; 315 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 316 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 317 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 318 &addr, &size, &flags) == 0) { 319 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 320 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 321 memh_valid = 1; 322 } 323 324 if (memh_valid) { 325 sc->sc_st = memt; 326 sc->sc_sh = memh; 327 } else if (ioh_valid) { 328 sc->sc_st = iot; 329 sc->sc_sh = ioh; 330 } else { 331 aprint_error(": unable to map device registers\n"); 332 return; 333 } 334 335 sc->sc_dmat = pa->pa_dmat; 336 337 fpp = fxp_pci_lookup(pa); 338 if (fpp == NULL) { 339 printf("\n"); 340 panic("fxp_pci_attach: impossible"); 341 } 342 343 sc->sc_rev = PCI_REVISION(pa->pa_class); 344 345 switch (fpp->fpp_prodid) { 346 case PCI_PRODUCT_INTEL_82557: 347 case PCI_PRODUCT_INTEL_82559ER: 348 case PCI_PRODUCT_INTEL_IN_BUSINESS: 349 { 350 const char *chipname = NULL; 351 352 if (sc->sc_rev >= FXP_REV_82558_A4) { 353 chipname = "i82558 Ethernet"; 354 /* 355 * Enable the MWI command for memory writes. 356 */ 357 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 358 sc->sc_flags |= FXPF_MWI; 359 } 360 if (sc->sc_rev >= FXP_REV_82559_A0) 361 chipname = "i82559 Ethernet"; 362 if (sc->sc_rev >= FXP_REV_82559S_A) 363 chipname = "i82559S Ethernet"; 364 if (sc->sc_rev >= FXP_REV_82550) 365 chipname = "i82550 Ethernet"; 366 367 /* 368 * Mark all i82559 and i82550 revisions as having 369 * the "resume bug". See i82557.c for details. 370 */ 371 if (sc->sc_rev >= FXP_REV_82559_A0) 372 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 373 374 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 375 fpp->fpp_name, sc->sc_rev); 376 break; 377 } 378 379 case PCI_PRODUCT_INTEL_82801BA_LAN: 380 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 381 382 /* 383 * The 82801BA Ethernet has a bug which requires us to send a 384 * NOP before a CU_RESUME if we're in 10baseT mode. 385 */ 386 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 387 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 388 break; 389 390 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 391 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 392 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 393 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 394 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 395 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 396 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 397 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 398 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 399 400 /* 401 * ICH3 chips apparently have problems with the enhanced 402 * features, so just treat them as an i82557. It also 403 * has the resume bug that the ICH2 has. 404 */ 405 sc->sc_rev = 1; 406 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 407 break; 408 case PCI_PRODUCT_INTEL_82801E_LAN_1: 409 case PCI_PRODUCT_INTEL_82801E_LAN_2: 410 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 411 412 /* 413 * XXX We have to read the C-ICH's developer's manual 414 * in detail 415 */ 416 break; 417 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 418 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 419 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 420 case PCI_PRODUCT_INTEL_PRO_100_VE_5: 421 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 422 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 423 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 424 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 425 case PCI_PRODUCT_INTEL_82801EB_LAN: 426 case PCI_PRODUCT_INTEL_82801FB_LAN: 427 case PCI_PRODUCT_INTEL_82801G_LAN: 428 default: 429 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 430 431 /* 432 * No particular quirks. 433 */ 434 break; 435 } 436 437 /* Make sure bus-mastering is enabled. */ 438 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 439 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 440 PCI_COMMAND_MASTER_ENABLE); 441 442 /* 443 * Under some circumstances (such as APM suspend/resume 444 * cycles, and across ACPI power state changes), the 445 * i82257-family can lose the contents of critical PCI 446 * configuration registers, causing the card to be 447 * non-responsive and useless. This occurs on the Sony VAIO 448 * Z505-series, among others. Preserve them here so they can 449 * be later restored (by fxp_pci_confreg_restore()). 450 */ 451 psc->psc_pc = pc; 452 psc->psc_tag = pa->pa_tag; 453 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 454 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 455 psc->psc_regs[PCI_BHLC_REG>>2] = 456 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 457 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 458 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 459 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 460 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 461 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 462 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 463 464 /* power up chip */ 465 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 466 pci_activate_null))) { 467 case EOPNOTSUPP: 468 break; 469 case 0: 470 sc->sc_enable = fxp_pci_enable; 471 sc->sc_disable = fxp_pci_disable; 472 break; 473 default: 474 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 475 error); 476 return; 477 } 478 479 /* Restore PCI configuration registers. */ 480 fxp_pci_confreg_restore(psc); 481 482 sc->sc_enabled = 1; 483 484 /* 485 * Map and establish our interrupt. 486 */ 487 if (pci_intr_map(pa, &ih)) { 488 aprint_error("%s: couldn't map interrupt\n", 489 sc->sc_dev.dv_xname); 490 return; 491 } 492 intrstr = pci_intr_string(pc, ih); 493 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 494 if (sc->sc_ih == NULL) { 495 aprint_error("%s: couldn't establish interrupt", 496 sc->sc_dev.dv_xname); 497 if (intrstr != NULL) 498 aprint_normal(" at %s", intrstr); 499 aprint_normal("\n"); 500 return; 501 } 502 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 503 504 /* Finish off the attach. */ 505 fxp_attach(sc); 506 if (sc->sc_disable != NULL) 507 fxp_disable(sc); 508 509 /* Add a suspend hook to restore PCI config state */ 510 psc->psc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 511 fxp_pci_powerhook, psc); 512 if (psc->psc_powerhook == NULL) 513 aprint_error( 514 "%s: WARNING: unable to establish pci power hook\n", 515 sc->sc_dev.dv_xname); 516 } 517 518 static int 519 fxp_pci_enable(struct fxp_softc *sc) 520 { 521 struct fxp_pci_softc *psc = (void *) sc; 522 523 #if 0 524 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 525 #endif 526 527 /* Bring the device into D0 power state. */ 528 pci_conf_write(psc->psc_pc, psc->psc_tag, 529 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 530 531 /* Now restore the configuration registers. */ 532 fxp_pci_confreg_restore(psc); 533 534 return (0); 535 } 536 537 static void 538 fxp_pci_disable(struct fxp_softc *sc) 539 { 540 struct fxp_pci_softc *psc = (void *) sc; 541 542 /* 543 * for some 82558_A4 and 82558_B0, entering D3 state makes 544 * media detection disordered. 545 */ 546 if (sc->sc_rev <= FXP_REV_82558_B0) 547 return; 548 549 #if 0 550 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 551 #endif 552 553 /* Put the device into D3 state. */ 554 pci_conf_write(psc->psc_pc, psc->psc_tag, 555 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 556 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 557 } 558