1 /* $NetBSD: if_fxp_pci.c,v 1.42 2005/07/29 13:13:34 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.42 2005/07/29 13:13:34 cube Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 static int fxp_pci_match(struct device *, struct cfdata *, void *); 96 static void fxp_pci_attach(struct device *, struct device *, void *); 97 98 static int fxp_pci_enable(struct fxp_softc *); 99 static void fxp_pci_disable(struct fxp_softc *); 100 101 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 102 static void fxp_pci_power(int why, void *arg); 103 104 CFATTACH_DECL(fxp_pci, sizeof(struct fxp_pci_softc), 105 fxp_pci_match, fxp_pci_attach, NULL, NULL); 106 107 static const struct fxp_pci_product { 108 u_int32_t fpp_prodid; /* PCI product ID */ 109 const char *fpp_name; /* device name */ 110 } fxp_pci_products[] = { 111 { PCI_PRODUCT_INTEL_82557, 112 "Intel i82557 Ethernet" }, 113 { PCI_PRODUCT_INTEL_82559ER, 114 "Intel i82559ER Ethernet" }, 115 { PCI_PRODUCT_INTEL_IN_BUSINESS, 116 "Intel InBusiness Ethernet" }, 117 { PCI_PRODUCT_INTEL_82801BA_LAN, 118 "Intel i82562 Ethernet" }, 119 { PCI_PRODUCT_INTEL_82801E_LAN_1, 120 "Intel i82559 Ethernet" }, 121 { PCI_PRODUCT_INTEL_82801E_LAN_2, 122 "Intel i82559 Ethernet" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 124 "Intel PRO/100 VE Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 128 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 130 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 132 "Intel PRO/100 VE (MOB) Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 134 "Intel PRO/100 VM Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 136 "Intel PRO/100 VM Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 140 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 142 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 144 "Intel PRO/100 VM (MOB) Network Controller" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 146 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 147 { PCI_PRODUCT_INTEL_PRO_100_M, 148 "Intel PRO/100 M Network Controller" }, 149 { PCI_PRODUCT_INTEL_82801EB_LAN, 150 "Intel 82801EB/ER (ICH5) Network Controller" }, 151 { PCI_PRODUCT_INTEL_82801FB_LAN, 152 "Intel 82562EZ (ICH6)" }, 153 { PCI_PRODUCT_INTEL_82801G_LAN, 154 "Intel 82801GB/GR (ICH7) Network Controller" }, 155 { 0, 156 NULL }, 157 }; 158 159 static const struct fxp_pci_product * 160 fxp_pci_lookup(const struct pci_attach_args *pa) 161 { 162 const struct fxp_pci_product *fpp; 163 164 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 165 return (NULL); 166 167 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 168 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 169 return (fpp); 170 171 return (NULL); 172 } 173 174 static int 175 fxp_pci_match(struct device *parent, struct cfdata *match, void *aux) 176 { 177 struct pci_attach_args *pa = aux; 178 179 if (fxp_pci_lookup(pa) != NULL) 180 return (1); 181 182 return (0); 183 } 184 185 /* 186 * Restore PCI configuration registers that may have been clobbered. 187 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 188 * ethernet, after an APM suspend/resume, as well as after an ACPI 189 * D3->D0 transition. We call this function from a power hook after 190 * APM resume events, as well as after the ACPI D3->D0 transition. 191 */ 192 static void 193 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 194 { 195 pcireg_t reg; 196 197 #if 0 198 /* 199 * Check to see if the command register is blank -- if so, then 200 * we'll assume that all the clobberable-registers have been 201 * clobbered. 202 */ 203 204 /* 205 * In general, the above metric is accurate. Unfortunately, 206 * it is inaccurate across a hibernation. Ideally APM/ACPI 207 * code should take note of hibernation events and execute 208 * a hibernation wakeup hook, but at present a hibernation wake 209 * is indistinguishable from a suspend wake. 210 */ 211 212 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 213 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 214 return; 215 #else 216 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 217 #endif 218 219 pci_conf_write(psc->psc_pc, psc->psc_tag, 220 PCI_COMMAND_STATUS_REG, 221 (reg & 0xffff0000) | 222 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 223 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 224 psc->psc_regs[PCI_BHLC_REG>>2]); 225 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 226 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 227 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 228 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 229 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 230 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 231 } 232 233 234 /* 235 * Power handler routine. Called when the system is transitioning into/out 236 * of power save modes. We restore the (bashed) PCI configuration registers 237 * on a resume. 238 */ 239 static void 240 fxp_pci_power(int why, void *arg) 241 { 242 struct fxp_pci_softc *psc = arg; 243 244 if (why == PWR_RESUME) 245 fxp_pci_confreg_restore(psc); 246 } 247 248 static void 249 fxp_pci_attach(struct device *parent, struct device *self, void *aux) 250 { 251 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 252 struct fxp_softc *sc = (struct fxp_softc *)self; 253 struct pci_attach_args *pa = aux; 254 pci_chipset_tag_t pc = pa->pa_pc; 255 pci_intr_handle_t ih; 256 const struct fxp_pci_product *fpp; 257 const char *intrstr = NULL; 258 bus_space_tag_t iot, memt; 259 bus_space_handle_t ioh, memh; 260 int ioh_valid, memh_valid; 261 bus_addr_t addr; 262 bus_size_t size; 263 int flags; 264 int pci_pwrmgmt_cap_reg; 265 266 aprint_naive(": Ethernet controller\n"); 267 268 /* 269 * Map control/status registers. 270 */ 271 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 272 PCI_MAPREG_TYPE_IO, 0, 273 &iot, &ioh, NULL, NULL) == 0); 274 275 /* 276 * Version 2.1 of the PCI spec, page 196, "Address Maps": 277 * 278 * Prefetchable 279 * 280 * Set to one if there are no side effects on reads, the 281 * device returns all bytes regardless of the byte enables, 282 * and host bridges can merge processor writes into this 283 * range without causing errors. Bit must be set to zero 284 * otherwise. 285 * 286 * The 82557 incorrectly sets the "prefetchable" bit, resulting 287 * in errors on systems which will do merged reads and writes. 288 * These errors manifest themselves as all-bits-set when reading 289 * from the EEPROM or other < 4 byte registers. 290 * 291 * We must work around this problem by always forcing the mapping 292 * for memory space to be uncacheable. On systems which cannot 293 * create an uncacheable mapping (because the firmware mapped it 294 * into only cacheable/prefetchable space due to the "prefetchable" 295 * bit), we can fall back onto i/o mapped access. 296 */ 297 memh_valid = 0; 298 memt = pa->pa_memt; 299 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 300 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 301 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 302 &addr, &size, &flags) == 0) { 303 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 304 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 305 memh_valid = 1; 306 } 307 308 if (memh_valid) { 309 sc->sc_st = memt; 310 sc->sc_sh = memh; 311 } else if (ioh_valid) { 312 sc->sc_st = iot; 313 sc->sc_sh = ioh; 314 } else { 315 aprint_error(": unable to map device registers\n"); 316 return; 317 } 318 319 sc->sc_dmat = pa->pa_dmat; 320 321 fpp = fxp_pci_lookup(pa); 322 if (fpp == NULL) { 323 printf("\n"); 324 panic("fxp_pci_attach: impossible"); 325 } 326 327 sc->sc_rev = PCI_REVISION(pa->pa_class); 328 329 switch (fpp->fpp_prodid) { 330 case PCI_PRODUCT_INTEL_82557: 331 case PCI_PRODUCT_INTEL_82559ER: 332 case PCI_PRODUCT_INTEL_IN_BUSINESS: 333 { 334 const char *chipname = NULL; 335 336 if (sc->sc_rev >= FXP_REV_82558_A4) { 337 chipname = "i82558 Ethernet"; 338 /* 339 * Enable the MWI command for memory writes. 340 */ 341 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 342 sc->sc_flags |= FXPF_MWI; 343 } 344 if (sc->sc_rev >= FXP_REV_82559_A0) 345 chipname = "i82559 Ethernet"; 346 if (sc->sc_rev >= FXP_REV_82559S_A) 347 chipname = "i82559S Ethernet"; 348 if (sc->sc_rev >= FXP_REV_82550) 349 chipname = "i82550 Ethernet"; 350 351 /* 352 * Mark all i82559 and i82550 revisions as having 353 * the "resume bug". See i82557.c for details. 354 */ 355 if (sc->sc_rev >= FXP_REV_82559_A0) 356 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 357 358 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 359 fpp->fpp_name, sc->sc_rev); 360 break; 361 } 362 363 case PCI_PRODUCT_INTEL_82801BA_LAN: 364 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 365 366 /* 367 * The 82801BA Ethernet has a bug which requires us to send a 368 * NOP before a CU_RESUME if we're in 10baseT mode. 369 */ 370 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 371 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 372 break; 373 374 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 375 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 376 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 377 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 378 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 379 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 380 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 381 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 382 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 383 384 /* 385 * ICH3 chips apparently have problems with the enhanced 386 * features, so just treat them as an i82557. It also 387 * has the resume bug that the ICH2 has. 388 */ 389 sc->sc_rev = 1; 390 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 391 break; 392 case PCI_PRODUCT_INTEL_82801E_LAN_1: 393 case PCI_PRODUCT_INTEL_82801E_LAN_2: 394 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 395 396 /* 397 * XXX We have to read the C-ICH's developer's manual 398 * in detail 399 */ 400 break; 401 case PCI_PRODUCT_INTEL_PRO_100_VE_2: 402 case PCI_PRODUCT_INTEL_PRO_100_VE_3: 403 case PCI_PRODUCT_INTEL_PRO_100_VE_4: 404 case PCI_PRODUCT_INTEL_PRO_100_VM_3: 405 case PCI_PRODUCT_INTEL_PRO_100_VM_4: 406 case PCI_PRODUCT_INTEL_PRO_100_VM_5: 407 case PCI_PRODUCT_INTEL_PRO_100_VM_6: 408 case PCI_PRODUCT_INTEL_82801EB_LAN: 409 case PCI_PRODUCT_INTEL_82801FB_LAN: 410 case PCI_PRODUCT_INTEL_82801G_LAN: 411 default: 412 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 413 414 /* 415 * No particular quirks. 416 */ 417 break; 418 } 419 420 /* Make sure bus-mastering is enabled. */ 421 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 422 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 423 PCI_COMMAND_MASTER_ENABLE); 424 425 /* 426 * Under some circumstances (such as APM suspend/resume 427 * cycles, and across ACPI power state changes), the 428 * i82257-family can lose the contents of critical PCI 429 * configuration registers, causing the card to be 430 * non-responsive and useless. This occurs on the Sony VAIO 431 * Z505-series, among others. Preserve them here so they can 432 * be later restored (by fxp_pci_confreg_restore()). 433 */ 434 psc->psc_pc = pc; 435 psc->psc_tag = pa->pa_tag; 436 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 437 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 438 psc->psc_regs[PCI_BHLC_REG>>2] = 439 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 440 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 441 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 442 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 443 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 444 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 445 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 446 447 /* 448 * Work around BIOS ACPI bugs where the chip is inadvertantly 449 * left in ACPI D3 (lowest power state). First confirm the device 450 * supports ACPI power management, then move it to the D0 (fully 451 * functional) state if it is not already there. 452 */ 453 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 454 &pci_pwrmgmt_cap_reg, 0)) { 455 pcireg_t reg; 456 457 sc->sc_enable = fxp_pci_enable; 458 sc->sc_disable = fxp_pci_disable; 459 460 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 461 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 462 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 463 PCI_PMCSR_STATE_D0; 464 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 465 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 466 psc->psc_pwrmgmt_csr); 467 } 468 /* Restore PCI configuration registers. */ 469 fxp_pci_confreg_restore(psc); 470 471 sc->sc_enabled = 1; 472 473 /* 474 * Map and establish our interrupt. 475 */ 476 if (pci_intr_map(pa, &ih)) { 477 aprint_error("%s: couldn't map interrupt\n", 478 sc->sc_dev.dv_xname); 479 return; 480 } 481 intrstr = pci_intr_string(pc, ih); 482 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 483 if (sc->sc_ih == NULL) { 484 aprint_error("%s: couldn't establish interrupt", 485 sc->sc_dev.dv_xname); 486 if (intrstr != NULL) 487 aprint_normal(" at %s", intrstr); 488 aprint_normal("\n"); 489 return; 490 } 491 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 492 493 /* Finish off the attach. */ 494 fxp_attach(sc); 495 if (sc->sc_disable != NULL) 496 fxp_disable(sc); 497 498 /* Add a suspend hook to restore PCI config state */ 499 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 500 if (psc->psc_powerhook == NULL) 501 aprint_error( 502 "%s: WARNING: unable to establish pci power hook\n", 503 sc->sc_dev.dv_xname); 504 } 505 506 static int 507 fxp_pci_enable(struct fxp_softc *sc) 508 { 509 struct fxp_pci_softc *psc = (void *) sc; 510 511 #if 0 512 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 513 #endif 514 515 /* Bring the device into D0 power state. */ 516 pci_conf_write(psc->psc_pc, psc->psc_tag, 517 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 518 519 /* Now restore the configuration registers. */ 520 fxp_pci_confreg_restore(psc); 521 522 return (0); 523 } 524 525 static void 526 fxp_pci_disable(struct fxp_softc *sc) 527 { 528 struct fxp_pci_softc *psc = (void *) sc; 529 530 /* 531 * for some 82558_A4 and 82558_B0, entering D3 state makes 532 * media detection disordered. 533 */ 534 if (sc->sc_rev <= FXP_REV_82558_B0) 535 return; 536 537 #if 0 538 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 539 #endif 540 541 /* Put the device into D3 state. */ 542 pci_conf_write(psc->psc_pc, psc->psc_tag, 543 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 544 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 545 } 546