1 /* $NetBSD: if_fxp_pci.c,v 1.77 2011/09/05 04:36:50 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Intel i82557 fast Ethernet controller 35 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.77 2011/09/05 04:36:50 msaitoh Exp $"); 40 41 #include "rnd.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #if NRND > 0 54 #include <sys/rnd.h> 55 #endif 56 57 #include <machine/endian.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <sys/bus.h> 65 #include <sys/intr.h> 66 67 #include <dev/mii/miivar.h> 68 69 #include <dev/ic/i82557reg.h> 70 #include <dev/ic/i82557var.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 76 struct fxp_pci_softc { 77 struct fxp_softc psc_fxp; 78 79 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 80 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 81 pcitag_t psc_tag; /* pci register tag */ 82 83 struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */ 84 }; 85 86 static int fxp_pci_match(device_t, cfdata_t, void *); 87 static void fxp_pci_attach(device_t, device_t, void *); 88 static int fxp_pci_detach(device_t, int); 89 90 static int fxp_pci_enable(struct fxp_softc *); 91 92 static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc); 93 static bool fxp_pci_resume(device_t dv, const pmf_qual_t *); 94 95 CFATTACH_DECL3_NEW(fxp_pci, sizeof(struct fxp_pci_softc), 96 fxp_pci_match, fxp_pci_attach, fxp_pci_detach, NULL, NULL, 97 null_childdetached, DVF_DETACH_SHUTDOWN); 98 99 static const struct fxp_pci_product { 100 uint32_t fpp_prodid; /* PCI product ID */ 101 const char *fpp_name; /* device name */ 102 } fxp_pci_products[] = { 103 { PCI_PRODUCT_INTEL_82552, 104 "Intel i82552 10/100 Network Connection" }, 105 { PCI_PRODUCT_INTEL_8255X, 106 "Intel i8255x Ethernet" }, 107 { PCI_PRODUCT_INTEL_82559ER, 108 "Intel i82559ER Ethernet" }, 109 { PCI_PRODUCT_INTEL_IN_BUSINESS, 110 "Intel InBusiness Ethernet" }, 111 { PCI_PRODUCT_INTEL_PRO_100, 112 "Intel PRO/100 Ethernet" }, 113 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 114 "Intel PRO/100 VE Network Controller" }, 115 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 116 "Intel PRO/100 VE Network Controller" }, 117 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 118 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 119 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 120 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 121 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 122 "Intel PRO/100 VE (MOB) Network Controller" }, 123 { PCI_PRODUCT_INTEL_PRO_100_VE_5, 124 "Intel PRO/100 VE (LOM) Network Controller" }, 125 { PCI_PRODUCT_INTEL_PRO_100_VE_6, 126 "Intel PRO/100 VE Network Controller" }, 127 { PCI_PRODUCT_INTEL_PRO_100_VE_7, 128 "Intel PRO/100 VE Network Controller" }, 129 { PCI_PRODUCT_INTEL_PRO_100_VE_8, 130 "Intel PRO/100 VE Network Controller" }, 131 { PCI_PRODUCT_INTEL_PRO_100_VE_9, 132 "Intel PRO/100 VE Network Controller" }, 133 { PCI_PRODUCT_INTEL_PRO_100_VE_10, 134 "Intel PRO/100 VE Network Controller" }, 135 { PCI_PRODUCT_INTEL_PRO_100_VE_11, 136 "Intel PRO/100 VE Network Controller" }, 137 { PCI_PRODUCT_INTEL_PRO_100_VM_0, 138 "Intel PRO/100 VM Network Controller" }, 139 { PCI_PRODUCT_INTEL_PRO_100_VM_1, 140 "Intel PRO/100 VM Network Controller" }, 141 { PCI_PRODUCT_INTEL_PRO_100_VM_2, 142 "Intel PRO/100 VM Network Controller" }, 143 { PCI_PRODUCT_INTEL_PRO_100_VM_3, 144 "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" }, 145 { PCI_PRODUCT_INTEL_PRO_100_VM_4, 146 "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" }, 147 { PCI_PRODUCT_INTEL_PRO_100_VM_5, 148 "Intel PRO/100 VM (MOB) Network Controller" }, 149 { PCI_PRODUCT_INTEL_PRO_100_VM_6, 150 "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" }, 151 { PCI_PRODUCT_INTEL_PRO_100_VM_7, 152 "Intel PRO/100 VM Network Connection" }, 153 { PCI_PRODUCT_INTEL_PRO_100_VM_8, 154 "Intel PRO/100 VM Network Connection" }, 155 { PCI_PRODUCT_INTEL_PRO_100_VM_9, 156 "Intel PRO/100 VM Network Connection" }, 157 { PCI_PRODUCT_INTEL_PRO_100_VM_10, 158 "Intel PRO/100 VM Network Connection" }, 159 { PCI_PRODUCT_INTEL_PRO_100_VM_11, 160 "Intel PRO/100 VM Network Connection" }, 161 { PCI_PRODUCT_INTEL_PRO_100_VM_12, 162 "Intel PRO/100 VM Network Connection" }, 163 { PCI_PRODUCT_INTEL_PRO_100_VM_13, 164 "Intel PRO/100 VM Network Connection" }, 165 { PCI_PRODUCT_INTEL_PRO_100_VM_14, 166 "Intel PRO/100 VM Network Connection" }, 167 { PCI_PRODUCT_INTEL_PRO_100_VM_15, 168 "Intel PRO/100 VM Network Connection" }, 169 { PCI_PRODUCT_INTEL_PRO_100_VM_16, 170 "Intel PRO/100 VM Network Connection" }, 171 { PCI_PRODUCT_INTEL_PRO_100_M, 172 "Intel PRO/100 M Network Controller" }, 173 { PCI_PRODUCT_INTEL_82801BA_LAN, 174 "Intel i82562 Ethernet" }, 175 { PCI_PRODUCT_INTEL_82801E_LAN_1, 176 "Intel i82801E Ethernet" }, 177 { PCI_PRODUCT_INTEL_82801E_LAN_2, 178 "Intel i82801E Ethernet" }, 179 { PCI_PRODUCT_INTEL_82801EB_LAN, 180 "Intel 82801EB/ER (ICH5) Network Controller" }, 181 { PCI_PRODUCT_INTEL_82801FB_LAN, 182 "Intel i82801FB LAN Controller" }, 183 { PCI_PRODUCT_INTEL_82801FB_LAN_2, 184 "Intel i82801FB LAN Controller" }, 185 { PCI_PRODUCT_INTEL_82801G_LAN, 186 "Intel 82801GB/GR (ICH7) Network Controller" }, 187 { PCI_PRODUCT_INTEL_82801GB_LAN, 188 "Intel 82801GB 10/100 Network Controller" }, 189 { 0, 190 NULL }, 191 }; 192 193 static const struct fxp_pci_product * 194 fxp_pci_lookup(const struct pci_attach_args *pa) 195 { 196 const struct fxp_pci_product *fpp; 197 198 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 199 return (NULL); 200 201 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 202 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 203 return (fpp); 204 205 return (NULL); 206 } 207 208 static int 209 fxp_pci_match(device_t parent, cfdata_t match, void *aux) 210 { 211 struct pci_attach_args *pa = aux; 212 213 if (fxp_pci_lookup(pa) != NULL) 214 return (1); 215 216 return (0); 217 } 218 219 /* 220 * On resume : (XXX it is necessary with new pmf framework ?) 221 * Restore PCI configuration registers that may have been clobbered. 222 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 223 * ethernet, after an APM suspend/resume, as well as after an ACPI 224 * D3->D0 transition. We call this function from a power hook after 225 * APM resume events, as well as after the ACPI D3->D0 transition. 226 */ 227 static void 228 fxp_pci_confreg_restore(struct fxp_pci_softc *psc) 229 { 230 pcireg_t reg; 231 232 #if 0 233 /* 234 * Check to see if the command register is blank -- if so, then 235 * we'll assume that all the clobberable-registers have been 236 * clobbered. 237 */ 238 239 /* 240 * In general, the above metric is accurate. Unfortunately, 241 * it is inaccurate across a hibernation. Ideally APM/ACPI 242 * code should take note of hibernation events and execute 243 * a hibernation wakeup hook, but at present a hibernation wake 244 * is indistinguishable from a suspend wake. 245 */ 246 247 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 248 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 249 return; 250 #else 251 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 252 #endif 253 254 pci_conf_write(psc->psc_pc, psc->psc_tag, 255 PCI_COMMAND_STATUS_REG, 256 (reg & 0xffff0000) | 257 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 258 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 259 psc->psc_regs[PCI_BHLC_REG>>2]); 260 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 261 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 262 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 263 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 264 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 265 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 266 } 267 268 static bool 269 fxp_pci_resume(device_t dv, const pmf_qual_t *qual) 270 { 271 struct fxp_pci_softc *psc = device_private(dv); 272 fxp_pci_confreg_restore(psc); 273 274 return true; 275 } 276 277 static int 278 fxp_pci_detach(device_t self, int flags) 279 { 280 struct fxp_pci_softc *psc = device_private(self); 281 struct fxp_softc *sc = &psc->psc_fxp; 282 int error; 283 284 /* Finish off the attach. */ 285 if ((error = fxp_detach(sc, flags)) != 0) 286 return error; 287 288 pmf_device_deregister(self); 289 290 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 291 292 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 293 294 return 0; 295 } 296 297 static void 298 fxp_pci_attach(device_t parent, device_t self, void *aux) 299 { 300 struct fxp_pci_softc *psc = device_private(self); 301 struct fxp_softc *sc = &psc->psc_fxp; 302 const struct pci_attach_args *pa = aux; 303 pci_chipset_tag_t pc = pa->pa_pc; 304 pci_intr_handle_t ih; 305 const struct fxp_pci_product *fpp; 306 const char *chipname = NULL; 307 const char *intrstr = NULL; 308 bus_space_tag_t iot, memt; 309 bus_space_handle_t ioh, memh; 310 int ioh_valid, memh_valid; 311 bus_addr_t addr; 312 int flags; 313 int error; 314 315 sc->sc_dev = self; 316 317 aprint_naive(": Ethernet controller\n"); 318 319 /* 320 * Map control/status registers. 321 */ 322 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 323 PCI_MAPREG_TYPE_IO, 0, 324 &iot, &ioh, NULL, NULL) == 0); 325 326 /* 327 * Version 2.1 of the PCI spec, page 196, "Address Maps": 328 * 329 * Prefetchable 330 * 331 * Set to one if there are no side effects on reads, the 332 * device returns all bytes regardless of the byte enables, 333 * and host bridges can merge processor writes into this 334 * range without causing errors. Bit must be set to zero 335 * otherwise. 336 * 337 * The 82557 incorrectly sets the "prefetchable" bit, resulting 338 * in errors on systems which will do merged reads and writes. 339 * These errors manifest themselves as all-bits-set when reading 340 * from the EEPROM or other < 4 byte registers. 341 * 342 * We must work around this problem by always forcing the mapping 343 * for memory space to be uncacheable. On systems which cannot 344 * create an uncacheable mapping (because the firmware mapped it 345 * into only cacheable/prefetchable space due to the "prefetchable" 346 * bit), we can fall back onto i/o mapped access. 347 */ 348 memh_valid = 0; 349 memt = pa->pa_memt; 350 if (((pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) && 351 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 352 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 353 &addr, &sc->sc_size, &flags) == 0) { 354 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 355 if (bus_space_map(memt, addr, sc->sc_size, flags, &memh) == 0) 356 memh_valid = 1; 357 } 358 359 if (memh_valid) { 360 sc->sc_st = memt; 361 sc->sc_sh = memh; 362 } else if (ioh_valid) { 363 sc->sc_st = iot; 364 sc->sc_sh = ioh; 365 } else { 366 aprint_error(": unable to map device registers\n"); 367 return; 368 } 369 370 sc->sc_dmat = pa->pa_dmat; 371 372 fpp = fxp_pci_lookup(pa); 373 if (fpp == NULL) { 374 printf("\n"); 375 panic("fxp_pci_attach: impossible"); 376 } 377 378 sc->sc_rev = PCI_REVISION(pa->pa_class); 379 380 switch (fpp->fpp_prodid) { 381 case PCI_PRODUCT_INTEL_8255X: 382 case PCI_PRODUCT_INTEL_IN_BUSINESS: 383 384 if (sc->sc_rev >= FXP_REV_82558_A4) { 385 chipname = "i82558 Ethernet"; 386 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 387 /* 388 * Enable the MWI command for memory writes. 389 */ 390 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 391 sc->sc_flags |= FXPF_MWI; 392 } 393 if (sc->sc_rev >= FXP_REV_82559_A0) { 394 chipname = "i82559 Ethernet"; 395 sc->sc_flags |= FXPF_82559_RXCSUM; 396 } 397 if (sc->sc_rev >= FXP_REV_82559S_A) 398 chipname = "i82559S Ethernet"; 399 if (sc->sc_rev >= FXP_REV_82550) { 400 chipname = "i82550 Ethernet"; 401 sc->sc_flags &= ~FXPF_82559_RXCSUM; 402 sc->sc_flags |= FXPF_EXT_RFA; 403 } 404 if (sc->sc_rev >= FXP_REV_82551_E) 405 chipname = "i82551 Ethernet"; 406 407 /* 408 * Mark all i82559 and i82550 revisions as having 409 * the "resume bug". See i82557.c for details. 410 */ 411 if (sc->sc_rev >= FXP_REV_82559_A0) 412 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 413 414 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 415 fpp->fpp_name, sc->sc_rev); 416 break; 417 418 case PCI_PRODUCT_INTEL_82559ER: 419 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 420 421 /* 422 * i82559ER/82551ER don't support RX hardware checksumming 423 * even though it has a newer revision number than 82559_A0. 424 */ 425 426 /* All i82559 have the "resume bug". */ 427 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 428 429 /* Enable the MWI command for memory writes. */ 430 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 431 sc->sc_flags |= FXPF_MWI; 432 433 if (sc->sc_rev >= FXP_REV_82551_E) 434 chipname = "Intel i82551ER Ethernet"; 435 436 aprint_normal(": %s, rev %d\n", chipname != NULL ? chipname : 437 fpp->fpp_name, sc->sc_rev); 438 break; 439 440 case PCI_PRODUCT_INTEL_82801BA_LAN: 441 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 442 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 443 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 444 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 445 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 446 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 447 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 448 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 449 /* 450 * The ICH-2 and ICH-3 have the "resume bug". 451 */ 452 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 453 /* FALLTHROUGH */ 454 455 default: 456 aprint_normal(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 457 if (sc->sc_rev >= FXP_REV_82558_A4) 458 sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB; 459 if (sc->sc_rev >= FXP_REV_82559_A0) 460 sc->sc_flags |= FXPF_82559_RXCSUM; 461 462 break; 463 } 464 465 /* Make sure bus-mastering is enabled. */ 466 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 467 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 468 PCI_COMMAND_MASTER_ENABLE); 469 470 /* 471 * Under some circumstances (such as APM suspend/resume 472 * cycles, and across ACPI power state changes), the 473 * i82257-family can lose the contents of critical PCI 474 * configuration registers, causing the card to be 475 * non-responsive and useless. This occurs on the Sony VAIO 476 * Z505-series, among others. Preserve them here so they can 477 * be later restored (by fxp_pci_confreg_restore()). 478 */ 479 psc->psc_pc = pc; 480 psc->psc_tag = pa->pa_tag; 481 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 482 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 483 psc->psc_regs[PCI_BHLC_REG>>2] = 484 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 485 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 486 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 487 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 488 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 489 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 490 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 491 492 /* power up chip */ 493 switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 494 pci_activate_null))) { 495 case EOPNOTSUPP: 496 break; 497 case 0: 498 sc->sc_enable = fxp_pci_enable; 499 sc->sc_disable = NULL; 500 break; 501 default: 502 aprint_error_dev(self, "cannot activate %d\n", error); 503 return; 504 } 505 506 /* Restore PCI configuration registers. */ 507 fxp_pci_confreg_restore(psc); 508 509 sc->sc_enabled = 1; 510 511 /* 512 * Map and establish our interrupt. 513 */ 514 if (pci_intr_map(pa, &ih)) { 515 aprint_error_dev(self, "couldn't map interrupt\n"); 516 return; 517 } 518 intrstr = pci_intr_string(pc, ih); 519 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 520 if (sc->sc_ih == NULL) { 521 aprint_error_dev(self, "couldn't establish interrupt"); 522 if (intrstr != NULL) 523 aprint_error(" at %s", intrstr); 524 aprint_error("\n"); 525 return; 526 } 527 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 528 529 /* Finish off the attach. */ 530 fxp_attach(sc); 531 if (sc->sc_disable != NULL) 532 fxp_disable(sc); 533 534 /* Add a suspend hook to restore PCI config state */ 535 if (pmf_device_register(self, NULL, fxp_pci_resume)) 536 pmf_class_network_register(self, &sc->sc_ethercom.ec_if); 537 else 538 aprint_error_dev(self, "couldn't establish power handler\n"); 539 } 540 541 static int 542 fxp_pci_enable(struct fxp_softc *sc) 543 { 544 struct fxp_pci_softc *psc = (void *) sc; 545 546 #if 0 547 printf("%s: going to power state D0\n", device_xname(self)); 548 #endif 549 550 /* Now restore the configuration registers. */ 551 fxp_pci_confreg_restore(psc); 552 553 return (0); 554 } 555