1 /* $NetBSD: if_fxp_pci.c,v 1.24 2002/07/22 08:25:45 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intel i82557 fast Ethernet controller 42 * driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.24 2002/07/22 08:25:45 msaitoh Exp $"); 47 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #if NRND > 0 61 #include <sys/rnd.h> 62 #endif 63 64 #include <machine/endian.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_ether.h> 70 71 #include <machine/bus.h> 72 #include <machine/intr.h> 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/ic/i82557reg.h> 77 #include <dev/ic/i82557var.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 struct fxp_pci_softc { 84 struct fxp_softc psc_fxp; 85 86 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 87 pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */ 88 pcitag_t psc_tag; /* pci register tag */ 89 void *psc_powerhook; /* power hook */ 90 91 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 92 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 93 }; 94 95 int fxp_pci_match __P((struct device *, struct cfdata *, void *)); 96 void fxp_pci_attach __P((struct device *, struct device *, void *)); 97 98 int fxp_pci_enable __P((struct fxp_softc *)); 99 void fxp_pci_disable __P((struct fxp_softc *)); 100 101 static void fxp_pci_confreg_restore __P((struct fxp_pci_softc *psc)); 102 static void fxp_pci_power __P((int why, void *arg)); 103 104 struct cfattach fxp_pci_ca = { 105 sizeof(struct fxp_pci_softc), fxp_pci_match, fxp_pci_attach 106 }; 107 108 const struct fxp_pci_product { 109 u_int32_t fpp_prodid; /* PCI product ID */ 110 const char *fpp_name; /* device name */ 111 } fxp_pci_products[] = { 112 { PCI_PRODUCT_INTEL_82557, 113 "Intel i82557 Ethernet" }, 114 { PCI_PRODUCT_INTEL_82559ER, 115 "Intel i82559ER Ethernet" }, 116 { PCI_PRODUCT_INTEL_IN_BUSINESS, 117 "Intel InBusiness Ethernet" }, 118 { PCI_PRODUCT_INTEL_82801BA_LAN, 119 "Intel i82562 Ethernet" }, 120 { PCI_PRODUCT_INTEL_82801E_LAN_1, 121 "Intel i82559 Ethernet" }, 122 { PCI_PRODUCT_INTEL_82801E_LAN_2, 123 "Intel i82559 Ethernet" }, 124 { PCI_PRODUCT_INTEL_PRO_100_VE_0, 125 "Intel PRO/100 VE Network Controller" }, 126 { PCI_PRODUCT_INTEL_PRO_100_VE_1, 127 "Intel PRO/100 VE Network Controller" }, 128 { PCI_PRODUCT_INTEL_PRO_100_VE_2, 129 "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" }, 130 { PCI_PRODUCT_INTEL_PRO_100_VE_3, 131 "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" }, 132 { PCI_PRODUCT_INTEL_PRO_100_VE_4, 133 "Intel PRO/100 VE (MOB) Network Controller" }, 134 { 0, 135 NULL }, 136 }; 137 138 static const struct fxp_pci_product * 139 fxp_pci_lookup(const struct pci_attach_args *pa) 140 { 141 const struct fxp_pci_product *fpp; 142 143 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 144 return (NULL); 145 146 for (fpp = fxp_pci_products; fpp->fpp_name != NULL; fpp++) 147 if (PCI_PRODUCT(pa->pa_id) == fpp->fpp_prodid) 148 return (fpp); 149 150 return (NULL); 151 } 152 153 int 154 fxp_pci_match(parent, match, aux) 155 struct device *parent; 156 struct cfdata *match; 157 void *aux; 158 { 159 struct pci_attach_args *pa = aux; 160 161 if (fxp_pci_lookup(pa) != NULL) 162 return (1); 163 164 return (0); 165 } 166 167 /* 168 * Restore PCI configuration registers that may have been clobbered. 169 * This is necessary due to bugs on the Sony VAIO Z505-series on-board 170 * ethernet, after an APM suspend/resume, as well as after an ACPI 171 * D3->D0 transition. We call this function from a power hook after 172 * APM resume events, as well as after the ACPI D3->D0 transition. 173 */ 174 static void 175 fxp_pci_confreg_restore(psc) 176 struct fxp_pci_softc *psc; 177 { 178 pcireg_t reg; 179 180 #if 0 181 /* 182 * Check to see if the command register is blank -- if so, then 183 * we'll assume that all the clobberable-registers have been 184 * clobbered. 185 */ 186 187 /* 188 * In general, the above metric is accurate. Unfortunately, 189 * it is inaccurate across a hibernation. Ideally APM/ACPI 190 * code should take note of hibernation events and execute 191 * a hibernation wakeup hook, but at present a hibernation wake 192 * is indistinguishable from a suspend wake. 193 */ 194 195 if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 196 PCI_COMMAND_STATUS_REG)) & 0xffff) != 0) 197 return; 198 #else 199 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 200 #endif 201 202 pci_conf_write(psc->psc_pc, psc->psc_tag, 203 PCI_COMMAND_STATUS_REG, 204 (reg & 0xffff0000) | 205 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 206 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 207 psc->psc_regs[PCI_BHLC_REG>>2]); 208 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0, 209 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]); 210 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4, 211 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]); 212 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8, 213 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]); 214 } 215 216 217 /* 218 * Power handler routine. Called when the system is transitioning into/out 219 * of power save modes. We restore the (bashed) PCI configuration registers 220 * on a resume. 221 */ 222 static void 223 fxp_pci_power(why, arg) 224 int why; 225 void *arg; 226 { 227 struct fxp_pci_softc *psc = arg; 228 229 if (why == PWR_RESUME) 230 fxp_pci_confreg_restore(psc); 231 } 232 233 void 234 fxp_pci_attach(parent, self, aux) 235 struct device *parent, *self; 236 void *aux; 237 { 238 struct fxp_pci_softc *psc = (struct fxp_pci_softc *)self; 239 struct fxp_softc *sc = (struct fxp_softc *)self; 240 struct pci_attach_args *pa = aux; 241 pci_chipset_tag_t pc = pa->pa_pc; 242 pci_intr_handle_t ih; 243 const struct fxp_pci_product *fpp; 244 const char *intrstr = NULL; 245 bus_space_tag_t iot, memt; 246 bus_space_handle_t ioh, memh; 247 int ioh_valid, memh_valid; 248 bus_addr_t addr; 249 bus_size_t size; 250 int flags; 251 int pci_pwrmgmt_cap_reg; 252 253 /* 254 * Map control/status registers. 255 */ 256 ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, 257 PCI_MAPREG_TYPE_IO, 0, 258 &iot, &ioh, NULL, NULL) == 0); 259 260 /* 261 * Version 2.1 of the PCI spec, page 196, "Address Maps": 262 * 263 * Prefetchable 264 * 265 * Set to one if there are no side effects on reads, the 266 * device returns all bytes regardless of the byte enables, 267 * and host bridges can merge processor writes into this 268 * range without causing errors. Bit must be set to zero 269 * otherwise. 270 * 271 * The 82557 incorrectly sets the "prefetchable" bit, resulting 272 * in errors on systems which will do merged reads and writes. 273 * These errors manifest themselves as all-bits-set when reading 274 * from the EEPROM or other < 4 byte registers. 275 * 276 * We must work around this problem by always forcing the mapping 277 * for memory space to be uncacheable. On systems which cannot 278 * create an uncacheable mapping (because the firmware mapped it 279 * into only cacheable/prefetchable space due to the "prefetchable" 280 * bit), we can fall back onto i/o mapped access. 281 */ 282 memh_valid = 0; 283 memt = pa->pa_memt; 284 if (((pa->pa_flags & PCI_FLAGS_MEM_ENABLED) != 0) && 285 pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA, 286 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 287 &addr, &size, &flags) == 0) { 288 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 289 if (bus_space_map(memt, addr, size, flags, &memh) == 0) 290 memh_valid = 1; 291 } 292 293 if (memh_valid) { 294 sc->sc_st = memt; 295 sc->sc_sh = memh; 296 } else if (ioh_valid) { 297 sc->sc_st = iot; 298 sc->sc_sh = ioh; 299 } else { 300 printf(": unable to map device registers\n"); 301 return; 302 } 303 304 sc->sc_dmat = pa->pa_dmat; 305 306 fpp = fxp_pci_lookup(pa); 307 if (fpp == NULL) { 308 printf("\n"); 309 panic("fxp_pci_attach: impossible"); 310 } 311 312 sc->sc_rev = PCI_REVISION(pa->pa_class); 313 314 switch (fpp->fpp_prodid) { 315 case PCI_PRODUCT_INTEL_82557: 316 case PCI_PRODUCT_INTEL_82559ER: 317 case PCI_PRODUCT_INTEL_IN_BUSINESS: 318 { 319 const char *chipname = NULL; 320 321 if (sc->sc_rev >= FXP_REV_82558_A4) { 322 chipname = "i82558 Ethernet"; 323 /* 324 * Enable the MWI command for memory writes. 325 */ 326 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 327 sc->sc_flags |= FXPF_MWI; 328 } 329 if (sc->sc_rev >= FXP_REV_82559_A0) 330 chipname = "i82559 Ethernet"; 331 if (sc->sc_rev >= FXP_REV_82559S_A) 332 chipname = "i82559S Ethernet"; 333 if (sc->sc_rev >= FXP_REV_82550) 334 chipname = "i82550 Ethernet"; 335 336 /* 337 * Mark all i82559 and i82550 revisions as having 338 * the "resume bug". See i82557.c for details. 339 */ 340 if (sc->sc_rev >= FXP_REV_82559_A0) 341 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 342 343 printf(": %s, rev %d\n", chipname != NULL ? chipname : 344 fpp->fpp_name, sc->sc_rev); 345 break; 346 } 347 348 case PCI_PRODUCT_INTEL_82801BA_LAN: 349 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 350 351 /* 352 * The 82801BA Ethernet has a bug which requires us to send a 353 * NOP before a CU_RESUME if we're in 10baseT mode. 354 */ 355 if (fpp->fpp_prodid == PCI_PRODUCT_INTEL_82801BA_LAN) 356 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 357 break; 358 359 case PCI_PRODUCT_INTEL_PRO_100_VE_0: 360 case PCI_PRODUCT_INTEL_PRO_100_VE_1: 361 case PCI_PRODUCT_INTEL_PRO_100_VM_0: 362 case PCI_PRODUCT_INTEL_PRO_100_VM_1: 363 case PCI_PRODUCT_INTEL_82562EH_HPNA_0: 364 case PCI_PRODUCT_INTEL_82562EH_HPNA_1: 365 case PCI_PRODUCT_INTEL_82562EH_HPNA_2: 366 case PCI_PRODUCT_INTEL_PRO_100_VM_2: 367 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 368 369 /* 370 * ICH3 chips apparently have problems with the enhanced 371 * features, so just treat them as an i82557. It also 372 * has the resume bug that the ICH2 has. 373 */ 374 sc->sc_rev = 1; 375 sc->sc_flags |= FXPF_HAS_RESUME_BUG; 376 break; 377 case PCI_PRODUCT_INTEL_82801E_LAN_1: 378 case PCI_PRODUCT_INTEL_82801E_LAN_2: 379 printf(": %s, rev %d\n", fpp->fpp_name, sc->sc_rev); 380 381 /* 382 * XXX We have to read the C-ICH's developer's manual 383 * in detail 384 */ 385 break; 386 } 387 388 /* Make sure bus-mastering is enabled. */ 389 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 390 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 391 PCI_COMMAND_MASTER_ENABLE); 392 393 /* 394 * Under some circumstances (such as APM suspend/resume 395 * cycles, and across ACPI power state changes), the 396 * i82257-family can lose the contents of critical PCI 397 * configuration registers, causing the card to be 398 * non-responsive and useless. This occurs on the Sony VAIO 399 * Z505-series, among others. Preserve them here so they can 400 * be later restored (by fxp_pci_confreg_restore()). 401 */ 402 psc->psc_pc = pc; 403 psc->psc_tag = pa->pa_tag; 404 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 405 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 406 psc->psc_regs[PCI_BHLC_REG>>2] = 407 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 408 psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] = 409 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0); 410 psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] = 411 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4); 412 psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] = 413 pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8); 414 415 /* 416 * Work around BIOS ACPI bugs where the chip is inadvertantly 417 * left in ACPI D3 (lowest power state). First confirm the device 418 * supports ACPI power management, then move it to the D0 (fully 419 * functional) state if it is not already there. 420 */ 421 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, 422 &pci_pwrmgmt_cap_reg, 0)) { 423 pcireg_t reg; 424 425 sc->sc_enable = fxp_pci_enable; 426 sc->sc_disable = fxp_pci_disable; 427 428 psc->psc_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 429 reg = pci_conf_read(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg); 430 psc->psc_pwrmgmt_csr = (reg & ~PCI_PMCSR_STATE_MASK) | 431 PCI_PMCSR_STATE_D0; 432 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) 433 pci_conf_write(pc, pa->pa_tag, psc->psc_pwrmgmt_csr_reg, 434 psc->psc_pwrmgmt_csr); 435 } 436 /* Restore PCI configuration registers. */ 437 fxp_pci_confreg_restore(psc); 438 439 sc->sc_enabled = 1; 440 441 /* 442 * Map and establish our interrupt. 443 */ 444 if (pci_intr_map(pa, &ih)) { 445 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 446 return; 447 } 448 intrstr = pci_intr_string(pc, ih); 449 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc); 450 if (sc->sc_ih == NULL) { 451 printf("%s: couldn't establish interrupt", 452 sc->sc_dev.dv_xname); 453 if (intrstr != NULL) 454 printf(" at %s", intrstr); 455 printf("\n"); 456 return; 457 } 458 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 459 460 /* Finish off the attach. */ 461 fxp_attach(sc); 462 if (sc->sc_disable != NULL) 463 fxp_disable(sc); 464 465 /* Add a suspend hook to restore PCI config state */ 466 psc->psc_powerhook = powerhook_establish(fxp_pci_power, psc); 467 if (psc->psc_powerhook == NULL) 468 printf ("%s: WARNING: unable to establish pci power hook\n", 469 sc->sc_dev.dv_xname); 470 } 471 472 int 473 fxp_pci_enable(struct fxp_softc *sc) 474 { 475 struct fxp_pci_softc *psc = (void *) sc; 476 477 #if 0 478 printf("%s: going to power state D0\n", sc->sc_dev.dv_xname); 479 #endif 480 481 /* Bring the device into D0 power state. */ 482 pci_conf_write(psc->psc_pc, psc->psc_tag, 483 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 484 485 /* Now restore the configuration registers. */ 486 fxp_pci_confreg_restore(psc); 487 488 return (0); 489 } 490 491 void 492 fxp_pci_disable(struct fxp_softc *sc) 493 { 494 struct fxp_pci_softc *psc = (void *) sc; 495 496 #if 0 497 printf("%s: going to power state D3\n", sc->sc_dev.dv_xname); 498 #endif 499 500 /* Put the device into D3 state. */ 501 pci_conf_write(psc->psc_pc, psc->psc_tag, 502 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 503 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 504 } 505