1 /* $NetBSD: if_ex_pci.c,v 1.50 2009/05/05 10:02:52 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_ex_pci.c,v 1.50 2009/05/05 10:02:52 cegger Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/ioctl.h> 41 #include <sys/errno.h> 42 #include <sys/syslog.h> 43 #include <sys/select.h> 44 #include <sys/device.h> 45 46 #include <net/if.h> 47 #include <net/if_dl.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <sys/cpu.h> 52 #include <sys/bus.h> 53 #include <sys/intr.h> 54 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/mii.h> 57 58 #include <dev/ic/elink3var.h> 59 #include <dev/ic/elink3reg.h> 60 #include <dev/ic/elinkxlreg.h> 61 #include <dev/ic/elinkxlvar.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 67 struct ex_pci_softc { 68 struct ex_softc sc_ex; 69 70 /* PCI function status space. 556,556B requests it. */ 71 bus_space_tag_t sc_funct; 72 bus_space_handle_t sc_funch; 73 74 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 75 pcireg_t psc_regs[0x40>>2]; /* saved PCI config regs (sparse) */ 76 pcitag_t psc_tag; /* pci device tag */ 77 78 int psc_pwrmgmt_csr_reg; /* ACPI power management register */ 79 pcireg_t psc_pwrmgmt_csr; /* ...and the contents at D0 */ 80 }; 81 82 /* 83 * PCI constants. 84 * XXX These should be in a common file! 85 */ 86 #define PCI_CONN 0x48 /* Connector type */ 87 #define PCI_CBIO 0x10 /* Configuration Base IO Address */ 88 #define PCI_POWERCTL 0xe0 89 #define PCI_FUNCMEM 0x18 90 91 #define PCI_INTR 4 92 #define PCI_INTRACK 0x00008000 93 94 static int ex_pci_match(device_t, cfdata_t, void *); 95 static void ex_pci_attach(device_t, device_t, void *); 96 static void ex_pci_intr_ack(struct ex_softc *); 97 98 static int ex_pci_enable(struct ex_softc *); 99 static void ex_pci_disable(struct ex_softc *); 100 101 static void ex_pci_confreg_restore(struct ex_pci_softc *); 102 static int ex_d3tod0(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t); 103 104 CFATTACH_DECL_NEW(ex_pci, sizeof(struct ex_pci_softc), 105 ex_pci_match, ex_pci_attach, NULL, NULL); 106 107 static const struct ex_pci_product { 108 uint32_t epp_prodid; /* PCI product ID */ 109 int epp_flags; /* initial softc flags */ 110 const char *epp_name; /* device name */ 111 } ex_pci_products[] = { 112 { PCI_PRODUCT_3COM_3C900TPO, 0, 113 "3c900-TPO Ethernet" }, 114 { PCI_PRODUCT_3COM_3C900COMBO, 0, 115 "3c900-COMBO Ethernet" }, 116 117 { PCI_PRODUCT_3COM_3C905TX, EX_CONF_MII, 118 "3c905-TX 10/100 Ethernet" }, 119 { PCI_PRODUCT_3COM_3C905T4, EX_CONF_MII, 120 "3c905-T4 10/100 Ethernet" }, 121 122 { PCI_PRODUCT_3COM_3C900BTPO, EX_CONF_90XB, 123 "3c900B-TPO Ethernet" }, 124 { PCI_PRODUCT_3COM_3C900BCOMBO, EX_CONF_90XB, 125 "3c900B-COMBO Ethernet" }, 126 { PCI_PRODUCT_3COM_3C900BTPC, EX_CONF_90XB, 127 "3c900B-TPC Ethernet" }, 128 129 { PCI_PRODUCT_3COM_3C905BTX, EX_CONF_90XB|EX_CONF_MII|EX_CONF_INTPHY, 130 "3c905B-TX 10/100 Ethernet" }, 131 { PCI_PRODUCT_3COM_3C905BT4, EX_CONF_90XB|EX_CONF_MII, 132 "3c905B-T4 10/100 Ethernet" }, 133 { PCI_PRODUCT_3COM_3C905BCOMBO, EX_CONF_90XB/*|EX_CONF_MII|EX_CONF_INTPHY*/, 134 "3c905B-COMBO 10/100 Ethernet" }, 135 { PCI_PRODUCT_3COM_3C905BFX, EX_CONF_90XB, 136 "3c905B-FX 10/100 Ethernet" }, 137 138 /* XXX Internal PHY? */ 139 { PCI_PRODUCT_3COM_3C980SRV, EX_CONF_90XB, 140 "3c980 Server Adapter 10/100 Ethernet" }, 141 { PCI_PRODUCT_3COM_3C980CTXM, EX_CONF_90XB|EX_CONF_MII, 142 "3c980C-TXM 10/100 Ethernet" }, 143 144 { PCI_PRODUCT_3COM_3C905CTX, EX_CONF_90XB|EX_CONF_MII, 145 "3c905C-TX 10/100 Ethernet with mngmt" }, 146 147 { PCI_PRODUCT_3COM_3C450TX, EX_CONF_90XB, 148 "3c450-TX 10/100 Ethernet" }, 149 150 { PCI_PRODUCT_3COM_3CSOHO100TX, EX_CONF_90XB, 151 "3cSOHO100-TX 10/100 Ethernet" }, 152 153 { PCI_PRODUCT_3COM_3C555, 154 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 155 EX_CONF_EEPROM_8BIT, 156 "3c555 MiniPCI 10/100 Ethernet" }, 157 158 { PCI_PRODUCT_3COM_3C556, 159 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 160 EX_CONF_PCI_FUNCREG | EX_CONF_RESETHACK | EX_CONF_INV_LED_POLARITY | 161 EX_CONF_PHY_POWER | EX_CONF_EEPROM_8BIT, 162 "3c556 MiniPCI 10/100 Ethernet" }, 163 164 { PCI_PRODUCT_3COM_3C556B, 165 EX_CONF_90XB | EX_CONF_MII | EX_CONF_EEPROM_OFF | 166 EX_CONF_PCI_FUNCREG | EX_CONF_RESETHACK | EX_CONF_INV_LED_POLARITY | 167 EX_CONF_PHY_POWER | EX_CONF_NO_XCVR_PWR, 168 "3c556B MiniPCI 10/100 Ethernet" }, 169 170 { PCI_PRODUCT_3COM_3C905CXTX, EX_CONF_90XB|EX_CONF_MII, 171 "3c905CX-TX 10/100 Ethernet with mngmt" }, 172 173 { PCI_PRODUCT_3COM_3C920BEMBW, EX_CONF_90XB|EX_CONF_MII, 174 "3c920B-EMB-WNM Integrated Fast Ethernet" }, 175 176 { 0, 0, 177 NULL }, 178 }; 179 180 static const struct ex_pci_product * 181 ex_pci_lookup(const struct pci_attach_args *pa) 182 { 183 const struct ex_pci_product *epp; 184 185 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_3COM) 186 return (NULL); 187 188 for (epp = ex_pci_products; epp->epp_name != NULL; epp++) 189 if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid) 190 return (epp); 191 return (NULL); 192 } 193 194 static int 195 ex_pci_match(device_t parent, cfdata_t match, 196 void *aux) 197 { 198 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 199 200 if (ex_pci_lookup(pa) != NULL) 201 return (2); /* beat ep_pci */ 202 203 return (0); 204 } 205 206 static void 207 ex_pci_attach(device_t parent, device_t self, void *aux) 208 { 209 struct ex_pci_softc *psc = device_private(self); 210 struct ex_softc *sc = &psc->sc_ex; 211 struct pci_attach_args *pa = aux; 212 pci_chipset_tag_t pc = pa->pa_pc; 213 pci_intr_handle_t ih; 214 const struct ex_pci_product *epp; 215 const char *intrstr = NULL; 216 int rev; 217 int error; 218 219 aprint_naive(": Ethernet controller\n"); 220 221 sc->sc_dev = self; 222 223 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 224 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 225 aprint_error(": can't map i/o space\n"); 226 return; 227 } 228 229 epp = ex_pci_lookup(pa); 230 if (epp == NULL) { 231 printf("\n"); 232 panic("ex_pci_attach: impossible"); 233 } 234 235 rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 236 aprint_normal(": 3Com %s (rev. 0x%x)\n", epp->epp_name, rev); 237 238 sc->sc_dmat = pa->pa_dmat; 239 240 sc->ex_bustype = EX_BUS_PCI; 241 sc->ex_conf = epp->epp_flags; 242 243 /* Enable the card. */ 244 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 245 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 246 PCI_COMMAND_MASTER_ENABLE); 247 248 psc->psc_pc = pc; 249 psc->psc_tag = pa->pa_tag; 250 psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] = 251 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 252 psc->psc_regs[PCI_BHLC_REG>>2] = 253 pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG); 254 psc->psc_regs[PCI_CBIO>>2] = 255 pci_conf_read(pc, pa->pa_tag, PCI_CBIO); 256 257 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) { 258 /* Map PCI function status window. */ 259 if (pci_mapreg_map(pa, PCI_FUNCMEM, PCI_MAPREG_TYPE_MEM, 0, 260 &psc->sc_funct, &psc->sc_funch, NULL, NULL)) { 261 aprint_error_dev(self, 262 "unable to map function status window\n"); 263 return; 264 } 265 sc->intr_ack = ex_pci_intr_ack; 266 267 psc->psc_regs[PCI_FUNCMEM>>2] = 268 pci_conf_read(pc, pa->pa_tag, PCI_FUNCMEM); 269 } 270 271 psc->psc_regs[PCI_INTERRUPT_REG>>2] = 272 pci_conf_read(pc, pa->pa_tag, PCI_INTERRUPT_REG); 273 /* power up chip */ 274 error = pci_activate(pa->pa_pc, pa->pa_tag, self, ex_d3tod0); 275 switch (error) { 276 case EOPNOTSUPP: 277 break; 278 case 0: 279 sc->enable = ex_pci_enable; 280 sc->disable = ex_pci_disable; 281 break; 282 default: 283 aprint_error_dev(self, "cannot activate %d\n", error); 284 return; 285 } 286 sc->enabled = 1; 287 288 /* Map and establish the interrupt. */ 289 if (pci_intr_map(pa, &ih)) { 290 aprint_error_dev(self, "couldn't map interrupt\n"); 291 return; 292 } 293 294 intrstr = pci_intr_string(pc, ih); 295 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ex_intr, sc); 296 if (sc->sc_ih == NULL) { 297 aprint_error_dev(self, "couldn't establish interrupt"); 298 if (intrstr != NULL) 299 aprint_error(" at %s", intrstr); 300 aprint_error("\n"); 301 return; 302 } 303 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 304 305 ex_config(sc); 306 307 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) 308 bus_space_write_4(psc->sc_funct, psc->sc_funch, PCI_INTR, 309 PCI_INTRACK); 310 311 if (sc->disable != NULL) 312 ex_disable(sc); 313 } 314 315 static void 316 ex_pci_intr_ack(struct ex_softc *sc) 317 { 318 struct ex_pci_softc *psc = (struct ex_pci_softc *)sc; 319 320 bus_space_write_4(psc->sc_funct, psc->sc_funch, PCI_INTR, 321 PCI_INTRACK); 322 } 323 324 static int 325 ex_d3tod0(pci_chipset_tag_t pc, pcitag_t tag, device_t self, pcireg_t state) 326 { 327 328 #define PCI_CACHE_LAT_BIST 0x0c 329 #define PCI_BAR0 0x10 330 #define PCI_BAR1 0x14 331 #define PCI_BAR2 0x18 332 #define PCI_BAR3 0x1C 333 #define PCI_BAR4 0x20 334 #define PCI_BAR5 0x24 335 #define PCI_EXP_ROM_BAR 0x30 336 #define PCI_INT_GNT_LAT 0x3c 337 338 uint32_t base0; 339 uint32_t base1; 340 uint32_t romaddr; 341 uint32_t pci_command; 342 uint32_t pci_int_lat; 343 uint32_t pci_cache_lat; 344 345 if (state != PCI_PMCSR_STATE_D3) 346 return 0; 347 348 aprint_normal_dev(self, "found in power state D%d, " 349 "attempting to recover.\n", state); 350 pci_command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 351 base0 = pci_conf_read(pc, tag, PCI_BAR0); 352 base1 = pci_conf_read(pc, tag, PCI_BAR1); 353 romaddr = pci_conf_read(pc, tag, PCI_EXP_ROM_BAR); 354 pci_cache_lat= pci_conf_read(pc, tag, PCI_CACHE_LAT_BIST); 355 pci_int_lat = pci_conf_read(pc, tag, PCI_INT_GNT_LAT); 356 357 pci_conf_write(pc, tag, PCI_POWERCTL, 0); 358 pci_conf_write(pc, tag, PCI_BAR0, base0); 359 pci_conf_write(pc, tag, PCI_BAR1, base1); 360 pci_conf_write(pc, tag, PCI_EXP_ROM_BAR, romaddr); 361 pci_conf_write(pc, tag, PCI_INT_GNT_LAT, pci_int_lat); 362 pci_conf_write(pc, tag, PCI_CACHE_LAT_BIST, pci_cache_lat); 363 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 364 (PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE)); 365 aprint_normal_dev(self, "changed power state to D0.\n"); 366 return 0; 367 } 368 369 static void 370 ex_pci_confreg_restore(struct ex_pci_softc *psc) 371 { 372 struct ex_softc *sc = (void *) psc; 373 pcireg_t reg; 374 375 reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 376 377 pci_conf_write(psc->psc_pc, psc->psc_tag, 378 PCI_COMMAND_STATUS_REG, 379 (reg & 0xffff0000) | 380 (psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff)); 381 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG, 382 psc->psc_regs[PCI_BHLC_REG>>2]); 383 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_CBIO, 384 psc->psc_regs[PCI_CBIO>>2]); 385 if (sc->ex_conf & EX_CONF_PCI_FUNCREG) 386 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_FUNCMEM, 387 psc->psc_regs[PCI_FUNCMEM>>2]); 388 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_INTERRUPT_REG, 389 psc->psc_regs[PCI_INTERRUPT_REG>>2]); 390 } 391 392 static int 393 ex_pci_enable(struct ex_softc *sc) 394 { 395 struct ex_pci_softc *psc = (void *) sc; 396 397 aprint_debug_dev(sc->sc_dev, "going to power state D0\n"); 398 399 /* Bring the device into D0 power state. */ 400 pci_conf_write(psc->psc_pc, psc->psc_tag, 401 psc->psc_pwrmgmt_csr_reg, psc->psc_pwrmgmt_csr); 402 403 /* Now restore the configuration registers. */ 404 ex_pci_confreg_restore(psc); 405 406 return (0); 407 } 408 409 static void 410 ex_pci_disable(struct ex_softc *sc) 411 { 412 struct ex_pci_softc *psc = (void *) sc; 413 414 aprint_debug_dev(sc->sc_dev, "going to power state D3\n"); 415 416 /* Put the device into D3 state. */ 417 pci_conf_write(psc->psc_pc, psc->psc_tag, 418 psc->psc_pwrmgmt_csr_reg, (psc->psc_pwrmgmt_csr & 419 ~PCI_PMCSR_STATE_MASK) | PCI_PMCSR_STATE_D3); 420 } 421