1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 #if 0 32 __FBSDID("$FreeBSD: head/sys/dev/ena/ena.c 333456 2018-05-10 09:37:54Z mw $"); 33 #endif 34 __KERNEL_RCSID(0, "$NetBSD: if_ena.c,v 1.15 2019/05/29 10:07:29 msaitoh Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/endian.h> 40 #include <sys/kernel.h> 41 #include <sys/kthread.h> 42 #include <sys/malloc.h> 43 #include <sys/mbuf.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/time.h> 49 #include <sys/workqueue.h> 50 #include <sys/callout.h> 51 #include <sys/interrupt.h> 52 #include <sys/cpu.h> 53 54 #include <net/if_ether.h> 55 #include <net/if_vlanvar.h> 56 57 #include <dev/pci/if_enavar.h> 58 59 /********************************************************* 60 * Function prototypes 61 *********************************************************/ 62 static int ena_probe(device_t, cfdata_t, void *); 63 static int ena_intr_msix_mgmnt(void *); 64 static int ena_allocate_pci_resources(struct pci_attach_args *, 65 struct ena_adapter *); 66 static void ena_free_pci_resources(struct ena_adapter *); 67 static int ena_change_mtu(struct ifnet *, int); 68 static void ena_init_io_rings_common(struct ena_adapter *, 69 struct ena_ring *, uint16_t); 70 static void ena_init_io_rings(struct ena_adapter *); 71 static void ena_free_io_ring_resources(struct ena_adapter *, unsigned int); 72 static void ena_free_all_io_rings_resources(struct ena_adapter *); 73 #if 0 74 static int ena_setup_tx_dma_tag(struct ena_adapter *); 75 static int ena_free_tx_dma_tag(struct ena_adapter *); 76 static int ena_setup_rx_dma_tag(struct ena_adapter *); 77 static int ena_free_rx_dma_tag(struct ena_adapter *); 78 #endif 79 static int ena_setup_tx_resources(struct ena_adapter *, int); 80 static void ena_free_tx_resources(struct ena_adapter *, int); 81 static int ena_setup_all_tx_resources(struct ena_adapter *); 82 static void ena_free_all_tx_resources(struct ena_adapter *); 83 static inline int validate_rx_req_id(struct ena_ring *, uint16_t); 84 static int ena_setup_rx_resources(struct ena_adapter *, unsigned int); 85 static void ena_free_rx_resources(struct ena_adapter *, unsigned int); 86 static int ena_setup_all_rx_resources(struct ena_adapter *); 87 static void ena_free_all_rx_resources(struct ena_adapter *); 88 static inline int ena_alloc_rx_mbuf(struct ena_adapter *, struct ena_ring *, 89 struct ena_rx_buffer *); 90 static void ena_free_rx_mbuf(struct ena_adapter *, struct ena_ring *, 91 struct ena_rx_buffer *); 92 static int ena_refill_rx_bufs(struct ena_ring *, uint32_t); 93 static void ena_free_rx_bufs(struct ena_adapter *, unsigned int); 94 static void ena_refill_all_rx_bufs(struct ena_adapter *); 95 static void ena_free_all_rx_bufs(struct ena_adapter *); 96 static void ena_free_tx_bufs(struct ena_adapter *, unsigned int); 97 static void ena_free_all_tx_bufs(struct ena_adapter *); 98 static void ena_destroy_all_tx_queues(struct ena_adapter *); 99 static void ena_destroy_all_rx_queues(struct ena_adapter *); 100 static void ena_destroy_all_io_queues(struct ena_adapter *); 101 static int ena_create_io_queues(struct ena_adapter *); 102 static int ena_tx_cleanup(struct ena_ring *); 103 static void ena_deferred_rx_cleanup(struct work *, void *); 104 static int ena_rx_cleanup(struct ena_ring *); 105 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 106 #if 0 107 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 108 struct mbuf *); 109 #endif 110 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 111 struct ena_com_rx_ctx *, uint16_t *); 112 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 113 struct mbuf *); 114 static int ena_handle_msix(void *); 115 static int ena_enable_msix(struct ena_adapter *); 116 static int ena_request_mgmnt_irq(struct ena_adapter *); 117 static int ena_request_io_irq(struct ena_adapter *); 118 static void ena_free_mgmnt_irq(struct ena_adapter *); 119 static void ena_free_io_irq(struct ena_adapter *); 120 static void ena_free_irqs(struct ena_adapter*); 121 static void ena_disable_msix(struct ena_adapter *); 122 static void ena_unmask_all_io_irqs(struct ena_adapter *); 123 static int ena_rss_configure(struct ena_adapter *); 124 static int ena_up_complete(struct ena_adapter *); 125 static int ena_up(struct ena_adapter *); 126 static void ena_down(struct ena_adapter *); 127 #if 0 128 static uint64_t ena_get_counter(struct ifnet *, ift_counter); 129 #endif 130 static int ena_media_change(struct ifnet *); 131 static void ena_media_status(struct ifnet *, struct ifmediareq *); 132 static int ena_init(struct ifnet *); 133 static int ena_ioctl(struct ifnet *, u_long, void *); 134 static int ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *); 135 static void ena_update_host_info(struct ena_admin_host_info *, struct ifnet *); 136 static void ena_update_hwassist(struct ena_adapter *); 137 static int ena_setup_ifnet(device_t, struct ena_adapter *, 138 struct ena_com_dev_get_features_ctx *); 139 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *); 140 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 141 struct mbuf **mbuf); 142 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 143 static void ena_start_xmit(struct ena_ring *); 144 static int ena_mq_start(struct ifnet *, struct mbuf *); 145 static void ena_deferred_mq_start(struct work *, void *); 146 #if 0 147 static void ena_qflush(struct ifnet *); 148 #endif 149 static int ena_calc_io_queue_num(struct pci_attach_args *, 150 struct ena_adapter *, struct ena_com_dev_get_features_ctx *); 151 static int ena_calc_queue_size(struct ena_adapter *, uint16_t *, 152 uint16_t *, struct ena_com_dev_get_features_ctx *); 153 #if 0 154 static int ena_rss_init_default(struct ena_adapter *); 155 static void ena_rss_init_default_deferred(void *); 156 #endif 157 static void ena_config_host_info(struct ena_com_dev *); 158 static void ena_attach(device_t, device_t, void *); 159 static int ena_detach(device_t, int); 160 static int ena_device_init(struct ena_adapter *, device_t, 161 struct ena_com_dev_get_features_ctx *, int *); 162 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *, 163 int); 164 static void ena_update_on_link_change(void *, struct ena_admin_aenq_entry *); 165 static void unimplemented_aenq_handler(void *, 166 struct ena_admin_aenq_entry *); 167 static void ena_timer_service(void *); 168 169 static const char ena_version[] = 170 DEVICE_NAME DRV_MODULE_NAME " v" DRV_MODULE_VERSION; 171 172 #if 0 173 static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD, 0, "ENA driver parameters"); 174 #endif 175 176 /* 177 * Tuneable number of buffers in the buf-ring (drbr) 178 */ 179 static int ena_buf_ring_size = 4096; 180 #if 0 181 SYSCTL_INT(_hw_ena, OID_AUTO, buf_ring_size, CTLFLAG_RWTUN, 182 &ena_buf_ring_size, 0, "Size of the bufring"); 183 #endif 184 185 /* 186 * Logging level for changing verbosity of the output 187 */ 188 int ena_log_level = ENA_ALERT | ENA_WARNING; 189 #if 0 190 SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, 191 &ena_log_level, 0, "Logging level indicating verbosity of the logs"); 192 #endif 193 194 static const ena_vendor_info_t ena_vendor_info_array[] = { 195 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_PF, 0}, 196 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_PF, 0}, 197 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_VF, 0}, 198 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_VF, 0}, 199 /* Last entry */ 200 { 0, 0, 0 } 201 }; 202 203 /* 204 * Contains pointers to event handlers, e.g. link state chage. 205 */ 206 static struct ena_aenq_handlers aenq_handlers; 207 208 int 209 ena_dma_alloc(device_t dmadev, bus_size_t size, 210 ena_mem_handle_t *dma , int mapflags) 211 { 212 struct ena_adapter *adapter = device_private(dmadev); 213 uint32_t maxsize; 214 bus_dma_segment_t seg; 215 int error, nsegs; 216 217 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; 218 219 #if 0 220 /* XXX what is this needed for ? */ 221 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); 222 if (unlikely(dma_space_addr == 0)) 223 dma_space_addr = BUS_SPACE_MAXADDR; 224 #endif 225 226 dma->tag = adapter->sc_dmat; 227 228 if ((error = bus_dmamap_create(dma->tag, maxsize, 1, maxsize, 0, 229 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->map)) != 0) { 230 ena_trace(ENA_ALERT, "bus_dmamap_create(%ju) failed: %d\n", 231 (uintmax_t)maxsize, error); 232 goto fail_create; 233 } 234 235 error = bus_dmamem_alloc(dma->tag, maxsize, 8, 0, &seg, 1, &nsegs, 236 BUS_DMA_ALLOCNOW); 237 if (error) { 238 ena_trace(ENA_ALERT, "bus_dmamem_alloc(%ju) failed: %d\n", 239 (uintmax_t)maxsize, error); 240 goto fail_alloc; 241 } 242 243 error = bus_dmamem_map(dma->tag, &seg, nsegs, maxsize, 244 &dma->vaddr, BUS_DMA_COHERENT); 245 if (error) { 246 ena_trace(ENA_ALERT, "bus_dmamem_map(%ju) failed: %d\n", 247 (uintmax_t)maxsize, error); 248 goto fail_map; 249 } 250 memset(dma->vaddr, 0, maxsize); 251 252 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 253 maxsize, NULL, mapflags); 254 if (error) { 255 ena_trace(ENA_ALERT, ": bus_dmamap_load failed: %d\n", error); 256 goto fail_load; 257 } 258 dma->paddr = dma->map->dm_segs[0].ds_addr; 259 260 return (0); 261 262 fail_load: 263 bus_dmamem_unmap(dma->tag, dma->vaddr, maxsize); 264 fail_map: 265 bus_dmamem_free(dma->tag, &seg, nsegs); 266 fail_alloc: 267 bus_dmamap_destroy(adapter->sc_dmat, dma->map); 268 fail_create: 269 return (error); 270 } 271 272 static int 273 ena_allocate_pci_resources(struct pci_attach_args *pa, 274 struct ena_adapter *adapter) 275 { 276 bus_size_t size; 277 278 /* 279 * Map control/status registers. 280 */ 281 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ENA_REG_BAR); 282 if (pci_mapreg_map(pa, ENA_REG_BAR, memtype, 0, &adapter->sc_btag, 283 &adapter->sc_bhandle, NULL, &size)) { 284 aprint_error(": can't map mem space\n"); 285 return ENXIO; 286 } 287 288 return (0); 289 } 290 291 static void 292 ena_free_pci_resources(struct ena_adapter *adapter) 293 { 294 /* Nothing to do */ 295 } 296 297 static int 298 ena_probe(device_t parent, cfdata_t match, void *aux) 299 { 300 struct pci_attach_args *pa = aux; 301 const ena_vendor_info_t *ent; 302 303 for (int i = 0; i < __arraycount(ena_vendor_info_array); i++) { 304 ent = &ena_vendor_info_array[i]; 305 306 if ((PCI_VENDOR(pa->pa_id) == ent->vendor_id) && 307 (PCI_PRODUCT(pa->pa_id) == ent->device_id)) { 308 return 1; 309 } 310 } 311 312 return 0; 313 } 314 315 static int 316 ena_change_mtu(struct ifnet *ifp, int new_mtu) 317 { 318 struct ena_adapter *adapter = if_getsoftc(ifp); 319 int rc; 320 321 if ((new_mtu > adapter->max_mtu) || (new_mtu < ENA_MIN_MTU)) { 322 device_printf(adapter->pdev, "Invalid MTU setting. " 323 "new_mtu: %d max mtu: %d min mtu: %d\n", 324 new_mtu, adapter->max_mtu, ENA_MIN_MTU); 325 return (EINVAL); 326 } 327 328 rc = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 329 if (likely(rc == 0)) { 330 ena_trace(ENA_DBG, "set MTU to %d\n", new_mtu); 331 if_setmtu(ifp, new_mtu); 332 } else { 333 device_printf(adapter->pdev, "Failed to set MTU to %d\n", 334 new_mtu); 335 } 336 337 return (rc); 338 } 339 340 #define EVCNT_INIT(st, f) \ 341 do { \ 342 evcnt_attach_dynamic(&st->f, EVCNT_TYPE_MISC, NULL, \ 343 st->name, #f); \ 344 } while (0) 345 346 static inline void 347 ena_alloc_counters_rx(struct ena_stats_rx *st, int queue) 348 { 349 snprintf(st->name, sizeof(st->name), "ena rxq%d", queue); 350 351 EVCNT_INIT(st, cnt); 352 EVCNT_INIT(st, bytes); 353 EVCNT_INIT(st, refil_partial); 354 EVCNT_INIT(st, bad_csum); 355 EVCNT_INIT(st, mjum_alloc_fail); 356 EVCNT_INIT(st, mbuf_alloc_fail); 357 EVCNT_INIT(st, dma_mapping_err); 358 EVCNT_INIT(st, bad_desc_num); 359 EVCNT_INIT(st, bad_req_id); 360 EVCNT_INIT(st, empty_rx_ring); 361 362 /* Make sure all code is updated when new fields added */ 363 CTASSERT(offsetof(struct ena_stats_rx, empty_rx_ring) 364 + sizeof(st->empty_rx_ring) == sizeof(*st)); 365 } 366 367 static inline void 368 ena_alloc_counters_tx(struct ena_stats_tx *st, int queue) 369 { 370 snprintf(st->name, sizeof(st->name), "ena txq%d", queue); 371 372 EVCNT_INIT(st, cnt); 373 EVCNT_INIT(st, bytes); 374 EVCNT_INIT(st, prepare_ctx_err); 375 EVCNT_INIT(st, dma_mapping_err); 376 EVCNT_INIT(st, doorbells); 377 EVCNT_INIT(st, missing_tx_comp); 378 EVCNT_INIT(st, bad_req_id); 379 EVCNT_INIT(st, collapse); 380 EVCNT_INIT(st, collapse_err); 381 382 /* Make sure all code is updated when new fields added */ 383 CTASSERT(offsetof(struct ena_stats_tx, collapse_err) 384 + sizeof(st->collapse_err) == sizeof(*st)); 385 } 386 387 static inline void 388 ena_alloc_counters_dev(struct ena_stats_dev *st, int queue) 389 { 390 snprintf(st->name, sizeof(st->name), "ena dev ioq%d", queue); 391 392 EVCNT_INIT(st, wd_expired); 393 EVCNT_INIT(st, interface_up); 394 EVCNT_INIT(st, interface_down); 395 EVCNT_INIT(st, admin_q_pause); 396 397 /* Make sure all code is updated when new fields added */ 398 CTASSERT(offsetof(struct ena_stats_dev, admin_q_pause) 399 + sizeof(st->admin_q_pause) == sizeof(*st)); 400 } 401 402 static inline void 403 ena_alloc_counters_hwstats(struct ena_hw_stats *st, int queue) 404 { 405 snprintf(st->name, sizeof(st->name), "ena hw ioq%d", queue); 406 407 EVCNT_INIT(st, rx_packets); 408 EVCNT_INIT(st, tx_packets); 409 EVCNT_INIT(st, rx_bytes); 410 EVCNT_INIT(st, tx_bytes); 411 EVCNT_INIT(st, rx_drops); 412 413 /* Make sure all code is updated when new fields added */ 414 CTASSERT(offsetof(struct ena_hw_stats, rx_drops) 415 + sizeof(st->rx_drops) == sizeof(*st)); 416 } 417 static inline void 418 ena_free_counters(struct evcnt *begin, int size) 419 { 420 struct evcnt *end = (struct evcnt *)((char *)begin + size); 421 422 for (; begin < end; ++begin) 423 counter_u64_free(*begin); 424 } 425 426 static inline void 427 ena_reset_counters(struct evcnt *begin, int size) 428 { 429 struct evcnt *end = (struct evcnt *)((char *)begin + size); 430 431 for (; begin < end; ++begin) 432 counter_u64_zero(*begin); 433 } 434 435 static void 436 ena_init_io_rings_common(struct ena_adapter *adapter, struct ena_ring *ring, 437 uint16_t qid) 438 { 439 440 ring->qid = qid; 441 ring->adapter = adapter; 442 ring->ena_dev = adapter->ena_dev; 443 } 444 445 static void 446 ena_init_io_rings(struct ena_adapter *adapter) 447 { 448 struct ena_com_dev *ena_dev; 449 struct ena_ring *txr, *rxr; 450 struct ena_que *que; 451 int i; 452 453 ena_dev = adapter->ena_dev; 454 455 for (i = 0; i < adapter->num_queues; i++) { 456 txr = &adapter->tx_ring[i]; 457 rxr = &adapter->rx_ring[i]; 458 459 /* TX/RX common ring state */ 460 ena_init_io_rings_common(adapter, txr, i); 461 ena_init_io_rings_common(adapter, rxr, i); 462 463 /* TX specific ring state */ 464 txr->ring_size = adapter->tx_ring_size; 465 txr->tx_max_header_size = ena_dev->tx_max_header_size; 466 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 467 txr->smoothed_interval = 468 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 469 470 /* Allocate a buf ring */ 471 txr->br = buf_ring_alloc(ena_buf_ring_size, M_DEVBUF, 472 M_WAITOK, &txr->ring_mtx); 473 474 /* Alloc TX statistics. */ 475 ena_alloc_counters_tx(&txr->tx_stats, i); 476 477 /* RX specific ring state */ 478 rxr->ring_size = adapter->rx_ring_size; 479 rxr->smoothed_interval = 480 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 481 482 /* Alloc RX statistics. */ 483 ena_alloc_counters_rx(&rxr->rx_stats, i); 484 485 /* Initialize locks */ 486 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 487 device_xname(adapter->pdev), i); 488 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 489 device_xname(adapter->pdev), i); 490 491 mutex_init(&txr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 492 mutex_init(&rxr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 493 494 que = &adapter->que[i]; 495 que->adapter = adapter; 496 que->id = i; 497 que->tx_ring = txr; 498 que->rx_ring = rxr; 499 500 txr->que = que; 501 rxr->que = que; 502 503 rxr->empty_rx_queue = 0; 504 } 505 } 506 507 static void 508 ena_free_io_ring_resources(struct ena_adapter *adapter, unsigned int qid) 509 { 510 struct ena_ring *txr = &adapter->tx_ring[qid]; 511 struct ena_ring *rxr = &adapter->rx_ring[qid]; 512 513 ena_free_counters((struct evcnt *)&txr->tx_stats, 514 sizeof(txr->tx_stats)); 515 ena_free_counters((struct evcnt *)&rxr->rx_stats, 516 sizeof(rxr->rx_stats)); 517 518 ENA_RING_MTX_LOCK(txr); 519 drbr_free(txr->br, M_DEVBUF); 520 ENA_RING_MTX_UNLOCK(txr); 521 522 mutex_destroy(&txr->ring_mtx); 523 mutex_destroy(&rxr->ring_mtx); 524 } 525 526 static void 527 ena_free_all_io_rings_resources(struct ena_adapter *adapter) 528 { 529 int i; 530 531 for (i = 0; i < adapter->num_queues; i++) 532 ena_free_io_ring_resources(adapter, i); 533 534 } 535 536 #if 0 537 static int 538 ena_setup_tx_dma_tag(struct ena_adapter *adapter) 539 { 540 int ret; 541 542 /* Create DMA tag for Tx buffers */ 543 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), 544 1, 0, /* alignment, bounds */ 545 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 546 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 547 NULL, NULL, /* filter, filterarg */ 548 ENA_TSO_MAXSIZE, /* maxsize */ 549 adapter->max_tx_sgl_size - 1, /* nsegments */ 550 ENA_TSO_MAXSIZE, /* maxsegsize */ 551 0, /* flags */ 552 NULL, /* lockfunc */ 553 NULL, /* lockfuncarg */ 554 &adapter->tx_buf_tag); 555 556 return (ret); 557 } 558 #endif 559 560 #if 0 561 static int 562 ena_setup_rx_dma_tag(struct ena_adapter *adapter) 563 { 564 int ret; 565 566 /* Create DMA tag for Rx buffers*/ 567 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */ 568 1, 0, /* alignment, bounds */ 569 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 570 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 571 NULL, NULL, /* filter, filterarg */ 572 MJUM16BYTES, /* maxsize */ 573 adapter->max_rx_sgl_size, /* nsegments */ 574 MJUM16BYTES, /* maxsegsize */ 575 0, /* flags */ 576 NULL, /* lockfunc */ 577 NULL, /* lockarg */ 578 &adapter->rx_buf_tag); 579 580 return (ret); 581 } 582 #endif 583 584 /** 585 * ena_setup_tx_resources - allocate Tx resources (Descriptors) 586 * @adapter: network interface device structure 587 * @qid: queue index 588 * 589 * Returns 0 on success, otherwise on failure. 590 **/ 591 static int 592 ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 593 { 594 struct ena_que *que = &adapter->que[qid]; 595 struct ena_ring *tx_ring = que->tx_ring; 596 int size, i, err; 597 #ifdef RSS 598 cpuset_t cpu_mask; 599 #endif 600 601 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 602 603 tx_ring->tx_buffer_info = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 604 if (unlikely(tx_ring->tx_buffer_info == NULL)) 605 return (ENOMEM); 606 607 size = sizeof(uint16_t) * tx_ring->ring_size; 608 tx_ring->free_tx_ids = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 609 if (unlikely(tx_ring->free_tx_ids == NULL)) 610 goto err_buf_info_free; 611 612 /* Req id stack for TX OOO completions */ 613 for (i = 0; i < tx_ring->ring_size; i++) 614 tx_ring->free_tx_ids[i] = i; 615 616 /* Reset TX statistics. */ 617 ena_reset_counters((struct evcnt *)&tx_ring->tx_stats, 618 sizeof(tx_ring->tx_stats)); 619 620 tx_ring->next_to_use = 0; 621 tx_ring->next_to_clean = 0; 622 623 /* Make sure that drbr is empty */ 624 ENA_RING_MTX_LOCK(tx_ring); 625 drbr_flush(adapter->ifp, tx_ring->br); 626 ENA_RING_MTX_UNLOCK(tx_ring); 627 628 /* ... and create the buffer DMA maps */ 629 for (i = 0; i < tx_ring->ring_size; i++) { 630 err = bus_dmamap_create(adapter->sc_dmat, 631 ENA_TSO_MAXSIZE, adapter->max_tx_sgl_size - 1, 632 ENA_TSO_MAXSIZE, 0, 0, 633 &tx_ring->tx_buffer_info[i].map); 634 if (unlikely(err != 0)) { 635 ena_trace(ENA_ALERT, 636 "Unable to create Tx DMA map for buffer %d\n", i); 637 goto err_buf_info_unmap; 638 } 639 } 640 641 /* Allocate workqueues */ 642 int rc = workqueue_create(&tx_ring->enqueue_tq, "ena_tx_enq", 643 ena_deferred_mq_start, tx_ring, 0, IPL_NET, WQ_PERCPU | WQ_MPSAFE); 644 if (unlikely(rc != 0)) { 645 ena_trace(ENA_ALERT, 646 "Unable to create workqueue for enqueue task\n"); 647 i = tx_ring->ring_size; 648 goto err_buf_info_unmap; 649 } 650 651 #if 0 652 /* RSS set cpu for thread */ 653 #ifdef RSS 654 CPU_SETOF(que->cpu, &cpu_mask); 655 taskqueue_start_threads_cpuset(&tx_ring->enqueue_tq, 1, IPL_NET, 656 &cpu_mask, "%s tx_ring enq (bucket %d)", 657 device_xname(adapter->pdev), que->cpu); 658 #else /* RSS */ 659 taskqueue_start_threads(&tx_ring->enqueue_tq, 1, IPL_NET, 660 "%s txeq %d", device_xname(adapter->pdev), que->cpu); 661 #endif /* RSS */ 662 #endif 663 664 return (0); 665 666 err_buf_info_unmap: 667 while (i--) { 668 bus_dmamap_destroy(adapter->sc_dmat, 669 tx_ring->tx_buffer_info[i].map); 670 } 671 free(tx_ring->free_tx_ids, M_DEVBUF); 672 tx_ring->free_tx_ids = NULL; 673 err_buf_info_free: 674 free(tx_ring->tx_buffer_info, M_DEVBUF); 675 tx_ring->tx_buffer_info = NULL; 676 677 return (ENOMEM); 678 } 679 680 /** 681 * ena_free_tx_resources - Free Tx Resources per Queue 682 * @adapter: network interface device structure 683 * @qid: queue index 684 * 685 * Free all transmit software resources 686 **/ 687 static void 688 ena_free_tx_resources(struct ena_adapter *adapter, int qid) 689 { 690 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 691 692 workqueue_wait(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 693 workqueue_destroy(tx_ring->enqueue_tq); 694 tx_ring->enqueue_tq = NULL; 695 696 ENA_RING_MTX_LOCK(tx_ring); 697 /* Flush buffer ring, */ 698 drbr_flush(adapter->ifp, tx_ring->br); 699 700 /* Free buffer DMA maps, */ 701 for (int i = 0; i < tx_ring->ring_size; i++) { 702 m_freem(tx_ring->tx_buffer_info[i].mbuf); 703 tx_ring->tx_buffer_info[i].mbuf = NULL; 704 bus_dmamap_unload(adapter->sc_dmat, 705 tx_ring->tx_buffer_info[i].map); 706 bus_dmamap_destroy(adapter->sc_dmat, 707 tx_ring->tx_buffer_info[i].map); 708 } 709 ENA_RING_MTX_UNLOCK(tx_ring); 710 711 /* And free allocated memory. */ 712 free(tx_ring->tx_buffer_info, M_DEVBUF); 713 tx_ring->tx_buffer_info = NULL; 714 715 free(tx_ring->free_tx_ids, M_DEVBUF); 716 tx_ring->free_tx_ids = NULL; 717 } 718 719 /** 720 * ena_setup_all_tx_resources - allocate all queues Tx resources 721 * @adapter: network interface device structure 722 * 723 * Returns 0 on success, otherwise on failure. 724 **/ 725 static int 726 ena_setup_all_tx_resources(struct ena_adapter *adapter) 727 { 728 int i, rc; 729 730 for (i = 0; i < adapter->num_queues; i++) { 731 rc = ena_setup_tx_resources(adapter, i); 732 if (rc != 0) { 733 device_printf(adapter->pdev, 734 "Allocation for Tx Queue %u failed\n", i); 735 goto err_setup_tx; 736 } 737 } 738 739 return (0); 740 741 err_setup_tx: 742 /* Rewind the index freeing the rings as we go */ 743 while (i--) 744 ena_free_tx_resources(adapter, i); 745 return (rc); 746 } 747 748 /** 749 * ena_free_all_tx_resources - Free Tx Resources for All Queues 750 * @adapter: network interface device structure 751 * 752 * Free all transmit software resources 753 **/ 754 static void 755 ena_free_all_tx_resources(struct ena_adapter *adapter) 756 { 757 int i; 758 759 for (i = 0; i < adapter->num_queues; i++) 760 ena_free_tx_resources(adapter, i); 761 } 762 763 static inline int 764 validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 765 { 766 if (likely(req_id < rx_ring->ring_size)) 767 return (0); 768 769 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 770 req_id); 771 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 772 773 /* Trigger device reset */ 774 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 775 rx_ring->adapter->trigger_reset = true; 776 777 return (EFAULT); 778 } 779 780 /** 781 * ena_setup_rx_resources - allocate Rx resources (Descriptors) 782 * @adapter: network interface device structure 783 * @qid: queue index 784 * 785 * Returns 0 on success, otherwise on failure. 786 **/ 787 static int 788 ena_setup_rx_resources(struct ena_adapter *adapter, unsigned int qid) 789 { 790 struct ena_que *que = &adapter->que[qid]; 791 struct ena_ring *rx_ring = que->rx_ring; 792 int size, err, i; 793 #ifdef RSS 794 cpuset_t cpu_mask; 795 #endif 796 797 size = sizeof(struct ena_rx_buffer) * rx_ring->ring_size; 798 799 /* 800 * Alloc extra element so in rx path 801 * we can always prefetch rx_info + 1 802 */ 803 size += sizeof(struct ena_rx_buffer); 804 805 rx_ring->rx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 806 807 size = sizeof(uint16_t) * rx_ring->ring_size; 808 rx_ring->free_rx_ids = malloc(size, M_DEVBUF, M_WAITOK); 809 810 for (i = 0; i < rx_ring->ring_size; i++) 811 rx_ring->free_rx_ids[i] = i; 812 813 /* Reset RX statistics. */ 814 ena_reset_counters((struct evcnt *)&rx_ring->rx_stats, 815 sizeof(rx_ring->rx_stats)); 816 817 rx_ring->next_to_clean = 0; 818 rx_ring->next_to_use = 0; 819 820 /* ... and create the buffer DMA maps */ 821 for (i = 0; i < rx_ring->ring_size; i++) { 822 err = bus_dmamap_create(adapter->sc_dmat, 823 MJUM16BYTES, adapter->max_rx_sgl_size, MJUM16BYTES, 824 0, 0, 825 &(rx_ring->rx_buffer_info[i].map)); 826 if (err != 0) { 827 ena_trace(ENA_ALERT, 828 "Unable to create Rx DMA map for buffer %d\n", i); 829 goto err_buf_info_unmap; 830 } 831 } 832 833 #ifdef LRO 834 /* Create LRO for the ring */ 835 if ((adapter->ifp->if_capenable & IFCAP_LRO) != 0) { 836 int err = tcp_lro_init(&rx_ring->lro); 837 if (err != 0) { 838 device_printf(adapter->pdev, 839 "LRO[%d] Initialization failed!\n", qid); 840 } else { 841 ena_trace(ENA_INFO, 842 "RX Soft LRO[%d] Initialized\n", qid); 843 rx_ring->lro.ifp = adapter->ifp; 844 } 845 } 846 #endif 847 848 /* Allocate workqueues */ 849 int rc = workqueue_create(&rx_ring->cmpl_tq, "ena_rx_comp", 850 ena_deferred_rx_cleanup, rx_ring, 0, IPL_NET, WQ_PERCPU | WQ_MPSAFE); 851 if (unlikely(rc != 0)) { 852 ena_trace(ENA_ALERT, 853 "Unable to create workqueue for RX completion task\n"); 854 goto err_buf_info_unmap; 855 } 856 857 #if 0 858 /* RSS set cpu for thread */ 859 #ifdef RSS 860 CPU_SETOF(que->cpu, &cpu_mask); 861 taskqueue_start_threads_cpuset(&rx_ring->cmpl_tq, 1, IPL_NET, &cpu_mask, 862 "%s rx_ring cmpl (bucket %d)", 863 device_xname(adapter->pdev), que->cpu); 864 #else 865 taskqueue_start_threads(&rx_ring->cmpl_tq, 1, IPL_NET, 866 "%s rx_ring cmpl %d", device_xname(adapter->pdev), que->cpu); 867 #endif 868 #endif 869 870 return (0); 871 872 err_buf_info_unmap: 873 while (i--) { 874 bus_dmamap_destroy(adapter->sc_dmat, 875 rx_ring->rx_buffer_info[i].map); 876 } 877 878 free(rx_ring->free_rx_ids, M_DEVBUF); 879 rx_ring->free_rx_ids = NULL; 880 free(rx_ring->rx_buffer_info, M_DEVBUF); 881 rx_ring->rx_buffer_info = NULL; 882 return (ENOMEM); 883 } 884 885 /** 886 * ena_free_rx_resources - Free Rx Resources 887 * @adapter: network interface device structure 888 * @qid: queue index 889 * 890 * Free all receive software resources 891 **/ 892 static void 893 ena_free_rx_resources(struct ena_adapter *adapter, unsigned int qid) 894 { 895 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 896 897 workqueue_wait(rx_ring->cmpl_tq, &rx_ring->cmpl_task); 898 workqueue_destroy(rx_ring->cmpl_tq); 899 rx_ring->cmpl_tq = NULL; 900 901 /* Free buffer DMA maps, */ 902 for (int i = 0; i < rx_ring->ring_size; i++) { 903 m_freem(rx_ring->rx_buffer_info[i].mbuf); 904 rx_ring->rx_buffer_info[i].mbuf = NULL; 905 bus_dmamap_unload(adapter->sc_dmat, 906 rx_ring->rx_buffer_info[i].map); 907 bus_dmamap_destroy(adapter->sc_dmat, 908 rx_ring->rx_buffer_info[i].map); 909 } 910 911 #ifdef LRO 912 /* free LRO resources, */ 913 tcp_lro_free(&rx_ring->lro); 914 #endif 915 916 /* free allocated memory */ 917 free(rx_ring->rx_buffer_info, M_DEVBUF); 918 rx_ring->rx_buffer_info = NULL; 919 920 free(rx_ring->free_rx_ids, M_DEVBUF); 921 rx_ring->free_rx_ids = NULL; 922 } 923 924 /** 925 * ena_setup_all_rx_resources - allocate all queues Rx resources 926 * @adapter: network interface device structure 927 * 928 * Returns 0 on success, otherwise on failure. 929 **/ 930 static int 931 ena_setup_all_rx_resources(struct ena_adapter *adapter) 932 { 933 int i, rc = 0; 934 935 for (i = 0; i < adapter->num_queues; i++) { 936 rc = ena_setup_rx_resources(adapter, i); 937 if (rc != 0) { 938 device_printf(adapter->pdev, 939 "Allocation for Rx Queue %u failed\n", i); 940 goto err_setup_rx; 941 } 942 } 943 return (0); 944 945 err_setup_rx: 946 /* rewind the index freeing the rings as we go */ 947 while (i--) 948 ena_free_rx_resources(adapter, i); 949 return (rc); 950 } 951 952 /** 953 * ena_free_all_rx_resources - Free Rx resources for all queues 954 * @adapter: network interface device structure 955 * 956 * Free all receive software resources 957 **/ 958 static void 959 ena_free_all_rx_resources(struct ena_adapter *adapter) 960 { 961 int i; 962 963 for (i = 0; i < adapter->num_queues; i++) 964 ena_free_rx_resources(adapter, i); 965 } 966 967 static inline int 968 ena_alloc_rx_mbuf(struct ena_adapter *adapter, 969 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 970 { 971 struct ena_com_buf *ena_buf; 972 int error; 973 int mlen; 974 975 /* if previous allocated frag is not used */ 976 if (unlikely(rx_info->mbuf != NULL)) 977 return (0); 978 979 /* Get mbuf using UMA allocator */ 980 rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); 981 982 if (unlikely(rx_info->mbuf == NULL)) { 983 counter_u64_add(rx_ring->rx_stats.mjum_alloc_fail, 1); 984 rx_info->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 985 if (unlikely(rx_info->mbuf == NULL)) { 986 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 987 return (ENOMEM); 988 } 989 mlen = MCLBYTES; 990 } else { 991 mlen = MJUM16BYTES; 992 } 993 /* Set mbuf length*/ 994 rx_info->mbuf->m_pkthdr.len = rx_info->mbuf->m_len = mlen; 995 996 /* Map packets for DMA */ 997 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 998 "Using tag %p for buffers' DMA mapping, mbuf %p len: %d", 999 adapter->sc_dmat,rx_info->mbuf, rx_info->mbuf->m_len); 1000 error = bus_dmamap_load_mbuf(adapter->sc_dmat, rx_info->map, 1001 rx_info->mbuf, BUS_DMA_NOWAIT); 1002 if (unlikely((error != 0) || (rx_info->map->dm_nsegs != 1))) { 1003 ena_trace(ENA_WARNING, "failed to map mbuf, error: %d, " 1004 "nsegs: %d\n", error, rx_info->map->dm_nsegs); 1005 counter_u64_add(rx_ring->rx_stats.dma_mapping_err, 1); 1006 goto exit; 1007 1008 } 1009 1010 bus_dmamap_sync(adapter->sc_dmat, rx_info->map, 0, 1011 rx_info->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1012 1013 ena_buf = &rx_info->ena_buf; 1014 ena_buf->paddr = rx_info->map->dm_segs[0].ds_addr; 1015 ena_buf->len = mlen; 1016 1017 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1018 "ALLOC RX BUF: mbuf %p, rx_info %p, len %d, paddr %#jx\n", 1019 rx_info->mbuf, rx_info,ena_buf->len, (uintmax_t)ena_buf->paddr); 1020 1021 return (0); 1022 1023 exit: 1024 m_freem(rx_info->mbuf); 1025 rx_info->mbuf = NULL; 1026 return (EFAULT); 1027 } 1028 1029 static void 1030 ena_free_rx_mbuf(struct ena_adapter *adapter, struct ena_ring *rx_ring, 1031 struct ena_rx_buffer *rx_info) 1032 { 1033 1034 if (rx_info->mbuf == NULL) { 1035 ena_trace(ENA_WARNING, "Trying to free unallocated buffer\n"); 1036 return; 1037 } 1038 1039 bus_dmamap_unload(adapter->sc_dmat, rx_info->map); 1040 m_freem(rx_info->mbuf); 1041 rx_info->mbuf = NULL; 1042 } 1043 1044 /** 1045 * ena_refill_rx_bufs - Refills ring with descriptors 1046 * @rx_ring: the ring which we want to feed with free descriptors 1047 * @num: number of descriptors to refill 1048 * Refills the ring with newly allocated DMA-mapped mbufs for receiving 1049 **/ 1050 static int 1051 ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num) 1052 { 1053 struct ena_adapter *adapter = rx_ring->adapter; 1054 uint16_t next_to_use, req_id; 1055 uint32_t i; 1056 int rc; 1057 1058 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, "refill qid: %d", 1059 rx_ring->qid); 1060 1061 next_to_use = rx_ring->next_to_use; 1062 1063 for (i = 0; i < num; i++) { 1064 struct ena_rx_buffer *rx_info; 1065 1066 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, 1067 "RX buffer - next to use: %d", next_to_use); 1068 1069 req_id = rx_ring->free_rx_ids[next_to_use]; 1070 rc = validate_rx_req_id(rx_ring, req_id); 1071 if (unlikely(rc != 0)) 1072 break; 1073 1074 rx_info = &rx_ring->rx_buffer_info[req_id]; 1075 1076 rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info); 1077 if (unlikely(rc != 0)) { 1078 ena_trace(ENA_WARNING, 1079 "failed to alloc buffer for rx queue %d\n", 1080 rx_ring->qid); 1081 break; 1082 } 1083 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 1084 &rx_info->ena_buf, req_id); 1085 if (unlikely(rc != 0)) { 1086 ena_trace(ENA_WARNING, 1087 "failed to add buffer for rx queue %d\n", 1088 rx_ring->qid); 1089 break; 1090 } 1091 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 1092 rx_ring->ring_size); 1093 } 1094 1095 if (unlikely(i < num)) { 1096 counter_u64_add(rx_ring->rx_stats.refil_partial, 1); 1097 ena_trace(ENA_WARNING, 1098 "refilled rx qid %d with only %d mbufs (from %d)\n", 1099 rx_ring->qid, i, num); 1100 } 1101 1102 if (likely(i != 0)) { 1103 wmb(); 1104 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 1105 } 1106 rx_ring->next_to_use = next_to_use; 1107 return (i); 1108 } 1109 1110 static void 1111 ena_free_rx_bufs(struct ena_adapter *adapter, unsigned int qid) 1112 { 1113 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 1114 unsigned int i; 1115 1116 for (i = 0; i < rx_ring->ring_size; i++) { 1117 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 1118 1119 if (rx_info->mbuf != NULL) 1120 ena_free_rx_mbuf(adapter, rx_ring, rx_info); 1121 } 1122 } 1123 1124 /** 1125 * ena_refill_all_rx_bufs - allocate all queues Rx buffers 1126 * @adapter: network interface device structure 1127 * 1128 */ 1129 static void 1130 ena_refill_all_rx_bufs(struct ena_adapter *adapter) 1131 { 1132 struct ena_ring *rx_ring; 1133 int i, rc, bufs_num; 1134 1135 for (i = 0; i < adapter->num_queues; i++) { 1136 rx_ring = &adapter->rx_ring[i]; 1137 bufs_num = rx_ring->ring_size - 1; 1138 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 1139 1140 if (unlikely(rc != bufs_num)) 1141 ena_trace(ENA_WARNING, "refilling Queue %d failed. " 1142 "Allocated %d buffers from: %d\n", i, rc, bufs_num); 1143 } 1144 } 1145 1146 static void 1147 ena_free_all_rx_bufs(struct ena_adapter *adapter) 1148 { 1149 int i; 1150 1151 for (i = 0; i < adapter->num_queues; i++) 1152 ena_free_rx_bufs(adapter, i); 1153 } 1154 1155 /** 1156 * ena_free_tx_bufs - Free Tx Buffers per Queue 1157 * @adapter: network interface device structure 1158 * @qid: queue index 1159 **/ 1160 static void 1161 ena_free_tx_bufs(struct ena_adapter *adapter, unsigned int qid) 1162 { 1163 bool print_once = true; 1164 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 1165 1166 ENA_RING_MTX_LOCK(tx_ring); 1167 for (int i = 0; i < tx_ring->ring_size; i++) { 1168 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 1169 1170 if (tx_info->mbuf == NULL) 1171 continue; 1172 1173 if (print_once) { 1174 device_printf(adapter->pdev, 1175 "free uncompleted tx mbuf qid %d idx 0x%x", 1176 qid, i); 1177 print_once = false; 1178 } else { 1179 ena_trace(ENA_DBG, 1180 "free uncompleted tx mbuf qid %d idx 0x%x", 1181 qid, i); 1182 } 1183 1184 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1185 m_free(tx_info->mbuf); 1186 tx_info->mbuf = NULL; 1187 } 1188 ENA_RING_MTX_UNLOCK(tx_ring); 1189 } 1190 1191 static void 1192 ena_free_all_tx_bufs(struct ena_adapter *adapter) 1193 { 1194 1195 for (int i = 0; i < adapter->num_queues; i++) 1196 ena_free_tx_bufs(adapter, i); 1197 } 1198 1199 static void 1200 ena_destroy_all_tx_queues(struct ena_adapter *adapter) 1201 { 1202 uint16_t ena_qid; 1203 int i; 1204 1205 for (i = 0; i < adapter->num_queues; i++) { 1206 ena_qid = ENA_IO_TXQ_IDX(i); 1207 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1208 } 1209 } 1210 1211 static void 1212 ena_destroy_all_rx_queues(struct ena_adapter *adapter) 1213 { 1214 uint16_t ena_qid; 1215 int i; 1216 1217 for (i = 0; i < adapter->num_queues; i++) { 1218 ena_qid = ENA_IO_RXQ_IDX(i); 1219 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1220 } 1221 } 1222 1223 static void 1224 ena_destroy_all_io_queues(struct ena_adapter *adapter) 1225 { 1226 ena_destroy_all_tx_queues(adapter); 1227 ena_destroy_all_rx_queues(adapter); 1228 } 1229 1230 static inline int 1231 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 1232 { 1233 struct ena_adapter *adapter = tx_ring->adapter; 1234 struct ena_tx_buffer *tx_info = NULL; 1235 1236 if (likely(req_id < tx_ring->ring_size)) { 1237 tx_info = &tx_ring->tx_buffer_info[req_id]; 1238 if (tx_info->mbuf != NULL) 1239 return (0); 1240 } 1241 1242 if (tx_info->mbuf == NULL) 1243 device_printf(adapter->pdev, 1244 "tx_info doesn't have valid mbuf\n"); 1245 else 1246 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 1247 1248 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 1249 1250 return (EFAULT); 1251 } 1252 1253 static int 1254 ena_create_io_queues(struct ena_adapter *adapter) 1255 { 1256 struct ena_com_dev *ena_dev = adapter->ena_dev; 1257 struct ena_com_create_io_ctx ctx; 1258 struct ena_ring *ring; 1259 uint16_t ena_qid; 1260 uint32_t msix_vector; 1261 int rc, i; 1262 1263 /* Create TX queues */ 1264 for (i = 0; i < adapter->num_queues; i++) { 1265 msix_vector = ENA_IO_IRQ_IDX(i); 1266 ena_qid = ENA_IO_TXQ_IDX(i); 1267 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1268 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1269 ctx.queue_size = adapter->tx_ring_size; 1270 ctx.msix_vector = msix_vector; 1271 ctx.qid = ena_qid; 1272 rc = ena_com_create_io_queue(ena_dev, &ctx); 1273 if (rc != 0) { 1274 device_printf(adapter->pdev, 1275 "Failed to create io TX queue #%d rc: %d\n", i, rc); 1276 goto err_tx; 1277 } 1278 ring = &adapter->tx_ring[i]; 1279 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1280 &ring->ena_com_io_sq, 1281 &ring->ena_com_io_cq); 1282 if (rc != 0) { 1283 device_printf(adapter->pdev, 1284 "Failed to get TX queue handlers. TX queue num" 1285 " %d rc: %d\n", i, rc); 1286 ena_com_destroy_io_queue(ena_dev, ena_qid); 1287 goto err_tx; 1288 } 1289 } 1290 1291 /* Create RX queues */ 1292 for (i = 0; i < adapter->num_queues; i++) { 1293 msix_vector = ENA_IO_IRQ_IDX(i); 1294 ena_qid = ENA_IO_RXQ_IDX(i); 1295 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1296 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1297 ctx.queue_size = adapter->rx_ring_size; 1298 ctx.msix_vector = msix_vector; 1299 ctx.qid = ena_qid; 1300 rc = ena_com_create_io_queue(ena_dev, &ctx); 1301 if (unlikely(rc != 0)) { 1302 device_printf(adapter->pdev, 1303 "Failed to create io RX queue[%d] rc: %d\n", i, rc); 1304 goto err_rx; 1305 } 1306 1307 ring = &adapter->rx_ring[i]; 1308 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1309 &ring->ena_com_io_sq, 1310 &ring->ena_com_io_cq); 1311 if (unlikely(rc != 0)) { 1312 device_printf(adapter->pdev, 1313 "Failed to get RX queue handlers. RX queue num" 1314 " %d rc: %d\n", i, rc); 1315 ena_com_destroy_io_queue(ena_dev, ena_qid); 1316 goto err_rx; 1317 } 1318 } 1319 1320 return (0); 1321 1322 err_rx: 1323 while (i--) 1324 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1325 i = adapter->num_queues; 1326 err_tx: 1327 while (i--) 1328 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1329 1330 return (ENXIO); 1331 } 1332 1333 /** 1334 * ena_tx_cleanup - clear sent packets and corresponding descriptors 1335 * @tx_ring: ring for which we want to clean packets 1336 * 1337 * Once packets are sent, we ask the device in a loop for no longer used 1338 * descriptors. We find the related mbuf chain in a map (index in an array) 1339 * and free it, then update ring state. 1340 * This is performed in "endless" loop, updating ring pointers every 1341 * TX_COMMIT. The first check of free descriptor is performed before the actual 1342 * loop, then repeated at the loop end. 1343 **/ 1344 static int 1345 ena_tx_cleanup(struct ena_ring *tx_ring) 1346 { 1347 struct ena_adapter *adapter; 1348 struct ena_com_io_cq* io_cq; 1349 uint16_t next_to_clean; 1350 uint16_t req_id; 1351 uint16_t ena_qid; 1352 unsigned int total_done = 0; 1353 int rc; 1354 int commit = TX_COMMIT; 1355 int budget = TX_BUDGET; 1356 int work_done; 1357 1358 adapter = tx_ring->que->adapter; 1359 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1360 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1361 next_to_clean = tx_ring->next_to_clean; 1362 1363 do { 1364 struct ena_tx_buffer *tx_info; 1365 struct mbuf *mbuf; 1366 1367 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 1368 if (unlikely(rc != 0)) 1369 break; 1370 1371 rc = validate_tx_req_id(tx_ring, req_id); 1372 if (unlikely(rc != 0)) 1373 break; 1374 1375 tx_info = &tx_ring->tx_buffer_info[req_id]; 1376 1377 mbuf = tx_info->mbuf; 1378 1379 tx_info->mbuf = NULL; 1380 bintime_clear(&tx_info->timestamp); 1381 1382 if (likely(tx_info->num_of_bufs != 0)) { 1383 /* Map is no longer required */ 1384 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1385 } 1386 1387 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed", 1388 tx_ring->qid, mbuf); 1389 1390 m_freem(mbuf); 1391 1392 total_done += tx_info->tx_descs; 1393 1394 tx_ring->free_tx_ids[next_to_clean] = req_id; 1395 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 1396 tx_ring->ring_size); 1397 1398 if (unlikely(--commit == 0)) { 1399 commit = TX_COMMIT; 1400 /* update ring state every TX_COMMIT descriptor */ 1401 tx_ring->next_to_clean = next_to_clean; 1402 ena_com_comp_ack( 1403 &adapter->ena_dev->io_sq_queues[ena_qid], 1404 total_done); 1405 ena_com_update_dev_comp_head(io_cq); 1406 total_done = 0; 1407 } 1408 } while (likely(--budget)); 1409 1410 work_done = TX_BUDGET - budget; 1411 1412 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d", 1413 tx_ring->qid, work_done); 1414 1415 /* If there is still something to commit update ring state */ 1416 if (likely(commit != TX_COMMIT)) { 1417 tx_ring->next_to_clean = next_to_clean; 1418 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 1419 total_done); 1420 ena_com_update_dev_comp_head(io_cq); 1421 } 1422 1423 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 1424 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, NULL); 1425 1426 return (work_done); 1427 } 1428 1429 #if 0 1430 static void 1431 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1432 struct mbuf *mbuf) 1433 { 1434 struct ena_adapter *adapter = rx_ring->adapter; 1435 1436 if (likely(adapter->rss_support)) { 1437 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 1438 1439 if (ena_rx_ctx->frag && 1440 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 1441 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1442 return; 1443 } 1444 1445 switch (ena_rx_ctx->l3_proto) { 1446 case ENA_ETH_IO_L3_PROTO_IPV4: 1447 switch (ena_rx_ctx->l4_proto) { 1448 case ENA_ETH_IO_L4_PROTO_TCP: 1449 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 1450 break; 1451 case ENA_ETH_IO_L4_PROTO_UDP: 1452 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 1453 break; 1454 default: 1455 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 1456 } 1457 break; 1458 case ENA_ETH_IO_L3_PROTO_IPV6: 1459 switch (ena_rx_ctx->l4_proto) { 1460 case ENA_ETH_IO_L4_PROTO_TCP: 1461 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 1462 break; 1463 case ENA_ETH_IO_L4_PROTO_UDP: 1464 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 1465 break; 1466 default: 1467 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 1468 } 1469 break; 1470 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 1471 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1472 break; 1473 default: 1474 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1475 } 1476 } else { 1477 mbuf->m_pkthdr.flowid = rx_ring->qid; 1478 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1479 } 1480 } 1481 #endif 1482 1483 /** 1484 * ena_rx_mbuf - assemble mbuf from descriptors 1485 * @rx_ring: ring for which we want to clean packets 1486 * @ena_bufs: buffer info 1487 * @ena_rx_ctx: metadata for this packet(s) 1488 * @next_to_clean: ring pointer, will be updated only upon success 1489 * 1490 **/ 1491 static struct mbuf* 1492 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 1493 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 1494 { 1495 struct mbuf *mbuf; 1496 struct ena_rx_buffer *rx_info; 1497 struct ena_adapter *adapter; 1498 unsigned int descs = ena_rx_ctx->descs; 1499 uint16_t ntc, len, req_id, buf = 0; 1500 1501 ntc = *next_to_clean; 1502 adapter = rx_ring->adapter; 1503 rx_info = &rx_ring->rx_buffer_info[ntc]; 1504 1505 if (unlikely(rx_info->mbuf == NULL)) { 1506 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1507 return (NULL); 1508 } 1509 1510 len = ena_bufs[buf].len; 1511 req_id = ena_bufs[buf].req_id; 1512 rx_info = &rx_ring->rx_buffer_info[req_id]; 1513 1514 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx", 1515 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 1516 1517 mbuf = rx_info->mbuf; 1518 KASSERT(mbuf->m_flags & M_PKTHDR); 1519 mbuf->m_pkthdr.len = len; 1520 mbuf->m_len = len; 1521 m_set_rcvif(mbuf, rx_ring->que->adapter->ifp); 1522 1523 /* Fill mbuf with hash key and it's interpretation for optimization */ 1524 #if 0 1525 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 1526 #endif 1527 1528 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf 0x%p, flags=0x%x, len: %d", 1529 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 1530 1531 /* DMA address is not needed anymore, unmap it */ 1532 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1533 1534 rx_info->mbuf = NULL; 1535 rx_ring->free_rx_ids[ntc] = req_id; 1536 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1537 1538 /* 1539 * While we have more than 1 descriptors for one rcvd packet, append 1540 * other mbufs to the main one 1541 */ 1542 while (--descs) { 1543 ++buf; 1544 len = ena_bufs[buf].len; 1545 req_id = ena_bufs[buf].req_id; 1546 rx_info = &rx_ring->rx_buffer_info[req_id]; 1547 1548 if (unlikely(rx_info->mbuf == NULL)) { 1549 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1550 /* 1551 * If one of the required mbufs was not allocated yet, 1552 * we can break there. 1553 * All earlier used descriptors will be reallocated 1554 * later and not used mbufs can be reused. 1555 * The next_to_clean pointer will not be updated in case 1556 * of an error, so caller should advance it manually 1557 * in error handling routine to keep it up to date 1558 * with hw ring. 1559 */ 1560 m_freem(mbuf); 1561 return (NULL); 1562 } 1563 1564 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 1565 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1566 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p", 1567 mbuf); 1568 } 1569 1570 ena_trace(ENA_DBG | ENA_RXPTH, 1571 "rx mbuf updated. len %d", mbuf->m_pkthdr.len); 1572 1573 /* Free already appended mbuf, it won't be useful anymore */ 1574 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1575 m_freem(rx_info->mbuf); 1576 rx_info->mbuf = NULL; 1577 1578 rx_ring->free_rx_ids[ntc] = req_id; 1579 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1580 } 1581 1582 *next_to_clean = ntc; 1583 1584 return (mbuf); 1585 } 1586 1587 /** 1588 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 1589 **/ 1590 static inline void 1591 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1592 struct mbuf *mbuf) 1593 { 1594 1595 /* IPv4 */ 1596 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { 1597 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1598 if (ena_rx_ctx->l3_csum_err) { 1599 /* ipv4 checksum error */ 1600 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1601 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1602 ena_trace(ENA_DBG, "RX IPv4 header checksum error"); 1603 return; 1604 } 1605 1606 /* TCP/UDP */ 1607 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1608 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1609 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv4 : M_CSUM_UDPv4; 1610 if (ena_rx_ctx->l4_csum_err) { 1611 /* TCP/UDP checksum error */ 1612 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1613 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1614 ena_trace(ENA_DBG, "RX L4 checksum error"); 1615 } 1616 } 1617 } 1618 /* IPv6 */ 1619 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { 1620 /* TCP/UDP */ 1621 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1622 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1623 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv6 : M_CSUM_UDPv6; 1624 if (ena_rx_ctx->l4_csum_err) { 1625 /* TCP/UDP checksum error */ 1626 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1627 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1628 ena_trace(ENA_DBG, "RX L4 checksum error"); 1629 } 1630 } 1631 } 1632 } 1633 1634 static void 1635 ena_deferred_rx_cleanup(struct work *wk, void *arg) 1636 { 1637 struct ena_ring *rx_ring = arg; 1638 int budget = CLEAN_BUDGET; 1639 1640 atomic_swap_uint(&rx_ring->task_pending, 0); 1641 1642 ENA_RING_MTX_LOCK(rx_ring); 1643 /* 1644 * If deferred task was executed, perform cleanup of all awaiting 1645 * descs (or until given budget is depleted to avoid infinite loop). 1646 */ 1647 while (likely(budget--)) { 1648 if (ena_rx_cleanup(rx_ring) == 0) 1649 break; 1650 } 1651 ENA_RING_MTX_UNLOCK(rx_ring); 1652 } 1653 1654 /** 1655 * ena_rx_cleanup - handle rx irq 1656 * @arg: ring for which irq is being handled 1657 **/ 1658 static int 1659 ena_rx_cleanup(struct ena_ring *rx_ring) 1660 { 1661 struct ena_adapter *adapter; 1662 struct mbuf *mbuf; 1663 struct ena_com_rx_ctx ena_rx_ctx; 1664 struct ena_com_io_cq* io_cq; 1665 struct ena_com_io_sq* io_sq; 1666 struct ifnet *ifp; 1667 uint16_t ena_qid; 1668 uint16_t next_to_clean; 1669 uint32_t refill_required; 1670 uint32_t refill_threshold; 1671 uint32_t do_if_input = 0; 1672 unsigned int qid; 1673 int rc, i; 1674 int budget = RX_BUDGET; 1675 1676 adapter = rx_ring->que->adapter; 1677 ifp = adapter->ifp; 1678 qid = rx_ring->que->id; 1679 ena_qid = ENA_IO_RXQ_IDX(qid); 1680 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1681 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1682 next_to_clean = rx_ring->next_to_clean; 1683 1684 ena_trace(ENA_DBG, "rx: qid %d", qid); 1685 1686 do { 1687 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1688 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 1689 ena_rx_ctx.descs = 0; 1690 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 1691 1692 if (unlikely(rc != 0)) 1693 goto error; 1694 1695 if (unlikely(ena_rx_ctx.descs == 0)) 1696 break; 1697 1698 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 1699 "descs #: %d l3 proto %d l4 proto %d hash: %x", 1700 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1701 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1702 1703 /* Receive mbuf from the ring */ 1704 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 1705 &ena_rx_ctx, &next_to_clean); 1706 1707 /* Exit if we failed to retrieve a buffer */ 1708 if (unlikely(mbuf == NULL)) { 1709 for (i = 0; i < ena_rx_ctx.descs; ++i) { 1710 rx_ring->free_rx_ids[next_to_clean] = 1711 rx_ring->ena_bufs[i].req_id; 1712 next_to_clean = 1713 ENA_RX_RING_IDX_NEXT(next_to_clean, 1714 rx_ring->ring_size); 1715 1716 } 1717 break; 1718 } 1719 1720 if (((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) || 1721 ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) || 1722 ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) || 1723 ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) || 1724 ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0)) { 1725 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 1726 } 1727 1728 counter_enter(); 1729 counter_u64_add_protected(rx_ring->rx_stats.bytes, 1730 mbuf->m_pkthdr.len); 1731 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 1732 mbuf->m_pkthdr.len); 1733 counter_exit(); 1734 /* 1735 * LRO is only for IP/TCP packets and TCP checksum of the packet 1736 * should be computed by hardware. 1737 */ 1738 do_if_input = 1; 1739 #ifdef LRO 1740 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 1741 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 1742 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 1743 /* 1744 * Send to the stack if: 1745 * - LRO not enabled, or 1746 * - no LRO resources, or 1747 * - lro enqueue fails 1748 */ 1749 if ((rx_ring->lro.lro_cnt != 0) && 1750 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 1751 do_if_input = 0; 1752 } 1753 #endif 1754 if (do_if_input != 0) { 1755 ena_trace(ENA_DBG | ENA_RXPTH, 1756 "calling if_input() with mbuf %p", mbuf); 1757 if_percpuq_enqueue(ifp->if_percpuq, mbuf); 1758 } 1759 1760 counter_enter(); 1761 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 1762 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 1763 counter_exit(); 1764 } while (--budget); 1765 1766 rx_ring->next_to_clean = next_to_clean; 1767 1768 refill_required = ena_com_free_desc(io_sq); 1769 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1770 1771 if (refill_required > refill_threshold) { 1772 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1773 ena_refill_rx_bufs(rx_ring, refill_required); 1774 } 1775 1776 #ifdef LRO 1777 tcp_lro_flush_all(&rx_ring->lro); 1778 #endif 1779 1780 return (RX_BUDGET - budget); 1781 1782 error: 1783 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 1784 return (RX_BUDGET - budget); 1785 } 1786 1787 /********************************************************************* 1788 * 1789 * MSIX & Interrupt Service routine 1790 * 1791 **********************************************************************/ 1792 1793 /** 1794 * ena_handle_msix - MSIX Interrupt Handler for admin/async queue 1795 * @arg: interrupt number 1796 **/ 1797 static int 1798 ena_intr_msix_mgmnt(void *arg) 1799 { 1800 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1801 1802 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1803 if (likely(adapter->running)) 1804 ena_com_aenq_intr_handler(adapter->ena_dev, arg); 1805 1806 return 1; 1807 } 1808 1809 /** 1810 * ena_handle_msix - MSIX Interrupt Handler for Tx/Rx 1811 * @arg: interrupt number 1812 **/ 1813 static int 1814 ena_handle_msix(void *arg) 1815 { 1816 struct ena_que *que = arg; 1817 struct ena_adapter *adapter = que->adapter; 1818 struct ifnet *ifp = adapter->ifp; 1819 struct ena_ring *tx_ring; 1820 struct ena_ring *rx_ring; 1821 struct ena_com_io_cq* io_cq; 1822 struct ena_eth_io_intr_reg intr_reg; 1823 int qid, ena_qid; 1824 int txc, rxc, i; 1825 1826 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1827 return 0; 1828 1829 ena_trace(ENA_DBG, "MSI-X TX/RX routine"); 1830 1831 tx_ring = que->tx_ring; 1832 rx_ring = que->rx_ring; 1833 qid = que->id; 1834 ena_qid = ENA_IO_TXQ_IDX(qid); 1835 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1836 1837 for (i = 0; i < CLEAN_BUDGET; ++i) { 1838 /* 1839 * If lock cannot be acquired, then deferred cleanup task was 1840 * being executed and rx ring is being cleaned up in 1841 * another thread. 1842 */ 1843 if (likely(ENA_RING_MTX_TRYLOCK(rx_ring) != 0)) { 1844 rxc = ena_rx_cleanup(rx_ring); 1845 ENA_RING_MTX_UNLOCK(rx_ring); 1846 } else { 1847 rxc = 0; 1848 } 1849 1850 /* Protection from calling ena_tx_cleanup from ena_start_xmit */ 1851 ENA_RING_MTX_LOCK(tx_ring); 1852 txc = ena_tx_cleanup(tx_ring); 1853 ENA_RING_MTX_UNLOCK(tx_ring); 1854 1855 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1856 return 0; 1857 1858 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 1859 break; 1860 } 1861 1862 /* Signal that work is done and unmask interrupt */ 1863 ena_com_update_intr_reg(&intr_reg, 1864 RX_IRQ_INTERVAL, 1865 TX_IRQ_INTERVAL, 1866 true); 1867 ena_com_unmask_intr(io_cq, &intr_reg); 1868 1869 return 1; 1870 } 1871 1872 static int 1873 ena_enable_msix(struct ena_adapter *adapter) 1874 { 1875 int msix_req; 1876 int counts[PCI_INTR_TYPE_SIZE]; 1877 int max_type; 1878 1879 /* Reserved the max msix vectors we might need */ 1880 msix_req = ENA_MAX_MSIX_VEC(adapter->num_queues); 1881 1882 counts[PCI_INTR_TYPE_INTX] = 0; 1883 counts[PCI_INTR_TYPE_MSI] = 0; 1884 counts[PCI_INTR_TYPE_MSIX] = msix_req; 1885 max_type = PCI_INTR_TYPE_MSIX; 1886 1887 if (pci_intr_alloc(&adapter->sc_pa, &adapter->sc_intrs, counts, 1888 max_type) != 0) { 1889 aprint_error_dev(adapter->pdev, 1890 "failed to allocate interrupt\n"); 1891 return ENOSPC; 1892 } 1893 1894 adapter->sc_nintrs = counts[PCI_INTR_TYPE_MSIX]; 1895 1896 if (counts[PCI_INTR_TYPE_MSIX] != msix_req) { 1897 device_printf(adapter->pdev, 1898 "Enable only %d MSI-x (out of %d), reduce " 1899 "the number of queues\n", adapter->sc_nintrs, msix_req); 1900 adapter->num_queues = adapter->sc_nintrs - ENA_ADMIN_MSIX_VEC; 1901 } 1902 1903 return 0; 1904 } 1905 1906 #if 0 1907 static void 1908 ena_setup_io_intr(struct ena_adapter *adapter) 1909 { 1910 static int last_bind_cpu = -1; 1911 int irq_idx; 1912 1913 for (int i = 0; i < adapter->num_queues; i++) { 1914 irq_idx = ENA_IO_IRQ_IDX(i); 1915 1916 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1917 "%s-TxRx-%d", device_xname(adapter->pdev), i); 1918 adapter->irq_tbl[irq_idx].handler = ena_handle_msix; 1919 adapter->irq_tbl[irq_idx].data = &adapter->que[i]; 1920 adapter->irq_tbl[irq_idx].vector = 1921 adapter->msix_entries[irq_idx].vector; 1922 ena_trace(ENA_INFO | ENA_IOQ, "ena_setup_io_intr vector: %d\n", 1923 adapter->msix_entries[irq_idx].vector); 1924 #ifdef RSS 1925 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1926 rss_getcpu(i % rss_getnumbuckets()); 1927 #else 1928 /* 1929 * We still want to bind rings to the corresponding cpu 1930 * using something similar to the RSS round-robin technique. 1931 */ 1932 if (unlikely(last_bind_cpu < 0)) 1933 last_bind_cpu = CPU_FIRST(); 1934 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1935 last_bind_cpu; 1936 last_bind_cpu = CPU_NEXT(last_bind_cpu); 1937 #endif 1938 } 1939 } 1940 #endif 1941 1942 static int 1943 ena_request_mgmnt_irq(struct ena_adapter *adapter) 1944 { 1945 const char *intrstr; 1946 char intrbuf[PCI_INTRSTR_LEN]; 1947 char intr_xname[INTRDEVNAMEBUF]; 1948 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 1949 const int irq_slot = ENA_MGMNT_IRQ_IDX; 1950 1951 KASSERT(adapter->sc_intrs != NULL); 1952 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 1953 1954 snprintf(intr_xname, sizeof(intr_xname), "%s mgmnt", 1955 device_xname(adapter->pdev)); 1956 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 1957 intrbuf, sizeof(intrbuf)); 1958 1959 adapter->sc_ihs[irq_slot] = pci_intr_establish_xname( 1960 pc, adapter->sc_intrs[irq_slot], 1961 IPL_NET, ena_intr_msix_mgmnt, adapter, intr_xname); 1962 1963 if (adapter->sc_ihs[irq_slot] == NULL) { 1964 device_printf(adapter->pdev, "failed to register " 1965 "interrupt handler for MGMNT irq %s\n", 1966 intrstr); 1967 return ENOMEM; 1968 } 1969 1970 aprint_normal_dev(adapter->pdev, 1971 "for MGMNT interrupting at %s\n", intrstr); 1972 1973 return 0; 1974 } 1975 1976 static int 1977 ena_request_io_irq(struct ena_adapter *adapter) 1978 { 1979 const char *intrstr; 1980 char intrbuf[PCI_INTRSTR_LEN]; 1981 char intr_xname[INTRDEVNAMEBUF]; 1982 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 1983 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 1984 void *vih; 1985 kcpuset_t *affinity; 1986 int i; 1987 1988 KASSERT(adapter->sc_intrs != NULL); 1989 1990 kcpuset_create(&affinity, false); 1991 1992 for (i = 0; i < adapter->num_queues; i++) { 1993 int irq_slot = i + irq_off; 1994 int affinity_to = (irq_slot) % ncpu; 1995 1996 KASSERT((void *)adapter->sc_intrs[irq_slot] != NULL); 1997 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 1998 1999 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 2000 device_xname(adapter->pdev), i); 2001 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 2002 intrbuf, sizeof(intrbuf)); 2003 2004 vih = pci_intr_establish_xname(adapter->sc_pa.pa_pc, 2005 adapter->sc_intrs[irq_slot], IPL_NET, 2006 ena_handle_msix, &adapter->que[i], intr_xname); 2007 2008 if (adapter->sc_ihs[ENA_MGMNT_IRQ_IDX] == NULL) { 2009 device_printf(adapter->pdev, "failed to register " 2010 "interrupt handler for IO queue %d irq %s\n", 2011 i, intrstr); 2012 goto err; 2013 } 2014 2015 kcpuset_zero(affinity); 2016 /* Round-robin affinity */ 2017 kcpuset_set(affinity, affinity_to); 2018 int error = interrupt_distribute(vih, affinity, NULL); 2019 if (error == 0) { 2020 aprint_normal_dev(adapter->pdev, 2021 "for IO queue %d interrupting at %s" 2022 " affinity to %u\n", i, intrstr, affinity_to); 2023 } else { 2024 aprint_normal_dev(adapter->pdev, 2025 "for IO queue %d interrupting at %s\n", i, intrstr); 2026 } 2027 2028 adapter->sc_ihs[irq_slot] = vih; 2029 2030 #ifdef RSS 2031 ena_trace(ENA_INFO, "queue %d - RSS bucket %d\n", 2032 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2033 #else 2034 ena_trace(ENA_INFO, "queue %d - cpu %d\n", 2035 i - ENA_IO_IRQ_FIRST_IDX, affinity_to); 2036 #endif 2037 } 2038 2039 kcpuset_destroy(affinity); 2040 return 0; 2041 2042 err: 2043 kcpuset_destroy(affinity); 2044 2045 for (i--; i >= 0; i--) { 2046 #if defined(DEBUG) || defined(DIAGNOSTIC) 2047 int irq_slot = i + irq_off; 2048 #endif 2049 KASSERT(adapter->sc_ihs[irq_slot] != NULL); 2050 pci_intr_disestablish(adapter->sc_pa.pa_pc, adapter->sc_ihs[i]); 2051 adapter->sc_ihs[i] = NULL; 2052 } 2053 2054 return ENOSPC; 2055 } 2056 2057 static void 2058 ena_free_mgmnt_irq(struct ena_adapter *adapter) 2059 { 2060 const int irq_slot = ENA_MGMNT_IRQ_IDX; 2061 2062 if (adapter->sc_ihs[irq_slot]) { 2063 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2064 adapter->sc_ihs[irq_slot]); 2065 adapter->sc_ihs[irq_slot] = NULL; 2066 } 2067 } 2068 2069 static void 2070 ena_free_io_irq(struct ena_adapter *adapter) 2071 { 2072 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2073 2074 for (int i = 0; i < adapter->num_queues; i++) { 2075 int irq_slot = i + irq_off; 2076 2077 if (adapter->sc_ihs[irq_slot]) { 2078 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2079 adapter->sc_ihs[i]); 2080 adapter->sc_ihs[i] = NULL; 2081 } 2082 } 2083 } 2084 2085 static void 2086 ena_free_irqs(struct ena_adapter* adapter) 2087 { 2088 2089 ena_free_io_irq(adapter); 2090 ena_free_mgmnt_irq(adapter); 2091 ena_disable_msix(adapter); 2092 } 2093 2094 static void 2095 ena_disable_msix(struct ena_adapter *adapter) 2096 { 2097 pci_intr_release(adapter->sc_pa.pa_pc, adapter->sc_intrs, 2098 adapter->sc_nintrs); 2099 } 2100 2101 static void 2102 ena_unmask_all_io_irqs(struct ena_adapter *adapter) 2103 { 2104 struct ena_com_io_cq* io_cq; 2105 struct ena_eth_io_intr_reg intr_reg; 2106 uint16_t ena_qid; 2107 int i; 2108 2109 /* Unmask interrupts for all queues */ 2110 for (i = 0; i < adapter->num_queues; i++) { 2111 ena_qid = ENA_IO_TXQ_IDX(i); 2112 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 2113 ena_com_update_intr_reg(&intr_reg, 0, 0, true); 2114 ena_com_unmask_intr(io_cq, &intr_reg); 2115 } 2116 } 2117 2118 /* Configure the Rx forwarding */ 2119 static int 2120 ena_rss_configure(struct ena_adapter *adapter) 2121 { 2122 struct ena_com_dev *ena_dev = adapter->ena_dev; 2123 int rc; 2124 2125 /* Set indirect table */ 2126 rc = ena_com_indirect_table_set(ena_dev); 2127 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2128 return (rc); 2129 2130 /* Configure hash function (if supported) */ 2131 rc = ena_com_set_hash_function(ena_dev); 2132 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2133 return (rc); 2134 2135 /* Configure hash inputs (if supported) */ 2136 rc = ena_com_set_hash_ctrl(ena_dev); 2137 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2138 return (rc); 2139 2140 return (0); 2141 } 2142 2143 static int 2144 ena_up_complete(struct ena_adapter *adapter) 2145 { 2146 int rc; 2147 2148 if (likely(adapter->rss_support)) { 2149 rc = ena_rss_configure(adapter); 2150 if (rc != 0) 2151 return (rc); 2152 } 2153 2154 rc = ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu); 2155 if (unlikely(rc != 0)) 2156 return (rc); 2157 2158 ena_refill_all_rx_bufs(adapter); 2159 ena_reset_counters((struct evcnt *)&adapter->hw_stats, 2160 sizeof(adapter->hw_stats)); 2161 2162 return (0); 2163 } 2164 2165 static int 2166 ena_up(struct ena_adapter *adapter) 2167 { 2168 int rc = 0; 2169 2170 #if 0 2171 if (unlikely(device_is_attached(adapter->pdev) == 0)) { 2172 device_printf(adapter->pdev, "device is not attached!\n"); 2173 return (ENXIO); 2174 } 2175 #endif 2176 2177 if (unlikely(!adapter->running)) { 2178 device_printf(adapter->pdev, "device is not running!\n"); 2179 return (ENXIO); 2180 } 2181 2182 if (!adapter->up) { 2183 device_printf(adapter->pdev, "device is going UP\n"); 2184 2185 /* setup interrupts for IO queues */ 2186 rc = ena_request_io_irq(adapter); 2187 if (unlikely(rc != 0)) { 2188 ena_trace(ENA_ALERT, "err_req_irq"); 2189 goto err_req_irq; 2190 } 2191 2192 /* allocate transmit descriptors */ 2193 rc = ena_setup_all_tx_resources(adapter); 2194 if (unlikely(rc != 0)) { 2195 ena_trace(ENA_ALERT, "err_setup_tx"); 2196 goto err_setup_tx; 2197 } 2198 2199 /* allocate receive descriptors */ 2200 rc = ena_setup_all_rx_resources(adapter); 2201 if (unlikely(rc != 0)) { 2202 ena_trace(ENA_ALERT, "err_setup_rx"); 2203 goto err_setup_rx; 2204 } 2205 2206 /* create IO queues for Rx & Tx */ 2207 rc = ena_create_io_queues(adapter); 2208 if (unlikely(rc != 0)) { 2209 ena_trace(ENA_ALERT, 2210 "create IO queues failed"); 2211 goto err_io_que; 2212 } 2213 2214 if (unlikely(adapter->link_status)) 2215 if_link_state_change(adapter->ifp, LINK_STATE_UP); 2216 2217 rc = ena_up_complete(adapter); 2218 if (unlikely(rc != 0)) 2219 goto err_up_complete; 2220 2221 counter_u64_add(adapter->dev_stats.interface_up, 1); 2222 2223 ena_update_hwassist(adapter); 2224 2225 if_setdrvflagbits(adapter->ifp, IFF_RUNNING, 2226 IFF_OACTIVE); 2227 2228 callout_reset(&adapter->timer_service, hz, 2229 ena_timer_service, (void *)adapter); 2230 2231 adapter->up = true; 2232 2233 ena_unmask_all_io_irqs(adapter); 2234 } 2235 2236 return (0); 2237 2238 err_up_complete: 2239 ena_destroy_all_io_queues(adapter); 2240 err_io_que: 2241 ena_free_all_rx_resources(adapter); 2242 err_setup_rx: 2243 ena_free_all_tx_resources(adapter); 2244 err_setup_tx: 2245 ena_free_io_irq(adapter); 2246 err_req_irq: 2247 return (rc); 2248 } 2249 2250 #if 0 2251 static uint64_t 2252 ena_get_counter(struct ifnet *ifp, ift_counter cnt) 2253 { 2254 struct ena_adapter *adapter; 2255 struct ena_hw_stats *stats; 2256 2257 adapter = if_getsoftc(ifp); 2258 stats = &adapter->hw_stats; 2259 2260 switch (cnt) { 2261 case IFCOUNTER_IPACKETS: 2262 return (counter_u64_fetch(stats->rx_packets)); 2263 case IFCOUNTER_OPACKETS: 2264 return (counter_u64_fetch(stats->tx_packets)); 2265 case IFCOUNTER_IBYTES: 2266 return (counter_u64_fetch(stats->rx_bytes)); 2267 case IFCOUNTER_OBYTES: 2268 return (counter_u64_fetch(stats->tx_bytes)); 2269 case IFCOUNTER_IQDROPS: 2270 return (counter_u64_fetch(stats->rx_drops)); 2271 default: 2272 return (if_get_counter_default(ifp, cnt)); 2273 } 2274 } 2275 #endif 2276 2277 static int 2278 ena_media_change(struct ifnet *ifp) 2279 { 2280 /* Media Change is not supported by firmware */ 2281 return (0); 2282 } 2283 2284 static void 2285 ena_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2286 { 2287 struct ena_adapter *adapter = if_getsoftc(ifp); 2288 ena_trace(ENA_DBG, "enter"); 2289 2290 mutex_enter(&adapter->global_mtx); 2291 2292 ifmr->ifm_status = IFM_AVALID; 2293 ifmr->ifm_active = IFM_ETHER; 2294 2295 if (!adapter->link_status) { 2296 mutex_exit(&adapter->global_mtx); 2297 ena_trace(ENA_INFO, "link_status = false"); 2298 return; 2299 } 2300 2301 ifmr->ifm_status |= IFM_ACTIVE; 2302 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2303 2304 mutex_exit(&adapter->global_mtx); 2305 } 2306 2307 static int 2308 ena_init(struct ifnet *ifp) 2309 { 2310 struct ena_adapter *adapter = if_getsoftc(ifp); 2311 2312 if (!adapter->up) { 2313 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2314 ena_up(adapter); 2315 rw_exit(&adapter->ioctl_sx); 2316 } 2317 2318 return 0; 2319 } 2320 2321 static int 2322 ena_ioctl(struct ifnet *ifp, u_long command, void *data) 2323 { 2324 struct ena_adapter *adapter; 2325 struct ifreq *ifr; 2326 int rc; 2327 2328 adapter = ifp->if_softc; 2329 ifr = (struct ifreq *)data; 2330 2331 /* 2332 * Acquiring lock to prevent from running up and down routines parallel. 2333 */ 2334 rc = 0; 2335 switch (command) { 2336 case SIOCSIFMTU: 2337 if (ifp->if_mtu == ifr->ifr_mtu) 2338 break; 2339 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2340 ena_down(adapter); 2341 2342 ena_change_mtu(ifp, ifr->ifr_mtu); 2343 2344 rc = ena_up(adapter); 2345 rw_exit(&adapter->ioctl_sx); 2346 break; 2347 2348 case SIOCSIFFLAGS: 2349 if ((ifp->if_flags & IFF_UP) != 0) { 2350 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2351 if ((ifp->if_flags & (IFF_PROMISC | 2352 IFF_ALLMULTI)) != 0) { 2353 device_printf(adapter->pdev, 2354 "ioctl promisc/allmulti\n"); 2355 } 2356 } else { 2357 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2358 rc = ena_up(adapter); 2359 rw_exit(&adapter->ioctl_sx); 2360 } 2361 } else { 2362 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2363 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2364 ena_down(adapter); 2365 rw_exit(&adapter->ioctl_sx); 2366 } 2367 } 2368 break; 2369 2370 case SIOCADDMULTI: 2371 case SIOCDELMULTI: 2372 break; 2373 2374 case SIOCSIFCAP: 2375 { 2376 struct ifcapreq *ifcr = data; 2377 int reinit = 0; 2378 2379 if (ifcr->ifcr_capenable != ifp->if_capenable) { 2380 ifp->if_capenable = ifcr->ifcr_capenable; 2381 reinit = 1; 2382 } 2383 2384 if ((reinit != 0) && 2385 ((if_getdrvflags(ifp) & IFF_RUNNING) != 0)) { 2386 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2387 ena_down(adapter); 2388 rc = ena_up(adapter); 2389 rw_exit(&adapter->ioctl_sx); 2390 } 2391 } 2392 2393 break; 2394 default: 2395 rc = ether_ioctl(ifp, command, data); 2396 break; 2397 } 2398 2399 return (rc); 2400 } 2401 2402 static int 2403 ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *feat) 2404 { 2405 int caps = 0; 2406 2407 if ((feat->offload.tx & 2408 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2409 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK | 2410 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)) != 0) 2411 caps |= IFCAP_CSUM_IPv4_Tx; 2412 2413 if ((feat->offload.tx & 2414 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK | 2415 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)) != 0) 2416 caps |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 2417 2418 if ((feat->offload.tx & 2419 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0) 2420 caps |= IFCAP_TSOv4; 2421 2422 if ((feat->offload.tx & 2423 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) != 0) 2424 caps |= IFCAP_TSOv6; 2425 2426 if ((feat->offload.rx_supported & 2427 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK | 2428 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)) != 0) 2429 caps |= IFCAP_CSUM_IPv4_Rx; 2430 2431 if ((feat->offload.rx_supported & 2432 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) != 0) 2433 caps |= IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 2434 2435 caps |= IFCAP_LRO; 2436 2437 return (caps); 2438 } 2439 2440 static void 2441 ena_update_host_info(struct ena_admin_host_info *host_info, struct ifnet *ifp) 2442 { 2443 2444 host_info->supported_network_features[0] = 2445 (uint32_t)if_getcapabilities(ifp); 2446 } 2447 2448 static void 2449 ena_update_hwassist(struct ena_adapter *adapter) 2450 { 2451 struct ifnet *ifp = adapter->ifp; 2452 uint32_t feat = adapter->tx_offload_cap; 2453 int cap = if_getcapenable(ifp); 2454 int flags = 0; 2455 2456 if_clearhwassist(ifp); 2457 2458 if ((cap & (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2459 != 0) { 2460 if ((feat & 2461 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) != 0) 2462 flags |= M_CSUM_IPv4; 2463 if ((feat & 2464 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2465 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)) != 0) 2466 flags |= M_CSUM_TCPv4 | M_CSUM_UDPv4; 2467 } 2468 2469 if ((cap & IFCAP_CSUM_TCPv6_Tx) != 0) 2470 flags |= M_CSUM_TCPv6; 2471 2472 if ((cap & IFCAP_CSUM_UDPv6_Tx) != 0) 2473 flags |= M_CSUM_UDPv6; 2474 2475 if ((cap & IFCAP_TSOv4) != 0) 2476 flags |= M_CSUM_TSOv4; 2477 2478 if ((cap & IFCAP_TSOv6) != 0) 2479 flags |= M_CSUM_TSOv6; 2480 2481 if_sethwassistbits(ifp, flags, 0); 2482 } 2483 2484 static int 2485 ena_setup_ifnet(device_t pdev, struct ena_adapter *adapter, 2486 struct ena_com_dev_get_features_ctx *feat) 2487 { 2488 struct ifnet *ifp; 2489 int caps = 0; 2490 2491 ifp = adapter->ifp = &adapter->sc_ec.ec_if; 2492 if (unlikely(ifp == NULL)) { 2493 ena_trace(ENA_ALERT, "can not allocate ifnet structure\n"); 2494 return (ENXIO); 2495 } 2496 if_initname(ifp, "ena", device_unit(pdev)); 2497 if_setdev(ifp, pdev); 2498 if_setsoftc(ifp, adapter); 2499 2500 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2501 if_setinitfn(ifp, ena_init); 2502 if_settransmitfn(ifp, ena_mq_start); 2503 #if 0 2504 if_setqflushfn(ifp, ena_qflush); 2505 #endif 2506 if_setioctlfn(ifp, ena_ioctl); 2507 #if 0 2508 if_setgetcounterfn(ifp, ena_get_counter); 2509 #endif 2510 2511 if_setsendqlen(ifp, adapter->tx_ring_size); 2512 if_setsendqready(ifp); 2513 if_setmtu(ifp, ETHERMTU); 2514 if_setbaudrate(ifp, 0); 2515 /* Zeroize capabilities... */ 2516 if_setcapabilities(ifp, 0); 2517 if_setcapenable(ifp, 0); 2518 /* check hardware support */ 2519 caps = ena_get_dev_offloads(feat); 2520 /* ... and set them */ 2521 if_setcapabilitiesbit(ifp, caps, 0); 2522 adapter->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2523 2524 #if 0 2525 /* TSO parameters */ 2526 /* XXX no limits on NetBSD, guarded by virtue of dmamap load failing */ 2527 ifp->if_hw_tsomax = ENA_TSO_MAXSIZE - 2528 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2529 ifp->if_hw_tsomaxsegcount = adapter->max_tx_sgl_size - 1; 2530 ifp->if_hw_tsomaxsegsize = ENA_TSO_MAXSIZE; 2531 #endif 2532 2533 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2534 if_setcapenable(ifp, if_getcapabilities(ifp)); 2535 2536 /* 2537 * Specify the media types supported by this adapter and register 2538 * callbacks to update media and link information 2539 */ 2540 adapter->sc_ec.ec_ifmedia = &adapter->media; 2541 ifmedia_init(&adapter->media, IFM_IMASK, 2542 ena_media_change, ena_media_status); 2543 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2544 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2545 2546 if_attach(ifp); 2547 if_deferred_start_init(ifp, NULL); 2548 2549 ether_ifattach(ifp, adapter->mac_addr); 2550 2551 return (0); 2552 } 2553 2554 static void 2555 ena_down(struct ena_adapter *adapter) 2556 { 2557 int rc; 2558 2559 if (adapter->up) { 2560 device_printf(adapter->pdev, "device is going DOWN\n"); 2561 2562 callout_halt(&adapter->timer_service, &adapter->global_mtx); 2563 2564 adapter->up = false; 2565 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, 2566 IFF_RUNNING); 2567 2568 ena_free_io_irq(adapter); 2569 2570 if (adapter->trigger_reset) { 2571 rc = ena_com_dev_reset(adapter->ena_dev, 2572 adapter->reset_reason); 2573 if (unlikely(rc != 0)) 2574 device_printf(adapter->pdev, 2575 "Device reset failed\n"); 2576 } 2577 2578 ena_destroy_all_io_queues(adapter); 2579 2580 ena_free_all_tx_bufs(adapter); 2581 ena_free_all_rx_bufs(adapter); 2582 ena_free_all_tx_resources(adapter); 2583 ena_free_all_rx_resources(adapter); 2584 2585 counter_u64_add(adapter->dev_stats.interface_down, 1); 2586 } 2587 } 2588 2589 static void 2590 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf) 2591 { 2592 struct ena_com_tx_meta *ena_meta; 2593 struct ether_vlan_header *eh; 2594 u32 mss; 2595 bool offload; 2596 uint16_t etype; 2597 int ehdrlen; 2598 struct ip *ip; 2599 int iphlen; 2600 struct tcphdr *th; 2601 2602 offload = false; 2603 ena_meta = &ena_tx_ctx->ena_meta; 2604 2605 #if 0 2606 u32 mss = mbuf->m_pkthdr.tso_segsz; 2607 2608 if (mss != 0) 2609 offload = true; 2610 #else 2611 mss = mbuf->m_pkthdr.len; /* XXX don't have tso_segsz */ 2612 #endif 2613 2614 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) 2615 offload = true; 2616 2617 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 2618 offload = true; 2619 2620 if (!offload) { 2621 ena_tx_ctx->meta_valid = 0; 2622 return; 2623 } 2624 2625 /* Determine where frame payload starts. */ 2626 eh = mtod(mbuf, struct ether_vlan_header *); 2627 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2628 etype = ntohs(eh->evl_proto); 2629 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2630 } else { 2631 etype = htons(eh->evl_encap_proto); 2632 ehdrlen = ETHER_HDR_LEN; 2633 } 2634 2635 ip = (struct ip *)(mbuf->m_data + ehdrlen); 2636 iphlen = ip->ip_hl << 2; 2637 th = (struct tcphdr *)((vaddr_t)ip + iphlen); 2638 2639 if ((mbuf->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 2640 ena_tx_ctx->l3_csum_enable = 1; 2641 } 2642 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 2643 ena_tx_ctx->tso_enable = 1; 2644 ena_meta->l4_hdr_len = (th->th_off); 2645 } 2646 2647 switch (etype) { 2648 case ETHERTYPE_IP: 2649 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 2650 if ((ip->ip_off & htons(IP_DF)) != 0) 2651 ena_tx_ctx->df = 1; 2652 break; 2653 case ETHERTYPE_IPV6: 2654 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 2655 2656 default: 2657 break; 2658 } 2659 2660 if (ip->ip_p == IPPROTO_TCP) { 2661 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 2662 if ((mbuf->m_pkthdr.csum_flags & 2663 (M_CSUM_TCPv4 | M_CSUM_TCPv6)) != 0) 2664 ena_tx_ctx->l4_csum_enable = 1; 2665 else 2666 ena_tx_ctx->l4_csum_enable = 0; 2667 } else if (ip->ip_p == IPPROTO_UDP) { 2668 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 2669 if ((mbuf->m_pkthdr.csum_flags & 2670 (M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2671 ena_tx_ctx->l4_csum_enable = 1; 2672 else 2673 ena_tx_ctx->l4_csum_enable = 0; 2674 } else { 2675 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 2676 ena_tx_ctx->l4_csum_enable = 0; 2677 } 2678 2679 ena_meta->mss = mss; 2680 ena_meta->l3_hdr_len = iphlen; 2681 ena_meta->l3_hdr_offset = ehdrlen; 2682 ena_tx_ctx->meta_valid = 1; 2683 } 2684 2685 static int 2686 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2687 { 2688 struct ena_adapter *adapter; 2689 struct mbuf *collapsed_mbuf; 2690 int num_frags; 2691 2692 adapter = tx_ring->adapter; 2693 num_frags = ena_mbuf_count(*mbuf); 2694 2695 /* One segment must be reserved for configuration descriptor. */ 2696 if (num_frags < adapter->max_tx_sgl_size) 2697 return (0); 2698 counter_u64_add(tx_ring->tx_stats.collapse, 1); 2699 2700 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 2701 adapter->max_tx_sgl_size - 1); 2702 if (unlikely(collapsed_mbuf == NULL)) { 2703 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 2704 return (ENOMEM); 2705 } 2706 2707 /* If mbuf was collapsed succesfully, original mbuf is released. */ 2708 *mbuf = collapsed_mbuf; 2709 2710 return (0); 2711 } 2712 2713 static int 2714 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2715 { 2716 struct ena_adapter *adapter; 2717 struct ena_tx_buffer *tx_info; 2718 struct ena_com_tx_ctx ena_tx_ctx; 2719 struct ena_com_dev *ena_dev; 2720 struct ena_com_buf *ena_buf; 2721 struct ena_com_io_sq* io_sq; 2722 void *push_hdr; 2723 uint16_t next_to_use; 2724 uint16_t req_id; 2725 uint16_t ena_qid; 2726 uint32_t header_len; 2727 int i, rc; 2728 int nb_hw_desc; 2729 2730 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2731 adapter = tx_ring->que->adapter; 2732 ena_dev = adapter->ena_dev; 2733 io_sq = &ena_dev->io_sq_queues[ena_qid]; 2734 2735 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 2736 if (unlikely(rc != 0)) { 2737 ena_trace(ENA_WARNING, 2738 "Failed to collapse mbuf! err: %d", rc); 2739 return (rc); 2740 } 2741 2742 next_to_use = tx_ring->next_to_use; 2743 req_id = tx_ring->free_tx_ids[next_to_use]; 2744 tx_info = &tx_ring->tx_buffer_info[req_id]; 2745 2746 tx_info->mbuf = *mbuf; 2747 tx_info->num_of_bufs = 0; 2748 2749 ena_buf = tx_info->bufs; 2750 2751 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes", (*mbuf)->m_pkthdr.len); 2752 2753 /* 2754 * header_len is just a hint for the device. Because FreeBSD is not 2755 * giving us information about packet header length and it is not 2756 * guaranteed that all packet headers will be in the 1st mbuf, setting 2757 * header_len to 0 is making the device ignore this value and resolve 2758 * header on it's own. 2759 */ 2760 header_len = 0; 2761 push_hdr = NULL; 2762 2763 rc = bus_dmamap_load_mbuf(adapter->sc_dmat, tx_info->map, 2764 *mbuf, BUS_DMA_NOWAIT); 2765 2766 if (unlikely((rc != 0) || (tx_info->map->dm_nsegs == 0))) { 2767 ena_trace(ENA_WARNING, 2768 "dmamap load failed! err: %d nsegs: %d", rc, 2769 tx_info->map->dm_nsegs); 2770 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 2771 tx_info->mbuf = NULL; 2772 if (rc == ENOMEM) 2773 return (ENA_COM_NO_MEM); 2774 else 2775 return (ENA_COM_INVAL); 2776 } 2777 2778 for (i = 0; i < tx_info->map->dm_nsegs; i++) { 2779 ena_buf->len = tx_info->map->dm_segs[i].ds_len; 2780 ena_buf->paddr = tx_info->map->dm_segs[i].ds_addr; 2781 ena_buf++; 2782 } 2783 tx_info->num_of_bufs = tx_info->map->dm_nsegs; 2784 2785 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2786 ena_tx_ctx.ena_bufs = tx_info->bufs; 2787 ena_tx_ctx.push_header = push_hdr; 2788 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2789 ena_tx_ctx.req_id = req_id; 2790 ena_tx_ctx.header_len = header_len; 2791 2792 /* Set flags and meta data */ 2793 ena_tx_csum(&ena_tx_ctx, *mbuf); 2794 /* Prepare the packet's descriptors and send them to device */ 2795 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 2796 if (unlikely(rc != 0)) { 2797 device_printf(adapter->pdev, "failed to prepare tx bufs\n"); 2798 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 2799 goto dma_error; 2800 } 2801 2802 counter_enter(); 2803 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 2804 counter_u64_add_protected(tx_ring->tx_stats.bytes, 2805 (*mbuf)->m_pkthdr.len); 2806 2807 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 2808 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 2809 (*mbuf)->m_pkthdr.len); 2810 counter_exit(); 2811 2812 tx_info->tx_descs = nb_hw_desc; 2813 getbinuptime(&tx_info->timestamp); 2814 tx_info->print_once = true; 2815 2816 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2817 tx_ring->ring_size); 2818 2819 bus_dmamap_sync(adapter->sc_dmat, tx_info->map, 0, 2820 tx_info->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2821 2822 return (0); 2823 2824 dma_error: 2825 tx_info->mbuf = NULL; 2826 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 2827 2828 return (rc); 2829 } 2830 2831 static void 2832 ena_start_xmit(struct ena_ring *tx_ring) 2833 { 2834 struct mbuf *mbuf; 2835 struct ena_adapter *adapter = tx_ring->adapter; 2836 struct ena_com_io_sq* io_sq; 2837 int ena_qid; 2838 int acum_pkts = 0; 2839 int ret = 0; 2840 2841 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2842 return; 2843 2844 if (unlikely(!adapter->link_status)) 2845 return; 2846 2847 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2848 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 2849 2850 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 2851 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 2852 " header csum flags %#jx", 2853 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 2854 2855 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 2856 ENA_TX_CLEANUP_THRESHOLD))) 2857 ena_tx_cleanup(tx_ring); 2858 2859 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 2860 if (ret == ENA_COM_NO_MEM) { 2861 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2862 } else if (ret == ENA_COM_NO_SPACE) { 2863 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2864 } else { 2865 m_freem(mbuf); 2866 drbr_advance(adapter->ifp, tx_ring->br); 2867 } 2868 2869 break; 2870 } 2871 2872 drbr_advance(adapter->ifp, tx_ring->br); 2873 2874 if (unlikely((if_getdrvflags(adapter->ifp) & 2875 IFF_RUNNING) == 0)) 2876 return; 2877 2878 acum_pkts++; 2879 2880 /* 2881 * If there's a BPF listener, bounce a copy of this frame 2882 * to him. 2883 */ 2884 bpf_mtap(adapter->ifp, mbuf, BPF_D_OUT); 2885 2886 if (unlikely(acum_pkts == DB_THRESHOLD)) { 2887 acum_pkts = 0; 2888 wmb(); 2889 /* Trigger the dma engine */ 2890 ena_com_write_sq_doorbell(io_sq); 2891 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2892 } 2893 2894 } 2895 2896 if (likely(acum_pkts != 0)) { 2897 wmb(); 2898 /* Trigger the dma engine */ 2899 ena_com_write_sq_doorbell(io_sq); 2900 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2901 } 2902 2903 if (!ena_com_sq_have_enough_space(io_sq, ENA_TX_CLEANUP_THRESHOLD)) 2904 ena_tx_cleanup(tx_ring); 2905 } 2906 2907 static void 2908 ena_deferred_mq_start(struct work *wk, void *arg) 2909 { 2910 struct ena_ring *tx_ring = (struct ena_ring *)arg; 2911 struct ifnet *ifp = tx_ring->adapter->ifp; 2912 2913 atomic_swap_uint(&tx_ring->task_pending, 0); 2914 2915 while (!drbr_empty(ifp, tx_ring->br) && 2916 (if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2917 ENA_RING_MTX_LOCK(tx_ring); 2918 ena_start_xmit(tx_ring); 2919 ENA_RING_MTX_UNLOCK(tx_ring); 2920 } 2921 } 2922 2923 static int 2924 ena_mq_start(struct ifnet *ifp, struct mbuf *m) 2925 { 2926 struct ena_adapter *adapter = ifp->if_softc; 2927 struct ena_ring *tx_ring; 2928 int ret, is_drbr_empty; 2929 uint32_t i; 2930 2931 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2932 return (ENODEV); 2933 2934 /* Which queue to use */ 2935 /* 2936 * If everything is setup correctly, it should be the 2937 * same bucket that the current CPU we're on is. 2938 * It should improve performance. 2939 */ 2940 #if 0 2941 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 2942 #ifdef RSS 2943 if (rss_hash2bucket(m->m_pkthdr.flowid, 2944 M_HASHTYPE_GET(m), &i) == 0) { 2945 i = i % adapter->num_queues; 2946 2947 } else 2948 #endif 2949 { 2950 i = m->m_pkthdr.flowid % adapter->num_queues; 2951 } 2952 } else { 2953 #endif 2954 i = cpu_index(curcpu()) % adapter->num_queues; 2955 #if 0 2956 } 2957 #endif 2958 tx_ring = &adapter->tx_ring[i]; 2959 2960 /* Check if drbr is empty before putting packet */ 2961 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 2962 ret = drbr_enqueue(ifp, tx_ring->br, m); 2963 if (unlikely(ret != 0)) { 2964 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 2965 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 2966 curcpu()); 2967 return (ret); 2968 } 2969 2970 if ((is_drbr_empty != 0) && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 2971 ena_start_xmit(tx_ring); 2972 ENA_RING_MTX_UNLOCK(tx_ring); 2973 } else { 2974 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 2975 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 2976 curcpu()); 2977 } 2978 2979 return (0); 2980 } 2981 2982 #if 0 2983 static void 2984 ena_qflush(struct ifnet *ifp) 2985 { 2986 struct ena_adapter *adapter = ifp->if_softc; 2987 struct ena_ring *tx_ring = adapter->tx_ring; 2988 int i; 2989 2990 for(i = 0; i < adapter->num_queues; ++i, ++tx_ring) 2991 if (!drbr_empty(ifp, tx_ring->br)) { 2992 ENA_RING_MTX_LOCK(tx_ring); 2993 drbr_flush(ifp, tx_ring->br); 2994 ENA_RING_MTX_UNLOCK(tx_ring); 2995 } 2996 2997 if_qflush(ifp); 2998 } 2999 #endif 3000 3001 static int 3002 ena_calc_io_queue_num(struct pci_attach_args *pa, 3003 struct ena_adapter *adapter, 3004 struct ena_com_dev_get_features_ctx *get_feat_ctx) 3005 { 3006 int io_sq_num, io_cq_num, io_queue_num; 3007 3008 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 3009 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 3010 3011 io_queue_num = min_t(int, mp_ncpus, ENA_MAX_NUM_IO_QUEUES); 3012 io_queue_num = min_t(int, io_queue_num, io_sq_num); 3013 io_queue_num = min_t(int, io_queue_num, io_cq_num); 3014 /* 1 IRQ for for mgmnt and 1 IRQ for each TX/RX pair */ 3015 io_queue_num = min_t(int, io_queue_num, 3016 pci_msix_count(pa->pa_pc, pa->pa_tag) - 1); 3017 #ifdef RSS 3018 io_queue_num = min_t(int, io_queue_num, rss_getnumbuckets()); 3019 #endif 3020 3021 return (io_queue_num); 3022 } 3023 3024 static int 3025 ena_calc_queue_size(struct ena_adapter *adapter, uint16_t *max_tx_sgl_size, 3026 uint16_t *max_rx_sgl_size, struct ena_com_dev_get_features_ctx *feat) 3027 { 3028 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 3029 uint32_t v; 3030 uint32_t q; 3031 3032 queue_size = min_t(uint32_t, queue_size, 3033 feat->max_queues.max_cq_depth); 3034 queue_size = min_t(uint32_t, queue_size, 3035 feat->max_queues.max_sq_depth); 3036 3037 /* round down to the nearest power of 2 */ 3038 v = queue_size; 3039 while (v != 0) { 3040 if (powerof2(queue_size) != 0) 3041 break; 3042 v /= 2; 3043 q = rounddown2(queue_size, v); 3044 if (q != 0) { 3045 queue_size = q; 3046 break; 3047 } 3048 } 3049 3050 if (unlikely(queue_size == 0)) { 3051 device_printf(adapter->pdev, "Invalid queue size\n"); 3052 return (ENA_COM_FAULT); 3053 } 3054 3055 *max_tx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3056 feat->max_queues.max_packet_tx_descs); 3057 *max_rx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3058 feat->max_queues.max_packet_rx_descs); 3059 3060 return (queue_size); 3061 } 3062 3063 #if 0 3064 static int 3065 ena_rss_init_default(struct ena_adapter *adapter) 3066 { 3067 struct ena_com_dev *ena_dev = adapter->ena_dev; 3068 device_t dev = adapter->pdev; 3069 int qid, rc, i; 3070 3071 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3072 if (unlikely(rc != 0)) { 3073 device_printf(dev, "Cannot init indirect table\n"); 3074 return (rc); 3075 } 3076 3077 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3078 #ifdef RSS 3079 qid = rss_get_indirection_to_bucket(i); 3080 qid = qid % adapter->num_queues; 3081 #else 3082 qid = i % adapter->num_queues; 3083 #endif 3084 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3085 ENA_IO_RXQ_IDX(qid)); 3086 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3087 device_printf(dev, "Cannot fill indirect table\n"); 3088 goto err_rss_destroy; 3089 } 3090 } 3091 3092 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3093 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3094 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3095 device_printf(dev, "Cannot fill hash function\n"); 3096 goto err_rss_destroy; 3097 } 3098 3099 rc = ena_com_set_default_hash_ctrl(ena_dev); 3100 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3101 device_printf(dev, "Cannot fill hash control\n"); 3102 goto err_rss_destroy; 3103 } 3104 3105 return (0); 3106 3107 err_rss_destroy: 3108 ena_com_rss_destroy(ena_dev); 3109 return (rc); 3110 } 3111 3112 static void 3113 ena_rss_init_default_deferred(void *arg) 3114 { 3115 struct ena_adapter *adapter; 3116 devclass_t dc; 3117 int max; 3118 int rc; 3119 3120 dc = devclass_find("ena"); 3121 if (unlikely(dc == NULL)) { 3122 ena_trace(ENA_ALERT, "No devclass ena\n"); 3123 return; 3124 } 3125 3126 max = devclass_get_maxunit(dc); 3127 while (max-- >= 0) { 3128 adapter = devclass_get_softc(dc, max); 3129 if (adapter != NULL) { 3130 rc = ena_rss_init_default(adapter); 3131 adapter->rss_support = true; 3132 if (unlikely(rc != 0)) { 3133 device_printf(adapter->pdev, 3134 "WARNING: RSS was not properly initialized," 3135 " it will affect bandwidth\n"); 3136 adapter->rss_support = false; 3137 } 3138 } 3139 } 3140 } 3141 SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL); 3142 #endif 3143 3144 static void 3145 ena_config_host_info(struct ena_com_dev *ena_dev) 3146 { 3147 struct ena_admin_host_info *host_info; 3148 int rc; 3149 3150 /* Allocate only the host info */ 3151 rc = ena_com_allocate_host_info(ena_dev); 3152 if (unlikely(rc != 0)) { 3153 ena_trace(ENA_ALERT, "Cannot allocate host info\n"); 3154 return; 3155 } 3156 3157 host_info = ena_dev->host_attr.host_info; 3158 3159 host_info->os_type = ENA_ADMIN_OS_FREEBSD; 3160 host_info->kernel_ver = osreldate; 3161 3162 snprintf(host_info->kernel_ver_str, sizeof(host_info->kernel_ver_str), 3163 "%d", osreldate); 3164 host_info->os_dist = 0; 3165 strncpy(host_info->os_dist_str, osrelease, 3166 sizeof(host_info->os_dist_str) - 1); 3167 3168 host_info->driver_version = 3169 (DRV_MODULE_VER_MAJOR) | 3170 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 3171 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 3172 3173 rc = ena_com_set_host_attributes(ena_dev); 3174 if (unlikely(rc != 0)) { 3175 if (rc == EOPNOTSUPP) 3176 ena_trace(ENA_WARNING, "Cannot set host attributes\n"); 3177 else 3178 ena_trace(ENA_ALERT, "Cannot set host attributes\n"); 3179 3180 goto err; 3181 } 3182 3183 return; 3184 3185 err: 3186 ena_com_delete_host_info(ena_dev); 3187 } 3188 3189 static int 3190 ena_device_init(struct ena_adapter *adapter, device_t pdev, 3191 struct ena_com_dev_get_features_ctx *get_feat_ctx, int *wd_active) 3192 { 3193 struct ena_com_dev* ena_dev = adapter->ena_dev; 3194 bool readless_supported; 3195 uint32_t aenq_groups; 3196 int dma_width; 3197 int rc; 3198 3199 rc = ena_com_mmio_reg_read_request_init(ena_dev); 3200 if (unlikely(rc != 0)) { 3201 device_printf(pdev, "failed to init mmio read less\n"); 3202 return (rc); 3203 } 3204 3205 /* 3206 * The PCIe configuration space revision id indicate if mmio reg 3207 * read is disabled 3208 */ 3209 const int rev = PCI_REVISION(adapter->sc_pa.pa_class); 3210 readless_supported = ((rev & ENA_MMIO_DISABLE_REG_READ) == 0); 3211 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 3212 3213 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 3214 if (unlikely(rc != 0)) { 3215 device_printf(pdev, "Can not reset device\n"); 3216 goto err_mmio_read_less; 3217 } 3218 3219 rc = ena_com_validate_version(ena_dev); 3220 if (unlikely(rc != 0)) { 3221 device_printf(pdev, "device version is too low\n"); 3222 goto err_mmio_read_less; 3223 } 3224 3225 dma_width = ena_com_get_dma_width(ena_dev); 3226 if (unlikely(dma_width < 0)) { 3227 device_printf(pdev, "Invalid dma width value %d", dma_width); 3228 rc = dma_width; 3229 goto err_mmio_read_less; 3230 } 3231 adapter->dma_width = dma_width; 3232 3233 /* ENA admin level init */ 3234 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 3235 if (unlikely(rc != 0)) { 3236 device_printf(pdev, 3237 "Can not initialize ena admin queue with device\n"); 3238 goto err_mmio_read_less; 3239 } 3240 3241 /* 3242 * To enable the msix interrupts the driver needs to know the number 3243 * of queues. So the driver uses polling mode to retrieve this 3244 * information 3245 */ 3246 ena_com_set_admin_polling_mode(ena_dev, true); 3247 3248 ena_config_host_info(ena_dev); 3249 3250 /* Get Device Attributes */ 3251 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 3252 if (unlikely(rc != 0)) { 3253 device_printf(pdev, 3254 "Cannot get attribute for ena device rc: %d\n", rc); 3255 goto err_admin_init; 3256 } 3257 3258 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT(ENA_ADMIN_KEEP_ALIVE); 3259 3260 aenq_groups &= get_feat_ctx->aenq.supported_groups; 3261 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 3262 if (unlikely(rc != 0)) { 3263 device_printf(pdev, "Cannot configure aenq groups rc: %d\n", rc); 3264 goto err_admin_init; 3265 } 3266 3267 *wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 3268 3269 return (0); 3270 3271 err_admin_init: 3272 ena_com_delete_host_info(ena_dev); 3273 ena_com_admin_destroy(ena_dev); 3274 err_mmio_read_less: 3275 ena_com_mmio_reg_read_request_destroy(ena_dev); 3276 3277 return (rc); 3278 } 3279 3280 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 3281 int io_vectors) 3282 { 3283 struct ena_com_dev *ena_dev = adapter->ena_dev; 3284 int rc; 3285 3286 rc = ena_enable_msix(adapter); 3287 if (unlikely(rc != 0)) { 3288 device_printf(adapter->pdev, "Error with MSI-X enablement\n"); 3289 return (rc); 3290 } 3291 3292 rc = ena_request_mgmnt_irq(adapter); 3293 if (unlikely(rc != 0)) { 3294 device_printf(adapter->pdev, "Cannot setup mgmnt queue intr\n"); 3295 goto err_disable_msix; 3296 } 3297 3298 ena_com_set_admin_polling_mode(ena_dev, false); 3299 3300 ena_com_admin_aenq_enable(ena_dev); 3301 3302 return (0); 3303 3304 err_disable_msix: 3305 ena_disable_msix(adapter); 3306 3307 return (rc); 3308 } 3309 3310 /* Function called on ENA_ADMIN_KEEP_ALIVE event */ 3311 static void ena_keep_alive_wd(void *adapter_data, 3312 struct ena_admin_aenq_entry *aenq_e) 3313 { 3314 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3315 struct ena_admin_aenq_keep_alive_desc *desc; 3316 sbintime_t stime; 3317 uint64_t rx_drops; 3318 3319 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3320 3321 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3322 counter_u64_zero(adapter->hw_stats.rx_drops); 3323 counter_u64_add(adapter->hw_stats.rx_drops, rx_drops); 3324 3325 stime = getsbinuptime(); 3326 (void) atomic_swap_64(&adapter->keep_alive_timestamp, stime); 3327 } 3328 3329 /* Check for keep alive expiration */ 3330 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 3331 { 3332 sbintime_t timestamp, time; 3333 3334 if (adapter->wd_active == 0) 3335 return; 3336 3337 if (likely(adapter->keep_alive_timeout == 0)) 3338 return; 3339 3340 /* FreeBSD uses atomic_load_acq_64() in place of the membar + read */ 3341 membar_sync(); 3342 timestamp = adapter->keep_alive_timestamp; 3343 3344 time = getsbinuptime() - timestamp; 3345 if (unlikely(time > adapter->keep_alive_timeout)) { 3346 device_printf(adapter->pdev, 3347 "Keep alive watchdog timeout.\n"); 3348 counter_u64_add(adapter->dev_stats.wd_expired, 1); 3349 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 3350 adapter->trigger_reset = true; 3351 } 3352 } 3353 3354 /* Check if admin queue is enabled */ 3355 static void check_for_admin_com_state(struct ena_adapter *adapter) 3356 { 3357 if (unlikely(ena_com_get_admin_running_state(adapter->ena_dev) == 3358 false)) { 3359 device_printf(adapter->pdev, 3360 "ENA admin queue is not in running state!\n"); 3361 counter_u64_add(adapter->dev_stats.admin_q_pause, 1); 3362 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 3363 adapter->trigger_reset = true; 3364 } 3365 } 3366 3367 static int 3368 check_missing_comp_in_queue(struct ena_adapter *adapter, 3369 struct ena_ring *tx_ring) 3370 { 3371 struct bintime curtime, time; 3372 struct ena_tx_buffer *tx_buf; 3373 uint32_t missed_tx = 0; 3374 int i; 3375 3376 getbinuptime(&curtime); 3377 3378 for (i = 0; i < tx_ring->ring_size; i++) { 3379 tx_buf = &tx_ring->tx_buffer_info[i]; 3380 3381 if (bintime_isset(&tx_buf->timestamp) == 0) 3382 continue; 3383 3384 time = curtime; 3385 bintime_sub(&time, &tx_buf->timestamp); 3386 3387 /* Check again if packet is still waiting */ 3388 if (unlikely(bttosbt(time) > adapter->missing_tx_timeout)) { 3389 3390 if (!tx_buf->print_once) 3391 ena_trace(ENA_WARNING, "Found a Tx that wasn't " 3392 "completed on time, qid %d, index %d.\n", 3393 tx_ring->qid, i); 3394 3395 tx_buf->print_once = true; 3396 missed_tx++; 3397 counter_u64_add(tx_ring->tx_stats.missing_tx_comp, 1); 3398 3399 if (unlikely(missed_tx > 3400 adapter->missing_tx_threshold)) { 3401 device_printf(adapter->pdev, 3402 "The number of lost tx completion " 3403 "is above the threshold (%d > %d). " 3404 "Reset the device\n", 3405 missed_tx, adapter->missing_tx_threshold); 3406 adapter->reset_reason = 3407 ENA_REGS_RESET_MISS_TX_CMPL; 3408 adapter->trigger_reset = true; 3409 return (EIO); 3410 } 3411 } 3412 } 3413 3414 return (0); 3415 } 3416 3417 /* 3418 * Check for TX which were not completed on time. 3419 * Timeout is defined by "missing_tx_timeout". 3420 * Reset will be performed if number of incompleted 3421 * transactions exceeds "missing_tx_threshold". 3422 */ 3423 static void 3424 check_for_missing_tx_completions(struct ena_adapter *adapter) 3425 { 3426 struct ena_ring *tx_ring; 3427 int i, budget, rc; 3428 3429 /* Make sure the driver doesn't turn the device in other process */ 3430 rmb(); 3431 3432 if (!adapter->up) 3433 return; 3434 3435 if (adapter->trigger_reset) 3436 return; 3437 3438 if (adapter->missing_tx_timeout == 0) 3439 return; 3440 3441 budget = adapter->missing_tx_max_queues; 3442 3443 for (i = adapter->next_monitored_tx_qid; i < adapter->num_queues; i++) { 3444 tx_ring = &adapter->tx_ring[i]; 3445 3446 rc = check_missing_comp_in_queue(adapter, tx_ring); 3447 if (unlikely(rc != 0)) 3448 return; 3449 3450 budget--; 3451 if (budget == 0) { 3452 i++; 3453 break; 3454 } 3455 } 3456 3457 adapter->next_monitored_tx_qid = i % adapter->num_queues; 3458 } 3459 3460 /* trigger deferred rx cleanup after 2 consecutive detections */ 3461 #define EMPTY_RX_REFILL 2 3462 /* For the rare case where the device runs out of Rx descriptors and the 3463 * msix handler failed to refill new Rx descriptors (due to a lack of memory 3464 * for example). 3465 * This case will lead to a deadlock: 3466 * The device won't send interrupts since all the new Rx packets will be dropped 3467 * The msix handler won't allocate new Rx descriptors so the device won't be 3468 * able to send new packets. 3469 * 3470 * When such a situation is detected - execute rx cleanup task in another thread 3471 */ 3472 static void 3473 check_for_empty_rx_ring(struct ena_adapter *adapter) 3474 { 3475 struct ena_ring *rx_ring; 3476 int i, refill_required; 3477 3478 if (!adapter->up) 3479 return; 3480 3481 if (adapter->trigger_reset) 3482 return; 3483 3484 for (i = 0; i < adapter->num_queues; i++) { 3485 rx_ring = &adapter->rx_ring[i]; 3486 3487 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 3488 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 3489 rx_ring->empty_rx_queue++; 3490 3491 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 3492 counter_u64_add(rx_ring->rx_stats.empty_rx_ring, 3493 1); 3494 3495 device_printf(adapter->pdev, 3496 "trigger refill for ring %d\n", i); 3497 3498 if (atomic_cas_uint(&rx_ring->task_pending, 0, 1) == 0) 3499 workqueue_enqueue(rx_ring->cmpl_tq, 3500 &rx_ring->cmpl_task, curcpu()); 3501 rx_ring->empty_rx_queue = 0; 3502 } 3503 } else { 3504 rx_ring->empty_rx_queue = 0; 3505 } 3506 } 3507 } 3508 3509 static void 3510 ena_timer_service(void *data) 3511 { 3512 struct ena_adapter *adapter = (struct ena_adapter *)data; 3513 struct ena_admin_host_info *host_info = 3514 adapter->ena_dev->host_attr.host_info; 3515 3516 check_for_missing_keep_alive(adapter); 3517 3518 check_for_admin_com_state(adapter); 3519 3520 check_for_missing_tx_completions(adapter); 3521 3522 check_for_empty_rx_ring(adapter); 3523 3524 if (host_info != NULL) 3525 ena_update_host_info(host_info, adapter->ifp); 3526 3527 if (unlikely(adapter->trigger_reset)) { 3528 device_printf(adapter->pdev, "Trigger reset is on\n"); 3529 workqueue_enqueue(adapter->reset_tq, &adapter->reset_task, 3530 curcpu()); 3531 return; 3532 } 3533 3534 /* 3535 * Schedule another timeout one second from now. 3536 */ 3537 callout_schedule(&adapter->timer_service, hz); 3538 } 3539 3540 static void 3541 ena_reset_task(struct work *wk, void *arg) 3542 { 3543 struct ena_com_dev_get_features_ctx get_feat_ctx; 3544 struct ena_adapter *adapter = (struct ena_adapter *)arg; 3545 struct ena_com_dev *ena_dev = adapter->ena_dev; 3546 bool dev_up; 3547 int rc; 3548 3549 if (unlikely(!adapter->trigger_reset)) { 3550 device_printf(adapter->pdev, 3551 "device reset scheduled but trigger_reset is off\n"); 3552 return; 3553 } 3554 3555 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3556 3557 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3558 3559 dev_up = adapter->up; 3560 3561 ena_com_set_admin_running_state(ena_dev, false); 3562 ena_down(adapter); 3563 ena_free_mgmnt_irq(adapter); 3564 ena_disable_msix(adapter); 3565 ena_com_abort_admin_commands(ena_dev); 3566 ena_com_wait_for_abort_completion(ena_dev); 3567 ena_com_admin_destroy(ena_dev); 3568 ena_com_mmio_reg_read_request_destroy(ena_dev); 3569 3570 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3571 adapter->trigger_reset = false; 3572 3573 /* Finished destroy part. Restart the device */ 3574 rc = ena_device_init(adapter, adapter->pdev, &get_feat_ctx, 3575 &adapter->wd_active); 3576 if (unlikely(rc != 0)) { 3577 device_printf(adapter->pdev, 3578 "ENA device init failed! (err: %d)\n", rc); 3579 goto err_dev_free; 3580 } 3581 3582 /* XXX dealloc and realloc MSI-X, probably a waste */ 3583 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 3584 adapter->num_queues); 3585 if (unlikely(rc != 0)) { 3586 device_printf(adapter->pdev, "Enable MSI-X failed\n"); 3587 goto err_com_free; 3588 } 3589 3590 /* If the interface was up before the reset bring it up */ 3591 if (dev_up) { 3592 rc = ena_up(adapter); 3593 if (unlikely(rc != 0)) { 3594 device_printf(adapter->pdev, 3595 "Failed to create I/O queues\n"); 3596 goto err_msix_free; 3597 } 3598 } 3599 3600 callout_reset(&adapter->timer_service, hz, 3601 ena_timer_service, (void *)adapter); 3602 3603 rw_exit(&adapter->ioctl_sx); 3604 3605 return; 3606 3607 err_msix_free: 3608 ena_free_mgmnt_irq(adapter); 3609 ena_disable_msix(adapter); 3610 err_com_free: 3611 ena_com_admin_destroy(ena_dev); 3612 err_dev_free: 3613 device_printf(adapter->pdev, "ENA reset failed!\n"); 3614 adapter->running = false; 3615 rw_exit(&adapter->ioctl_sx); 3616 } 3617 3618 /** 3619 * ena_attach - Device Initialization Routine 3620 * @pdev: device information struct 3621 * 3622 * Returns 0 on success, otherwise on failure. 3623 * 3624 * ena_attach initializes an adapter identified by a device structure. 3625 * The OS initialization, configuring of the adapter private structure, 3626 * and a hardware reset occur. 3627 **/ 3628 static void 3629 ena_attach(device_t parent, device_t self, void *aux) 3630 { 3631 struct pci_attach_args *pa = aux; 3632 struct ena_com_dev_get_features_ctx get_feat_ctx; 3633 static int version_printed; 3634 struct ena_adapter *adapter = device_private(self); 3635 struct ena_com_dev *ena_dev = NULL; 3636 uint16_t tx_sgl_size = 0; 3637 uint16_t rx_sgl_size = 0; 3638 pcireg_t reg; 3639 int io_queue_num; 3640 int queue_size; 3641 int rc; 3642 3643 adapter->pdev = self; 3644 adapter->ifp = &adapter->sc_ec.ec_if; 3645 adapter->sc_pa = *pa; /* used after attach for adapter reset too */ 3646 3647 if (pci_dma64_available(pa)) 3648 adapter->sc_dmat = pa->pa_dmat64; 3649 else 3650 adapter->sc_dmat = pa->pa_dmat; 3651 3652 pci_aprint_devinfo(pa, NULL); 3653 3654 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3655 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) { 3656 reg |= PCI_COMMAND_MASTER_ENABLE; 3657 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 3658 } 3659 3660 mutex_init(&adapter->global_mtx, MUTEX_DEFAULT, IPL_NET); 3661 rw_init(&adapter->ioctl_sx); 3662 3663 /* Set up the timer service */ 3664 adapter->keep_alive_timeout = DEFAULT_KEEP_ALIVE_TO; 3665 adapter->missing_tx_timeout = DEFAULT_TX_CMP_TO; 3666 adapter->missing_tx_max_queues = DEFAULT_TX_MONITORED_QUEUES; 3667 adapter->missing_tx_threshold = DEFAULT_TX_CMP_THRESHOLD; 3668 3669 if (version_printed++ == 0) 3670 device_printf(parent, "%s\n", ena_version); 3671 3672 rc = ena_allocate_pci_resources(pa, adapter); 3673 if (unlikely(rc != 0)) { 3674 device_printf(parent, "PCI resource allocation failed!\n"); 3675 ena_free_pci_resources(adapter); 3676 return; 3677 } 3678 3679 /* Allocate memory for ena_dev structure */ 3680 ena_dev = malloc(sizeof(struct ena_com_dev), M_DEVBUF, 3681 M_WAITOK | M_ZERO); 3682 3683 adapter->ena_dev = ena_dev; 3684 ena_dev->dmadev = self; 3685 ena_dev->bus = malloc(sizeof(struct ena_bus), M_DEVBUF, 3686 M_WAITOK | M_ZERO); 3687 3688 /* Store register resources */ 3689 ((struct ena_bus*)(ena_dev->bus))->reg_bar_t = adapter->sc_btag; 3690 ((struct ena_bus*)(ena_dev->bus))->reg_bar_h = adapter->sc_bhandle; 3691 3692 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3693 3694 /* Device initialization */ 3695 rc = ena_device_init(adapter, self, &get_feat_ctx, &adapter->wd_active); 3696 if (unlikely(rc != 0)) { 3697 device_printf(self, "ENA device init failed! (err: %d)\n", rc); 3698 rc = ENXIO; 3699 goto err_bus_free; 3700 } 3701 3702 adapter->keep_alive_timestamp = getsbinuptime(); 3703 3704 adapter->tx_offload_cap = get_feat_ctx.offload.tx; 3705 3706 /* Set for sure that interface is not up */ 3707 adapter->up = false; 3708 3709 memcpy(adapter->mac_addr, get_feat_ctx.dev_attr.mac_addr, 3710 ETHER_ADDR_LEN); 3711 3712 /* calculate IO queue number to create */ 3713 io_queue_num = ena_calc_io_queue_num(pa, adapter, &get_feat_ctx); 3714 3715 ENA_ASSERT(io_queue_num > 0, "Invalid queue number: %d\n", 3716 io_queue_num); 3717 adapter->num_queues = io_queue_num; 3718 3719 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 3720 3721 /* calculatre ring sizes */ 3722 queue_size = ena_calc_queue_size(adapter,&tx_sgl_size, 3723 &rx_sgl_size, &get_feat_ctx); 3724 if (unlikely((queue_size <= 0) || (io_queue_num <= 0))) { 3725 rc = ENA_COM_FAULT; 3726 goto err_com_free; 3727 } 3728 3729 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3730 3731 adapter->tx_ring_size = queue_size; 3732 adapter->rx_ring_size = queue_size; 3733 3734 adapter->max_tx_sgl_size = tx_sgl_size; 3735 adapter->max_rx_sgl_size = rx_sgl_size; 3736 3737 #if 0 3738 /* set up dma tags for rx and tx buffers */ 3739 rc = ena_setup_tx_dma_tag(adapter); 3740 if (unlikely(rc != 0)) { 3741 device_printf(self, "Failed to create TX DMA tag\n"); 3742 goto err_com_free; 3743 } 3744 3745 rc = ena_setup_rx_dma_tag(adapter); 3746 if (unlikely(rc != 0)) { 3747 device_printf(self, "Failed to create RX DMA tag\n"); 3748 goto err_tx_tag_free; 3749 } 3750 #endif 3751 3752 /* initialize rings basic information */ 3753 device_printf(self, "initalize %d io queues\n", io_queue_num); 3754 ena_init_io_rings(adapter); 3755 3756 /* setup network interface */ 3757 rc = ena_setup_ifnet(self, adapter, &get_feat_ctx); 3758 if (unlikely(rc != 0)) { 3759 device_printf(self, "Error with network interface setup\n"); 3760 goto err_io_free; 3761 } 3762 3763 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3764 if (unlikely(rc != 0)) { 3765 device_printf(self, 3766 "Failed to enable and set the admin interrupts\n"); 3767 goto err_ifp_free; 3768 } 3769 3770 callout_init(&adapter->timer_service, CALLOUT_MPSAFE); 3771 3772 /* Initialize reset task queue */ 3773 rc = workqueue_create(&adapter->reset_tq, "ena_reset_enq", 3774 ena_reset_task, adapter, 0, IPL_NET, WQ_PERCPU | WQ_MPSAFE); 3775 if (unlikely(rc != 0)) { 3776 ena_trace(ENA_ALERT, 3777 "Unable to create workqueue for reset task\n"); 3778 goto err_ifp_free; 3779 } 3780 3781 /* Initialize statistics */ 3782 ena_alloc_counters_dev(&adapter->dev_stats, io_queue_num); 3783 ena_alloc_counters_hwstats(&adapter->hw_stats, io_queue_num); 3784 #if 0 3785 ena_sysctl_add_nodes(adapter); 3786 #endif 3787 3788 /* Tell the stack that the interface is not active */ 3789 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, IFF_RUNNING); 3790 3791 adapter->running = true; 3792 return; 3793 3794 err_ifp_free: 3795 if_detach(adapter->ifp); 3796 if_free(adapter->ifp); 3797 err_io_free: 3798 ena_free_all_io_rings_resources(adapter); 3799 #if 0 3800 ena_free_rx_dma_tag(adapter); 3801 err_tx_tag_free: 3802 ena_free_tx_dma_tag(adapter); 3803 #endif 3804 err_com_free: 3805 ena_com_admin_destroy(ena_dev); 3806 ena_com_delete_host_info(ena_dev); 3807 ena_com_mmio_reg_read_request_destroy(ena_dev); 3808 err_bus_free: 3809 free(ena_dev->bus, M_DEVBUF); 3810 free(ena_dev, M_DEVBUF); 3811 ena_free_pci_resources(adapter); 3812 } 3813 3814 /** 3815 * ena_detach - Device Removal Routine 3816 * @pdev: device information struct 3817 * 3818 * ena_detach is called by the device subsystem to alert the driver 3819 * that it should release a PCI device. 3820 **/ 3821 static int 3822 ena_detach(device_t pdev, int flags) 3823 { 3824 struct ena_adapter *adapter = device_private(pdev); 3825 struct ena_com_dev *ena_dev = adapter->ena_dev; 3826 #if 0 3827 int rc; 3828 #endif 3829 3830 /* Make sure VLANS are not using driver */ 3831 if (VLAN_ATTACHED(&adapter->sc_ec)) { 3832 device_printf(adapter->pdev ,"VLAN is in use, detach first\n"); 3833 return (EBUSY); 3834 } 3835 3836 /* Free reset task and callout */ 3837 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3838 callout_destroy(&adapter->timer_service); 3839 workqueue_wait(adapter->reset_tq, &adapter->reset_task); 3840 workqueue_destroy(adapter->reset_tq); 3841 adapter->reset_tq = NULL; 3842 3843 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3844 ena_down(adapter); 3845 rw_exit(&adapter->ioctl_sx); 3846 3847 if (adapter->ifp != NULL) { 3848 ether_ifdetach(adapter->ifp); 3849 if_free(adapter->ifp); 3850 } 3851 3852 ena_free_all_io_rings_resources(adapter); 3853 3854 ena_free_counters((struct evcnt *)&adapter->hw_stats, 3855 sizeof(struct ena_hw_stats)); 3856 ena_free_counters((struct evcnt *)&adapter->dev_stats, 3857 sizeof(struct ena_stats_dev)); 3858 3859 if (likely(adapter->rss_support)) 3860 ena_com_rss_destroy(ena_dev); 3861 3862 #if 0 3863 rc = ena_free_rx_dma_tag(adapter); 3864 if (unlikely(rc != 0)) 3865 device_printf(adapter->pdev, 3866 "Unmapped RX DMA tag associations\n"); 3867 3868 rc = ena_free_tx_dma_tag(adapter); 3869 if (unlikely(rc != 0)) 3870 device_printf(adapter->pdev, 3871 "Unmapped TX DMA tag associations\n"); 3872 #endif 3873 3874 /* Reset the device only if the device is running. */ 3875 if (adapter->running) 3876 ena_com_dev_reset(ena_dev, adapter->reset_reason); 3877 3878 ena_com_delete_host_info(ena_dev); 3879 3880 ena_free_irqs(adapter); 3881 3882 ena_com_abort_admin_commands(ena_dev); 3883 3884 ena_com_wait_for_abort_completion(ena_dev); 3885 3886 ena_com_admin_destroy(ena_dev); 3887 3888 ena_com_mmio_reg_read_request_destroy(ena_dev); 3889 3890 ena_free_pci_resources(adapter); 3891 3892 mutex_destroy(&adapter->global_mtx); 3893 rw_destroy(&adapter->ioctl_sx); 3894 3895 if (ena_dev->bus != NULL) 3896 free(ena_dev->bus, M_DEVBUF); 3897 3898 if (ena_dev != NULL) 3899 free(ena_dev, M_DEVBUF); 3900 3901 return 0; 3902 } 3903 3904 /****************************************************************************** 3905 ******************************** AENQ Handlers ******************************* 3906 *****************************************************************************/ 3907 /** 3908 * ena_update_on_link_change: 3909 * Notify the network interface about the change in link status 3910 **/ 3911 static void 3912 ena_update_on_link_change(void *adapter_data, 3913 struct ena_admin_aenq_entry *aenq_e) 3914 { 3915 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3916 struct ena_admin_aenq_link_change_desc *aenq_desc; 3917 int status; 3918 struct ifnet *ifp; 3919 3920 aenq_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3921 ifp = adapter->ifp; 3922 status = aenq_desc->flags & 3923 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3924 3925 if (status != 0) { 3926 device_printf(adapter->pdev, "link is UP\n"); 3927 if_link_state_change(ifp, LINK_STATE_UP); 3928 } else if (status == 0) { 3929 device_printf(adapter->pdev, "link is DOWN\n"); 3930 if_link_state_change(ifp, LINK_STATE_DOWN); 3931 } else { 3932 device_printf(adapter->pdev, "invalid value recvd\n"); 3933 BUG(); 3934 } 3935 3936 adapter->link_status = status; 3937 } 3938 3939 /** 3940 * This handler will called for unknown event group or unimplemented handlers 3941 **/ 3942 static void 3943 unimplemented_aenq_handler(void *data, 3944 struct ena_admin_aenq_entry *aenq_e) 3945 { 3946 return; 3947 } 3948 3949 static struct ena_aenq_handlers aenq_handlers = { 3950 .handlers = { 3951 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3952 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 3953 }, 3954 .unimplemented_handler = unimplemented_aenq_handler 3955 }; 3956 3957 #ifdef __FreeBSD__ 3958 /********************************************************************* 3959 * FreeBSD Device Interface Entry Points 3960 *********************************************************************/ 3961 3962 static device_method_t ena_methods[] = { 3963 /* Device interface */ 3964 DEVMETHOD(device_probe, ena_probe), 3965 DEVMETHOD(device_attach, ena_attach), 3966 DEVMETHOD(device_detach, ena_detach), 3967 DEVMETHOD_END 3968 }; 3969 3970 static driver_t ena_driver = { 3971 "ena", ena_methods, sizeof(struct ena_adapter), 3972 }; 3973 3974 devclass_t ena_devclass; 3975 DRIVER_MODULE(ena, pci, ena_driver, ena_devclass, 0, 0); 3976 MODULE_DEPEND(ena, pci, 1, 1, 1); 3977 MODULE_DEPEND(ena, ether, 1, 1, 1); 3978 3979 /*********************************************************************/ 3980 #endif /* __FreeBSD__ */ 3981 3982 #ifdef __NetBSD__ 3983 CFATTACH_DECL_NEW(ena, sizeof(struct ena_adapter), ena_probe, ena_attach, 3984 ena_detach, NULL); 3985 #endif /* __NetBSD */ 3986