1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifdef _KERNEL_OPT 32 #include "opt_net_mpsafe.h" 33 #endif 34 35 #include <sys/cdefs.h> 36 #if 0 37 __FBSDID("$FreeBSD: head/sys/dev/ena/ena.c 333456 2018-05-10 09:37:54Z mw $"); 38 #endif 39 __KERNEL_RCSID(0, "$NetBSD: if_ena.c,v 1.25 2020/08/03 19:44:06 jmcneill Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/time.h> 54 #include <sys/workqueue.h> 55 #include <sys/callout.h> 56 #include <sys/interrupt.h> 57 #include <sys/cpu.h> 58 59 #include <net/if_ether.h> 60 #include <net/if_vlanvar.h> 61 62 #include <dev/pci/if_enavar.h> 63 64 #ifdef NET_MPSAFE 65 #define WQ_FLAGS WQ_MPSAFE 66 #define CALLOUT_FLAGS CALLOUT_MPSAFE 67 #else 68 #define WQ_FLAGS 0 69 #define CALLOUT_FLAGS 0 70 #endif 71 72 /********************************************************* 73 * Function prototypes 74 *********************************************************/ 75 static int ena_probe(device_t, cfdata_t, void *); 76 static int ena_intr_msix_mgmnt(void *); 77 static int ena_allocate_pci_resources(struct pci_attach_args *, 78 struct ena_adapter *); 79 static void ena_free_pci_resources(struct ena_adapter *); 80 static int ena_change_mtu(struct ifnet *, int); 81 static void ena_init_io_rings_common(struct ena_adapter *, 82 struct ena_ring *, uint16_t); 83 static void ena_init_io_rings(struct ena_adapter *); 84 static void ena_free_io_ring_resources(struct ena_adapter *, unsigned int); 85 static void ena_free_all_io_rings_resources(struct ena_adapter *); 86 #if 0 87 static int ena_setup_tx_dma_tag(struct ena_adapter *); 88 static int ena_free_tx_dma_tag(struct ena_adapter *); 89 static int ena_setup_rx_dma_tag(struct ena_adapter *); 90 static int ena_free_rx_dma_tag(struct ena_adapter *); 91 #endif 92 static int ena_setup_tx_resources(struct ena_adapter *, int); 93 static void ena_free_tx_resources(struct ena_adapter *, int); 94 static int ena_setup_all_tx_resources(struct ena_adapter *); 95 static void ena_free_all_tx_resources(struct ena_adapter *); 96 static inline int validate_rx_req_id(struct ena_ring *, uint16_t); 97 static int ena_setup_rx_resources(struct ena_adapter *, unsigned int); 98 static void ena_free_rx_resources(struct ena_adapter *, unsigned int); 99 static int ena_setup_all_rx_resources(struct ena_adapter *); 100 static void ena_free_all_rx_resources(struct ena_adapter *); 101 static inline int ena_alloc_rx_mbuf(struct ena_adapter *, struct ena_ring *, 102 struct ena_rx_buffer *); 103 static void ena_free_rx_mbuf(struct ena_adapter *, struct ena_ring *, 104 struct ena_rx_buffer *); 105 static int ena_refill_rx_bufs(struct ena_ring *, uint32_t); 106 static void ena_free_rx_bufs(struct ena_adapter *, unsigned int); 107 static void ena_refill_all_rx_bufs(struct ena_adapter *); 108 static void ena_free_all_rx_bufs(struct ena_adapter *); 109 static void ena_free_tx_bufs(struct ena_adapter *, unsigned int); 110 static void ena_free_all_tx_bufs(struct ena_adapter *); 111 static void ena_destroy_all_tx_queues(struct ena_adapter *); 112 static void ena_destroy_all_rx_queues(struct ena_adapter *); 113 static void ena_destroy_all_io_queues(struct ena_adapter *); 114 static int ena_create_io_queues(struct ena_adapter *); 115 static int ena_tx_cleanup(struct ena_ring *); 116 static void ena_deferred_rx_cleanup(struct work *, void *); 117 static int ena_rx_cleanup(struct ena_ring *); 118 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 119 #if 0 120 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 121 struct mbuf *); 122 #endif 123 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 124 struct ena_com_rx_ctx *, uint16_t *); 125 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 126 struct mbuf *); 127 static int ena_handle_msix(void *); 128 static int ena_enable_msix(struct ena_adapter *); 129 static int ena_request_mgmnt_irq(struct ena_adapter *); 130 static int ena_request_io_irq(struct ena_adapter *); 131 static void ena_free_mgmnt_irq(struct ena_adapter *); 132 static void ena_free_io_irq(struct ena_adapter *); 133 static void ena_free_irqs(struct ena_adapter*); 134 static void ena_disable_msix(struct ena_adapter *); 135 static void ena_unmask_all_io_irqs(struct ena_adapter *); 136 static int ena_rss_configure(struct ena_adapter *); 137 static int ena_up_complete(struct ena_adapter *); 138 static int ena_up(struct ena_adapter *); 139 static void ena_down(struct ena_adapter *); 140 #if 0 141 static uint64_t ena_get_counter(struct ifnet *, ift_counter); 142 #endif 143 static int ena_media_change(struct ifnet *); 144 static void ena_media_status(struct ifnet *, struct ifmediareq *); 145 static int ena_init(struct ifnet *); 146 static int ena_ioctl(struct ifnet *, u_long, void *); 147 static int ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *); 148 static void ena_update_host_info(struct ena_admin_host_info *, struct ifnet *); 149 static void ena_update_hwassist(struct ena_adapter *); 150 static int ena_setup_ifnet(device_t, struct ena_adapter *, 151 struct ena_com_dev_get_features_ctx *); 152 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *); 153 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 154 struct mbuf **mbuf); 155 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 156 static void ena_start_xmit(struct ena_ring *); 157 static int ena_mq_start(struct ifnet *, struct mbuf *); 158 static void ena_deferred_mq_start(struct work *, void *); 159 #if 0 160 static void ena_qflush(struct ifnet *); 161 #endif 162 static int ena_calc_io_queue_num(struct pci_attach_args *, 163 struct ena_adapter *, struct ena_com_dev_get_features_ctx *); 164 static int ena_calc_queue_size(struct ena_adapter *, uint16_t *, 165 uint16_t *, struct ena_com_dev_get_features_ctx *); 166 #if 0 167 static int ena_rss_init_default(struct ena_adapter *); 168 static void ena_rss_init_default_deferred(void *); 169 #endif 170 static void ena_config_host_info(struct ena_com_dev *); 171 static void ena_attach(device_t, device_t, void *); 172 static int ena_detach(device_t, int); 173 static int ena_device_init(struct ena_adapter *, device_t, 174 struct ena_com_dev_get_features_ctx *, int *); 175 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *, 176 int); 177 static void ena_update_on_link_change(void *, struct ena_admin_aenq_entry *); 178 static void unimplemented_aenq_handler(void *, 179 struct ena_admin_aenq_entry *); 180 static void ena_timer_service(void *); 181 182 static const char ena_version[] = 183 DEVICE_NAME DRV_MODULE_NAME " v" DRV_MODULE_VERSION; 184 185 #if 0 186 static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD, 0, "ENA driver parameters"); 187 #endif 188 189 /* 190 * Tuneable number of buffers in the buf-ring (drbr) 191 */ 192 static int ena_buf_ring_size = 4096; 193 #if 0 194 SYSCTL_INT(_hw_ena, OID_AUTO, buf_ring_size, CTLFLAG_RWTUN, 195 &ena_buf_ring_size, 0, "Size of the bufring"); 196 #endif 197 198 /* 199 * Logging level for changing verbosity of the output 200 */ 201 int ena_log_level = ENA_ALERT | ENA_WARNING; 202 #if 0 203 SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, 204 &ena_log_level, 0, "Logging level indicating verbosity of the logs"); 205 #endif 206 207 static const ena_vendor_info_t ena_vendor_info_array[] = { 208 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_PF, 0}, 209 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_PF, 0}, 210 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_VF, 0}, 211 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_VF, 0}, 212 /* Last entry */ 213 { 0, 0, 0 } 214 }; 215 216 /* 217 * Contains pointers to event handlers, e.g. link state chage. 218 */ 219 static struct ena_aenq_handlers aenq_handlers; 220 221 int 222 ena_dma_alloc(device_t dmadev, bus_size_t size, 223 ena_mem_handle_t *dma , int mapflags) 224 { 225 struct ena_adapter *adapter = device_private(dmadev); 226 uint32_t maxsize; 227 bus_dma_segment_t seg; 228 int error, nsegs; 229 230 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; 231 232 #if 0 233 /* XXX what is this needed for ? */ 234 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); 235 if (unlikely(dma_space_addr == 0)) 236 dma_space_addr = BUS_SPACE_MAXADDR; 237 #endif 238 239 dma->tag = adapter->sc_dmat; 240 241 if ((error = bus_dmamap_create(dma->tag, maxsize, 1, maxsize, 0, 242 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->map)) != 0) { 243 ena_trace(ENA_ALERT, "bus_dmamap_create(%ju) failed: %d\n", 244 (uintmax_t)maxsize, error); 245 goto fail_create; 246 } 247 248 error = bus_dmamem_alloc(dma->tag, maxsize, 8, 0, &seg, 1, &nsegs, 249 BUS_DMA_ALLOCNOW); 250 if (error) { 251 ena_trace(ENA_ALERT, "bus_dmamem_alloc(%ju) failed: %d\n", 252 (uintmax_t)maxsize, error); 253 goto fail_alloc; 254 } 255 256 error = bus_dmamem_map(dma->tag, &seg, nsegs, maxsize, 257 &dma->vaddr, BUS_DMA_COHERENT); 258 if (error) { 259 ena_trace(ENA_ALERT, "bus_dmamem_map(%ju) failed: %d\n", 260 (uintmax_t)maxsize, error); 261 goto fail_map; 262 } 263 memset(dma->vaddr, 0, maxsize); 264 265 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 266 maxsize, NULL, mapflags); 267 if (error) { 268 ena_trace(ENA_ALERT, ": bus_dmamap_load failed: %d\n", error); 269 goto fail_load; 270 } 271 dma->paddr = dma->map->dm_segs[0].ds_addr; 272 273 return (0); 274 275 fail_load: 276 bus_dmamem_unmap(dma->tag, dma->vaddr, maxsize); 277 fail_map: 278 bus_dmamem_free(dma->tag, &seg, nsegs); 279 fail_alloc: 280 bus_dmamap_destroy(adapter->sc_dmat, dma->map); 281 fail_create: 282 return (error); 283 } 284 285 static int 286 ena_allocate_pci_resources(struct pci_attach_args *pa, 287 struct ena_adapter *adapter) 288 { 289 pcireg_t memtype, reg; 290 bus_addr_t memaddr; 291 bus_size_t mapsize; 292 int flags, error; 293 int msixoff; 294 295 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ENA_REG_BAR); 296 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 297 aprint_error_dev(adapter->pdev, "invalid type (type=0x%x)\n", 298 memtype); 299 return ENXIO; 300 } 301 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 302 if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) || 303 ((reg & PCI_COMMAND_MEM_ENABLE) == 0)) { 304 /* 305 * Enable address decoding for memory range in case BIOS or 306 * UEFI didn't set it. 307 */ 308 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 309 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 310 reg); 311 } 312 313 adapter->sc_btag = pa->pa_memt; 314 error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, ENA_REG_BAR, 315 memtype, &memaddr, &mapsize, &flags); 316 if (error) { 317 aprint_error_dev(adapter->pdev, "can't get map info\n"); 318 return ENXIO; 319 } 320 321 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 322 NULL)) { 323 pcireg_t msixtbl; 324 uint32_t table_offset; 325 int bir; 326 327 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 328 msixoff + PCI_MSIX_TBLOFFSET); 329 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 330 bir = msixtbl & PCI_MSIX_TBLBIR_MASK; 331 if (bir == PCI_MAPREG_NUM(ENA_REG_BAR)) 332 mapsize = table_offset; 333 } 334 335 error = bus_space_map(adapter->sc_btag, memaddr, mapsize, flags, 336 &adapter->sc_bhandle); 337 if (error != 0) { 338 aprint_error_dev(adapter->pdev, 339 "can't map mem space (error=%d)\n", error); 340 return ENXIO; 341 } 342 343 return (0); 344 } 345 346 static void 347 ena_free_pci_resources(struct ena_adapter *adapter) 348 { 349 /* Nothing to do */ 350 } 351 352 static int 353 ena_probe(device_t parent, cfdata_t match, void *aux) 354 { 355 struct pci_attach_args *pa = aux; 356 const ena_vendor_info_t *ent; 357 358 for (int i = 0; i < __arraycount(ena_vendor_info_array); i++) { 359 ent = &ena_vendor_info_array[i]; 360 361 if ((PCI_VENDOR(pa->pa_id) == ent->vendor_id) && 362 (PCI_PRODUCT(pa->pa_id) == ent->device_id)) { 363 return 1; 364 } 365 } 366 367 return 0; 368 } 369 370 static int 371 ena_change_mtu(struct ifnet *ifp, int new_mtu) 372 { 373 struct ena_adapter *adapter = if_getsoftc(ifp); 374 int rc; 375 376 if ((new_mtu > adapter->max_mtu) || (new_mtu < ENA_MIN_MTU)) { 377 device_printf(adapter->pdev, "Invalid MTU setting. " 378 "new_mtu: %d max mtu: %d min mtu: %d\n", 379 new_mtu, adapter->max_mtu, ENA_MIN_MTU); 380 return (EINVAL); 381 } 382 383 rc = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 384 if (likely(rc == 0)) { 385 ena_trace(ENA_DBG, "set MTU to %d\n", new_mtu); 386 if_setmtu(ifp, new_mtu); 387 } else { 388 device_printf(adapter->pdev, "Failed to set MTU to %d\n", 389 new_mtu); 390 } 391 392 return (rc); 393 } 394 395 #define EVCNT_INIT(st, f) \ 396 do { \ 397 evcnt_attach_dynamic(&st->f, EVCNT_TYPE_MISC, NULL, \ 398 st->name, #f); \ 399 } while (0) 400 401 static inline void 402 ena_alloc_counters_rx(struct ena_stats_rx *st, int queue) 403 { 404 snprintf(st->name, sizeof(st->name), "ena rxq%d", queue); 405 406 EVCNT_INIT(st, cnt); 407 EVCNT_INIT(st, bytes); 408 EVCNT_INIT(st, refil_partial); 409 EVCNT_INIT(st, bad_csum); 410 EVCNT_INIT(st, mjum_alloc_fail); 411 EVCNT_INIT(st, mbuf_alloc_fail); 412 EVCNT_INIT(st, dma_mapping_err); 413 EVCNT_INIT(st, bad_desc_num); 414 EVCNT_INIT(st, bad_req_id); 415 EVCNT_INIT(st, empty_rx_ring); 416 417 /* Make sure all code is updated when new fields added */ 418 CTASSERT(offsetof(struct ena_stats_rx, empty_rx_ring) 419 + sizeof(st->empty_rx_ring) == sizeof(*st)); 420 } 421 422 static inline void 423 ena_alloc_counters_tx(struct ena_stats_tx *st, int queue) 424 { 425 snprintf(st->name, sizeof(st->name), "ena txq%d", queue); 426 427 EVCNT_INIT(st, cnt); 428 EVCNT_INIT(st, bytes); 429 EVCNT_INIT(st, prepare_ctx_err); 430 EVCNT_INIT(st, dma_mapping_err); 431 EVCNT_INIT(st, doorbells); 432 EVCNT_INIT(st, missing_tx_comp); 433 EVCNT_INIT(st, bad_req_id); 434 EVCNT_INIT(st, collapse); 435 EVCNT_INIT(st, collapse_err); 436 437 /* Make sure all code is updated when new fields added */ 438 CTASSERT(offsetof(struct ena_stats_tx, collapse_err) 439 + sizeof(st->collapse_err) == sizeof(*st)); 440 } 441 442 static inline void 443 ena_alloc_counters_dev(struct ena_stats_dev *st, int queue) 444 { 445 snprintf(st->name, sizeof(st->name), "ena dev ioq%d", queue); 446 447 EVCNT_INIT(st, wd_expired); 448 EVCNT_INIT(st, interface_up); 449 EVCNT_INIT(st, interface_down); 450 EVCNT_INIT(st, admin_q_pause); 451 452 /* Make sure all code is updated when new fields added */ 453 CTASSERT(offsetof(struct ena_stats_dev, admin_q_pause) 454 + sizeof(st->admin_q_pause) == sizeof(*st)); 455 } 456 457 static inline void 458 ena_alloc_counters_hwstats(struct ena_hw_stats *st, int queue) 459 { 460 snprintf(st->name, sizeof(st->name), "ena hw ioq%d", queue); 461 462 EVCNT_INIT(st, rx_packets); 463 EVCNT_INIT(st, tx_packets); 464 EVCNT_INIT(st, rx_bytes); 465 EVCNT_INIT(st, tx_bytes); 466 EVCNT_INIT(st, rx_drops); 467 468 /* Make sure all code is updated when new fields added */ 469 CTASSERT(offsetof(struct ena_hw_stats, rx_drops) 470 + sizeof(st->rx_drops) == sizeof(*st)); 471 } 472 static inline void 473 ena_free_counters(struct evcnt *begin, int size) 474 { 475 struct evcnt *end = (struct evcnt *)((char *)begin + size); 476 477 for (; begin < end; ++begin) 478 counter_u64_free(*begin); 479 } 480 481 static inline void 482 ena_reset_counters(struct evcnt *begin, int size) 483 { 484 struct evcnt *end = (struct evcnt *)((char *)begin + size); 485 486 for (; begin < end; ++begin) 487 counter_u64_zero(*begin); 488 } 489 490 static void 491 ena_init_io_rings_common(struct ena_adapter *adapter, struct ena_ring *ring, 492 uint16_t qid) 493 { 494 495 ring->qid = qid; 496 ring->adapter = adapter; 497 ring->ena_dev = adapter->ena_dev; 498 } 499 500 static void 501 ena_init_io_rings(struct ena_adapter *adapter) 502 { 503 struct ena_com_dev *ena_dev; 504 struct ena_ring *txr, *rxr; 505 struct ena_que *que; 506 int i; 507 508 ena_dev = adapter->ena_dev; 509 510 for (i = 0; i < adapter->num_queues; i++) { 511 txr = &adapter->tx_ring[i]; 512 rxr = &adapter->rx_ring[i]; 513 514 /* TX/RX common ring state */ 515 ena_init_io_rings_common(adapter, txr, i); 516 ena_init_io_rings_common(adapter, rxr, i); 517 518 /* TX specific ring state */ 519 txr->ring_size = adapter->tx_ring_size; 520 txr->tx_max_header_size = ena_dev->tx_max_header_size; 521 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 522 txr->smoothed_interval = 523 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 524 525 /* Allocate a buf ring */ 526 txr->br = buf_ring_alloc(ena_buf_ring_size, M_DEVBUF, 527 M_WAITOK, &txr->ring_mtx); 528 529 /* Alloc TX statistics. */ 530 ena_alloc_counters_tx(&txr->tx_stats, i); 531 532 /* RX specific ring state */ 533 rxr->ring_size = adapter->rx_ring_size; 534 rxr->smoothed_interval = 535 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 536 537 /* Alloc RX statistics. */ 538 ena_alloc_counters_rx(&rxr->rx_stats, i); 539 540 /* Initialize locks */ 541 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 542 device_xname(adapter->pdev), i); 543 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 544 device_xname(adapter->pdev), i); 545 546 mutex_init(&txr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 547 mutex_init(&rxr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 548 549 que = &adapter->que[i]; 550 que->adapter = adapter; 551 que->id = i; 552 que->tx_ring = txr; 553 que->rx_ring = rxr; 554 555 txr->que = que; 556 rxr->que = que; 557 558 rxr->empty_rx_queue = 0; 559 } 560 } 561 562 static void 563 ena_free_io_ring_resources(struct ena_adapter *adapter, unsigned int qid) 564 { 565 struct ena_ring *txr = &adapter->tx_ring[qid]; 566 struct ena_ring *rxr = &adapter->rx_ring[qid]; 567 568 ena_free_counters((struct evcnt *)&txr->tx_stats, 569 sizeof(txr->tx_stats)); 570 ena_free_counters((struct evcnt *)&rxr->rx_stats, 571 sizeof(rxr->rx_stats)); 572 573 ENA_RING_MTX_LOCK(txr); 574 drbr_free(txr->br, M_DEVBUF); 575 ENA_RING_MTX_UNLOCK(txr); 576 577 mutex_destroy(&txr->ring_mtx); 578 mutex_destroy(&rxr->ring_mtx); 579 } 580 581 static void 582 ena_free_all_io_rings_resources(struct ena_adapter *adapter) 583 { 584 int i; 585 586 for (i = 0; i < adapter->num_queues; i++) 587 ena_free_io_ring_resources(adapter, i); 588 589 } 590 591 #if 0 592 static int 593 ena_setup_tx_dma_tag(struct ena_adapter *adapter) 594 { 595 int ret; 596 597 /* Create DMA tag for Tx buffers */ 598 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), 599 1, 0, /* alignment, bounds */ 600 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 601 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 602 NULL, NULL, /* filter, filterarg */ 603 ENA_TSO_MAXSIZE, /* maxsize */ 604 adapter->max_tx_sgl_size - 1, /* nsegments */ 605 ENA_TSO_MAXSIZE, /* maxsegsize */ 606 0, /* flags */ 607 NULL, /* lockfunc */ 608 NULL, /* lockfuncarg */ 609 &adapter->tx_buf_tag); 610 611 return (ret); 612 } 613 #endif 614 615 #if 0 616 static int 617 ena_setup_rx_dma_tag(struct ena_adapter *adapter) 618 { 619 int ret; 620 621 /* Create DMA tag for Rx buffers*/ 622 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */ 623 1, 0, /* alignment, bounds */ 624 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 625 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 626 NULL, NULL, /* filter, filterarg */ 627 MJUM16BYTES, /* maxsize */ 628 adapter->max_rx_sgl_size, /* nsegments */ 629 MJUM16BYTES, /* maxsegsize */ 630 0, /* flags */ 631 NULL, /* lockfunc */ 632 NULL, /* lockarg */ 633 &adapter->rx_buf_tag); 634 635 return (ret); 636 } 637 #endif 638 639 /** 640 * ena_setup_tx_resources - allocate Tx resources (Descriptors) 641 * @adapter: network interface device structure 642 * @qid: queue index 643 * 644 * Returns 0 on success, otherwise on failure. 645 **/ 646 static int 647 ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 648 { 649 struct ena_que *que = &adapter->que[qid]; 650 struct ena_ring *tx_ring = que->tx_ring; 651 int size, i, err; 652 #ifdef RSS 653 cpuset_t cpu_mask; 654 #endif 655 656 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 657 tx_ring->tx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 658 659 size = sizeof(uint16_t) * tx_ring->ring_size; 660 tx_ring->free_tx_ids = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 661 662 /* Req id stack for TX OOO completions */ 663 for (i = 0; i < tx_ring->ring_size; i++) 664 tx_ring->free_tx_ids[i] = i; 665 666 /* Reset TX statistics. */ 667 ena_reset_counters((struct evcnt *)&tx_ring->tx_stats, 668 sizeof(tx_ring->tx_stats)); 669 670 tx_ring->next_to_use = 0; 671 tx_ring->next_to_clean = 0; 672 673 /* Make sure that drbr is empty */ 674 ENA_RING_MTX_LOCK(tx_ring); 675 drbr_flush(adapter->ifp, tx_ring->br); 676 ENA_RING_MTX_UNLOCK(tx_ring); 677 678 /* ... and create the buffer DMA maps */ 679 for (i = 0; i < tx_ring->ring_size; i++) { 680 err = bus_dmamap_create(adapter->sc_dmat, 681 ENA_TSO_MAXSIZE, adapter->max_tx_sgl_size - 1, 682 ENA_TSO_MAXSIZE, 0, 0, 683 &tx_ring->tx_buffer_info[i].map); 684 if (unlikely(err != 0)) { 685 ena_trace(ENA_ALERT, 686 "Unable to create Tx DMA map for buffer %d\n", i); 687 goto err_buf_info_unmap; 688 } 689 } 690 691 /* Allocate workqueues */ 692 int rc = workqueue_create(&tx_ring->enqueue_tq, "ena_tx_enq", 693 ena_deferred_mq_start, tx_ring, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 694 if (unlikely(rc != 0)) { 695 ena_trace(ENA_ALERT, 696 "Unable to create workqueue for enqueue task\n"); 697 i = tx_ring->ring_size; 698 goto err_buf_info_unmap; 699 } 700 701 #if 0 702 /* RSS set cpu for thread */ 703 #ifdef RSS 704 CPU_SETOF(que->cpu, &cpu_mask); 705 taskqueue_start_threads_cpuset(&tx_ring->enqueue_tq, 1, IPL_NET, 706 &cpu_mask, "%s tx_ring enq (bucket %d)", 707 device_xname(adapter->pdev), que->cpu); 708 #else /* RSS */ 709 taskqueue_start_threads(&tx_ring->enqueue_tq, 1, IPL_NET, 710 "%s txeq %d", device_xname(adapter->pdev), que->cpu); 711 #endif /* RSS */ 712 #endif 713 714 return (0); 715 716 err_buf_info_unmap: 717 while (i--) { 718 bus_dmamap_destroy(adapter->sc_dmat, 719 tx_ring->tx_buffer_info[i].map); 720 } 721 free(tx_ring->free_tx_ids, M_DEVBUF); 722 tx_ring->free_tx_ids = NULL; 723 free(tx_ring->tx_buffer_info, M_DEVBUF); 724 tx_ring->tx_buffer_info = NULL; 725 726 return (ENOMEM); 727 } 728 729 /** 730 * ena_free_tx_resources - Free Tx Resources per Queue 731 * @adapter: network interface device structure 732 * @qid: queue index 733 * 734 * Free all transmit software resources 735 **/ 736 static void 737 ena_free_tx_resources(struct ena_adapter *adapter, int qid) 738 { 739 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 740 741 workqueue_wait(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 742 workqueue_destroy(tx_ring->enqueue_tq); 743 tx_ring->enqueue_tq = NULL; 744 745 ENA_RING_MTX_LOCK(tx_ring); 746 /* Flush buffer ring, */ 747 drbr_flush(adapter->ifp, tx_ring->br); 748 749 /* Free buffer DMA maps, */ 750 for (int i = 0; i < tx_ring->ring_size; i++) { 751 m_freem(tx_ring->tx_buffer_info[i].mbuf); 752 tx_ring->tx_buffer_info[i].mbuf = NULL; 753 bus_dmamap_unload(adapter->sc_dmat, 754 tx_ring->tx_buffer_info[i].map); 755 bus_dmamap_destroy(adapter->sc_dmat, 756 tx_ring->tx_buffer_info[i].map); 757 } 758 ENA_RING_MTX_UNLOCK(tx_ring); 759 760 /* And free allocated memory. */ 761 free(tx_ring->tx_buffer_info, M_DEVBUF); 762 tx_ring->tx_buffer_info = NULL; 763 764 free(tx_ring->free_tx_ids, M_DEVBUF); 765 tx_ring->free_tx_ids = NULL; 766 } 767 768 /** 769 * ena_setup_all_tx_resources - allocate all queues Tx resources 770 * @adapter: network interface device structure 771 * 772 * Returns 0 on success, otherwise on failure. 773 **/ 774 static int 775 ena_setup_all_tx_resources(struct ena_adapter *adapter) 776 { 777 int i, rc; 778 779 for (i = 0; i < adapter->num_queues; i++) { 780 rc = ena_setup_tx_resources(adapter, i); 781 if (rc != 0) { 782 device_printf(adapter->pdev, 783 "Allocation for Tx Queue %u failed\n", i); 784 goto err_setup_tx; 785 } 786 } 787 788 return (0); 789 790 err_setup_tx: 791 /* Rewind the index freeing the rings as we go */ 792 while (i--) 793 ena_free_tx_resources(adapter, i); 794 return (rc); 795 } 796 797 /** 798 * ena_free_all_tx_resources - Free Tx Resources for All Queues 799 * @adapter: network interface device structure 800 * 801 * Free all transmit software resources 802 **/ 803 static void 804 ena_free_all_tx_resources(struct ena_adapter *adapter) 805 { 806 int i; 807 808 for (i = 0; i < adapter->num_queues; i++) 809 ena_free_tx_resources(adapter, i); 810 } 811 812 static inline int 813 validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 814 { 815 if (likely(req_id < rx_ring->ring_size)) 816 return (0); 817 818 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 819 req_id); 820 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 821 822 /* Trigger device reset */ 823 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 824 rx_ring->adapter->trigger_reset = true; 825 826 return (EFAULT); 827 } 828 829 /** 830 * ena_setup_rx_resources - allocate Rx resources (Descriptors) 831 * @adapter: network interface device structure 832 * @qid: queue index 833 * 834 * Returns 0 on success, otherwise on failure. 835 **/ 836 static int 837 ena_setup_rx_resources(struct ena_adapter *adapter, unsigned int qid) 838 { 839 struct ena_que *que = &adapter->que[qid]; 840 struct ena_ring *rx_ring = que->rx_ring; 841 int size, err, i; 842 #ifdef RSS 843 cpuset_t cpu_mask; 844 #endif 845 846 size = sizeof(struct ena_rx_buffer) * rx_ring->ring_size; 847 848 /* 849 * Alloc extra element so in rx path 850 * we can always prefetch rx_info + 1 851 */ 852 size += sizeof(struct ena_rx_buffer); 853 854 rx_ring->rx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 855 856 size = sizeof(uint16_t) * rx_ring->ring_size; 857 rx_ring->free_rx_ids = malloc(size, M_DEVBUF, M_WAITOK); 858 859 for (i = 0; i < rx_ring->ring_size; i++) 860 rx_ring->free_rx_ids[i] = i; 861 862 /* Reset RX statistics. */ 863 ena_reset_counters((struct evcnt *)&rx_ring->rx_stats, 864 sizeof(rx_ring->rx_stats)); 865 866 rx_ring->next_to_clean = 0; 867 rx_ring->next_to_use = 0; 868 869 /* ... and create the buffer DMA maps */ 870 for (i = 0; i < rx_ring->ring_size; i++) { 871 err = bus_dmamap_create(adapter->sc_dmat, 872 MJUM16BYTES, adapter->max_rx_sgl_size, MJUM16BYTES, 873 0, 0, 874 &(rx_ring->rx_buffer_info[i].map)); 875 if (err != 0) { 876 ena_trace(ENA_ALERT, 877 "Unable to create Rx DMA map for buffer %d\n", i); 878 goto err_buf_info_unmap; 879 } 880 } 881 882 #ifdef LRO 883 /* Create LRO for the ring */ 884 if ((adapter->ifp->if_capenable & IFCAP_LRO) != 0) { 885 int err = tcp_lro_init(&rx_ring->lro); 886 if (err != 0) { 887 device_printf(adapter->pdev, 888 "LRO[%d] Initialization failed!\n", qid); 889 } else { 890 ena_trace(ENA_INFO, 891 "RX Soft LRO[%d] Initialized\n", qid); 892 rx_ring->lro.ifp = adapter->ifp; 893 } 894 } 895 #endif 896 897 /* Allocate workqueues */ 898 int rc = workqueue_create(&rx_ring->cmpl_tq, "ena_rx_comp", 899 ena_deferred_rx_cleanup, rx_ring, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 900 if (unlikely(rc != 0)) { 901 ena_trace(ENA_ALERT, 902 "Unable to create workqueue for RX completion task\n"); 903 goto err_buf_info_unmap; 904 } 905 906 #if 0 907 /* RSS set cpu for thread */ 908 #ifdef RSS 909 CPU_SETOF(que->cpu, &cpu_mask); 910 taskqueue_start_threads_cpuset(&rx_ring->cmpl_tq, 1, IPL_NET, &cpu_mask, 911 "%s rx_ring cmpl (bucket %d)", 912 device_xname(adapter->pdev), que->cpu); 913 #else 914 taskqueue_start_threads(&rx_ring->cmpl_tq, 1, IPL_NET, 915 "%s rx_ring cmpl %d", device_xname(adapter->pdev), que->cpu); 916 #endif 917 #endif 918 919 return (0); 920 921 err_buf_info_unmap: 922 while (i--) { 923 bus_dmamap_destroy(adapter->sc_dmat, 924 rx_ring->rx_buffer_info[i].map); 925 } 926 927 free(rx_ring->free_rx_ids, M_DEVBUF); 928 rx_ring->free_rx_ids = NULL; 929 free(rx_ring->rx_buffer_info, M_DEVBUF); 930 rx_ring->rx_buffer_info = NULL; 931 return (ENOMEM); 932 } 933 934 /** 935 * ena_free_rx_resources - Free Rx Resources 936 * @adapter: network interface device structure 937 * @qid: queue index 938 * 939 * Free all receive software resources 940 **/ 941 static void 942 ena_free_rx_resources(struct ena_adapter *adapter, unsigned int qid) 943 { 944 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 945 946 workqueue_wait(rx_ring->cmpl_tq, &rx_ring->cmpl_task); 947 workqueue_destroy(rx_ring->cmpl_tq); 948 rx_ring->cmpl_tq = NULL; 949 950 /* Free buffer DMA maps, */ 951 for (int i = 0; i < rx_ring->ring_size; i++) { 952 m_freem(rx_ring->rx_buffer_info[i].mbuf); 953 rx_ring->rx_buffer_info[i].mbuf = NULL; 954 bus_dmamap_unload(adapter->sc_dmat, 955 rx_ring->rx_buffer_info[i].map); 956 bus_dmamap_destroy(adapter->sc_dmat, 957 rx_ring->rx_buffer_info[i].map); 958 } 959 960 #ifdef LRO 961 /* free LRO resources, */ 962 tcp_lro_free(&rx_ring->lro); 963 #endif 964 965 /* free allocated memory */ 966 free(rx_ring->rx_buffer_info, M_DEVBUF); 967 rx_ring->rx_buffer_info = NULL; 968 969 free(rx_ring->free_rx_ids, M_DEVBUF); 970 rx_ring->free_rx_ids = NULL; 971 } 972 973 /** 974 * ena_setup_all_rx_resources - allocate all queues Rx resources 975 * @adapter: network interface device structure 976 * 977 * Returns 0 on success, otherwise on failure. 978 **/ 979 static int 980 ena_setup_all_rx_resources(struct ena_adapter *adapter) 981 { 982 int i, rc = 0; 983 984 for (i = 0; i < adapter->num_queues; i++) { 985 rc = ena_setup_rx_resources(adapter, i); 986 if (rc != 0) { 987 device_printf(adapter->pdev, 988 "Allocation for Rx Queue %u failed\n", i); 989 goto err_setup_rx; 990 } 991 } 992 return (0); 993 994 err_setup_rx: 995 /* rewind the index freeing the rings as we go */ 996 while (i--) 997 ena_free_rx_resources(adapter, i); 998 return (rc); 999 } 1000 1001 /** 1002 * ena_free_all_rx_resources - Free Rx resources for all queues 1003 * @adapter: network interface device structure 1004 * 1005 * Free all receive software resources 1006 **/ 1007 static void 1008 ena_free_all_rx_resources(struct ena_adapter *adapter) 1009 { 1010 int i; 1011 1012 for (i = 0; i < adapter->num_queues; i++) 1013 ena_free_rx_resources(adapter, i); 1014 } 1015 1016 static inline int 1017 ena_alloc_rx_mbuf(struct ena_adapter *adapter, 1018 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 1019 { 1020 struct ena_com_buf *ena_buf; 1021 int error; 1022 int mlen; 1023 1024 /* if previous allocated frag is not used */ 1025 if (unlikely(rx_info->mbuf != NULL)) 1026 return (0); 1027 1028 /* Get mbuf using UMA allocator */ 1029 rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); 1030 1031 if (unlikely(rx_info->mbuf == NULL)) { 1032 counter_u64_add(rx_ring->rx_stats.mjum_alloc_fail, 1); 1033 rx_info->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1034 if (unlikely(rx_info->mbuf == NULL)) { 1035 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1036 return (ENOMEM); 1037 } 1038 mlen = MCLBYTES; 1039 } else { 1040 mlen = MJUM16BYTES; 1041 } 1042 /* Set mbuf length*/ 1043 rx_info->mbuf->m_pkthdr.len = rx_info->mbuf->m_len = mlen; 1044 1045 /* Map packets for DMA */ 1046 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1047 "Using tag %p for buffers' DMA mapping, mbuf %p len: %d", 1048 adapter->sc_dmat,rx_info->mbuf, rx_info->mbuf->m_len); 1049 error = bus_dmamap_load_mbuf(adapter->sc_dmat, rx_info->map, 1050 rx_info->mbuf, BUS_DMA_NOWAIT); 1051 if (unlikely((error != 0) || (rx_info->map->dm_nsegs != 1))) { 1052 ena_trace(ENA_WARNING, "failed to map mbuf, error: %d, " 1053 "nsegs: %d\n", error, rx_info->map->dm_nsegs); 1054 counter_u64_add(rx_ring->rx_stats.dma_mapping_err, 1); 1055 goto exit; 1056 1057 } 1058 1059 bus_dmamap_sync(adapter->sc_dmat, rx_info->map, 0, 1060 rx_info->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1061 1062 ena_buf = &rx_info->ena_buf; 1063 ena_buf->paddr = rx_info->map->dm_segs[0].ds_addr; 1064 ena_buf->len = mlen; 1065 1066 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1067 "ALLOC RX BUF: mbuf %p, rx_info %p, len %d, paddr %#jx\n", 1068 rx_info->mbuf, rx_info,ena_buf->len, (uintmax_t)ena_buf->paddr); 1069 1070 return (0); 1071 1072 exit: 1073 m_freem(rx_info->mbuf); 1074 rx_info->mbuf = NULL; 1075 return (EFAULT); 1076 } 1077 1078 static void 1079 ena_free_rx_mbuf(struct ena_adapter *adapter, struct ena_ring *rx_ring, 1080 struct ena_rx_buffer *rx_info) 1081 { 1082 1083 if (rx_info->mbuf == NULL) { 1084 ena_trace(ENA_WARNING, "Trying to free unallocated buffer\n"); 1085 return; 1086 } 1087 1088 bus_dmamap_unload(adapter->sc_dmat, rx_info->map); 1089 m_freem(rx_info->mbuf); 1090 rx_info->mbuf = NULL; 1091 } 1092 1093 /** 1094 * ena_refill_rx_bufs - Refills ring with descriptors 1095 * @rx_ring: the ring which we want to feed with free descriptors 1096 * @num: number of descriptors to refill 1097 * Refills the ring with newly allocated DMA-mapped mbufs for receiving 1098 **/ 1099 static int 1100 ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num) 1101 { 1102 struct ena_adapter *adapter = rx_ring->adapter; 1103 uint16_t next_to_use, req_id; 1104 uint32_t i; 1105 int rc; 1106 1107 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, "refill qid: %d", 1108 rx_ring->qid); 1109 1110 next_to_use = rx_ring->next_to_use; 1111 1112 for (i = 0; i < num; i++) { 1113 struct ena_rx_buffer *rx_info; 1114 1115 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, 1116 "RX buffer - next to use: %d", next_to_use); 1117 1118 req_id = rx_ring->free_rx_ids[next_to_use]; 1119 rc = validate_rx_req_id(rx_ring, req_id); 1120 if (unlikely(rc != 0)) 1121 break; 1122 1123 rx_info = &rx_ring->rx_buffer_info[req_id]; 1124 1125 rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info); 1126 if (unlikely(rc != 0)) { 1127 ena_trace(ENA_WARNING, 1128 "failed to alloc buffer for rx queue %d\n", 1129 rx_ring->qid); 1130 break; 1131 } 1132 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 1133 &rx_info->ena_buf, req_id); 1134 if (unlikely(rc != 0)) { 1135 ena_trace(ENA_WARNING, 1136 "failed to add buffer for rx queue %d\n", 1137 rx_ring->qid); 1138 break; 1139 } 1140 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 1141 rx_ring->ring_size); 1142 } 1143 1144 if (unlikely(i < num)) { 1145 counter_u64_add(rx_ring->rx_stats.refil_partial, 1); 1146 ena_trace(ENA_WARNING, 1147 "refilled rx qid %d with only %d mbufs (from %d)\n", 1148 rx_ring->qid, i, num); 1149 } 1150 1151 if (likely(i != 0)) { 1152 wmb(); 1153 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 1154 } 1155 rx_ring->next_to_use = next_to_use; 1156 return (i); 1157 } 1158 1159 static void 1160 ena_free_rx_bufs(struct ena_adapter *adapter, unsigned int qid) 1161 { 1162 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 1163 unsigned int i; 1164 1165 for (i = 0; i < rx_ring->ring_size; i++) { 1166 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 1167 1168 if (rx_info->mbuf != NULL) 1169 ena_free_rx_mbuf(adapter, rx_ring, rx_info); 1170 } 1171 } 1172 1173 /** 1174 * ena_refill_all_rx_bufs - allocate all queues Rx buffers 1175 * @adapter: network interface device structure 1176 * 1177 */ 1178 static void 1179 ena_refill_all_rx_bufs(struct ena_adapter *adapter) 1180 { 1181 struct ena_ring *rx_ring; 1182 int i, rc, bufs_num; 1183 1184 for (i = 0; i < adapter->num_queues; i++) { 1185 rx_ring = &adapter->rx_ring[i]; 1186 bufs_num = rx_ring->ring_size - 1; 1187 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 1188 1189 if (unlikely(rc != bufs_num)) 1190 ena_trace(ENA_WARNING, "refilling Queue %d failed. " 1191 "Allocated %d buffers from: %d\n", i, rc, bufs_num); 1192 } 1193 } 1194 1195 static void 1196 ena_free_all_rx_bufs(struct ena_adapter *adapter) 1197 { 1198 int i; 1199 1200 for (i = 0; i < adapter->num_queues; i++) 1201 ena_free_rx_bufs(adapter, i); 1202 } 1203 1204 /** 1205 * ena_free_tx_bufs - Free Tx Buffers per Queue 1206 * @adapter: network interface device structure 1207 * @qid: queue index 1208 **/ 1209 static void 1210 ena_free_tx_bufs(struct ena_adapter *adapter, unsigned int qid) 1211 { 1212 bool print_once = true; 1213 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 1214 1215 ENA_RING_MTX_LOCK(tx_ring); 1216 for (int i = 0; i < tx_ring->ring_size; i++) { 1217 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 1218 1219 if (tx_info->mbuf == NULL) 1220 continue; 1221 1222 if (print_once) { 1223 device_printf(adapter->pdev, 1224 "free uncompleted tx mbuf qid %d idx 0x%x", 1225 qid, i); 1226 print_once = false; 1227 } else { 1228 ena_trace(ENA_DBG, 1229 "free uncompleted tx mbuf qid %d idx 0x%x", 1230 qid, i); 1231 } 1232 1233 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1234 m_free(tx_info->mbuf); 1235 tx_info->mbuf = NULL; 1236 } 1237 ENA_RING_MTX_UNLOCK(tx_ring); 1238 } 1239 1240 static void 1241 ena_free_all_tx_bufs(struct ena_adapter *adapter) 1242 { 1243 1244 for (int i = 0; i < adapter->num_queues; i++) 1245 ena_free_tx_bufs(adapter, i); 1246 } 1247 1248 static void 1249 ena_destroy_all_tx_queues(struct ena_adapter *adapter) 1250 { 1251 uint16_t ena_qid; 1252 int i; 1253 1254 for (i = 0; i < adapter->num_queues; i++) { 1255 ena_qid = ENA_IO_TXQ_IDX(i); 1256 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1257 } 1258 } 1259 1260 static void 1261 ena_destroy_all_rx_queues(struct ena_adapter *adapter) 1262 { 1263 uint16_t ena_qid; 1264 int i; 1265 1266 for (i = 0; i < adapter->num_queues; i++) { 1267 ena_qid = ENA_IO_RXQ_IDX(i); 1268 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1269 } 1270 } 1271 1272 static void 1273 ena_destroy_all_io_queues(struct ena_adapter *adapter) 1274 { 1275 ena_destroy_all_tx_queues(adapter); 1276 ena_destroy_all_rx_queues(adapter); 1277 } 1278 1279 static inline int 1280 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 1281 { 1282 struct ena_adapter *adapter = tx_ring->adapter; 1283 struct ena_tx_buffer *tx_info = NULL; 1284 1285 if (likely(req_id < tx_ring->ring_size)) { 1286 tx_info = &tx_ring->tx_buffer_info[req_id]; 1287 if (tx_info->mbuf != NULL) 1288 return (0); 1289 } 1290 1291 if (tx_info->mbuf == NULL) 1292 device_printf(adapter->pdev, 1293 "tx_info doesn't have valid mbuf\n"); 1294 else 1295 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 1296 1297 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 1298 1299 return (EFAULT); 1300 } 1301 1302 static int 1303 ena_create_io_queues(struct ena_adapter *adapter) 1304 { 1305 struct ena_com_dev *ena_dev = adapter->ena_dev; 1306 struct ena_com_create_io_ctx ctx; 1307 struct ena_ring *ring; 1308 uint16_t ena_qid; 1309 uint32_t msix_vector; 1310 int rc, i; 1311 1312 /* Create TX queues */ 1313 for (i = 0; i < adapter->num_queues; i++) { 1314 msix_vector = ENA_IO_IRQ_IDX(i); 1315 ena_qid = ENA_IO_TXQ_IDX(i); 1316 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1317 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1318 ctx.queue_size = adapter->tx_ring_size; 1319 ctx.msix_vector = msix_vector; 1320 ctx.qid = ena_qid; 1321 rc = ena_com_create_io_queue(ena_dev, &ctx); 1322 if (rc != 0) { 1323 device_printf(adapter->pdev, 1324 "Failed to create io TX queue #%d rc: %d\n", i, rc); 1325 goto err_tx; 1326 } 1327 ring = &adapter->tx_ring[i]; 1328 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1329 &ring->ena_com_io_sq, 1330 &ring->ena_com_io_cq); 1331 if (rc != 0) { 1332 device_printf(adapter->pdev, 1333 "Failed to get TX queue handlers. TX queue num" 1334 " %d rc: %d\n", i, rc); 1335 ena_com_destroy_io_queue(ena_dev, ena_qid); 1336 goto err_tx; 1337 } 1338 } 1339 1340 /* Create RX queues */ 1341 for (i = 0; i < adapter->num_queues; i++) { 1342 msix_vector = ENA_IO_IRQ_IDX(i); 1343 ena_qid = ENA_IO_RXQ_IDX(i); 1344 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1345 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1346 ctx.queue_size = adapter->rx_ring_size; 1347 ctx.msix_vector = msix_vector; 1348 ctx.qid = ena_qid; 1349 rc = ena_com_create_io_queue(ena_dev, &ctx); 1350 if (unlikely(rc != 0)) { 1351 device_printf(adapter->pdev, 1352 "Failed to create io RX queue[%d] rc: %d\n", i, rc); 1353 goto err_rx; 1354 } 1355 1356 ring = &adapter->rx_ring[i]; 1357 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1358 &ring->ena_com_io_sq, 1359 &ring->ena_com_io_cq); 1360 if (unlikely(rc != 0)) { 1361 device_printf(adapter->pdev, 1362 "Failed to get RX queue handlers. RX queue num" 1363 " %d rc: %d\n", i, rc); 1364 ena_com_destroy_io_queue(ena_dev, ena_qid); 1365 goto err_rx; 1366 } 1367 } 1368 1369 return (0); 1370 1371 err_rx: 1372 while (i--) 1373 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1374 i = adapter->num_queues; 1375 err_tx: 1376 while (i--) 1377 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1378 1379 return (ENXIO); 1380 } 1381 1382 /** 1383 * ena_tx_cleanup - clear sent packets and corresponding descriptors 1384 * @tx_ring: ring for which we want to clean packets 1385 * 1386 * Once packets are sent, we ask the device in a loop for no longer used 1387 * descriptors. We find the related mbuf chain in a map (index in an array) 1388 * and free it, then update ring state. 1389 * This is performed in "endless" loop, updating ring pointers every 1390 * TX_COMMIT. The first check of free descriptor is performed before the actual 1391 * loop, then repeated at the loop end. 1392 **/ 1393 static int 1394 ena_tx_cleanup(struct ena_ring *tx_ring) 1395 { 1396 struct ena_adapter *adapter; 1397 struct ena_com_io_cq* io_cq; 1398 uint16_t next_to_clean; 1399 uint16_t req_id; 1400 uint16_t ena_qid; 1401 unsigned int total_done = 0; 1402 int rc; 1403 int commit = TX_COMMIT; 1404 int budget = TX_BUDGET; 1405 int work_done; 1406 1407 adapter = tx_ring->que->adapter; 1408 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1409 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1410 next_to_clean = tx_ring->next_to_clean; 1411 1412 do { 1413 struct ena_tx_buffer *tx_info; 1414 struct mbuf *mbuf; 1415 1416 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 1417 if (unlikely(rc != 0)) 1418 break; 1419 1420 rc = validate_tx_req_id(tx_ring, req_id); 1421 if (unlikely(rc != 0)) 1422 break; 1423 1424 tx_info = &tx_ring->tx_buffer_info[req_id]; 1425 1426 mbuf = tx_info->mbuf; 1427 1428 tx_info->mbuf = NULL; 1429 bintime_clear(&tx_info->timestamp); 1430 1431 if (likely(tx_info->num_of_bufs != 0)) { 1432 /* Map is no longer required */ 1433 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1434 } 1435 1436 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed", 1437 tx_ring->qid, mbuf); 1438 1439 m_freem(mbuf); 1440 1441 total_done += tx_info->tx_descs; 1442 1443 tx_ring->free_tx_ids[next_to_clean] = req_id; 1444 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 1445 tx_ring->ring_size); 1446 1447 if (unlikely(--commit == 0)) { 1448 commit = TX_COMMIT; 1449 /* update ring state every TX_COMMIT descriptor */ 1450 tx_ring->next_to_clean = next_to_clean; 1451 ena_com_comp_ack( 1452 &adapter->ena_dev->io_sq_queues[ena_qid], 1453 total_done); 1454 ena_com_update_dev_comp_head(io_cq); 1455 total_done = 0; 1456 } 1457 } while (likely(--budget)); 1458 1459 work_done = TX_BUDGET - budget; 1460 1461 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d", 1462 tx_ring->qid, work_done); 1463 1464 /* If there is still something to commit update ring state */ 1465 if (likely(commit != TX_COMMIT)) { 1466 tx_ring->next_to_clean = next_to_clean; 1467 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 1468 total_done); 1469 ena_com_update_dev_comp_head(io_cq); 1470 } 1471 1472 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 1473 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, NULL); 1474 1475 return (work_done); 1476 } 1477 1478 #if 0 1479 static void 1480 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1481 struct mbuf *mbuf) 1482 { 1483 struct ena_adapter *adapter = rx_ring->adapter; 1484 1485 if (likely(adapter->rss_support)) { 1486 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 1487 1488 if (ena_rx_ctx->frag && 1489 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 1490 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1491 return; 1492 } 1493 1494 switch (ena_rx_ctx->l3_proto) { 1495 case ENA_ETH_IO_L3_PROTO_IPV4: 1496 switch (ena_rx_ctx->l4_proto) { 1497 case ENA_ETH_IO_L4_PROTO_TCP: 1498 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 1499 break; 1500 case ENA_ETH_IO_L4_PROTO_UDP: 1501 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 1502 break; 1503 default: 1504 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 1505 } 1506 break; 1507 case ENA_ETH_IO_L3_PROTO_IPV6: 1508 switch (ena_rx_ctx->l4_proto) { 1509 case ENA_ETH_IO_L4_PROTO_TCP: 1510 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 1511 break; 1512 case ENA_ETH_IO_L4_PROTO_UDP: 1513 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 1514 break; 1515 default: 1516 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 1517 } 1518 break; 1519 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 1520 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1521 break; 1522 default: 1523 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1524 } 1525 } else { 1526 mbuf->m_pkthdr.flowid = rx_ring->qid; 1527 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1528 } 1529 } 1530 #endif 1531 1532 /** 1533 * ena_rx_mbuf - assemble mbuf from descriptors 1534 * @rx_ring: ring for which we want to clean packets 1535 * @ena_bufs: buffer info 1536 * @ena_rx_ctx: metadata for this packet(s) 1537 * @next_to_clean: ring pointer, will be updated only upon success 1538 * 1539 **/ 1540 static struct mbuf* 1541 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 1542 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 1543 { 1544 struct mbuf *mbuf; 1545 struct ena_rx_buffer *rx_info; 1546 struct ena_adapter *adapter; 1547 unsigned int descs = ena_rx_ctx->descs; 1548 uint16_t ntc, len, req_id, buf = 0; 1549 1550 ntc = *next_to_clean; 1551 adapter = rx_ring->adapter; 1552 rx_info = &rx_ring->rx_buffer_info[ntc]; 1553 1554 if (unlikely(rx_info->mbuf == NULL)) { 1555 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1556 return (NULL); 1557 } 1558 1559 len = ena_bufs[buf].len; 1560 req_id = ena_bufs[buf].req_id; 1561 rx_info = &rx_ring->rx_buffer_info[req_id]; 1562 1563 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx", 1564 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 1565 1566 mbuf = rx_info->mbuf; 1567 KASSERT(mbuf->m_flags & M_PKTHDR); 1568 mbuf->m_pkthdr.len = len; 1569 mbuf->m_len = len; 1570 m_set_rcvif(mbuf, rx_ring->que->adapter->ifp); 1571 1572 /* Fill mbuf with hash key and it's interpretation for optimization */ 1573 #if 0 1574 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 1575 #endif 1576 1577 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf %p, flags=0x%x, len: %d", 1578 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 1579 1580 /* DMA address is not needed anymore, unmap it */ 1581 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1582 1583 rx_info->mbuf = NULL; 1584 rx_ring->free_rx_ids[ntc] = req_id; 1585 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1586 1587 /* 1588 * While we have more than 1 descriptors for one rcvd packet, append 1589 * other mbufs to the main one 1590 */ 1591 while (--descs) { 1592 ++buf; 1593 len = ena_bufs[buf].len; 1594 req_id = ena_bufs[buf].req_id; 1595 rx_info = &rx_ring->rx_buffer_info[req_id]; 1596 1597 if (unlikely(rx_info->mbuf == NULL)) { 1598 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1599 /* 1600 * If one of the required mbufs was not allocated yet, 1601 * we can break there. 1602 * All earlier used descriptors will be reallocated 1603 * later and not used mbufs can be reused. 1604 * The next_to_clean pointer will not be updated in case 1605 * of an error, so caller should advance it manually 1606 * in error handling routine to keep it up to date 1607 * with hw ring. 1608 */ 1609 m_freem(mbuf); 1610 return (NULL); 1611 } 1612 1613 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 1614 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1615 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p", 1616 mbuf); 1617 } 1618 1619 ena_trace(ENA_DBG | ENA_RXPTH, 1620 "rx mbuf updated. len %d", mbuf->m_pkthdr.len); 1621 1622 /* Free already appended mbuf, it won't be useful anymore */ 1623 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1624 m_freem(rx_info->mbuf); 1625 rx_info->mbuf = NULL; 1626 1627 rx_ring->free_rx_ids[ntc] = req_id; 1628 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1629 } 1630 1631 *next_to_clean = ntc; 1632 1633 return (mbuf); 1634 } 1635 1636 /** 1637 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 1638 **/ 1639 static inline void 1640 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1641 struct mbuf *mbuf) 1642 { 1643 1644 /* IPv4 */ 1645 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { 1646 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1647 if (ena_rx_ctx->l3_csum_err) { 1648 /* ipv4 checksum error */ 1649 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1650 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1651 ena_trace(ENA_DBG, "RX IPv4 header checksum error"); 1652 return; 1653 } 1654 1655 /* TCP/UDP */ 1656 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1657 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1658 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv4 : M_CSUM_UDPv4; 1659 if (ena_rx_ctx->l4_csum_err) { 1660 /* TCP/UDP checksum error */ 1661 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1662 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1663 ena_trace(ENA_DBG, "RX L4 checksum error"); 1664 } 1665 } 1666 } 1667 /* IPv6 */ 1668 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { 1669 /* TCP/UDP */ 1670 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1671 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1672 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv6 : M_CSUM_UDPv6; 1673 if (ena_rx_ctx->l4_csum_err) { 1674 /* TCP/UDP checksum error */ 1675 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1676 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1677 ena_trace(ENA_DBG, "RX L4 checksum error"); 1678 } 1679 } 1680 } 1681 } 1682 1683 static void 1684 ena_deferred_rx_cleanup(struct work *wk, void *arg) 1685 { 1686 struct ena_ring *rx_ring = arg; 1687 int budget = CLEAN_BUDGET; 1688 1689 atomic_swap_uint(&rx_ring->task_pending, 0); 1690 1691 ENA_RING_MTX_LOCK(rx_ring); 1692 /* 1693 * If deferred task was executed, perform cleanup of all awaiting 1694 * descs (or until given budget is depleted to avoid infinite loop). 1695 */ 1696 while (likely(budget--)) { 1697 if (ena_rx_cleanup(rx_ring) == 0) 1698 break; 1699 } 1700 ENA_RING_MTX_UNLOCK(rx_ring); 1701 } 1702 1703 /** 1704 * ena_rx_cleanup - handle rx irq 1705 * @arg: ring for which irq is being handled 1706 **/ 1707 static int 1708 ena_rx_cleanup(struct ena_ring *rx_ring) 1709 { 1710 struct ena_adapter *adapter; 1711 struct mbuf *mbuf; 1712 struct ena_com_rx_ctx ena_rx_ctx; 1713 struct ena_com_io_cq* io_cq; 1714 struct ena_com_io_sq* io_sq; 1715 struct ifnet *ifp; 1716 uint16_t ena_qid; 1717 uint16_t next_to_clean; 1718 uint32_t refill_required; 1719 uint32_t refill_threshold; 1720 uint32_t do_if_input = 0; 1721 unsigned int qid; 1722 int rc, i; 1723 int budget = RX_BUDGET; 1724 1725 adapter = rx_ring->que->adapter; 1726 ifp = adapter->ifp; 1727 qid = rx_ring->que->id; 1728 ena_qid = ENA_IO_RXQ_IDX(qid); 1729 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1730 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1731 next_to_clean = rx_ring->next_to_clean; 1732 1733 ena_trace(ENA_DBG, "rx: qid %d", qid); 1734 1735 do { 1736 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1737 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 1738 ena_rx_ctx.descs = 0; 1739 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 1740 1741 if (unlikely(rc != 0)) 1742 goto error; 1743 1744 if (unlikely(ena_rx_ctx.descs == 0)) 1745 break; 1746 1747 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 1748 "descs #: %d l3 proto %d l4 proto %d hash: %x", 1749 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1750 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1751 1752 /* Receive mbuf from the ring */ 1753 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 1754 &ena_rx_ctx, &next_to_clean); 1755 1756 /* Exit if we failed to retrieve a buffer */ 1757 if (unlikely(mbuf == NULL)) { 1758 for (i = 0; i < ena_rx_ctx.descs; ++i) { 1759 rx_ring->free_rx_ids[next_to_clean] = 1760 rx_ring->ena_bufs[i].req_id; 1761 next_to_clean = 1762 ENA_RX_RING_IDX_NEXT(next_to_clean, 1763 rx_ring->ring_size); 1764 1765 } 1766 break; 1767 } 1768 1769 if (((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) || 1770 ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) || 1771 ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) || 1772 ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) || 1773 ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0)) { 1774 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 1775 } 1776 1777 counter_enter(); 1778 counter_u64_add_protected(rx_ring->rx_stats.bytes, 1779 mbuf->m_pkthdr.len); 1780 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 1781 mbuf->m_pkthdr.len); 1782 counter_exit(); 1783 /* 1784 * LRO is only for IP/TCP packets and TCP checksum of the packet 1785 * should be computed by hardware. 1786 */ 1787 do_if_input = 1; 1788 #ifdef LRO 1789 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 1790 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 1791 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 1792 /* 1793 * Send to the stack if: 1794 * - LRO not enabled, or 1795 * - no LRO resources, or 1796 * - lro enqueue fails 1797 */ 1798 if ((rx_ring->lro.lro_cnt != 0) && 1799 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 1800 do_if_input = 0; 1801 } 1802 #endif 1803 if (do_if_input != 0) { 1804 ena_trace(ENA_DBG | ENA_RXPTH, 1805 "calling if_input() with mbuf %p", mbuf); 1806 if_percpuq_enqueue(ifp->if_percpuq, mbuf); 1807 } 1808 1809 counter_enter(); 1810 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 1811 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 1812 counter_exit(); 1813 } while (--budget); 1814 1815 rx_ring->next_to_clean = next_to_clean; 1816 1817 refill_required = ena_com_free_desc(io_sq); 1818 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1819 1820 if (refill_required > refill_threshold) { 1821 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1822 ena_refill_rx_bufs(rx_ring, refill_required); 1823 } 1824 1825 #ifdef LRO 1826 tcp_lro_flush_all(&rx_ring->lro); 1827 #endif 1828 1829 return (RX_BUDGET - budget); 1830 1831 error: 1832 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 1833 return (RX_BUDGET - budget); 1834 } 1835 1836 /********************************************************************* 1837 * 1838 * MSIX & Interrupt Service routine 1839 * 1840 **********************************************************************/ 1841 1842 /** 1843 * ena_handle_msix - MSIX Interrupt Handler for admin/async queue 1844 * @arg: interrupt number 1845 **/ 1846 static int 1847 ena_intr_msix_mgmnt(void *arg) 1848 { 1849 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1850 1851 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1852 if (likely(adapter->running)) 1853 ena_com_aenq_intr_handler(adapter->ena_dev, arg); 1854 1855 return 1; 1856 } 1857 1858 /** 1859 * ena_handle_msix - MSIX Interrupt Handler for Tx/Rx 1860 * @arg: interrupt number 1861 **/ 1862 static int 1863 ena_handle_msix(void *arg) 1864 { 1865 struct ena_que *que = arg; 1866 struct ena_adapter *adapter = que->adapter; 1867 struct ifnet *ifp = adapter->ifp; 1868 struct ena_ring *tx_ring; 1869 struct ena_ring *rx_ring; 1870 struct ena_com_io_cq* io_cq; 1871 struct ena_eth_io_intr_reg intr_reg; 1872 int qid, ena_qid; 1873 int txc, rxc, i; 1874 1875 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1876 return 0; 1877 1878 ena_trace(ENA_DBG, "MSI-X TX/RX routine"); 1879 1880 tx_ring = que->tx_ring; 1881 rx_ring = que->rx_ring; 1882 qid = que->id; 1883 ena_qid = ENA_IO_TXQ_IDX(qid); 1884 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1885 1886 for (i = 0; i < CLEAN_BUDGET; ++i) { 1887 /* 1888 * If lock cannot be acquired, then deferred cleanup task was 1889 * being executed and rx ring is being cleaned up in 1890 * another thread. 1891 */ 1892 if (likely(ENA_RING_MTX_TRYLOCK(rx_ring) != 0)) { 1893 rxc = ena_rx_cleanup(rx_ring); 1894 ENA_RING_MTX_UNLOCK(rx_ring); 1895 } else { 1896 rxc = 0; 1897 } 1898 1899 /* Protection from calling ena_tx_cleanup from ena_start_xmit */ 1900 ENA_RING_MTX_LOCK(tx_ring); 1901 txc = ena_tx_cleanup(tx_ring); 1902 ENA_RING_MTX_UNLOCK(tx_ring); 1903 1904 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1905 return 0; 1906 1907 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 1908 break; 1909 } 1910 1911 /* Signal that work is done and unmask interrupt */ 1912 ena_com_update_intr_reg(&intr_reg, 1913 RX_IRQ_INTERVAL, 1914 TX_IRQ_INTERVAL, 1915 true); 1916 ena_com_unmask_intr(io_cq, &intr_reg); 1917 1918 return 1; 1919 } 1920 1921 static int 1922 ena_enable_msix(struct ena_adapter *adapter) 1923 { 1924 int msix_req; 1925 int counts[PCI_INTR_TYPE_SIZE]; 1926 int max_type; 1927 1928 /* Reserved the max msix vectors we might need */ 1929 msix_req = ENA_MAX_MSIX_VEC(adapter->num_queues); 1930 1931 counts[PCI_INTR_TYPE_INTX] = 0; 1932 counts[PCI_INTR_TYPE_MSI] = 0; 1933 counts[PCI_INTR_TYPE_MSIX] = msix_req; 1934 max_type = PCI_INTR_TYPE_MSIX; 1935 1936 if (pci_intr_alloc(&adapter->sc_pa, &adapter->sc_intrs, counts, 1937 max_type) != 0) { 1938 aprint_error_dev(adapter->pdev, 1939 "failed to allocate interrupt\n"); 1940 return ENOSPC; 1941 } 1942 1943 adapter->sc_nintrs = counts[PCI_INTR_TYPE_MSIX]; 1944 1945 if (counts[PCI_INTR_TYPE_MSIX] != msix_req) { 1946 device_printf(adapter->pdev, 1947 "Enable only %d MSI-x (out of %d), reduce " 1948 "the number of queues\n", adapter->sc_nintrs, msix_req); 1949 adapter->num_queues = adapter->sc_nintrs - ENA_ADMIN_MSIX_VEC; 1950 } 1951 1952 return 0; 1953 } 1954 1955 #if 0 1956 static void 1957 ena_setup_io_intr(struct ena_adapter *adapter) 1958 { 1959 static int last_bind_cpu = -1; 1960 int irq_idx; 1961 1962 for (int i = 0; i < adapter->num_queues; i++) { 1963 irq_idx = ENA_IO_IRQ_IDX(i); 1964 1965 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1966 "%s-TxRx-%d", device_xname(adapter->pdev), i); 1967 adapter->irq_tbl[irq_idx].handler = ena_handle_msix; 1968 adapter->irq_tbl[irq_idx].data = &adapter->que[i]; 1969 adapter->irq_tbl[irq_idx].vector = 1970 adapter->msix_entries[irq_idx].vector; 1971 ena_trace(ENA_INFO | ENA_IOQ, "ena_setup_io_intr vector: %d\n", 1972 adapter->msix_entries[irq_idx].vector); 1973 #ifdef RSS 1974 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1975 rss_getcpu(i % rss_getnumbuckets()); 1976 #else 1977 /* 1978 * We still want to bind rings to the corresponding cpu 1979 * using something similar to the RSS round-robin technique. 1980 */ 1981 if (unlikely(last_bind_cpu < 0)) 1982 last_bind_cpu = CPU_FIRST(); 1983 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1984 last_bind_cpu; 1985 last_bind_cpu = CPU_NEXT(last_bind_cpu); 1986 #endif 1987 } 1988 } 1989 #endif 1990 1991 static int 1992 ena_request_mgmnt_irq(struct ena_adapter *adapter) 1993 { 1994 const char *intrstr; 1995 char intrbuf[PCI_INTRSTR_LEN]; 1996 char intr_xname[INTRDEVNAMEBUF]; 1997 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 1998 const int irq_slot = ENA_MGMNT_IRQ_IDX; 1999 2000 KASSERT(adapter->sc_intrs != NULL); 2001 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 2002 2003 snprintf(intr_xname, sizeof(intr_xname), "%s mgmnt", 2004 device_xname(adapter->pdev)); 2005 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 2006 intrbuf, sizeof(intrbuf)); 2007 2008 adapter->sc_ihs[irq_slot] = pci_intr_establish_xname( 2009 pc, adapter->sc_intrs[irq_slot], 2010 IPL_NET, ena_intr_msix_mgmnt, adapter, intr_xname); 2011 2012 if (adapter->sc_ihs[irq_slot] == NULL) { 2013 device_printf(adapter->pdev, "failed to register " 2014 "interrupt handler for MGMNT irq %s\n", 2015 intrstr); 2016 return ENOMEM; 2017 } 2018 2019 aprint_normal_dev(adapter->pdev, 2020 "for MGMNT interrupting at %s\n", intrstr); 2021 2022 return 0; 2023 } 2024 2025 static int 2026 ena_request_io_irq(struct ena_adapter *adapter) 2027 { 2028 const char *intrstr; 2029 char intrbuf[PCI_INTRSTR_LEN]; 2030 char intr_xname[INTRDEVNAMEBUF]; 2031 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 2032 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2033 void *vih; 2034 kcpuset_t *affinity; 2035 int i; 2036 2037 KASSERT(adapter->sc_intrs != NULL); 2038 2039 kcpuset_create(&affinity, false); 2040 2041 for (i = 0; i < adapter->num_queues; i++) { 2042 int irq_slot = i + irq_off; 2043 int affinity_to = (irq_slot) % ncpu; 2044 2045 KASSERT((void *)adapter->sc_intrs[irq_slot] != NULL); 2046 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 2047 2048 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 2049 device_xname(adapter->pdev), i); 2050 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 2051 intrbuf, sizeof(intrbuf)); 2052 2053 vih = pci_intr_establish_xname(adapter->sc_pa.pa_pc, 2054 adapter->sc_intrs[irq_slot], IPL_NET, 2055 ena_handle_msix, &adapter->que[i], intr_xname); 2056 2057 if (adapter->sc_ihs[ENA_MGMNT_IRQ_IDX] == NULL) { 2058 device_printf(adapter->pdev, "failed to register " 2059 "interrupt handler for IO queue %d irq %s\n", 2060 i, intrstr); 2061 goto err; 2062 } 2063 2064 kcpuset_zero(affinity); 2065 /* Round-robin affinity */ 2066 kcpuset_set(affinity, affinity_to); 2067 int error = interrupt_distribute(vih, affinity, NULL); 2068 if (error == 0) { 2069 aprint_normal_dev(adapter->pdev, 2070 "for IO queue %d interrupting at %s" 2071 " affinity to %u\n", i, intrstr, affinity_to); 2072 } else { 2073 aprint_normal_dev(adapter->pdev, 2074 "for IO queue %d interrupting at %s\n", i, intrstr); 2075 } 2076 2077 adapter->sc_ihs[irq_slot] = vih; 2078 2079 #ifdef RSS 2080 ena_trace(ENA_INFO, "queue %d - RSS bucket %d\n", 2081 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2082 #else 2083 ena_trace(ENA_INFO, "queue %d - cpu %d\n", 2084 i - ENA_IO_IRQ_FIRST_IDX, affinity_to); 2085 #endif 2086 } 2087 2088 kcpuset_destroy(affinity); 2089 return 0; 2090 2091 err: 2092 kcpuset_destroy(affinity); 2093 2094 for (i--; i >= 0; i--) { 2095 int irq_slot __diagused = i + irq_off; 2096 KASSERT(adapter->sc_ihs[irq_slot] != NULL); 2097 pci_intr_disestablish(adapter->sc_pa.pa_pc, adapter->sc_ihs[i]); 2098 adapter->sc_ihs[i] = NULL; 2099 } 2100 2101 return ENOSPC; 2102 } 2103 2104 static void 2105 ena_free_mgmnt_irq(struct ena_adapter *adapter) 2106 { 2107 const int irq_slot = ENA_MGMNT_IRQ_IDX; 2108 2109 if (adapter->sc_ihs[irq_slot]) { 2110 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2111 adapter->sc_ihs[irq_slot]); 2112 adapter->sc_ihs[irq_slot] = NULL; 2113 } 2114 } 2115 2116 static void 2117 ena_free_io_irq(struct ena_adapter *adapter) 2118 { 2119 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2120 2121 for (int i = 0; i < adapter->num_queues; i++) { 2122 int irq_slot = i + irq_off; 2123 2124 if (adapter->sc_ihs[irq_slot]) { 2125 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2126 adapter->sc_ihs[i]); 2127 adapter->sc_ihs[i] = NULL; 2128 } 2129 } 2130 } 2131 2132 static void 2133 ena_free_irqs(struct ena_adapter* adapter) 2134 { 2135 2136 ena_free_io_irq(adapter); 2137 ena_free_mgmnt_irq(adapter); 2138 ena_disable_msix(adapter); 2139 } 2140 2141 static void 2142 ena_disable_msix(struct ena_adapter *adapter) 2143 { 2144 pci_intr_release(adapter->sc_pa.pa_pc, adapter->sc_intrs, 2145 adapter->sc_nintrs); 2146 } 2147 2148 static void 2149 ena_unmask_all_io_irqs(struct ena_adapter *adapter) 2150 { 2151 struct ena_com_io_cq* io_cq; 2152 struct ena_eth_io_intr_reg intr_reg; 2153 uint16_t ena_qid; 2154 int i; 2155 2156 /* Unmask interrupts for all queues */ 2157 for (i = 0; i < adapter->num_queues; i++) { 2158 ena_qid = ENA_IO_TXQ_IDX(i); 2159 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 2160 ena_com_update_intr_reg(&intr_reg, 0, 0, true); 2161 ena_com_unmask_intr(io_cq, &intr_reg); 2162 } 2163 } 2164 2165 /* Configure the Rx forwarding */ 2166 static int 2167 ena_rss_configure(struct ena_adapter *adapter) 2168 { 2169 struct ena_com_dev *ena_dev = adapter->ena_dev; 2170 int rc; 2171 2172 /* Set indirect table */ 2173 rc = ena_com_indirect_table_set(ena_dev); 2174 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2175 return (rc); 2176 2177 /* Configure hash function (if supported) */ 2178 rc = ena_com_set_hash_function(ena_dev); 2179 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2180 return (rc); 2181 2182 /* Configure hash inputs (if supported) */ 2183 rc = ena_com_set_hash_ctrl(ena_dev); 2184 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2185 return (rc); 2186 2187 return (0); 2188 } 2189 2190 static int 2191 ena_up_complete(struct ena_adapter *adapter) 2192 { 2193 int rc; 2194 2195 if (likely(adapter->rss_support)) { 2196 rc = ena_rss_configure(adapter); 2197 if (rc != 0) 2198 return (rc); 2199 } 2200 2201 rc = ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu); 2202 if (unlikely(rc != 0)) 2203 return (rc); 2204 2205 ena_refill_all_rx_bufs(adapter); 2206 ena_reset_counters((struct evcnt *)&adapter->hw_stats, 2207 sizeof(adapter->hw_stats)); 2208 2209 return (0); 2210 } 2211 2212 static int 2213 ena_up(struct ena_adapter *adapter) 2214 { 2215 int rc = 0; 2216 2217 #if 0 2218 if (unlikely(device_is_attached(adapter->pdev) == 0)) { 2219 device_printf(adapter->pdev, "device is not attached!\n"); 2220 return (ENXIO); 2221 } 2222 #endif 2223 2224 if (unlikely(!adapter->running)) { 2225 device_printf(adapter->pdev, "device is not running!\n"); 2226 return (ENXIO); 2227 } 2228 2229 if (!adapter->up) { 2230 device_printf(adapter->pdev, "device is going UP\n"); 2231 2232 /* setup interrupts for IO queues */ 2233 rc = ena_request_io_irq(adapter); 2234 if (unlikely(rc != 0)) { 2235 ena_trace(ENA_ALERT, "err_req_irq"); 2236 goto err_req_irq; 2237 } 2238 2239 /* allocate transmit descriptors */ 2240 rc = ena_setup_all_tx_resources(adapter); 2241 if (unlikely(rc != 0)) { 2242 ena_trace(ENA_ALERT, "err_setup_tx"); 2243 goto err_setup_tx; 2244 } 2245 2246 /* allocate receive descriptors */ 2247 rc = ena_setup_all_rx_resources(adapter); 2248 if (unlikely(rc != 0)) { 2249 ena_trace(ENA_ALERT, "err_setup_rx"); 2250 goto err_setup_rx; 2251 } 2252 2253 /* create IO queues for Rx & Tx */ 2254 rc = ena_create_io_queues(adapter); 2255 if (unlikely(rc != 0)) { 2256 ena_trace(ENA_ALERT, 2257 "create IO queues failed"); 2258 goto err_io_que; 2259 } 2260 2261 if (unlikely(adapter->link_status)) 2262 if_link_state_change(adapter->ifp, LINK_STATE_UP); 2263 2264 rc = ena_up_complete(adapter); 2265 if (unlikely(rc != 0)) 2266 goto err_up_complete; 2267 2268 counter_u64_add(adapter->dev_stats.interface_up, 1); 2269 2270 ena_update_hwassist(adapter); 2271 2272 if_setdrvflagbits(adapter->ifp, IFF_RUNNING, 2273 IFF_OACTIVE); 2274 2275 callout_schedule(&adapter->timer_service, hz); 2276 2277 adapter->up = true; 2278 2279 ena_unmask_all_io_irqs(adapter); 2280 } 2281 2282 return (0); 2283 2284 err_up_complete: 2285 ena_destroy_all_io_queues(adapter); 2286 err_io_que: 2287 ena_free_all_rx_resources(adapter); 2288 err_setup_rx: 2289 ena_free_all_tx_resources(adapter); 2290 err_setup_tx: 2291 ena_free_io_irq(adapter); 2292 err_req_irq: 2293 return (rc); 2294 } 2295 2296 #if 0 2297 static uint64_t 2298 ena_get_counter(struct ifnet *ifp, ift_counter cnt) 2299 { 2300 struct ena_adapter *adapter; 2301 struct ena_hw_stats *stats; 2302 2303 adapter = if_getsoftc(ifp); 2304 stats = &adapter->hw_stats; 2305 2306 switch (cnt) { 2307 case IFCOUNTER_IPACKETS: 2308 return (counter_u64_fetch(stats->rx_packets)); 2309 case IFCOUNTER_OPACKETS: 2310 return (counter_u64_fetch(stats->tx_packets)); 2311 case IFCOUNTER_IBYTES: 2312 return (counter_u64_fetch(stats->rx_bytes)); 2313 case IFCOUNTER_OBYTES: 2314 return (counter_u64_fetch(stats->tx_bytes)); 2315 case IFCOUNTER_IQDROPS: 2316 return (counter_u64_fetch(stats->rx_drops)); 2317 default: 2318 return (if_get_counter_default(ifp, cnt)); 2319 } 2320 } 2321 #endif 2322 2323 static int 2324 ena_media_change(struct ifnet *ifp) 2325 { 2326 /* Media Change is not supported by firmware */ 2327 return (0); 2328 } 2329 2330 static void 2331 ena_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2332 { 2333 struct ena_adapter *adapter = if_getsoftc(ifp); 2334 ena_trace(ENA_DBG, "enter"); 2335 2336 mutex_enter(&adapter->global_mtx); 2337 2338 ifmr->ifm_status = IFM_AVALID; 2339 ifmr->ifm_active = IFM_ETHER; 2340 2341 if (!adapter->link_status) { 2342 mutex_exit(&adapter->global_mtx); 2343 ena_trace(ENA_INFO, "link_status = false"); 2344 return; 2345 } 2346 2347 ifmr->ifm_status |= IFM_ACTIVE; 2348 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2349 2350 mutex_exit(&adapter->global_mtx); 2351 } 2352 2353 static int 2354 ena_init(struct ifnet *ifp) 2355 { 2356 struct ena_adapter *adapter = if_getsoftc(ifp); 2357 2358 if (!adapter->up) { 2359 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2360 ena_up(adapter); 2361 rw_exit(&adapter->ioctl_sx); 2362 } 2363 2364 return 0; 2365 } 2366 2367 static int 2368 ena_ioctl(struct ifnet *ifp, u_long command, void *data) 2369 { 2370 struct ena_adapter *adapter; 2371 struct ifreq *ifr; 2372 int rc; 2373 2374 adapter = ifp->if_softc; 2375 ifr = (struct ifreq *)data; 2376 2377 /* 2378 * Acquiring lock to prevent from running up and down routines parallel. 2379 */ 2380 rc = 0; 2381 switch (command) { 2382 case SIOCSIFMTU: 2383 if (ifp->if_mtu == ifr->ifr_mtu) 2384 break; 2385 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2386 ena_down(adapter); 2387 2388 ena_change_mtu(ifp, ifr->ifr_mtu); 2389 2390 rc = ena_up(adapter); 2391 rw_exit(&adapter->ioctl_sx); 2392 break; 2393 2394 case SIOCSIFFLAGS: 2395 if ((ifp->if_flags & IFF_UP) != 0) { 2396 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2397 if ((ifp->if_flags & (IFF_PROMISC | 2398 IFF_ALLMULTI)) != 0) { 2399 device_printf(adapter->pdev, 2400 "ioctl promisc/allmulti\n"); 2401 } 2402 } else { 2403 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2404 rc = ena_up(adapter); 2405 rw_exit(&adapter->ioctl_sx); 2406 } 2407 } else { 2408 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2409 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2410 ena_down(adapter); 2411 rw_exit(&adapter->ioctl_sx); 2412 } 2413 } 2414 break; 2415 2416 case SIOCADDMULTI: 2417 case SIOCDELMULTI: 2418 break; 2419 2420 case SIOCSIFCAP: 2421 { 2422 struct ifcapreq *ifcr = data; 2423 int reinit = 0; 2424 2425 if (ifcr->ifcr_capenable != ifp->if_capenable) { 2426 ifp->if_capenable = ifcr->ifcr_capenable; 2427 reinit = 1; 2428 } 2429 2430 if ((reinit != 0) && 2431 ((if_getdrvflags(ifp) & IFF_RUNNING) != 0)) { 2432 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2433 ena_down(adapter); 2434 rc = ena_up(adapter); 2435 rw_exit(&adapter->ioctl_sx); 2436 } 2437 } 2438 2439 break; 2440 default: 2441 rc = ether_ioctl(ifp, command, data); 2442 break; 2443 } 2444 2445 return (rc); 2446 } 2447 2448 static int 2449 ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *feat) 2450 { 2451 int caps = 0; 2452 2453 if ((feat->offload.tx & 2454 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2455 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK | 2456 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)) != 0) 2457 caps |= IFCAP_CSUM_IPv4_Tx; 2458 2459 if ((feat->offload.tx & 2460 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK | 2461 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)) != 0) 2462 caps |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 2463 2464 if ((feat->offload.tx & 2465 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0) 2466 caps |= IFCAP_TSOv4; 2467 2468 if ((feat->offload.tx & 2469 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) != 0) 2470 caps |= IFCAP_TSOv6; 2471 2472 if ((feat->offload.rx_supported & 2473 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK | 2474 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)) != 0) 2475 caps |= IFCAP_CSUM_IPv4_Rx; 2476 2477 if ((feat->offload.rx_supported & 2478 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) != 0) 2479 caps |= IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 2480 2481 caps |= IFCAP_LRO; 2482 2483 return (caps); 2484 } 2485 2486 static void 2487 ena_update_host_info(struct ena_admin_host_info *host_info, struct ifnet *ifp) 2488 { 2489 2490 host_info->supported_network_features[0] = 2491 (uint32_t)if_getcapabilities(ifp); 2492 } 2493 2494 static void 2495 ena_update_hwassist(struct ena_adapter *adapter) 2496 { 2497 struct ifnet *ifp = adapter->ifp; 2498 uint32_t feat = adapter->tx_offload_cap; 2499 int cap = if_getcapenable(ifp); 2500 int flags = 0; 2501 2502 if_clearhwassist(ifp); 2503 2504 if ((cap & (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2505 != 0) { 2506 if ((feat & 2507 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) != 0) 2508 flags |= M_CSUM_IPv4; 2509 if ((feat & 2510 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2511 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)) != 0) 2512 flags |= M_CSUM_TCPv4 | M_CSUM_UDPv4; 2513 } 2514 2515 if ((cap & IFCAP_CSUM_TCPv6_Tx) != 0) 2516 flags |= M_CSUM_TCPv6; 2517 2518 if ((cap & IFCAP_CSUM_UDPv6_Tx) != 0) 2519 flags |= M_CSUM_UDPv6; 2520 2521 if ((cap & IFCAP_TSOv4) != 0) 2522 flags |= M_CSUM_TSOv4; 2523 2524 if ((cap & IFCAP_TSOv6) != 0) 2525 flags |= M_CSUM_TSOv6; 2526 2527 if_sethwassistbits(ifp, flags, 0); 2528 } 2529 2530 static int 2531 ena_setup_ifnet(device_t pdev, struct ena_adapter *adapter, 2532 struct ena_com_dev_get_features_ctx *feat) 2533 { 2534 struct ifnet *ifp; 2535 int caps = 0; 2536 2537 ifp = adapter->ifp = &adapter->sc_ec.ec_if; 2538 if (unlikely(ifp == NULL)) { 2539 ena_trace(ENA_ALERT, "can not allocate ifnet structure\n"); 2540 return (ENXIO); 2541 } 2542 if_initname(ifp, "ena", device_unit(pdev)); 2543 if_setdev(ifp, pdev); 2544 if_setsoftc(ifp, adapter); 2545 2546 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2547 if_setinitfn(ifp, ena_init); 2548 if_settransmitfn(ifp, ena_mq_start); 2549 #if 0 2550 if_setqflushfn(ifp, ena_qflush); 2551 #endif 2552 if_setioctlfn(ifp, ena_ioctl); 2553 #if 0 2554 if_setgetcounterfn(ifp, ena_get_counter); 2555 #endif 2556 2557 if_setsendqlen(ifp, adapter->tx_ring_size); 2558 if_setsendqready(ifp); 2559 if_setmtu(ifp, ETHERMTU); 2560 if_setbaudrate(ifp, 0); 2561 /* Zeroize capabilities... */ 2562 if_setcapabilities(ifp, 0); 2563 if_setcapenable(ifp, 0); 2564 /* check hardware support */ 2565 caps = ena_get_dev_offloads(feat); 2566 /* ... and set them */ 2567 if_setcapabilitiesbit(ifp, caps, 0); 2568 adapter->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2569 2570 #if 0 2571 /* TSO parameters */ 2572 /* XXX no limits on NetBSD, guarded by virtue of dmamap load failing */ 2573 ifp->if_hw_tsomax = ENA_TSO_MAXSIZE - 2574 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2575 ifp->if_hw_tsomaxsegcount = adapter->max_tx_sgl_size - 1; 2576 ifp->if_hw_tsomaxsegsize = ENA_TSO_MAXSIZE; 2577 #endif 2578 2579 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2580 if_setcapenable(ifp, if_getcapabilities(ifp)); 2581 2582 /* 2583 * Specify the media types supported by this adapter and register 2584 * callbacks to update media and link information 2585 */ 2586 adapter->sc_ec.ec_ifmedia = &adapter->media; 2587 ifmedia_init(&adapter->media, IFM_IMASK, 2588 ena_media_change, ena_media_status); 2589 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2590 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2591 2592 if_attach(ifp); 2593 if_deferred_start_init(ifp, NULL); 2594 2595 ether_ifattach(ifp, adapter->mac_addr); 2596 2597 return (0); 2598 } 2599 2600 static void 2601 ena_down(struct ena_adapter *adapter) 2602 { 2603 int rc; 2604 2605 if (adapter->up) { 2606 device_printf(adapter->pdev, "device is going DOWN\n"); 2607 2608 callout_halt(&adapter->timer_service, &adapter->global_mtx); 2609 2610 adapter->up = false; 2611 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, 2612 IFF_RUNNING); 2613 2614 ena_free_io_irq(adapter); 2615 2616 if (adapter->trigger_reset) { 2617 rc = ena_com_dev_reset(adapter->ena_dev, 2618 adapter->reset_reason); 2619 if (unlikely(rc != 0)) 2620 device_printf(adapter->pdev, 2621 "Device reset failed\n"); 2622 } 2623 2624 ena_destroy_all_io_queues(adapter); 2625 2626 ena_free_all_tx_bufs(adapter); 2627 ena_free_all_rx_bufs(adapter); 2628 ena_free_all_tx_resources(adapter); 2629 ena_free_all_rx_resources(adapter); 2630 2631 counter_u64_add(adapter->dev_stats.interface_down, 1); 2632 } 2633 } 2634 2635 static void 2636 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf) 2637 { 2638 struct ena_com_tx_meta *ena_meta; 2639 struct ether_vlan_header *eh; 2640 u32 mss; 2641 bool offload; 2642 uint16_t etype; 2643 int ehdrlen; 2644 struct ip *ip; 2645 int iphlen; 2646 struct tcphdr *th; 2647 2648 offload = false; 2649 ena_meta = &ena_tx_ctx->ena_meta; 2650 2651 #if 0 2652 u32 mss = mbuf->m_pkthdr.tso_segsz; 2653 2654 if (mss != 0) 2655 offload = true; 2656 #else 2657 mss = mbuf->m_pkthdr.len; /* XXX don't have tso_segsz */ 2658 #endif 2659 2660 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) 2661 offload = true; 2662 2663 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 2664 offload = true; 2665 2666 if (!offload) { 2667 ena_tx_ctx->meta_valid = 0; 2668 return; 2669 } 2670 2671 /* Determine where frame payload starts. */ 2672 eh = mtod(mbuf, struct ether_vlan_header *); 2673 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2674 etype = ntohs(eh->evl_proto); 2675 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2676 } else { 2677 etype = htons(eh->evl_encap_proto); 2678 ehdrlen = ETHER_HDR_LEN; 2679 } 2680 2681 ip = (struct ip *)(mbuf->m_data + ehdrlen); 2682 iphlen = ip->ip_hl << 2; 2683 th = (struct tcphdr *)((vaddr_t)ip + iphlen); 2684 2685 if ((mbuf->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 2686 ena_tx_ctx->l3_csum_enable = 1; 2687 } 2688 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 2689 ena_tx_ctx->tso_enable = 1; 2690 ena_meta->l4_hdr_len = (th->th_off); 2691 } 2692 2693 switch (etype) { 2694 case ETHERTYPE_IP: 2695 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 2696 if ((ip->ip_off & htons(IP_DF)) != 0) 2697 ena_tx_ctx->df = 1; 2698 break; 2699 case ETHERTYPE_IPV6: 2700 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 2701 2702 default: 2703 break; 2704 } 2705 2706 if (ip->ip_p == IPPROTO_TCP) { 2707 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 2708 if ((mbuf->m_pkthdr.csum_flags & 2709 (M_CSUM_TCPv4 | M_CSUM_TCPv6)) != 0) 2710 ena_tx_ctx->l4_csum_enable = 1; 2711 else 2712 ena_tx_ctx->l4_csum_enable = 0; 2713 } else if (ip->ip_p == IPPROTO_UDP) { 2714 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 2715 if ((mbuf->m_pkthdr.csum_flags & 2716 (M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2717 ena_tx_ctx->l4_csum_enable = 1; 2718 else 2719 ena_tx_ctx->l4_csum_enable = 0; 2720 } else { 2721 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 2722 ena_tx_ctx->l4_csum_enable = 0; 2723 } 2724 2725 ena_meta->mss = mss; 2726 ena_meta->l3_hdr_len = iphlen; 2727 ena_meta->l3_hdr_offset = ehdrlen; 2728 ena_tx_ctx->meta_valid = 1; 2729 } 2730 2731 static int 2732 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2733 { 2734 struct ena_adapter *adapter; 2735 struct mbuf *collapsed_mbuf; 2736 int num_frags; 2737 2738 adapter = tx_ring->adapter; 2739 num_frags = ena_mbuf_count(*mbuf); 2740 2741 /* One segment must be reserved for configuration descriptor. */ 2742 if (num_frags < adapter->max_tx_sgl_size) 2743 return (0); 2744 counter_u64_add(tx_ring->tx_stats.collapse, 1); 2745 2746 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 2747 adapter->max_tx_sgl_size - 1); 2748 if (unlikely(collapsed_mbuf == NULL)) { 2749 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 2750 return (ENOMEM); 2751 } 2752 2753 /* If mbuf was collapsed succesfully, original mbuf is released. */ 2754 *mbuf = collapsed_mbuf; 2755 2756 return (0); 2757 } 2758 2759 static int 2760 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2761 { 2762 struct ena_adapter *adapter; 2763 struct ena_tx_buffer *tx_info; 2764 struct ena_com_tx_ctx ena_tx_ctx; 2765 struct ena_com_dev *ena_dev; 2766 struct ena_com_buf *ena_buf; 2767 struct ena_com_io_sq* io_sq; 2768 void *push_hdr; 2769 uint16_t next_to_use; 2770 uint16_t req_id; 2771 uint16_t ena_qid; 2772 uint32_t header_len; 2773 int i, rc; 2774 int nb_hw_desc; 2775 2776 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2777 adapter = tx_ring->que->adapter; 2778 ena_dev = adapter->ena_dev; 2779 io_sq = &ena_dev->io_sq_queues[ena_qid]; 2780 2781 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 2782 if (unlikely(rc != 0)) { 2783 ena_trace(ENA_WARNING, 2784 "Failed to collapse mbuf! err: %d", rc); 2785 return (rc); 2786 } 2787 2788 next_to_use = tx_ring->next_to_use; 2789 req_id = tx_ring->free_tx_ids[next_to_use]; 2790 tx_info = &tx_ring->tx_buffer_info[req_id]; 2791 2792 tx_info->mbuf = *mbuf; 2793 tx_info->num_of_bufs = 0; 2794 2795 ena_buf = tx_info->bufs; 2796 2797 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes", (*mbuf)->m_pkthdr.len); 2798 2799 /* 2800 * header_len is just a hint for the device. Because FreeBSD is not 2801 * giving us information about packet header length and it is not 2802 * guaranteed that all packet headers will be in the 1st mbuf, setting 2803 * header_len to 0 is making the device ignore this value and resolve 2804 * header on it's own. 2805 */ 2806 header_len = 0; 2807 push_hdr = NULL; 2808 2809 rc = bus_dmamap_load_mbuf(adapter->sc_dmat, tx_info->map, 2810 *mbuf, BUS_DMA_NOWAIT); 2811 2812 if (unlikely((rc != 0) || (tx_info->map->dm_nsegs == 0))) { 2813 ena_trace(ENA_WARNING, 2814 "dmamap load failed! err: %d nsegs: %d", rc, 2815 tx_info->map->dm_nsegs); 2816 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 2817 tx_info->mbuf = NULL; 2818 if (rc == ENOMEM) 2819 return (ENA_COM_NO_MEM); 2820 else 2821 return (ENA_COM_INVAL); 2822 } 2823 2824 for (i = 0; i < tx_info->map->dm_nsegs; i++) { 2825 ena_buf->len = tx_info->map->dm_segs[i].ds_len; 2826 ena_buf->paddr = tx_info->map->dm_segs[i].ds_addr; 2827 ena_buf++; 2828 } 2829 tx_info->num_of_bufs = tx_info->map->dm_nsegs; 2830 2831 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2832 ena_tx_ctx.ena_bufs = tx_info->bufs; 2833 ena_tx_ctx.push_header = push_hdr; 2834 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2835 ena_tx_ctx.req_id = req_id; 2836 ena_tx_ctx.header_len = header_len; 2837 2838 /* Set flags and meta data */ 2839 ena_tx_csum(&ena_tx_ctx, *mbuf); 2840 /* Prepare the packet's descriptors and send them to device */ 2841 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 2842 if (unlikely(rc != 0)) { 2843 device_printf(adapter->pdev, "failed to prepare tx bufs\n"); 2844 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 2845 goto dma_error; 2846 } 2847 2848 counter_enter(); 2849 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 2850 counter_u64_add_protected(tx_ring->tx_stats.bytes, 2851 (*mbuf)->m_pkthdr.len); 2852 2853 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 2854 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 2855 (*mbuf)->m_pkthdr.len); 2856 counter_exit(); 2857 2858 tx_info->tx_descs = nb_hw_desc; 2859 getbinuptime(&tx_info->timestamp); 2860 tx_info->print_once = true; 2861 2862 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2863 tx_ring->ring_size); 2864 2865 bus_dmamap_sync(adapter->sc_dmat, tx_info->map, 0, 2866 tx_info->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2867 2868 return (0); 2869 2870 dma_error: 2871 tx_info->mbuf = NULL; 2872 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 2873 2874 return (rc); 2875 } 2876 2877 static void 2878 ena_start_xmit(struct ena_ring *tx_ring) 2879 { 2880 struct mbuf *mbuf; 2881 struct ena_adapter *adapter = tx_ring->adapter; 2882 struct ena_com_io_sq* io_sq; 2883 int ena_qid; 2884 int acum_pkts = 0; 2885 int ret = 0; 2886 2887 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2888 return; 2889 2890 if (unlikely(!adapter->link_status)) 2891 return; 2892 2893 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2894 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 2895 2896 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 2897 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 2898 " header csum flags %#jx", 2899 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 2900 2901 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 2902 ENA_TX_CLEANUP_THRESHOLD))) 2903 ena_tx_cleanup(tx_ring); 2904 2905 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 2906 if (ret == ENA_COM_NO_MEM) { 2907 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2908 } else if (ret == ENA_COM_NO_SPACE) { 2909 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2910 } else { 2911 m_freem(mbuf); 2912 drbr_advance(adapter->ifp, tx_ring->br); 2913 } 2914 2915 break; 2916 } 2917 2918 drbr_advance(adapter->ifp, tx_ring->br); 2919 2920 if (unlikely((if_getdrvflags(adapter->ifp) & 2921 IFF_RUNNING) == 0)) 2922 return; 2923 2924 acum_pkts++; 2925 2926 /* 2927 * If there's a BPF listener, bounce a copy of this frame 2928 * to him. 2929 */ 2930 bpf_mtap(adapter->ifp, mbuf, BPF_D_OUT); 2931 2932 if (unlikely(acum_pkts == DB_THRESHOLD)) { 2933 acum_pkts = 0; 2934 wmb(); 2935 /* Trigger the dma engine */ 2936 ena_com_write_sq_doorbell(io_sq); 2937 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2938 } 2939 2940 } 2941 2942 if (likely(acum_pkts != 0)) { 2943 wmb(); 2944 /* Trigger the dma engine */ 2945 ena_com_write_sq_doorbell(io_sq); 2946 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2947 } 2948 2949 if (!ena_com_sq_have_enough_space(io_sq, ENA_TX_CLEANUP_THRESHOLD)) 2950 ena_tx_cleanup(tx_ring); 2951 } 2952 2953 static void 2954 ena_deferred_mq_start(struct work *wk, void *arg) 2955 { 2956 struct ena_ring *tx_ring = (struct ena_ring *)arg; 2957 struct ifnet *ifp = tx_ring->adapter->ifp; 2958 2959 atomic_swap_uint(&tx_ring->task_pending, 0); 2960 2961 while (!drbr_empty(ifp, tx_ring->br) && 2962 (if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2963 ENA_RING_MTX_LOCK(tx_ring); 2964 ena_start_xmit(tx_ring); 2965 ENA_RING_MTX_UNLOCK(tx_ring); 2966 } 2967 } 2968 2969 static int 2970 ena_mq_start(struct ifnet *ifp, struct mbuf *m) 2971 { 2972 struct ena_adapter *adapter = ifp->if_softc; 2973 struct ena_ring *tx_ring; 2974 int ret, is_drbr_empty; 2975 uint32_t i; 2976 2977 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2978 return (ENODEV); 2979 2980 /* Which queue to use */ 2981 /* 2982 * If everything is setup correctly, it should be the 2983 * same bucket that the current CPU we're on is. 2984 * It should improve performance. 2985 */ 2986 #if 0 2987 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 2988 #ifdef RSS 2989 if (rss_hash2bucket(m->m_pkthdr.flowid, 2990 M_HASHTYPE_GET(m), &i) == 0) { 2991 i = i % adapter->num_queues; 2992 2993 } else 2994 #endif 2995 { 2996 i = m->m_pkthdr.flowid % adapter->num_queues; 2997 } 2998 } else { 2999 #endif 3000 i = cpu_index(curcpu()) % adapter->num_queues; 3001 #if 0 3002 } 3003 #endif 3004 tx_ring = &adapter->tx_ring[i]; 3005 3006 /* Check if drbr is empty before putting packet */ 3007 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 3008 ret = drbr_enqueue(ifp, tx_ring->br, m); 3009 if (unlikely(ret != 0)) { 3010 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 3011 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 3012 curcpu()); 3013 return (ret); 3014 } 3015 3016 if ((is_drbr_empty != 0) && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 3017 ena_start_xmit(tx_ring); 3018 ENA_RING_MTX_UNLOCK(tx_ring); 3019 } else { 3020 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 3021 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 3022 curcpu()); 3023 } 3024 3025 return (0); 3026 } 3027 3028 #if 0 3029 static void 3030 ena_qflush(struct ifnet *ifp) 3031 { 3032 struct ena_adapter *adapter = ifp->if_softc; 3033 struct ena_ring *tx_ring = adapter->tx_ring; 3034 int i; 3035 3036 for(i = 0; i < adapter->num_queues; ++i, ++tx_ring) 3037 if (!drbr_empty(ifp, tx_ring->br)) { 3038 ENA_RING_MTX_LOCK(tx_ring); 3039 drbr_flush(ifp, tx_ring->br); 3040 ENA_RING_MTX_UNLOCK(tx_ring); 3041 } 3042 3043 if_qflush(ifp); 3044 } 3045 #endif 3046 3047 static int 3048 ena_calc_io_queue_num(struct pci_attach_args *pa, 3049 struct ena_adapter *adapter, 3050 struct ena_com_dev_get_features_ctx *get_feat_ctx) 3051 { 3052 int io_sq_num, io_cq_num, io_queue_num; 3053 3054 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 3055 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 3056 3057 io_queue_num = min_t(int, mp_ncpus, ENA_MAX_NUM_IO_QUEUES); 3058 io_queue_num = min_t(int, io_queue_num, io_sq_num); 3059 io_queue_num = min_t(int, io_queue_num, io_cq_num); 3060 /* 1 IRQ for for mgmnt and 1 IRQ for each TX/RX pair */ 3061 io_queue_num = min_t(int, io_queue_num, 3062 pci_msix_count(pa->pa_pc, pa->pa_tag) - 1); 3063 #ifdef RSS 3064 io_queue_num = min_t(int, io_queue_num, rss_getnumbuckets()); 3065 #endif 3066 3067 return (io_queue_num); 3068 } 3069 3070 static int 3071 ena_calc_queue_size(struct ena_adapter *adapter, uint16_t *max_tx_sgl_size, 3072 uint16_t *max_rx_sgl_size, struct ena_com_dev_get_features_ctx *feat) 3073 { 3074 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 3075 uint32_t v; 3076 uint32_t q; 3077 3078 queue_size = min_t(uint32_t, queue_size, 3079 feat->max_queues.max_cq_depth); 3080 queue_size = min_t(uint32_t, queue_size, 3081 feat->max_queues.max_sq_depth); 3082 3083 /* round down to the nearest power of 2 */ 3084 v = queue_size; 3085 while (v != 0) { 3086 if (powerof2(queue_size) != 0) 3087 break; 3088 v /= 2; 3089 q = rounddown2(queue_size, v); 3090 if (q != 0) { 3091 queue_size = q; 3092 break; 3093 } 3094 } 3095 3096 if (unlikely(queue_size == 0)) { 3097 device_printf(adapter->pdev, "Invalid queue size\n"); 3098 return (ENA_COM_FAULT); 3099 } 3100 3101 *max_tx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3102 feat->max_queues.max_packet_tx_descs); 3103 *max_rx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3104 feat->max_queues.max_packet_rx_descs); 3105 3106 return (queue_size); 3107 } 3108 3109 #if 0 3110 static int 3111 ena_rss_init_default(struct ena_adapter *adapter) 3112 { 3113 struct ena_com_dev *ena_dev = adapter->ena_dev; 3114 device_t dev = adapter->pdev; 3115 int qid, rc, i; 3116 3117 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3118 if (unlikely(rc != 0)) { 3119 device_printf(dev, "Cannot init indirect table\n"); 3120 return (rc); 3121 } 3122 3123 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3124 #ifdef RSS 3125 qid = rss_get_indirection_to_bucket(i); 3126 qid = qid % adapter->num_queues; 3127 #else 3128 qid = i % adapter->num_queues; 3129 #endif 3130 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3131 ENA_IO_RXQ_IDX(qid)); 3132 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3133 device_printf(dev, "Cannot fill indirect table\n"); 3134 goto err_rss_destroy; 3135 } 3136 } 3137 3138 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3139 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3140 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3141 device_printf(dev, "Cannot fill hash function\n"); 3142 goto err_rss_destroy; 3143 } 3144 3145 rc = ena_com_set_default_hash_ctrl(ena_dev); 3146 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3147 device_printf(dev, "Cannot fill hash control\n"); 3148 goto err_rss_destroy; 3149 } 3150 3151 return (0); 3152 3153 err_rss_destroy: 3154 ena_com_rss_destroy(ena_dev); 3155 return (rc); 3156 } 3157 3158 static void 3159 ena_rss_init_default_deferred(void *arg) 3160 { 3161 struct ena_adapter *adapter; 3162 devclass_t dc; 3163 int max; 3164 int rc; 3165 3166 dc = devclass_find("ena"); 3167 if (unlikely(dc == NULL)) { 3168 ena_trace(ENA_ALERT, "No devclass ena\n"); 3169 return; 3170 } 3171 3172 max = devclass_get_maxunit(dc); 3173 while (max-- >= 0) { 3174 adapter = devclass_get_softc(dc, max); 3175 if (adapter != NULL) { 3176 rc = ena_rss_init_default(adapter); 3177 adapter->rss_support = true; 3178 if (unlikely(rc != 0)) { 3179 device_printf(adapter->pdev, 3180 "WARNING: RSS was not properly initialized," 3181 " it will affect bandwidth\n"); 3182 adapter->rss_support = false; 3183 } 3184 } 3185 } 3186 } 3187 SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL); 3188 #endif 3189 3190 static void 3191 ena_config_host_info(struct ena_com_dev *ena_dev) 3192 { 3193 struct ena_admin_host_info *host_info; 3194 int rc; 3195 3196 /* Allocate only the host info */ 3197 rc = ena_com_allocate_host_info(ena_dev); 3198 if (unlikely(rc != 0)) { 3199 ena_trace(ENA_ALERT, "Cannot allocate host info\n"); 3200 return; 3201 } 3202 3203 host_info = ena_dev->host_attr.host_info; 3204 3205 host_info->os_type = ENA_ADMIN_OS_FREEBSD; 3206 host_info->kernel_ver = osreldate; 3207 3208 snprintf(host_info->kernel_ver_str, sizeof(host_info->kernel_ver_str), 3209 "%d", osreldate); 3210 host_info->os_dist = 0; 3211 strncpy(host_info->os_dist_str, osrelease, 3212 sizeof(host_info->os_dist_str) - 1); 3213 3214 host_info->driver_version = 3215 (DRV_MODULE_VER_MAJOR) | 3216 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 3217 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 3218 3219 rc = ena_com_set_host_attributes(ena_dev); 3220 if (unlikely(rc != 0)) { 3221 if (rc == EOPNOTSUPP) 3222 ena_trace(ENA_WARNING, "Cannot set host attributes\n"); 3223 else 3224 ena_trace(ENA_ALERT, "Cannot set host attributes\n"); 3225 3226 goto err; 3227 } 3228 3229 return; 3230 3231 err: 3232 ena_com_delete_host_info(ena_dev); 3233 } 3234 3235 static int 3236 ena_device_init(struct ena_adapter *adapter, device_t pdev, 3237 struct ena_com_dev_get_features_ctx *get_feat_ctx, int *wd_active) 3238 { 3239 struct ena_com_dev* ena_dev = adapter->ena_dev; 3240 bool readless_supported; 3241 uint32_t aenq_groups; 3242 int dma_width; 3243 int rc; 3244 3245 rc = ena_com_mmio_reg_read_request_init(ena_dev); 3246 if (unlikely(rc != 0)) { 3247 device_printf(pdev, "failed to init mmio read less\n"); 3248 return (rc); 3249 } 3250 3251 /* 3252 * The PCIe configuration space revision id indicate if mmio reg 3253 * read is disabled 3254 */ 3255 const int rev = PCI_REVISION(adapter->sc_pa.pa_class); 3256 readless_supported = ((rev & ENA_MMIO_DISABLE_REG_READ) == 0); 3257 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 3258 3259 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 3260 if (unlikely(rc != 0)) { 3261 device_printf(pdev, "Can not reset device\n"); 3262 goto err_mmio_read_less; 3263 } 3264 3265 rc = ena_com_validate_version(ena_dev); 3266 if (unlikely(rc != 0)) { 3267 device_printf(pdev, "device version is too low\n"); 3268 goto err_mmio_read_less; 3269 } 3270 3271 dma_width = ena_com_get_dma_width(ena_dev); 3272 if (unlikely(dma_width < 0)) { 3273 device_printf(pdev, "Invalid dma width value %d", dma_width); 3274 rc = dma_width; 3275 goto err_mmio_read_less; 3276 } 3277 adapter->dma_width = dma_width; 3278 3279 /* ENA admin level init */ 3280 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 3281 if (unlikely(rc != 0)) { 3282 device_printf(pdev, 3283 "Can not initialize ena admin queue with device\n"); 3284 goto err_mmio_read_less; 3285 } 3286 3287 /* 3288 * To enable the msix interrupts the driver needs to know the number 3289 * of queues. So the driver uses polling mode to retrieve this 3290 * information 3291 */ 3292 ena_com_set_admin_polling_mode(ena_dev, true); 3293 3294 ena_config_host_info(ena_dev); 3295 3296 /* Get Device Attributes */ 3297 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 3298 if (unlikely(rc != 0)) { 3299 device_printf(pdev, 3300 "Cannot get attribute for ena device rc: %d\n", rc); 3301 goto err_admin_init; 3302 } 3303 3304 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT(ENA_ADMIN_KEEP_ALIVE); 3305 3306 aenq_groups &= get_feat_ctx->aenq.supported_groups; 3307 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 3308 if (unlikely(rc != 0)) { 3309 device_printf(pdev, "Cannot configure aenq groups rc: %d\n", rc); 3310 goto err_admin_init; 3311 } 3312 3313 *wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 3314 3315 return (0); 3316 3317 err_admin_init: 3318 ena_com_delete_host_info(ena_dev); 3319 ena_com_admin_destroy(ena_dev); 3320 err_mmio_read_less: 3321 ena_com_mmio_reg_read_request_destroy(ena_dev); 3322 3323 return (rc); 3324 } 3325 3326 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 3327 int io_vectors) 3328 { 3329 struct ena_com_dev *ena_dev = adapter->ena_dev; 3330 int rc; 3331 3332 rc = ena_enable_msix(adapter); 3333 if (unlikely(rc != 0)) { 3334 device_printf(adapter->pdev, "Error with MSI-X enablement\n"); 3335 return (rc); 3336 } 3337 3338 rc = ena_request_mgmnt_irq(adapter); 3339 if (unlikely(rc != 0)) { 3340 device_printf(adapter->pdev, "Cannot setup mgmnt queue intr\n"); 3341 goto err_disable_msix; 3342 } 3343 3344 ena_com_set_admin_polling_mode(ena_dev, false); 3345 3346 ena_com_admin_aenq_enable(ena_dev); 3347 3348 return (0); 3349 3350 err_disable_msix: 3351 ena_disable_msix(adapter); 3352 3353 return (rc); 3354 } 3355 3356 /* Function called on ENA_ADMIN_KEEP_ALIVE event */ 3357 static void ena_keep_alive_wd(void *adapter_data, 3358 struct ena_admin_aenq_entry *aenq_e) 3359 { 3360 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3361 struct ena_admin_aenq_keep_alive_desc *desc; 3362 uint64_t rx_drops; 3363 3364 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3365 3366 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3367 counter_u64_zero(adapter->hw_stats.rx_drops); 3368 counter_u64_add(adapter->hw_stats.rx_drops, rx_drops); 3369 3370 atomic_store_release(&adapter->keep_alive_timestamp, getsbinuptime()); 3371 } 3372 3373 /* Check for keep alive expiration */ 3374 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 3375 { 3376 sbintime_t timestamp, time; 3377 3378 if (adapter->wd_active == 0) 3379 return; 3380 3381 if (likely(adapter->keep_alive_timeout == 0)) 3382 return; 3383 3384 timestamp = atomic_load_acquire(&adapter->keep_alive_timestamp); 3385 3386 time = getsbinuptime() - timestamp; 3387 if (unlikely(time > adapter->keep_alive_timeout)) { 3388 device_printf(adapter->pdev, 3389 "Keep alive watchdog timeout.\n"); 3390 counter_u64_add(adapter->dev_stats.wd_expired, 1); 3391 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 3392 adapter->trigger_reset = true; 3393 } 3394 } 3395 3396 /* Check if admin queue is enabled */ 3397 static void check_for_admin_com_state(struct ena_adapter *adapter) 3398 { 3399 if (unlikely(ena_com_get_admin_running_state(adapter->ena_dev) == 3400 false)) { 3401 device_printf(adapter->pdev, 3402 "ENA admin queue is not in running state!\n"); 3403 counter_u64_add(adapter->dev_stats.admin_q_pause, 1); 3404 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 3405 adapter->trigger_reset = true; 3406 } 3407 } 3408 3409 static int 3410 check_missing_comp_in_queue(struct ena_adapter *adapter, 3411 struct ena_ring *tx_ring) 3412 { 3413 struct bintime curtime, time; 3414 struct ena_tx_buffer *tx_buf; 3415 uint32_t missed_tx = 0; 3416 int i; 3417 3418 getbinuptime(&curtime); 3419 3420 for (i = 0; i < tx_ring->ring_size; i++) { 3421 tx_buf = &tx_ring->tx_buffer_info[i]; 3422 3423 if (bintime_isset(&tx_buf->timestamp) == 0) 3424 continue; 3425 3426 time = curtime; 3427 bintime_sub(&time, &tx_buf->timestamp); 3428 3429 /* Check again if packet is still waiting */ 3430 if (unlikely(bttosbt(time) > adapter->missing_tx_timeout)) { 3431 3432 if (!tx_buf->print_once) 3433 ena_trace(ENA_WARNING, "Found a Tx that wasn't " 3434 "completed on time, qid %d, index %d.\n", 3435 tx_ring->qid, i); 3436 3437 tx_buf->print_once = true; 3438 missed_tx++; 3439 counter_u64_add(tx_ring->tx_stats.missing_tx_comp, 1); 3440 3441 if (unlikely(missed_tx > 3442 adapter->missing_tx_threshold)) { 3443 device_printf(adapter->pdev, 3444 "The number of lost tx completion " 3445 "is above the threshold (%d > %d). " 3446 "Reset the device\n", 3447 missed_tx, adapter->missing_tx_threshold); 3448 adapter->reset_reason = 3449 ENA_REGS_RESET_MISS_TX_CMPL; 3450 adapter->trigger_reset = true; 3451 return (EIO); 3452 } 3453 } 3454 } 3455 3456 return (0); 3457 } 3458 3459 /* 3460 * Check for TX which were not completed on time. 3461 * Timeout is defined by "missing_tx_timeout". 3462 * Reset will be performed if number of incompleted 3463 * transactions exceeds "missing_tx_threshold". 3464 */ 3465 static void 3466 check_for_missing_tx_completions(struct ena_adapter *adapter) 3467 { 3468 struct ena_ring *tx_ring; 3469 int i, budget, rc; 3470 3471 /* Make sure the driver doesn't turn the device in other process */ 3472 rmb(); 3473 3474 if (!adapter->up) 3475 return; 3476 3477 if (adapter->trigger_reset) 3478 return; 3479 3480 if (adapter->missing_tx_timeout == 0) 3481 return; 3482 3483 budget = adapter->missing_tx_max_queues; 3484 3485 for (i = adapter->next_monitored_tx_qid; i < adapter->num_queues; i++) { 3486 tx_ring = &adapter->tx_ring[i]; 3487 3488 rc = check_missing_comp_in_queue(adapter, tx_ring); 3489 if (unlikely(rc != 0)) 3490 return; 3491 3492 budget--; 3493 if (budget == 0) { 3494 i++; 3495 break; 3496 } 3497 } 3498 3499 adapter->next_monitored_tx_qid = i % adapter->num_queues; 3500 } 3501 3502 /* trigger deferred rx cleanup after 2 consecutive detections */ 3503 #define EMPTY_RX_REFILL 2 3504 /* For the rare case where the device runs out of Rx descriptors and the 3505 * msix handler failed to refill new Rx descriptors (due to a lack of memory 3506 * for example). 3507 * This case will lead to a deadlock: 3508 * The device won't send interrupts since all the new Rx packets will be dropped 3509 * The msix handler won't allocate new Rx descriptors so the device won't be 3510 * able to send new packets. 3511 * 3512 * When such a situation is detected - execute rx cleanup task in another thread 3513 */ 3514 static void 3515 check_for_empty_rx_ring(struct ena_adapter *adapter) 3516 { 3517 struct ena_ring *rx_ring; 3518 int i, refill_required; 3519 3520 if (!adapter->up) 3521 return; 3522 3523 if (adapter->trigger_reset) 3524 return; 3525 3526 for (i = 0; i < adapter->num_queues; i++) { 3527 rx_ring = &adapter->rx_ring[i]; 3528 3529 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 3530 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 3531 rx_ring->empty_rx_queue++; 3532 3533 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 3534 counter_u64_add(rx_ring->rx_stats.empty_rx_ring, 3535 1); 3536 3537 device_printf(adapter->pdev, 3538 "trigger refill for ring %d\n", i); 3539 3540 if (atomic_cas_uint(&rx_ring->task_pending, 0, 1) == 0) 3541 workqueue_enqueue(rx_ring->cmpl_tq, 3542 &rx_ring->cmpl_task, curcpu()); 3543 rx_ring->empty_rx_queue = 0; 3544 } 3545 } else { 3546 rx_ring->empty_rx_queue = 0; 3547 } 3548 } 3549 } 3550 3551 static void 3552 ena_timer_service(void *data) 3553 { 3554 struct ena_adapter *adapter = (struct ena_adapter *)data; 3555 struct ena_admin_host_info *host_info = 3556 adapter->ena_dev->host_attr.host_info; 3557 3558 check_for_missing_keep_alive(adapter); 3559 3560 check_for_admin_com_state(adapter); 3561 3562 check_for_missing_tx_completions(adapter); 3563 3564 check_for_empty_rx_ring(adapter); 3565 3566 if (host_info != NULL) 3567 ena_update_host_info(host_info, adapter->ifp); 3568 3569 if (unlikely(adapter->trigger_reset)) { 3570 device_printf(adapter->pdev, "Trigger reset is on\n"); 3571 workqueue_enqueue(adapter->reset_tq, &adapter->reset_task, 3572 curcpu()); 3573 return; 3574 } 3575 3576 /* 3577 * Schedule another timeout one second from now. 3578 */ 3579 callout_schedule(&adapter->timer_service, hz); 3580 } 3581 3582 static void 3583 ena_reset_task(struct work *wk, void *arg) 3584 { 3585 struct ena_com_dev_get_features_ctx get_feat_ctx; 3586 struct ena_adapter *adapter = (struct ena_adapter *)arg; 3587 struct ena_com_dev *ena_dev = adapter->ena_dev; 3588 bool dev_up; 3589 int rc; 3590 3591 if (unlikely(!adapter->trigger_reset)) { 3592 device_printf(adapter->pdev, 3593 "device reset scheduled but trigger_reset is off\n"); 3594 return; 3595 } 3596 3597 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3598 3599 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3600 3601 dev_up = adapter->up; 3602 3603 ena_com_set_admin_running_state(ena_dev, false); 3604 ena_down(adapter); 3605 ena_free_mgmnt_irq(adapter); 3606 ena_disable_msix(adapter); 3607 ena_com_abort_admin_commands(ena_dev); 3608 ena_com_wait_for_abort_completion(ena_dev); 3609 ena_com_admin_destroy(ena_dev); 3610 ena_com_mmio_reg_read_request_destroy(ena_dev); 3611 3612 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3613 adapter->trigger_reset = false; 3614 3615 /* Finished destroy part. Restart the device */ 3616 rc = ena_device_init(adapter, adapter->pdev, &get_feat_ctx, 3617 &adapter->wd_active); 3618 if (unlikely(rc != 0)) { 3619 device_printf(adapter->pdev, 3620 "ENA device init failed! (err: %d)\n", rc); 3621 goto err_dev_free; 3622 } 3623 3624 /* XXX dealloc and realloc MSI-X, probably a waste */ 3625 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 3626 adapter->num_queues); 3627 if (unlikely(rc != 0)) { 3628 device_printf(adapter->pdev, "Enable MSI-X failed\n"); 3629 goto err_com_free; 3630 } 3631 3632 /* If the interface was up before the reset bring it up */ 3633 if (dev_up) { 3634 rc = ena_up(adapter); 3635 if (unlikely(rc != 0)) { 3636 device_printf(adapter->pdev, 3637 "Failed to create I/O queues\n"); 3638 goto err_msix_free; 3639 } 3640 } 3641 3642 callout_schedule(&adapter->timer_service, hz); 3643 3644 rw_exit(&adapter->ioctl_sx); 3645 3646 return; 3647 3648 err_msix_free: 3649 ena_free_mgmnt_irq(adapter); 3650 ena_disable_msix(adapter); 3651 err_com_free: 3652 ena_com_admin_destroy(ena_dev); 3653 err_dev_free: 3654 device_printf(adapter->pdev, "ENA reset failed!\n"); 3655 adapter->running = false; 3656 rw_exit(&adapter->ioctl_sx); 3657 } 3658 3659 /** 3660 * ena_attach - Device Initialization Routine 3661 * @pdev: device information struct 3662 * 3663 * Returns 0 on success, otherwise on failure. 3664 * 3665 * ena_attach initializes an adapter identified by a device structure. 3666 * The OS initialization, configuring of the adapter private structure, 3667 * and a hardware reset occur. 3668 **/ 3669 static void 3670 ena_attach(device_t parent, device_t self, void *aux) 3671 { 3672 struct pci_attach_args *pa = aux; 3673 struct ena_com_dev_get_features_ctx get_feat_ctx; 3674 static int version_printed; 3675 struct ena_adapter *adapter = device_private(self); 3676 struct ena_com_dev *ena_dev = NULL; 3677 uint16_t tx_sgl_size = 0; 3678 uint16_t rx_sgl_size = 0; 3679 pcireg_t reg; 3680 int io_queue_num; 3681 int queue_size; 3682 int rc; 3683 3684 adapter->pdev = self; 3685 adapter->ifp = &adapter->sc_ec.ec_if; 3686 adapter->sc_pa = *pa; /* used after attach for adapter reset too */ 3687 3688 if (pci_dma64_available(pa)) 3689 adapter->sc_dmat = pa->pa_dmat64; 3690 else 3691 adapter->sc_dmat = pa->pa_dmat; 3692 3693 pci_aprint_devinfo(pa, NULL); 3694 3695 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3696 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) { 3697 reg |= PCI_COMMAND_MASTER_ENABLE; 3698 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 3699 } 3700 3701 mutex_init(&adapter->global_mtx, MUTEX_DEFAULT, IPL_NET); 3702 rw_init(&adapter->ioctl_sx); 3703 3704 /* Set up the timer service */ 3705 adapter->keep_alive_timeout = DEFAULT_KEEP_ALIVE_TO; 3706 adapter->missing_tx_timeout = DEFAULT_TX_CMP_TO; 3707 adapter->missing_tx_max_queues = DEFAULT_TX_MONITORED_QUEUES; 3708 adapter->missing_tx_threshold = DEFAULT_TX_CMP_THRESHOLD; 3709 3710 if (version_printed++ == 0) 3711 device_printf(parent, "%s\n", ena_version); 3712 3713 rc = ena_allocate_pci_resources(pa, adapter); 3714 if (unlikely(rc != 0)) { 3715 device_printf(parent, "PCI resource allocation failed!\n"); 3716 ena_free_pci_resources(adapter); 3717 return; 3718 } 3719 3720 /* Allocate memory for ena_dev structure */ 3721 ena_dev = malloc(sizeof(struct ena_com_dev), M_DEVBUF, 3722 M_WAITOK | M_ZERO); 3723 3724 adapter->ena_dev = ena_dev; 3725 ena_dev->dmadev = self; 3726 ena_dev->bus = malloc(sizeof(struct ena_bus), M_DEVBUF, 3727 M_WAITOK | M_ZERO); 3728 3729 /* Store register resources */ 3730 ((struct ena_bus*)(ena_dev->bus))->reg_bar_t = adapter->sc_btag; 3731 ((struct ena_bus*)(ena_dev->bus))->reg_bar_h = adapter->sc_bhandle; 3732 3733 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3734 3735 /* Device initialization */ 3736 rc = ena_device_init(adapter, self, &get_feat_ctx, &adapter->wd_active); 3737 if (unlikely(rc != 0)) { 3738 device_printf(self, "ENA device init failed! (err: %d)\n", rc); 3739 rc = ENXIO; 3740 goto err_bus_free; 3741 } 3742 3743 adapter->keep_alive_timestamp = getsbinuptime(); 3744 3745 adapter->tx_offload_cap = get_feat_ctx.offload.tx; 3746 3747 /* Set for sure that interface is not up */ 3748 adapter->up = false; 3749 3750 memcpy(adapter->mac_addr, get_feat_ctx.dev_attr.mac_addr, 3751 ETHER_ADDR_LEN); 3752 3753 /* calculate IO queue number to create */ 3754 io_queue_num = ena_calc_io_queue_num(pa, adapter, &get_feat_ctx); 3755 3756 ENA_ASSERT(io_queue_num > 0, "Invalid queue number: %d\n", 3757 io_queue_num); 3758 adapter->num_queues = io_queue_num; 3759 3760 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 3761 3762 /* calculatre ring sizes */ 3763 queue_size = ena_calc_queue_size(adapter,&tx_sgl_size, 3764 &rx_sgl_size, &get_feat_ctx); 3765 if (unlikely((queue_size <= 0) || (io_queue_num <= 0))) { 3766 rc = ENA_COM_FAULT; 3767 goto err_com_free; 3768 } 3769 3770 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3771 3772 adapter->tx_ring_size = queue_size; 3773 adapter->rx_ring_size = queue_size; 3774 3775 adapter->max_tx_sgl_size = tx_sgl_size; 3776 adapter->max_rx_sgl_size = rx_sgl_size; 3777 3778 #if 0 3779 /* set up dma tags for rx and tx buffers */ 3780 rc = ena_setup_tx_dma_tag(adapter); 3781 if (unlikely(rc != 0)) { 3782 device_printf(self, "Failed to create TX DMA tag\n"); 3783 goto err_com_free; 3784 } 3785 3786 rc = ena_setup_rx_dma_tag(adapter); 3787 if (unlikely(rc != 0)) { 3788 device_printf(self, "Failed to create RX DMA tag\n"); 3789 goto err_tx_tag_free; 3790 } 3791 #endif 3792 3793 /* initialize rings basic information */ 3794 device_printf(self, "initialize %d io queues\n", io_queue_num); 3795 ena_init_io_rings(adapter); 3796 3797 /* setup network interface */ 3798 rc = ena_setup_ifnet(self, adapter, &get_feat_ctx); 3799 if (unlikely(rc != 0)) { 3800 device_printf(self, "Error with network interface setup\n"); 3801 goto err_io_free; 3802 } 3803 3804 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3805 if (unlikely(rc != 0)) { 3806 device_printf(self, 3807 "Failed to enable and set the admin interrupts\n"); 3808 goto err_ifp_free; 3809 } 3810 3811 callout_init(&adapter->timer_service, CALLOUT_FLAGS); 3812 callout_setfunc(&adapter->timer_service, ena_timer_service, adapter); 3813 3814 /* Initialize reset task queue */ 3815 rc = workqueue_create(&adapter->reset_tq, "ena_reset_enq", 3816 ena_reset_task, adapter, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 3817 if (unlikely(rc != 0)) { 3818 ena_trace(ENA_ALERT, 3819 "Unable to create workqueue for reset task\n"); 3820 goto err_ifp_free; 3821 } 3822 3823 /* Initialize statistics */ 3824 ena_alloc_counters_dev(&adapter->dev_stats, io_queue_num); 3825 ena_alloc_counters_hwstats(&adapter->hw_stats, io_queue_num); 3826 #if 0 3827 ena_sysctl_add_nodes(adapter); 3828 #endif 3829 3830 /* Tell the stack that the interface is not active */ 3831 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, IFF_RUNNING); 3832 3833 adapter->running = true; 3834 return; 3835 3836 err_ifp_free: 3837 if_detach(adapter->ifp); 3838 if_free(adapter->ifp); 3839 err_io_free: 3840 ena_free_all_io_rings_resources(adapter); 3841 #if 0 3842 ena_free_rx_dma_tag(adapter); 3843 err_tx_tag_free: 3844 ena_free_tx_dma_tag(adapter); 3845 #endif 3846 err_com_free: 3847 ena_com_admin_destroy(ena_dev); 3848 ena_com_delete_host_info(ena_dev); 3849 ena_com_mmio_reg_read_request_destroy(ena_dev); 3850 err_bus_free: 3851 free(ena_dev->bus, M_DEVBUF); 3852 free(ena_dev, M_DEVBUF); 3853 ena_free_pci_resources(adapter); 3854 } 3855 3856 /** 3857 * ena_detach - Device Removal Routine 3858 * @pdev: device information struct 3859 * 3860 * ena_detach is called by the device subsystem to alert the driver 3861 * that it should release a PCI device. 3862 **/ 3863 static int 3864 ena_detach(device_t pdev, int flags) 3865 { 3866 struct ena_adapter *adapter = device_private(pdev); 3867 struct ena_com_dev *ena_dev = adapter->ena_dev; 3868 #if 0 3869 int rc; 3870 #endif 3871 3872 /* Make sure VLANS are not using driver */ 3873 if (VLAN_ATTACHED(&adapter->sc_ec)) { 3874 device_printf(adapter->pdev ,"VLAN is in use, detach first\n"); 3875 return (EBUSY); 3876 } 3877 3878 /* Free reset task and callout */ 3879 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3880 callout_destroy(&adapter->timer_service); 3881 workqueue_wait(adapter->reset_tq, &adapter->reset_task); 3882 workqueue_destroy(adapter->reset_tq); 3883 adapter->reset_tq = NULL; 3884 3885 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3886 ena_down(adapter); 3887 rw_exit(&adapter->ioctl_sx); 3888 3889 if (adapter->ifp != NULL) { 3890 ether_ifdetach(adapter->ifp); 3891 if_free(adapter->ifp); 3892 } 3893 ifmedia_fini(&adapter->media); 3894 3895 ena_free_all_io_rings_resources(adapter); 3896 3897 ena_free_counters((struct evcnt *)&adapter->hw_stats, 3898 sizeof(struct ena_hw_stats)); 3899 ena_free_counters((struct evcnt *)&adapter->dev_stats, 3900 sizeof(struct ena_stats_dev)); 3901 3902 if (likely(adapter->rss_support)) 3903 ena_com_rss_destroy(ena_dev); 3904 3905 #if 0 3906 rc = ena_free_rx_dma_tag(adapter); 3907 if (unlikely(rc != 0)) 3908 device_printf(adapter->pdev, 3909 "Unmapped RX DMA tag associations\n"); 3910 3911 rc = ena_free_tx_dma_tag(adapter); 3912 if (unlikely(rc != 0)) 3913 device_printf(adapter->pdev, 3914 "Unmapped TX DMA tag associations\n"); 3915 #endif 3916 3917 /* Reset the device only if the device is running. */ 3918 if (adapter->running) 3919 ena_com_dev_reset(ena_dev, adapter->reset_reason); 3920 3921 ena_com_delete_host_info(ena_dev); 3922 3923 ena_free_irqs(adapter); 3924 3925 ena_com_abort_admin_commands(ena_dev); 3926 3927 ena_com_wait_for_abort_completion(ena_dev); 3928 3929 ena_com_admin_destroy(ena_dev); 3930 3931 ena_com_mmio_reg_read_request_destroy(ena_dev); 3932 3933 ena_free_pci_resources(adapter); 3934 3935 mutex_destroy(&adapter->global_mtx); 3936 rw_destroy(&adapter->ioctl_sx); 3937 3938 if (ena_dev->bus != NULL) 3939 free(ena_dev->bus, M_DEVBUF); 3940 3941 if (ena_dev != NULL) 3942 free(ena_dev, M_DEVBUF); 3943 3944 return 0; 3945 } 3946 3947 /****************************************************************************** 3948 ******************************** AENQ Handlers ******************************* 3949 *****************************************************************************/ 3950 /** 3951 * ena_update_on_link_change: 3952 * Notify the network interface about the change in link status 3953 **/ 3954 static void 3955 ena_update_on_link_change(void *adapter_data, 3956 struct ena_admin_aenq_entry *aenq_e) 3957 { 3958 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3959 struct ena_admin_aenq_link_change_desc *aenq_desc; 3960 int status; 3961 struct ifnet *ifp; 3962 3963 aenq_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3964 ifp = adapter->ifp; 3965 status = aenq_desc->flags & 3966 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3967 3968 if (status != 0) { 3969 device_printf(adapter->pdev, "link is UP\n"); 3970 if_link_state_change(ifp, LINK_STATE_UP); 3971 } else if (status == 0) { 3972 device_printf(adapter->pdev, "link is DOWN\n"); 3973 if_link_state_change(ifp, LINK_STATE_DOWN); 3974 } else { 3975 device_printf(adapter->pdev, "invalid value recvd\n"); 3976 BUG(); 3977 } 3978 3979 adapter->link_status = status; 3980 } 3981 3982 /** 3983 * This handler will called for unknown event group or unimplemented handlers 3984 **/ 3985 static void 3986 unimplemented_aenq_handler(void *data, 3987 struct ena_admin_aenq_entry *aenq_e) 3988 { 3989 return; 3990 } 3991 3992 static struct ena_aenq_handlers aenq_handlers = { 3993 .handlers = { 3994 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3995 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 3996 }, 3997 .unimplemented_handler = unimplemented_aenq_handler 3998 }; 3999 4000 #ifdef __FreeBSD__ 4001 /********************************************************************* 4002 * FreeBSD Device Interface Entry Points 4003 *********************************************************************/ 4004 4005 static device_method_t ena_methods[] = { 4006 /* Device interface */ 4007 DEVMETHOD(device_probe, ena_probe), 4008 DEVMETHOD(device_attach, ena_attach), 4009 DEVMETHOD(device_detach, ena_detach), 4010 DEVMETHOD_END 4011 }; 4012 4013 static driver_t ena_driver = { 4014 "ena", ena_methods, sizeof(struct ena_adapter), 4015 }; 4016 4017 devclass_t ena_devclass; 4018 DRIVER_MODULE(ena, pci, ena_driver, ena_devclass, 0, 0); 4019 MODULE_DEPEND(ena, pci, 1, 1, 1); 4020 MODULE_DEPEND(ena, ether, 1, 1, 1); 4021 4022 /*********************************************************************/ 4023 #endif /* __FreeBSD__ */ 4024 4025 #ifdef __NetBSD__ 4026 CFATTACH_DECL_NEW(ena, sizeof(struct ena_adapter), ena_probe, ena_attach, 4027 ena_detach, NULL); 4028 #endif /* __NetBSD */ 4029