1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 #if 0 32 __FBSDID("$FreeBSD: head/sys/dev/ena/ena.c 333456 2018-05-10 09:37:54Z mw $"); 33 #endif 34 __KERNEL_RCSID(0, "$NetBSD: if_ena.c,v 1.5 2018/06/26 06:48:01 msaitoh Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/endian.h> 40 #include <sys/kernel.h> 41 #include <sys/kthread.h> 42 #include <sys/malloc.h> 43 #include <sys/mbuf.h> 44 #include <sys/module.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/time.h> 49 #include <sys/workqueue.h> 50 #include <sys/callout.h> 51 #include <sys/interrupt.h> 52 #include <sys/cpu.h> 53 54 #include <sys/bus.h> 55 56 #include <net/if_ether.h> 57 #include <net/if_vlanvar.h> 58 59 #include <dev/pci/if_enavar.h> 60 61 /********************************************************* 62 * Function prototypes 63 *********************************************************/ 64 static int ena_probe(device_t, cfdata_t, void *); 65 static int ena_intr_msix_mgmnt(void *); 66 static int ena_allocate_pci_resources(struct pci_attach_args *, 67 struct ena_adapter *); 68 static void ena_free_pci_resources(struct ena_adapter *); 69 static int ena_change_mtu(struct ifnet *, int); 70 static void ena_init_io_rings_common(struct ena_adapter *, 71 struct ena_ring *, uint16_t); 72 static void ena_init_io_rings(struct ena_adapter *); 73 static void ena_free_io_ring_resources(struct ena_adapter *, unsigned int); 74 static void ena_free_all_io_rings_resources(struct ena_adapter *); 75 #if 0 76 static int ena_setup_tx_dma_tag(struct ena_adapter *); 77 static int ena_free_tx_dma_tag(struct ena_adapter *); 78 static int ena_setup_rx_dma_tag(struct ena_adapter *); 79 static int ena_free_rx_dma_tag(struct ena_adapter *); 80 #endif 81 static int ena_setup_tx_resources(struct ena_adapter *, int); 82 static void ena_free_tx_resources(struct ena_adapter *, int); 83 static int ena_setup_all_tx_resources(struct ena_adapter *); 84 static void ena_free_all_tx_resources(struct ena_adapter *); 85 static inline int validate_rx_req_id(struct ena_ring *, uint16_t); 86 static int ena_setup_rx_resources(struct ena_adapter *, unsigned int); 87 static void ena_free_rx_resources(struct ena_adapter *, unsigned int); 88 static int ena_setup_all_rx_resources(struct ena_adapter *); 89 static void ena_free_all_rx_resources(struct ena_adapter *); 90 static inline int ena_alloc_rx_mbuf(struct ena_adapter *, struct ena_ring *, 91 struct ena_rx_buffer *); 92 static void ena_free_rx_mbuf(struct ena_adapter *, struct ena_ring *, 93 struct ena_rx_buffer *); 94 static int ena_refill_rx_bufs(struct ena_ring *, uint32_t); 95 static void ena_free_rx_bufs(struct ena_adapter *, unsigned int); 96 static void ena_refill_all_rx_bufs(struct ena_adapter *); 97 static void ena_free_all_rx_bufs(struct ena_adapter *); 98 static void ena_free_tx_bufs(struct ena_adapter *, unsigned int); 99 static void ena_free_all_tx_bufs(struct ena_adapter *); 100 static void ena_destroy_all_tx_queues(struct ena_adapter *); 101 static void ena_destroy_all_rx_queues(struct ena_adapter *); 102 static void ena_destroy_all_io_queues(struct ena_adapter *); 103 static int ena_create_io_queues(struct ena_adapter *); 104 static int ena_tx_cleanup(struct ena_ring *); 105 static void ena_deferred_rx_cleanup(struct work *, void *); 106 static int ena_rx_cleanup(struct ena_ring *); 107 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 108 #if 0 109 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 110 struct mbuf *); 111 #endif 112 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 113 struct ena_com_rx_ctx *, uint16_t *); 114 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 115 struct mbuf *); 116 static int ena_handle_msix(void *); 117 static int ena_enable_msix(struct ena_adapter *); 118 static int ena_request_mgmnt_irq(struct ena_adapter *); 119 static int ena_request_io_irq(struct ena_adapter *); 120 static void ena_free_mgmnt_irq(struct ena_adapter *); 121 static void ena_free_io_irq(struct ena_adapter *); 122 static void ena_free_irqs(struct ena_adapter*); 123 static void ena_disable_msix(struct ena_adapter *); 124 static void ena_unmask_all_io_irqs(struct ena_adapter *); 125 static int ena_rss_configure(struct ena_adapter *); 126 static int ena_up_complete(struct ena_adapter *); 127 static int ena_up(struct ena_adapter *); 128 static void ena_down(struct ena_adapter *); 129 #if 0 130 static uint64_t ena_get_counter(struct ifnet *, ift_counter); 131 #endif 132 static int ena_media_change(struct ifnet *); 133 static void ena_media_status(struct ifnet *, struct ifmediareq *); 134 static int ena_init(struct ifnet *); 135 static int ena_ioctl(struct ifnet *, u_long, void *); 136 static int ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *); 137 static void ena_update_host_info(struct ena_admin_host_info *, struct ifnet *); 138 static void ena_update_hwassist(struct ena_adapter *); 139 static int ena_setup_ifnet(device_t, struct ena_adapter *, 140 struct ena_com_dev_get_features_ctx *); 141 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *); 142 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 143 struct mbuf **mbuf); 144 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 145 static void ena_start_xmit(struct ena_ring *); 146 static int ena_mq_start(struct ifnet *, struct mbuf *); 147 static void ena_deferred_mq_start(struct work *, void *); 148 #if 0 149 static void ena_qflush(struct ifnet *); 150 #endif 151 static int ena_calc_io_queue_num(struct pci_attach_args *, 152 struct ena_adapter *, struct ena_com_dev_get_features_ctx *); 153 static int ena_calc_queue_size(struct ena_adapter *, uint16_t *, 154 uint16_t *, struct ena_com_dev_get_features_ctx *); 155 #if 0 156 static int ena_rss_init_default(struct ena_adapter *); 157 static void ena_rss_init_default_deferred(void *); 158 #endif 159 static void ena_config_host_info(struct ena_com_dev *); 160 static void ena_attach(device_t, device_t, void *); 161 static int ena_detach(device_t, int); 162 static int ena_device_init(struct ena_adapter *, device_t, 163 struct ena_com_dev_get_features_ctx *, int *); 164 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *, 165 int); 166 static void ena_update_on_link_change(void *, struct ena_admin_aenq_entry *); 167 static void unimplemented_aenq_handler(void *, 168 struct ena_admin_aenq_entry *); 169 static void ena_timer_service(void *); 170 171 static const char ena_version[] = 172 DEVICE_NAME DRV_MODULE_NAME " v" DRV_MODULE_VERSION; 173 174 #if 0 175 static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD, 0, "ENA driver parameters"); 176 #endif 177 178 /* 179 * Tuneable number of buffers in the buf-ring (drbr) 180 */ 181 static int ena_buf_ring_size = 4096; 182 #if 0 183 SYSCTL_INT(_hw_ena, OID_AUTO, buf_ring_size, CTLFLAG_RWTUN, 184 &ena_buf_ring_size, 0, "Size of the bufring"); 185 #endif 186 187 /* 188 * Logging level for changing verbosity of the output 189 */ 190 int ena_log_level = ENA_ALERT | ENA_WARNING; 191 #if 0 192 SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, 193 &ena_log_level, 0, "Logging level indicating verbosity of the logs"); 194 #endif 195 196 static const ena_vendor_info_t ena_vendor_info_array[] = { 197 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_PF, 0}, 198 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_PF, 0}, 199 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_VF, 0}, 200 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_VF, 0}, 201 /* Last entry */ 202 { 0, 0, 0 } 203 }; 204 205 /* 206 * Contains pointers to event handlers, e.g. link state chage. 207 */ 208 static struct ena_aenq_handlers aenq_handlers; 209 210 int 211 ena_dma_alloc(device_t dmadev, bus_size_t size, 212 ena_mem_handle_t *dma , int mapflags) 213 { 214 struct ena_adapter *adapter = device_private(dmadev); 215 uint32_t maxsize; 216 bus_dma_segment_t seg; 217 int error, nsegs; 218 219 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; 220 221 #if 0 222 /* XXX what is this needed for ? */ 223 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); 224 if (unlikely(dma_space_addr == 0)) 225 dma_space_addr = BUS_SPACE_MAXADDR; 226 #endif 227 228 dma->tag = adapter->sc_dmat; 229 230 if ((error = bus_dmamap_create(dma->tag, maxsize, 1, maxsize, 0, 231 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->map)) != 0) { 232 ena_trace(ENA_ALERT, "bus_dmamap_create(%ju) failed: %d\n", 233 (uintmax_t)maxsize, error); 234 goto fail_create; 235 } 236 237 error = bus_dmamem_alloc(dma->tag, maxsize, 8, 0, &seg, 1, &nsegs, 238 BUS_DMA_ALLOCNOW); 239 if (error) { 240 ena_trace(ENA_ALERT, "bus_dmamem_alloc(%ju) failed: %d\n", 241 (uintmax_t)maxsize, error); 242 goto fail_alloc; 243 } 244 245 error = bus_dmamem_map(dma->tag, &seg, nsegs, maxsize, 246 &dma->vaddr, BUS_DMA_COHERENT); 247 if (error) { 248 ena_trace(ENA_ALERT, "bus_dmamem_map(%ju) failed: %d\n", 249 (uintmax_t)maxsize, error); 250 goto fail_map; 251 } 252 memset(dma->vaddr, 0, maxsize); 253 254 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 255 maxsize, NULL, mapflags); 256 if (error) { 257 ena_trace(ENA_ALERT, ": bus_dmamap_load failed: %d\n", error); 258 goto fail_load; 259 } 260 dma->paddr = dma->map->dm_segs[0].ds_addr; 261 262 return (0); 263 264 fail_load: 265 bus_dmamem_unmap(dma->tag, dma->vaddr, maxsize); 266 fail_map: 267 bus_dmamem_free(dma->tag, &seg, nsegs); 268 fail_alloc: 269 bus_dmamap_destroy(adapter->sc_dmat, dma->map); 270 fail_create: 271 return (error); 272 } 273 274 static int 275 ena_allocate_pci_resources(struct pci_attach_args *pa, 276 struct ena_adapter *adapter) 277 { 278 bus_size_t size; 279 280 /* 281 * Map control/status registers. 282 */ 283 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ENA_REG_BAR); 284 if (pci_mapreg_map(pa, ENA_REG_BAR, memtype, 0, &adapter->sc_btag, 285 &adapter->sc_bhandle, NULL, &size)) { 286 aprint_error(": can't map mem space\n"); 287 return ENXIO; 288 } 289 290 return (0); 291 } 292 293 static void 294 ena_free_pci_resources(struct ena_adapter *adapter) 295 { 296 /* Nothing to do */ 297 } 298 299 static int 300 ena_probe(device_t parent, cfdata_t match, void *aux) 301 { 302 struct pci_attach_args *pa = aux; 303 const ena_vendor_info_t *ent; 304 305 for (int i = 0; i < __arraycount(ena_vendor_info_array); i++) { 306 ent = &ena_vendor_info_array[i]; 307 308 if ((PCI_VENDOR(pa->pa_id) == ent->vendor_id) && 309 (PCI_PRODUCT(pa->pa_id) == ent->device_id)) { 310 return 1; 311 } 312 } 313 314 return 0; 315 } 316 317 static int 318 ena_change_mtu(struct ifnet *ifp, int new_mtu) 319 { 320 struct ena_adapter *adapter = if_getsoftc(ifp); 321 int rc; 322 323 if ((new_mtu > adapter->max_mtu) || (new_mtu < ENA_MIN_MTU)) { 324 device_printf(adapter->pdev, "Invalid MTU setting. " 325 "new_mtu: %d max mtu: %d min mtu: %d\n", 326 new_mtu, adapter->max_mtu, ENA_MIN_MTU); 327 return (EINVAL); 328 } 329 330 rc = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 331 if (likely(rc == 0)) { 332 ena_trace(ENA_DBG, "set MTU to %d\n", new_mtu); 333 if_setmtu(ifp, new_mtu); 334 } else { 335 device_printf(adapter->pdev, "Failed to set MTU to %d\n", 336 new_mtu); 337 } 338 339 return (rc); 340 } 341 342 #define EVCNT_INIT(st, f) \ 343 do { \ 344 evcnt_attach_dynamic(&st->f, EVCNT_TYPE_MISC, NULL, \ 345 st->name, #f); \ 346 } while (0) 347 348 static inline void 349 ena_alloc_counters_rx(struct ena_stats_rx *st, int queue) 350 { 351 snprintf(st->name, sizeof(st->name), "ena rxq%d", queue); 352 353 EVCNT_INIT(st, cnt); 354 EVCNT_INIT(st, bytes); 355 EVCNT_INIT(st, refil_partial); 356 EVCNT_INIT(st, bad_csum); 357 EVCNT_INIT(st, mjum_alloc_fail); 358 EVCNT_INIT(st, mbuf_alloc_fail); 359 EVCNT_INIT(st, dma_mapping_err); 360 EVCNT_INIT(st, bad_desc_num); 361 EVCNT_INIT(st, bad_req_id); 362 EVCNT_INIT(st, empty_rx_ring); 363 364 /* Make sure all code is updated when new fields added */ 365 CTASSERT(offsetof(struct ena_stats_rx, empty_rx_ring) 366 + sizeof(st->empty_rx_ring) == sizeof(*st)); 367 } 368 369 static inline void 370 ena_alloc_counters_tx(struct ena_stats_tx *st, int queue) 371 { 372 snprintf(st->name, sizeof(st->name), "ena txq%d", queue); 373 374 EVCNT_INIT(st, cnt); 375 EVCNT_INIT(st, bytes); 376 EVCNT_INIT(st, prepare_ctx_err); 377 EVCNT_INIT(st, dma_mapping_err); 378 EVCNT_INIT(st, doorbells); 379 EVCNT_INIT(st, missing_tx_comp); 380 EVCNT_INIT(st, bad_req_id); 381 EVCNT_INIT(st, collapse); 382 EVCNT_INIT(st, collapse_err); 383 384 /* Make sure all code is updated when new fields added */ 385 CTASSERT(offsetof(struct ena_stats_tx, collapse_err) 386 + sizeof(st->collapse_err) == sizeof(*st)); 387 } 388 389 static inline void 390 ena_alloc_counters_dev(struct ena_stats_dev *st, int queue) 391 { 392 snprintf(st->name, sizeof(st->name), "ena dev ioq%d", queue); 393 394 EVCNT_INIT(st, wd_expired); 395 EVCNT_INIT(st, interface_up); 396 EVCNT_INIT(st, interface_down); 397 EVCNT_INIT(st, admin_q_pause); 398 399 /* Make sure all code is updated when new fields added */ 400 CTASSERT(offsetof(struct ena_stats_dev, admin_q_pause) 401 + sizeof(st->admin_q_pause) == sizeof(*st)); 402 } 403 404 static inline void 405 ena_alloc_counters_hwstats(struct ena_hw_stats *st, int queue) 406 { 407 snprintf(st->name, sizeof(st->name), "ena hw ioq%d", queue); 408 409 EVCNT_INIT(st, rx_packets); 410 EVCNT_INIT(st, tx_packets); 411 EVCNT_INIT(st, rx_bytes); 412 EVCNT_INIT(st, tx_bytes); 413 EVCNT_INIT(st, rx_drops); 414 415 /* Make sure all code is updated when new fields added */ 416 CTASSERT(offsetof(struct ena_hw_stats, rx_drops) 417 + sizeof(st->rx_drops) == sizeof(*st)); 418 } 419 static inline void 420 ena_free_counters(struct evcnt *begin, int size) 421 { 422 struct evcnt *end = (struct evcnt *)((char *)begin + size); 423 424 for (; begin < end; ++begin) 425 counter_u64_free(*begin); 426 } 427 428 static inline void 429 ena_reset_counters(struct evcnt *begin, int size) 430 { 431 struct evcnt *end = (struct evcnt *)((char *)begin + size); 432 433 for (; begin < end; ++begin) 434 counter_u64_zero(*begin); 435 } 436 437 static void 438 ena_init_io_rings_common(struct ena_adapter *adapter, struct ena_ring *ring, 439 uint16_t qid) 440 { 441 442 ring->qid = qid; 443 ring->adapter = adapter; 444 ring->ena_dev = adapter->ena_dev; 445 } 446 447 static void 448 ena_init_io_rings(struct ena_adapter *adapter) 449 { 450 struct ena_com_dev *ena_dev; 451 struct ena_ring *txr, *rxr; 452 struct ena_que *que; 453 int i; 454 455 ena_dev = adapter->ena_dev; 456 457 for (i = 0; i < adapter->num_queues; i++) { 458 txr = &adapter->tx_ring[i]; 459 rxr = &adapter->rx_ring[i]; 460 461 /* TX/RX common ring state */ 462 ena_init_io_rings_common(adapter, txr, i); 463 ena_init_io_rings_common(adapter, rxr, i); 464 465 /* TX specific ring state */ 466 txr->ring_size = adapter->tx_ring_size; 467 txr->tx_max_header_size = ena_dev->tx_max_header_size; 468 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 469 txr->smoothed_interval = 470 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 471 472 /* Allocate a buf ring */ 473 txr->br = buf_ring_alloc(ena_buf_ring_size, M_DEVBUF, 474 M_WAITOK, &txr->ring_mtx); 475 476 /* Alloc TX statistics. */ 477 ena_alloc_counters_tx(&txr->tx_stats, i); 478 479 /* RX specific ring state */ 480 rxr->ring_size = adapter->rx_ring_size; 481 rxr->smoothed_interval = 482 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 483 484 /* Alloc RX statistics. */ 485 ena_alloc_counters_rx(&rxr->rx_stats, i); 486 487 /* Initialize locks */ 488 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 489 device_xname(adapter->pdev), i); 490 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 491 device_xname(adapter->pdev), i); 492 493 mutex_init(&txr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 494 mutex_init(&rxr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 495 496 que = &adapter->que[i]; 497 que->adapter = adapter; 498 que->id = i; 499 que->tx_ring = txr; 500 que->rx_ring = rxr; 501 502 txr->que = que; 503 rxr->que = que; 504 505 rxr->empty_rx_queue = 0; 506 } 507 } 508 509 static void 510 ena_free_io_ring_resources(struct ena_adapter *adapter, unsigned int qid) 511 { 512 struct ena_ring *txr = &adapter->tx_ring[qid]; 513 struct ena_ring *rxr = &adapter->rx_ring[qid]; 514 515 ena_free_counters((struct evcnt *)&txr->tx_stats, 516 sizeof(txr->tx_stats)); 517 ena_free_counters((struct evcnt *)&rxr->rx_stats, 518 sizeof(rxr->rx_stats)); 519 520 ENA_RING_MTX_LOCK(txr); 521 drbr_free(txr->br, M_DEVBUF); 522 ENA_RING_MTX_UNLOCK(txr); 523 524 mutex_destroy(&txr->ring_mtx); 525 mutex_destroy(&rxr->ring_mtx); 526 } 527 528 static void 529 ena_free_all_io_rings_resources(struct ena_adapter *adapter) 530 { 531 int i; 532 533 for (i = 0; i < adapter->num_queues; i++) 534 ena_free_io_ring_resources(adapter, i); 535 536 } 537 538 #if 0 539 static int 540 ena_setup_tx_dma_tag(struct ena_adapter *adapter) 541 { 542 int ret; 543 544 /* Create DMA tag for Tx buffers */ 545 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), 546 1, 0, /* alignment, bounds */ 547 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 548 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 549 NULL, NULL, /* filter, filterarg */ 550 ENA_TSO_MAXSIZE, /* maxsize */ 551 adapter->max_tx_sgl_size - 1, /* nsegments */ 552 ENA_TSO_MAXSIZE, /* maxsegsize */ 553 0, /* flags */ 554 NULL, /* lockfunc */ 555 NULL, /* lockfuncarg */ 556 &adapter->tx_buf_tag); 557 558 return (ret); 559 } 560 #endif 561 562 #if 0 563 static int 564 ena_setup_rx_dma_tag(struct ena_adapter *adapter) 565 { 566 int ret; 567 568 /* Create DMA tag for Rx buffers*/ 569 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */ 570 1, 0, /* alignment, bounds */ 571 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 572 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 573 NULL, NULL, /* filter, filterarg */ 574 MJUM16BYTES, /* maxsize */ 575 adapter->max_rx_sgl_size, /* nsegments */ 576 MJUM16BYTES, /* maxsegsize */ 577 0, /* flags */ 578 NULL, /* lockfunc */ 579 NULL, /* lockarg */ 580 &adapter->rx_buf_tag); 581 582 return (ret); 583 } 584 #endif 585 586 /** 587 * ena_setup_tx_resources - allocate Tx resources (Descriptors) 588 * @adapter: network interface device structure 589 * @qid: queue index 590 * 591 * Returns 0 on success, otherwise on failure. 592 **/ 593 static int 594 ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 595 { 596 struct ena_que *que = &adapter->que[qid]; 597 struct ena_ring *tx_ring = que->tx_ring; 598 int size, i, err; 599 #ifdef RSS 600 cpuset_t cpu_mask; 601 #endif 602 603 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 604 605 tx_ring->tx_buffer_info = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 606 if (unlikely(tx_ring->tx_buffer_info == NULL)) 607 return (ENOMEM); 608 609 size = sizeof(uint16_t) * tx_ring->ring_size; 610 tx_ring->free_tx_ids = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 611 if (unlikely(tx_ring->free_tx_ids == NULL)) 612 goto err_buf_info_free; 613 614 /* Req id stack for TX OOO completions */ 615 for (i = 0; i < tx_ring->ring_size; i++) 616 tx_ring->free_tx_ids[i] = i; 617 618 /* Reset TX statistics. */ 619 ena_reset_counters((struct evcnt *)&tx_ring->tx_stats, 620 sizeof(tx_ring->tx_stats)); 621 622 tx_ring->next_to_use = 0; 623 tx_ring->next_to_clean = 0; 624 625 /* Make sure that drbr is empty */ 626 ENA_RING_MTX_LOCK(tx_ring); 627 drbr_flush(adapter->ifp, tx_ring->br); 628 ENA_RING_MTX_UNLOCK(tx_ring); 629 630 /* ... and create the buffer DMA maps */ 631 for (i = 0; i < tx_ring->ring_size; i++) { 632 err = bus_dmamap_create(adapter->sc_dmat, 633 ENA_TSO_MAXSIZE, adapter->max_tx_sgl_size - 1, 634 ENA_TSO_MAXSIZE, 0, 0, 635 &tx_ring->tx_buffer_info[i].map); 636 if (unlikely(err != 0)) { 637 ena_trace(ENA_ALERT, 638 "Unable to create Tx DMA map for buffer %d\n", i); 639 goto err_buf_info_unmap; 640 } 641 } 642 643 /* Allocate workqueues */ 644 int rc = workqueue_create(&tx_ring->enqueue_tq, "ena_tx_enque", 645 ena_deferred_mq_start, tx_ring, 0, IPL_NET, 0); 646 if (unlikely(rc == 0)) { 647 ena_trace(ENA_ALERT, 648 "Unable to create workqueue for enqueue task\n"); 649 i = tx_ring->ring_size; 650 goto err_buf_info_unmap; 651 } 652 653 #if 0 654 /* RSS set cpu for thread */ 655 #ifdef RSS 656 CPU_SETOF(que->cpu, &cpu_mask); 657 taskqueue_start_threads_cpuset(&tx_ring->enqueue_tq, 1, IPL_NET, 658 &cpu_mask, "%s tx_ring enq (bucket %d)", 659 device_xname(adapter->pdev), que->cpu); 660 #else /* RSS */ 661 taskqueue_start_threads(&tx_ring->enqueue_tq, 1, IPL_NET, 662 "%s txeq %d", device_xname(adapter->pdev), que->cpu); 663 #endif /* RSS */ 664 #endif 665 666 return (0); 667 668 err_buf_info_unmap: 669 while (i--) { 670 bus_dmamap_destroy(adapter->sc_dmat, 671 tx_ring->tx_buffer_info[i].map); 672 } 673 free(tx_ring->free_tx_ids, M_DEVBUF); 674 tx_ring->free_tx_ids = NULL; 675 err_buf_info_free: 676 free(tx_ring->tx_buffer_info, M_DEVBUF); 677 tx_ring->tx_buffer_info = NULL; 678 679 return (ENOMEM); 680 } 681 682 /** 683 * ena_free_tx_resources - Free Tx Resources per Queue 684 * @adapter: network interface device structure 685 * @qid: queue index 686 * 687 * Free all transmit software resources 688 **/ 689 static void 690 ena_free_tx_resources(struct ena_adapter *adapter, int qid) 691 { 692 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 693 694 workqueue_wait(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 695 workqueue_destroy(tx_ring->enqueue_tq); 696 tx_ring->enqueue_tq = NULL; 697 698 ENA_RING_MTX_LOCK(tx_ring); 699 /* Flush buffer ring, */ 700 drbr_flush(adapter->ifp, tx_ring->br); 701 702 /* Free buffer DMA maps, */ 703 for (int i = 0; i < tx_ring->ring_size; i++) { 704 m_freem(tx_ring->tx_buffer_info[i].mbuf); 705 tx_ring->tx_buffer_info[i].mbuf = NULL; 706 bus_dmamap_unload(adapter->sc_dmat, 707 tx_ring->tx_buffer_info[i].map); 708 bus_dmamap_destroy(adapter->sc_dmat, 709 tx_ring->tx_buffer_info[i].map); 710 } 711 ENA_RING_MTX_UNLOCK(tx_ring); 712 713 /* And free allocated memory. */ 714 free(tx_ring->tx_buffer_info, M_DEVBUF); 715 tx_ring->tx_buffer_info = NULL; 716 717 free(tx_ring->free_tx_ids, M_DEVBUF); 718 tx_ring->free_tx_ids = NULL; 719 } 720 721 /** 722 * ena_setup_all_tx_resources - allocate all queues Tx resources 723 * @adapter: network interface device structure 724 * 725 * Returns 0 on success, otherwise on failure. 726 **/ 727 static int 728 ena_setup_all_tx_resources(struct ena_adapter *adapter) 729 { 730 int i, rc; 731 732 for (i = 0; i < adapter->num_queues; i++) { 733 rc = ena_setup_tx_resources(adapter, i); 734 if (rc != 0) { 735 device_printf(adapter->pdev, 736 "Allocation for Tx Queue %u failed\n", i); 737 goto err_setup_tx; 738 } 739 } 740 741 return (0); 742 743 err_setup_tx: 744 /* Rewind the index freeing the rings as we go */ 745 while (i--) 746 ena_free_tx_resources(adapter, i); 747 return (rc); 748 } 749 750 /** 751 * ena_free_all_tx_resources - Free Tx Resources for All Queues 752 * @adapter: network interface device structure 753 * 754 * Free all transmit software resources 755 **/ 756 static void 757 ena_free_all_tx_resources(struct ena_adapter *adapter) 758 { 759 int i; 760 761 for (i = 0; i < adapter->num_queues; i++) 762 ena_free_tx_resources(adapter, i); 763 } 764 765 static inline int 766 validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 767 { 768 if (likely(req_id < rx_ring->ring_size)) 769 return (0); 770 771 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 772 req_id); 773 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 774 775 /* Trigger device reset */ 776 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 777 rx_ring->adapter->trigger_reset = true; 778 779 return (EFAULT); 780 } 781 782 /** 783 * ena_setup_rx_resources - allocate Rx resources (Descriptors) 784 * @adapter: network interface device structure 785 * @qid: queue index 786 * 787 * Returns 0 on success, otherwise on failure. 788 **/ 789 static int 790 ena_setup_rx_resources(struct ena_adapter *adapter, unsigned int qid) 791 { 792 struct ena_que *que = &adapter->que[qid]; 793 struct ena_ring *rx_ring = que->rx_ring; 794 int size, err, i; 795 #ifdef RSS 796 cpuset_t cpu_mask; 797 #endif 798 799 size = sizeof(struct ena_rx_buffer) * rx_ring->ring_size; 800 801 /* 802 * Alloc extra element so in rx path 803 * we can always prefetch rx_info + 1 804 */ 805 size += sizeof(struct ena_rx_buffer); 806 807 rx_ring->rx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 808 809 size = sizeof(uint16_t) * rx_ring->ring_size; 810 rx_ring->free_rx_ids = malloc(size, M_DEVBUF, M_WAITOK); 811 812 for (i = 0; i < rx_ring->ring_size; i++) 813 rx_ring->free_rx_ids[i] = i; 814 815 /* Reset RX statistics. */ 816 ena_reset_counters((struct evcnt *)&rx_ring->rx_stats, 817 sizeof(rx_ring->rx_stats)); 818 819 rx_ring->next_to_clean = 0; 820 rx_ring->next_to_use = 0; 821 822 /* ... and create the buffer DMA maps */ 823 for (i = 0; i < rx_ring->ring_size; i++) { 824 err = bus_dmamap_create(adapter->sc_dmat, 825 MJUM16BYTES, adapter->max_rx_sgl_size, MJUM16BYTES, 826 0, 0, 827 &(rx_ring->rx_buffer_info[i].map)); 828 if (err != 0) { 829 ena_trace(ENA_ALERT, 830 "Unable to create Rx DMA map for buffer %d\n", i); 831 goto err_buf_info_unmap; 832 } 833 } 834 835 #ifdef LRO 836 /* Create LRO for the ring */ 837 if ((adapter->ifp->if_capenable & IFCAP_LRO) != 0) { 838 int err = tcp_lro_init(&rx_ring->lro); 839 if (err != 0) { 840 device_printf(adapter->pdev, 841 "LRO[%d] Initialization failed!\n", qid); 842 } else { 843 ena_trace(ENA_INFO, 844 "RX Soft LRO[%d] Initialized\n", qid); 845 rx_ring->lro.ifp = adapter->ifp; 846 } 847 } 848 #endif 849 850 /* Allocate workqueues */ 851 int rc = workqueue_create(&rx_ring->cmpl_tq, "ena RX completion", 852 ena_deferred_rx_cleanup, rx_ring, 0, IPL_NET, 0); 853 if (unlikely(rc != 0)) { 854 ena_trace(ENA_ALERT, 855 "Unable to create workqueue for RX completion task\n"); 856 goto err_buf_info_unmap; 857 } 858 859 #if 0 860 /* RSS set cpu for thread */ 861 #ifdef RSS 862 CPU_SETOF(que->cpu, &cpu_mask); 863 taskqueue_start_threads_cpuset(&rx_ring->cmpl_tq, 1, IPL_NET, &cpu_mask, 864 "%s rx_ring cmpl (bucket %d)", 865 device_xname(adapter->pdev), que->cpu); 866 #else 867 taskqueue_start_threads(&rx_ring->cmpl_tq, 1, IPL_NET, 868 "%s rx_ring cmpl %d", device_xname(adapter->pdev), que->cpu); 869 #endif 870 #endif 871 872 return (0); 873 874 err_buf_info_unmap: 875 while (i--) { 876 bus_dmamap_destroy(adapter->sc_dmat, 877 rx_ring->rx_buffer_info[i].map); 878 } 879 880 free(rx_ring->free_rx_ids, M_DEVBUF); 881 rx_ring->free_rx_ids = NULL; 882 free(rx_ring->rx_buffer_info, M_DEVBUF); 883 rx_ring->rx_buffer_info = NULL; 884 return (ENOMEM); 885 } 886 887 /** 888 * ena_free_rx_resources - Free Rx Resources 889 * @adapter: network interface device structure 890 * @qid: queue index 891 * 892 * Free all receive software resources 893 **/ 894 static void 895 ena_free_rx_resources(struct ena_adapter *adapter, unsigned int qid) 896 { 897 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 898 899 workqueue_wait(rx_ring->cmpl_tq, &rx_ring->cmpl_task); 900 workqueue_destroy(rx_ring->cmpl_tq); 901 rx_ring->cmpl_tq = NULL; 902 903 /* Free buffer DMA maps, */ 904 for (int i = 0; i < rx_ring->ring_size; i++) { 905 m_freem(rx_ring->rx_buffer_info[i].mbuf); 906 rx_ring->rx_buffer_info[i].mbuf = NULL; 907 bus_dmamap_unload(adapter->sc_dmat, 908 rx_ring->rx_buffer_info[i].map); 909 bus_dmamap_destroy(adapter->sc_dmat, 910 rx_ring->rx_buffer_info[i].map); 911 } 912 913 #ifdef LRO 914 /* free LRO resources, */ 915 tcp_lro_free(&rx_ring->lro); 916 #endif 917 918 /* free allocated memory */ 919 free(rx_ring->rx_buffer_info, M_DEVBUF); 920 rx_ring->rx_buffer_info = NULL; 921 922 free(rx_ring->free_rx_ids, M_DEVBUF); 923 rx_ring->free_rx_ids = NULL; 924 } 925 926 /** 927 * ena_setup_all_rx_resources - allocate all queues Rx resources 928 * @adapter: network interface device structure 929 * 930 * Returns 0 on success, otherwise on failure. 931 **/ 932 static int 933 ena_setup_all_rx_resources(struct ena_adapter *adapter) 934 { 935 int i, rc = 0; 936 937 for (i = 0; i < adapter->num_queues; i++) { 938 rc = ena_setup_rx_resources(adapter, i); 939 if (rc != 0) { 940 device_printf(adapter->pdev, 941 "Allocation for Rx Queue %u failed\n", i); 942 goto err_setup_rx; 943 } 944 } 945 return (0); 946 947 err_setup_rx: 948 /* rewind the index freeing the rings as we go */ 949 while (i--) 950 ena_free_rx_resources(adapter, i); 951 return (rc); 952 } 953 954 /** 955 * ena_free_all_rx_resources - Free Rx resources for all queues 956 * @adapter: network interface device structure 957 * 958 * Free all receive software resources 959 **/ 960 static void 961 ena_free_all_rx_resources(struct ena_adapter *adapter) 962 { 963 int i; 964 965 for (i = 0; i < adapter->num_queues; i++) 966 ena_free_rx_resources(adapter, i); 967 } 968 969 static inline int 970 ena_alloc_rx_mbuf(struct ena_adapter *adapter, 971 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 972 { 973 struct ena_com_buf *ena_buf; 974 int error; 975 int mlen; 976 977 /* if previous allocated frag is not used */ 978 if (unlikely(rx_info->mbuf != NULL)) 979 return (0); 980 981 /* Get mbuf using UMA allocator */ 982 rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); 983 984 if (unlikely(rx_info->mbuf == NULL)) { 985 counter_u64_add(rx_ring->rx_stats.mjum_alloc_fail, 1); 986 rx_info->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 987 if (unlikely(rx_info->mbuf == NULL)) { 988 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 989 return (ENOMEM); 990 } 991 mlen = MCLBYTES; 992 } else { 993 mlen = MJUM16BYTES; 994 } 995 /* Set mbuf length*/ 996 rx_info->mbuf->m_pkthdr.len = rx_info->mbuf->m_len = mlen; 997 998 /* Map packets for DMA */ 999 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1000 "Using tag %p for buffers' DMA mapping, mbuf %p len: %d", 1001 adapter->sc_dmat,rx_info->mbuf, rx_info->mbuf->m_len); 1002 error = bus_dmamap_load_mbuf(adapter->sc_dmat, rx_info->map, 1003 rx_info->mbuf, BUS_DMA_NOWAIT); 1004 if (unlikely((error != 0) || (rx_info->map->dm_nsegs != 1))) { 1005 ena_trace(ENA_WARNING, "failed to map mbuf, error: %d, " 1006 "nsegs: %d\n", error, rx_info->map->dm_nsegs); 1007 counter_u64_add(rx_ring->rx_stats.dma_mapping_err, 1); 1008 goto exit; 1009 1010 } 1011 1012 bus_dmamap_sync(adapter->sc_dmat, rx_info->map, 0, 1013 rx_info->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1014 1015 ena_buf = &rx_info->ena_buf; 1016 ena_buf->paddr = rx_info->map->dm_segs[0].ds_addr; 1017 ena_buf->len = mlen; 1018 1019 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1020 "ALLOC RX BUF: mbuf %p, rx_info %p, len %d, paddr %#jx\n", 1021 rx_info->mbuf, rx_info,ena_buf->len, (uintmax_t)ena_buf->paddr); 1022 1023 return (0); 1024 1025 exit: 1026 m_freem(rx_info->mbuf); 1027 rx_info->mbuf = NULL; 1028 return (EFAULT); 1029 } 1030 1031 static void 1032 ena_free_rx_mbuf(struct ena_adapter *adapter, struct ena_ring *rx_ring, 1033 struct ena_rx_buffer *rx_info) 1034 { 1035 1036 if (rx_info->mbuf == NULL) { 1037 ena_trace(ENA_WARNING, "Trying to free unallocated buffer\n"); 1038 return; 1039 } 1040 1041 bus_dmamap_unload(adapter->sc_dmat, rx_info->map); 1042 m_freem(rx_info->mbuf); 1043 rx_info->mbuf = NULL; 1044 } 1045 1046 /** 1047 * ena_refill_rx_bufs - Refills ring with descriptors 1048 * @rx_ring: the ring which we want to feed with free descriptors 1049 * @num: number of descriptors to refill 1050 * Refills the ring with newly allocated DMA-mapped mbufs for receiving 1051 **/ 1052 static int 1053 ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num) 1054 { 1055 struct ena_adapter *adapter = rx_ring->adapter; 1056 uint16_t next_to_use, req_id; 1057 uint32_t i; 1058 int rc; 1059 1060 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, "refill qid: %d", 1061 rx_ring->qid); 1062 1063 next_to_use = rx_ring->next_to_use; 1064 1065 for (i = 0; i < num; i++) { 1066 struct ena_rx_buffer *rx_info; 1067 1068 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, 1069 "RX buffer - next to use: %d", next_to_use); 1070 1071 req_id = rx_ring->free_rx_ids[next_to_use]; 1072 rc = validate_rx_req_id(rx_ring, req_id); 1073 if (unlikely(rc != 0)) 1074 break; 1075 1076 rx_info = &rx_ring->rx_buffer_info[req_id]; 1077 1078 rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info); 1079 if (unlikely(rc != 0)) { 1080 ena_trace(ENA_WARNING, 1081 "failed to alloc buffer for rx queue %d\n", 1082 rx_ring->qid); 1083 break; 1084 } 1085 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 1086 &rx_info->ena_buf, req_id); 1087 if (unlikely(rc != 0)) { 1088 ena_trace(ENA_WARNING, 1089 "failed to add buffer for rx queue %d\n", 1090 rx_ring->qid); 1091 break; 1092 } 1093 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 1094 rx_ring->ring_size); 1095 } 1096 1097 if (unlikely(i < num)) { 1098 counter_u64_add(rx_ring->rx_stats.refil_partial, 1); 1099 ena_trace(ENA_WARNING, 1100 "refilled rx qid %d with only %d mbufs (from %d)\n", 1101 rx_ring->qid, i, num); 1102 } 1103 1104 if (likely(i != 0)) { 1105 wmb(); 1106 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 1107 } 1108 rx_ring->next_to_use = next_to_use; 1109 return (i); 1110 } 1111 1112 static void 1113 ena_free_rx_bufs(struct ena_adapter *adapter, unsigned int qid) 1114 { 1115 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 1116 unsigned int i; 1117 1118 for (i = 0; i < rx_ring->ring_size; i++) { 1119 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 1120 1121 if (rx_info->mbuf != NULL) 1122 ena_free_rx_mbuf(adapter, rx_ring, rx_info); 1123 } 1124 } 1125 1126 /** 1127 * ena_refill_all_rx_bufs - allocate all queues Rx buffers 1128 * @adapter: network interface device structure 1129 * 1130 */ 1131 static void 1132 ena_refill_all_rx_bufs(struct ena_adapter *adapter) 1133 { 1134 struct ena_ring *rx_ring; 1135 int i, rc, bufs_num; 1136 1137 for (i = 0; i < adapter->num_queues; i++) { 1138 rx_ring = &adapter->rx_ring[i]; 1139 bufs_num = rx_ring->ring_size - 1; 1140 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 1141 1142 if (unlikely(rc != bufs_num)) 1143 ena_trace(ENA_WARNING, "refilling Queue %d failed. " 1144 "Allocated %d buffers from: %d\n", i, rc, bufs_num); 1145 } 1146 } 1147 1148 static void 1149 ena_free_all_rx_bufs(struct ena_adapter *adapter) 1150 { 1151 int i; 1152 1153 for (i = 0; i < adapter->num_queues; i++) 1154 ena_free_rx_bufs(adapter, i); 1155 } 1156 1157 /** 1158 * ena_free_tx_bufs - Free Tx Buffers per Queue 1159 * @adapter: network interface device structure 1160 * @qid: queue index 1161 **/ 1162 static void 1163 ena_free_tx_bufs(struct ena_adapter *adapter, unsigned int qid) 1164 { 1165 bool print_once = true; 1166 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 1167 1168 ENA_RING_MTX_LOCK(tx_ring); 1169 for (int i = 0; i < tx_ring->ring_size; i++) { 1170 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 1171 1172 if (tx_info->mbuf == NULL) 1173 continue; 1174 1175 if (print_once) { 1176 device_printf(adapter->pdev, 1177 "free uncompleted tx mbuf qid %d idx 0x%x", 1178 qid, i); 1179 print_once = false; 1180 } else { 1181 ena_trace(ENA_DBG, 1182 "free uncompleted tx mbuf qid %d idx 0x%x", 1183 qid, i); 1184 } 1185 1186 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1187 m_free(tx_info->mbuf); 1188 tx_info->mbuf = NULL; 1189 } 1190 ENA_RING_MTX_UNLOCK(tx_ring); 1191 } 1192 1193 static void 1194 ena_free_all_tx_bufs(struct ena_adapter *adapter) 1195 { 1196 1197 for (int i = 0; i < adapter->num_queues; i++) 1198 ena_free_tx_bufs(adapter, i); 1199 } 1200 1201 static void 1202 ena_destroy_all_tx_queues(struct ena_adapter *adapter) 1203 { 1204 uint16_t ena_qid; 1205 int i; 1206 1207 for (i = 0; i < adapter->num_queues; i++) { 1208 ena_qid = ENA_IO_TXQ_IDX(i); 1209 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1210 } 1211 } 1212 1213 static void 1214 ena_destroy_all_rx_queues(struct ena_adapter *adapter) 1215 { 1216 uint16_t ena_qid; 1217 int i; 1218 1219 for (i = 0; i < adapter->num_queues; i++) { 1220 ena_qid = ENA_IO_RXQ_IDX(i); 1221 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1222 } 1223 } 1224 1225 static void 1226 ena_destroy_all_io_queues(struct ena_adapter *adapter) 1227 { 1228 ena_destroy_all_tx_queues(adapter); 1229 ena_destroy_all_rx_queues(adapter); 1230 } 1231 1232 static inline int 1233 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 1234 { 1235 struct ena_adapter *adapter = tx_ring->adapter; 1236 struct ena_tx_buffer *tx_info = NULL; 1237 1238 if (likely(req_id < tx_ring->ring_size)) { 1239 tx_info = &tx_ring->tx_buffer_info[req_id]; 1240 if (tx_info->mbuf != NULL) 1241 return (0); 1242 } 1243 1244 if (tx_info->mbuf == NULL) 1245 device_printf(adapter->pdev, 1246 "tx_info doesn't have valid mbuf\n"); 1247 else 1248 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 1249 1250 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 1251 1252 return (EFAULT); 1253 } 1254 1255 static int 1256 ena_create_io_queues(struct ena_adapter *adapter) 1257 { 1258 struct ena_com_dev *ena_dev = adapter->ena_dev; 1259 struct ena_com_create_io_ctx ctx; 1260 struct ena_ring *ring; 1261 uint16_t ena_qid; 1262 uint32_t msix_vector; 1263 int rc, i; 1264 1265 /* Create TX queues */ 1266 for (i = 0; i < adapter->num_queues; i++) { 1267 msix_vector = ENA_IO_IRQ_IDX(i); 1268 ena_qid = ENA_IO_TXQ_IDX(i); 1269 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1270 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1271 ctx.queue_size = adapter->tx_ring_size; 1272 ctx.msix_vector = msix_vector; 1273 ctx.qid = ena_qid; 1274 rc = ena_com_create_io_queue(ena_dev, &ctx); 1275 if (rc != 0) { 1276 device_printf(adapter->pdev, 1277 "Failed to create io TX queue #%d rc: %d\n", i, rc); 1278 goto err_tx; 1279 } 1280 ring = &adapter->tx_ring[i]; 1281 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1282 &ring->ena_com_io_sq, 1283 &ring->ena_com_io_cq); 1284 if (rc != 0) { 1285 device_printf(adapter->pdev, 1286 "Failed to get TX queue handlers. TX queue num" 1287 " %d rc: %d\n", i, rc); 1288 ena_com_destroy_io_queue(ena_dev, ena_qid); 1289 goto err_tx; 1290 } 1291 } 1292 1293 /* Create RX queues */ 1294 for (i = 0; i < adapter->num_queues; i++) { 1295 msix_vector = ENA_IO_IRQ_IDX(i); 1296 ena_qid = ENA_IO_RXQ_IDX(i); 1297 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1298 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1299 ctx.queue_size = adapter->rx_ring_size; 1300 ctx.msix_vector = msix_vector; 1301 ctx.qid = ena_qid; 1302 rc = ena_com_create_io_queue(ena_dev, &ctx); 1303 if (unlikely(rc != 0)) { 1304 device_printf(adapter->pdev, 1305 "Failed to create io RX queue[%d] rc: %d\n", i, rc); 1306 goto err_rx; 1307 } 1308 1309 ring = &adapter->rx_ring[i]; 1310 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1311 &ring->ena_com_io_sq, 1312 &ring->ena_com_io_cq); 1313 if (unlikely(rc != 0)) { 1314 device_printf(adapter->pdev, 1315 "Failed to get RX queue handlers. RX queue num" 1316 " %d rc: %d\n", i, rc); 1317 ena_com_destroy_io_queue(ena_dev, ena_qid); 1318 goto err_rx; 1319 } 1320 } 1321 1322 return (0); 1323 1324 err_rx: 1325 while (i--) 1326 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1327 i = adapter->num_queues; 1328 err_tx: 1329 while (i--) 1330 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1331 1332 return (ENXIO); 1333 } 1334 1335 /** 1336 * ena_tx_cleanup - clear sent packets and corresponding descriptors 1337 * @tx_ring: ring for which we want to clean packets 1338 * 1339 * Once packets are sent, we ask the device in a loop for no longer used 1340 * descriptors. We find the related mbuf chain in a map (index in an array) 1341 * and free it, then update ring state. 1342 * This is performed in "endless" loop, updating ring pointers every 1343 * TX_COMMIT. The first check of free descriptor is performed before the actual 1344 * loop, then repeated at the loop end. 1345 **/ 1346 static int 1347 ena_tx_cleanup(struct ena_ring *tx_ring) 1348 { 1349 struct ena_adapter *adapter; 1350 struct ena_com_io_cq* io_cq; 1351 uint16_t next_to_clean; 1352 uint16_t req_id; 1353 uint16_t ena_qid; 1354 unsigned int total_done = 0; 1355 int rc; 1356 int commit = TX_COMMIT; 1357 int budget = TX_BUDGET; 1358 int work_done; 1359 1360 adapter = tx_ring->que->adapter; 1361 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1362 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1363 next_to_clean = tx_ring->next_to_clean; 1364 1365 do { 1366 struct ena_tx_buffer *tx_info; 1367 struct mbuf *mbuf; 1368 1369 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 1370 if (unlikely(rc != 0)) 1371 break; 1372 1373 rc = validate_tx_req_id(tx_ring, req_id); 1374 if (unlikely(rc != 0)) 1375 break; 1376 1377 tx_info = &tx_ring->tx_buffer_info[req_id]; 1378 1379 mbuf = tx_info->mbuf; 1380 1381 tx_info->mbuf = NULL; 1382 bintime_clear(&tx_info->timestamp); 1383 1384 if (likely(tx_info->num_of_bufs != 0)) { 1385 /* Map is no longer required */ 1386 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1387 } 1388 1389 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed", 1390 tx_ring->qid, mbuf); 1391 1392 m_freem(mbuf); 1393 1394 total_done += tx_info->tx_descs; 1395 1396 tx_ring->free_tx_ids[next_to_clean] = req_id; 1397 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 1398 tx_ring->ring_size); 1399 1400 if (unlikely(--commit == 0)) { 1401 commit = TX_COMMIT; 1402 /* update ring state every TX_COMMIT descriptor */ 1403 tx_ring->next_to_clean = next_to_clean; 1404 ena_com_comp_ack( 1405 &adapter->ena_dev->io_sq_queues[ena_qid], 1406 total_done); 1407 ena_com_update_dev_comp_head(io_cq); 1408 total_done = 0; 1409 } 1410 } while (likely(--budget)); 1411 1412 work_done = TX_BUDGET - budget; 1413 1414 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d", 1415 tx_ring->qid, work_done); 1416 1417 /* If there is still something to commit update ring state */ 1418 if (likely(commit != TX_COMMIT)) { 1419 tx_ring->next_to_clean = next_to_clean; 1420 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 1421 total_done); 1422 ena_com_update_dev_comp_head(io_cq); 1423 } 1424 1425 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, NULL); 1426 1427 return (work_done); 1428 } 1429 1430 #if 0 1431 static void 1432 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1433 struct mbuf *mbuf) 1434 { 1435 struct ena_adapter *adapter = rx_ring->adapter; 1436 1437 if (likely(adapter->rss_support)) { 1438 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 1439 1440 if (ena_rx_ctx->frag && 1441 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 1442 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1443 return; 1444 } 1445 1446 switch (ena_rx_ctx->l3_proto) { 1447 case ENA_ETH_IO_L3_PROTO_IPV4: 1448 switch (ena_rx_ctx->l4_proto) { 1449 case ENA_ETH_IO_L4_PROTO_TCP: 1450 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 1451 break; 1452 case ENA_ETH_IO_L4_PROTO_UDP: 1453 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 1454 break; 1455 default: 1456 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 1457 } 1458 break; 1459 case ENA_ETH_IO_L3_PROTO_IPV6: 1460 switch (ena_rx_ctx->l4_proto) { 1461 case ENA_ETH_IO_L4_PROTO_TCP: 1462 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 1463 break; 1464 case ENA_ETH_IO_L4_PROTO_UDP: 1465 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 1466 break; 1467 default: 1468 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 1469 } 1470 break; 1471 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 1472 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1473 break; 1474 default: 1475 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1476 } 1477 } else { 1478 mbuf->m_pkthdr.flowid = rx_ring->qid; 1479 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1480 } 1481 } 1482 #endif 1483 1484 /** 1485 * ena_rx_mbuf - assemble mbuf from descriptors 1486 * @rx_ring: ring for which we want to clean packets 1487 * @ena_bufs: buffer info 1488 * @ena_rx_ctx: metadata for this packet(s) 1489 * @next_to_clean: ring pointer, will be updated only upon success 1490 * 1491 **/ 1492 static struct mbuf* 1493 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 1494 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 1495 { 1496 struct mbuf *mbuf; 1497 struct ena_rx_buffer *rx_info; 1498 struct ena_adapter *adapter; 1499 unsigned int descs = ena_rx_ctx->descs; 1500 uint16_t ntc, len, req_id, buf = 0; 1501 1502 ntc = *next_to_clean; 1503 adapter = rx_ring->adapter; 1504 rx_info = &rx_ring->rx_buffer_info[ntc]; 1505 1506 if (unlikely(rx_info->mbuf == NULL)) { 1507 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1508 return (NULL); 1509 } 1510 1511 len = ena_bufs[buf].len; 1512 req_id = ena_bufs[buf].req_id; 1513 rx_info = &rx_ring->rx_buffer_info[req_id]; 1514 1515 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx", 1516 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 1517 1518 mbuf = rx_info->mbuf; 1519 KASSERT(mbuf->m_flags & M_PKTHDR); 1520 mbuf->m_pkthdr.len = len; 1521 mbuf->m_len = len; 1522 m_set_rcvif(mbuf, rx_ring->que->adapter->ifp); 1523 1524 /* Fill mbuf with hash key and it's interpretation for optimization */ 1525 #if 0 1526 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 1527 #endif 1528 1529 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf 0x%p, flags=0x%x, len: %d", 1530 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 1531 1532 /* DMA address is not needed anymore, unmap it */ 1533 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1534 1535 rx_info->mbuf = NULL; 1536 rx_ring->free_rx_ids[ntc] = req_id; 1537 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1538 1539 /* 1540 * While we have more than 1 descriptors for one rcvd packet, append 1541 * other mbufs to the main one 1542 */ 1543 while (--descs) { 1544 ++buf; 1545 len = ena_bufs[buf].len; 1546 req_id = ena_bufs[buf].req_id; 1547 rx_info = &rx_ring->rx_buffer_info[req_id]; 1548 1549 if (unlikely(rx_info->mbuf == NULL)) { 1550 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1551 /* 1552 * If one of the required mbufs was not allocated yet, 1553 * we can break there. 1554 * All earlier used descriptors will be reallocated 1555 * later and not used mbufs can be reused. 1556 * The next_to_clean pointer will not be updated in case 1557 * of an error, so caller should advance it manually 1558 * in error handling routine to keep it up to date 1559 * with hw ring. 1560 */ 1561 m_freem(mbuf); 1562 return (NULL); 1563 } 1564 1565 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 1566 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1567 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p", 1568 mbuf); 1569 } 1570 1571 ena_trace(ENA_DBG | ENA_RXPTH, 1572 "rx mbuf updated. len %d", mbuf->m_pkthdr.len); 1573 1574 /* Free already appended mbuf, it won't be useful anymore */ 1575 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1576 m_freem(rx_info->mbuf); 1577 rx_info->mbuf = NULL; 1578 1579 rx_ring->free_rx_ids[ntc] = req_id; 1580 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1581 } 1582 1583 *next_to_clean = ntc; 1584 1585 return (mbuf); 1586 } 1587 1588 /** 1589 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 1590 **/ 1591 static inline void 1592 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1593 struct mbuf *mbuf) 1594 { 1595 1596 /* if IP and error */ 1597 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) && 1598 ena_rx_ctx->l3_csum_err)) { 1599 /* ipv4 checksum error */ 1600 mbuf->m_pkthdr.csum_flags = 0; 1601 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1602 ena_trace(ENA_DBG, "RX IPv4 header checksum error"); 1603 return; 1604 } 1605 1606 /* if TCP/UDP */ 1607 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1608 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1609 if (ena_rx_ctx->l4_csum_err) { 1610 /* TCP/UDP checksum error */ 1611 mbuf->m_pkthdr.csum_flags = M_CSUM_IPv4_BAD; 1612 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1613 ena_trace(ENA_DBG, "RX L4 checksum error"); 1614 } else { 1615 mbuf->m_pkthdr.csum_flags = M_CSUM_IPv4; 1616 } 1617 } 1618 } 1619 1620 static void 1621 ena_deferred_rx_cleanup(struct work *wk, void *arg) 1622 { 1623 struct ena_ring *rx_ring = arg; 1624 int budget = CLEAN_BUDGET; 1625 1626 ENA_RING_MTX_LOCK(rx_ring); 1627 /* 1628 * If deferred task was executed, perform cleanup of all awaiting 1629 * descs (or until given budget is depleted to avoid infinite loop). 1630 */ 1631 while (likely(budget--)) { 1632 if (ena_rx_cleanup(rx_ring) == 0) 1633 break; 1634 } 1635 ENA_RING_MTX_UNLOCK(rx_ring); 1636 } 1637 1638 /** 1639 * ena_rx_cleanup - handle rx irq 1640 * @arg: ring for which irq is being handled 1641 **/ 1642 static int 1643 ena_rx_cleanup(struct ena_ring *rx_ring) 1644 { 1645 struct ena_adapter *adapter; 1646 struct mbuf *mbuf; 1647 struct ena_com_rx_ctx ena_rx_ctx; 1648 struct ena_com_io_cq* io_cq; 1649 struct ena_com_io_sq* io_sq; 1650 struct ifnet *ifp; 1651 uint16_t ena_qid; 1652 uint16_t next_to_clean; 1653 uint32_t refill_required; 1654 uint32_t refill_threshold; 1655 #ifdef LRO 1656 uint32_t do_if_input = 0; 1657 #endif 1658 unsigned int qid; 1659 int rc, i; 1660 int budget = RX_BUDGET; 1661 1662 adapter = rx_ring->que->adapter; 1663 ifp = adapter->ifp; 1664 qid = rx_ring->que->id; 1665 ena_qid = ENA_IO_RXQ_IDX(qid); 1666 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1667 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1668 next_to_clean = rx_ring->next_to_clean; 1669 1670 ena_trace(ENA_DBG, "rx: qid %d", qid); 1671 1672 do { 1673 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1674 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 1675 ena_rx_ctx.descs = 0; 1676 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 1677 1678 if (unlikely(rc != 0)) 1679 goto error; 1680 1681 if (unlikely(ena_rx_ctx.descs == 0)) 1682 break; 1683 1684 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 1685 "descs #: %d l3 proto %d l4 proto %d hash: %x", 1686 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1687 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1688 1689 /* Receive mbuf from the ring */ 1690 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 1691 &ena_rx_ctx, &next_to_clean); 1692 1693 /* Exit if we failed to retrieve a buffer */ 1694 if (unlikely(mbuf == NULL)) { 1695 for (i = 0; i < ena_rx_ctx.descs; ++i) { 1696 rx_ring->free_rx_ids[next_to_clean] = 1697 rx_ring->ena_bufs[i].req_id; 1698 next_to_clean = 1699 ENA_RX_RING_IDX_NEXT(next_to_clean, 1700 rx_ring->ring_size); 1701 1702 } 1703 break; 1704 } 1705 1706 if (((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) || 1707 ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) || 1708 ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) || 1709 ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) || 1710 ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0)) { 1711 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 1712 } 1713 1714 counter_enter(); 1715 counter_u64_add_protected(rx_ring->rx_stats.bytes, 1716 mbuf->m_pkthdr.len); 1717 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 1718 mbuf->m_pkthdr.len); 1719 counter_exit(); 1720 #ifdef LRO 1721 /* 1722 * LRO is only for IP/TCP packets and TCP checksum of the packet 1723 * should be computed by hardware. 1724 */ 1725 do_if_input = 1; 1726 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 1727 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 1728 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 1729 /* 1730 * Send to the stack if: 1731 * - LRO not enabled, or 1732 * - no LRO resources, or 1733 * - lro enqueue fails 1734 */ 1735 if ((rx_ring->lro.lro_cnt != 0) && 1736 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 1737 do_if_input = 0; 1738 } 1739 if (do_if_input != 0) { 1740 ena_trace(ENA_DBG | ENA_RXPTH, 1741 "calling if_input() with mbuf %p", mbuf); 1742 (*ifp->if_input)(ifp, mbuf); 1743 } 1744 #endif 1745 1746 counter_enter(); 1747 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 1748 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 1749 counter_exit(); 1750 } while (--budget); 1751 1752 rx_ring->next_to_clean = next_to_clean; 1753 1754 refill_required = ena_com_free_desc(io_sq); 1755 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1756 1757 if (refill_required > refill_threshold) { 1758 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1759 ena_refill_rx_bufs(rx_ring, refill_required); 1760 } 1761 1762 #ifdef LRO 1763 tcp_lro_flush_all(&rx_ring->lro); 1764 #endif 1765 1766 return (RX_BUDGET - budget); 1767 1768 error: 1769 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 1770 return (RX_BUDGET - budget); 1771 } 1772 1773 /********************************************************************* 1774 * 1775 * MSIX & Interrupt Service routine 1776 * 1777 **********************************************************************/ 1778 1779 /** 1780 * ena_handle_msix - MSIX Interrupt Handler for admin/async queue 1781 * @arg: interrupt number 1782 **/ 1783 static int 1784 ena_intr_msix_mgmnt(void *arg) 1785 { 1786 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1787 1788 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1789 if (likely(adapter->running)) 1790 ena_com_aenq_intr_handler(adapter->ena_dev, arg); 1791 1792 return 1; 1793 } 1794 1795 /** 1796 * ena_handle_msix - MSIX Interrupt Handler for Tx/Rx 1797 * @arg: interrupt number 1798 **/ 1799 static int 1800 ena_handle_msix(void *arg) 1801 { 1802 struct ena_que *que = arg; 1803 struct ena_adapter *adapter = que->adapter; 1804 struct ifnet *ifp = adapter->ifp; 1805 struct ena_ring *tx_ring; 1806 struct ena_ring *rx_ring; 1807 struct ena_com_io_cq* io_cq; 1808 struct ena_eth_io_intr_reg intr_reg; 1809 int qid, ena_qid; 1810 int txc, rxc, i; 1811 1812 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1813 return 0; 1814 1815 ena_trace(ENA_DBG, "MSI-X TX/RX routine"); 1816 1817 tx_ring = que->tx_ring; 1818 rx_ring = que->rx_ring; 1819 qid = que->id; 1820 ena_qid = ENA_IO_TXQ_IDX(qid); 1821 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1822 1823 for (i = 0; i < CLEAN_BUDGET; ++i) { 1824 /* 1825 * If lock cannot be acquired, then deferred cleanup task was 1826 * being executed and rx ring is being cleaned up in 1827 * another thread. 1828 */ 1829 if (likely(ENA_RING_MTX_TRYLOCK(rx_ring) != 0)) { 1830 rxc = ena_rx_cleanup(rx_ring); 1831 ENA_RING_MTX_UNLOCK(rx_ring); 1832 } else { 1833 rxc = 0; 1834 } 1835 1836 /* Protection from calling ena_tx_cleanup from ena_start_xmit */ 1837 ENA_RING_MTX_LOCK(tx_ring); 1838 txc = ena_tx_cleanup(tx_ring); 1839 ENA_RING_MTX_UNLOCK(tx_ring); 1840 1841 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1842 return 0; 1843 1844 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 1845 break; 1846 } 1847 1848 /* Signal that work is done and unmask interrupt */ 1849 ena_com_update_intr_reg(&intr_reg, 1850 RX_IRQ_INTERVAL, 1851 TX_IRQ_INTERVAL, 1852 true); 1853 ena_com_unmask_intr(io_cq, &intr_reg); 1854 1855 return 1; 1856 } 1857 1858 static int 1859 ena_enable_msix(struct ena_adapter *adapter) 1860 { 1861 int msix_req; 1862 int counts[PCI_INTR_TYPE_SIZE]; 1863 int max_type; 1864 1865 /* Reserved the max msix vectors we might need */ 1866 msix_req = ENA_MAX_MSIX_VEC(adapter->num_queues); 1867 1868 counts[PCI_INTR_TYPE_INTX] = 0; 1869 counts[PCI_INTR_TYPE_MSI] = 0; 1870 counts[PCI_INTR_TYPE_MSIX] = msix_req; 1871 max_type = PCI_INTR_TYPE_MSIX; 1872 1873 if (pci_intr_alloc(&adapter->sc_pa, &adapter->sc_intrs, counts, 1874 max_type) != 0) { 1875 aprint_error_dev(adapter->pdev, 1876 "failed to allocate interrupt\n"); 1877 return ENOSPC; 1878 } 1879 1880 adapter->sc_nintrs = counts[PCI_INTR_TYPE_MSIX]; 1881 1882 if (counts[PCI_INTR_TYPE_MSIX] != msix_req) { 1883 device_printf(adapter->pdev, 1884 "Enable only %d MSI-x (out of %d), reduce " 1885 "the number of queues\n", adapter->sc_nintrs, msix_req); 1886 adapter->num_queues = adapter->sc_nintrs - ENA_ADMIN_MSIX_VEC; 1887 } 1888 1889 return 0; 1890 } 1891 1892 #if 0 1893 static void 1894 ena_setup_io_intr(struct ena_adapter *adapter) 1895 { 1896 static int last_bind_cpu = -1; 1897 int irq_idx; 1898 1899 for (int i = 0; i < adapter->num_queues; i++) { 1900 irq_idx = ENA_IO_IRQ_IDX(i); 1901 1902 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1903 "%s-TxRx-%d", device_xname(adapter->pdev), i); 1904 adapter->irq_tbl[irq_idx].handler = ena_handle_msix; 1905 adapter->irq_tbl[irq_idx].data = &adapter->que[i]; 1906 adapter->irq_tbl[irq_idx].vector = 1907 adapter->msix_entries[irq_idx].vector; 1908 ena_trace(ENA_INFO | ENA_IOQ, "ena_setup_io_intr vector: %d\n", 1909 adapter->msix_entries[irq_idx].vector); 1910 #ifdef RSS 1911 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1912 rss_getcpu(i % rss_getnumbuckets()); 1913 #else 1914 /* 1915 * We still want to bind rings to the corresponding cpu 1916 * using something similar to the RSS round-robin technique. 1917 */ 1918 if (unlikely(last_bind_cpu < 0)) 1919 last_bind_cpu = CPU_FIRST(); 1920 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1921 last_bind_cpu; 1922 last_bind_cpu = CPU_NEXT(last_bind_cpu); 1923 #endif 1924 } 1925 } 1926 #endif 1927 1928 static int 1929 ena_request_mgmnt_irq(struct ena_adapter *adapter) 1930 { 1931 const char *intrstr; 1932 char intrbuf[PCI_INTRSTR_LEN]; 1933 char intr_xname[INTRDEVNAMEBUF]; 1934 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 1935 const int irq_slot = ENA_MGMNT_IRQ_IDX; 1936 1937 KASSERT(adapter->sc_intrs != NULL); 1938 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 1939 1940 snprintf(intr_xname, sizeof(intr_xname), "%s mgmnt", 1941 device_xname(adapter->pdev)); 1942 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 1943 intrbuf, sizeof(intrbuf)); 1944 1945 adapter->sc_ihs[irq_slot] = pci_intr_establish_xname( 1946 pc, adapter->sc_intrs[irq_slot], 1947 IPL_NET, ena_intr_msix_mgmnt, adapter, intr_xname); 1948 1949 if (adapter->sc_ihs[irq_slot] == NULL) { 1950 device_printf(adapter->pdev, "failed to register " 1951 "interrupt handler for MGMNT irq %s\n", 1952 intrstr); 1953 return ENOMEM; 1954 } 1955 1956 aprint_normal_dev(adapter->pdev, 1957 "for MGMNT interrupting at %s\n", intrstr); 1958 1959 return 0; 1960 } 1961 1962 static int 1963 ena_request_io_irq(struct ena_adapter *adapter) 1964 { 1965 const char *intrstr; 1966 char intrbuf[PCI_INTRSTR_LEN]; 1967 char intr_xname[INTRDEVNAMEBUF]; 1968 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 1969 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 1970 void *vih; 1971 kcpuset_t *affinity; 1972 int i; 1973 1974 KASSERT(adapter->sc_intrs != NULL); 1975 1976 kcpuset_create(&affinity, false); 1977 1978 for (i = 0; i < adapter->num_queues; i++) { 1979 int irq_slot = i + irq_off; 1980 int affinity_to = (irq_slot) % ncpu; 1981 1982 KASSERT((void *)adapter->sc_intrs[irq_slot] != NULL); 1983 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 1984 1985 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 1986 device_xname(adapter->pdev), i); 1987 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 1988 intrbuf, sizeof(intrbuf)); 1989 1990 vih = pci_intr_establish_xname(adapter->sc_pa.pa_pc, 1991 adapter->sc_intrs[irq_slot], IPL_NET, 1992 ena_handle_msix, &adapter->que[i], intr_xname); 1993 1994 if (adapter->sc_ihs[ENA_MGMNT_IRQ_IDX] == NULL) { 1995 device_printf(adapter->pdev, "failed to register " 1996 "interrupt handler for IO queue %d irq %s\n", 1997 i, intrstr); 1998 goto err; 1999 } 2000 2001 kcpuset_zero(affinity); 2002 /* Round-robin affinity */ 2003 kcpuset_set(affinity, affinity_to); 2004 int error = interrupt_distribute(vih, affinity, NULL); 2005 if (error == 0) { 2006 aprint_normal_dev(adapter->pdev, 2007 "for IO queue %d interrupting at %s" 2008 " affinity to %u\n", i, intrstr, affinity_to); 2009 } else { 2010 aprint_normal_dev(adapter->pdev, 2011 "for IO queue %d interrupting at %s\n", i, intrstr); 2012 } 2013 2014 adapter->sc_ihs[irq_slot] = vih; 2015 2016 #ifdef RSS 2017 ena_trace(ENA_INFO, "queue %d - RSS bucket %d\n", 2018 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2019 #else 2020 ena_trace(ENA_INFO, "queue %d - cpu %d\n", 2021 i - ENA_IO_IRQ_FIRST_IDX, affinity_to); 2022 #endif 2023 } 2024 2025 kcpuset_destroy(affinity); 2026 return 0; 2027 2028 err: 2029 kcpuset_destroy(affinity); 2030 2031 for (i--; i >= 0; i--) { 2032 int irq_slot = i + irq_off; 2033 KASSERT(adapter->sc_ihs[irq_slot] != NULL); 2034 pci_intr_disestablish(adapter->sc_pa.pa_pc, adapter->sc_ihs[i]); 2035 adapter->sc_ihs[i] = NULL; 2036 } 2037 2038 return ENOSPC; 2039 } 2040 2041 static void 2042 ena_free_mgmnt_irq(struct ena_adapter *adapter) 2043 { 2044 const int irq_slot = ENA_MGMNT_IRQ_IDX; 2045 2046 if (adapter->sc_ihs[irq_slot]) { 2047 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2048 adapter->sc_ihs[irq_slot]); 2049 adapter->sc_ihs[irq_slot] = NULL; 2050 } 2051 } 2052 2053 static void 2054 ena_free_io_irq(struct ena_adapter *adapter) 2055 { 2056 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2057 2058 for (int i = 0; i < adapter->num_queues; i++) { 2059 int irq_slot = i + irq_off; 2060 2061 if (adapter->sc_ihs[irq_slot]) { 2062 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2063 adapter->sc_ihs[i]); 2064 adapter->sc_ihs[i] = NULL; 2065 } 2066 } 2067 } 2068 2069 static void 2070 ena_free_irqs(struct ena_adapter* adapter) 2071 { 2072 2073 ena_free_io_irq(adapter); 2074 ena_free_mgmnt_irq(adapter); 2075 ena_disable_msix(adapter); 2076 } 2077 2078 static void 2079 ena_disable_msix(struct ena_adapter *adapter) 2080 { 2081 pci_intr_release(adapter->sc_pa.pa_pc, adapter->sc_intrs, 2082 adapter->sc_nintrs); 2083 } 2084 2085 static void 2086 ena_unmask_all_io_irqs(struct ena_adapter *adapter) 2087 { 2088 struct ena_com_io_cq* io_cq; 2089 struct ena_eth_io_intr_reg intr_reg; 2090 uint16_t ena_qid; 2091 int i; 2092 2093 /* Unmask interrupts for all queues */ 2094 for (i = 0; i < adapter->num_queues; i++) { 2095 ena_qid = ENA_IO_TXQ_IDX(i); 2096 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 2097 ena_com_update_intr_reg(&intr_reg, 0, 0, true); 2098 ena_com_unmask_intr(io_cq, &intr_reg); 2099 } 2100 } 2101 2102 /* Configure the Rx forwarding */ 2103 static int 2104 ena_rss_configure(struct ena_adapter *adapter) 2105 { 2106 struct ena_com_dev *ena_dev = adapter->ena_dev; 2107 int rc; 2108 2109 /* Set indirect table */ 2110 rc = ena_com_indirect_table_set(ena_dev); 2111 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2112 return (rc); 2113 2114 /* Configure hash function (if supported) */ 2115 rc = ena_com_set_hash_function(ena_dev); 2116 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2117 return (rc); 2118 2119 /* Configure hash inputs (if supported) */ 2120 rc = ena_com_set_hash_ctrl(ena_dev); 2121 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2122 return (rc); 2123 2124 return (0); 2125 } 2126 2127 static int 2128 ena_up_complete(struct ena_adapter *adapter) 2129 { 2130 int rc; 2131 2132 if (likely(adapter->rss_support)) { 2133 rc = ena_rss_configure(adapter); 2134 if (rc != 0) 2135 return (rc); 2136 } 2137 2138 rc = ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu); 2139 if (unlikely(rc != 0)) 2140 return (rc); 2141 2142 ena_refill_all_rx_bufs(adapter); 2143 ena_reset_counters((struct evcnt *)&adapter->hw_stats, 2144 sizeof(adapter->hw_stats)); 2145 2146 return (0); 2147 } 2148 2149 static int 2150 ena_up(struct ena_adapter *adapter) 2151 { 2152 int rc = 0; 2153 2154 #if 0 2155 if (unlikely(device_is_attached(adapter->pdev) == 0)) { 2156 device_printf(adapter->pdev, "device is not attached!\n"); 2157 return (ENXIO); 2158 } 2159 #endif 2160 2161 if (unlikely(!adapter->running)) { 2162 device_printf(adapter->pdev, "device is not running!\n"); 2163 return (ENXIO); 2164 } 2165 2166 if (!adapter->up) { 2167 device_printf(adapter->pdev, "device is going UP\n"); 2168 2169 /* setup interrupts for IO queues */ 2170 rc = ena_request_io_irq(adapter); 2171 if (unlikely(rc != 0)) { 2172 ena_trace(ENA_ALERT, "err_req_irq"); 2173 goto err_req_irq; 2174 } 2175 2176 /* allocate transmit descriptors */ 2177 rc = ena_setup_all_tx_resources(adapter); 2178 if (unlikely(rc != 0)) { 2179 ena_trace(ENA_ALERT, "err_setup_tx"); 2180 goto err_setup_tx; 2181 } 2182 2183 /* allocate receive descriptors */ 2184 rc = ena_setup_all_rx_resources(adapter); 2185 if (unlikely(rc != 0)) { 2186 ena_trace(ENA_ALERT, "err_setup_rx"); 2187 goto err_setup_rx; 2188 } 2189 2190 /* create IO queues for Rx & Tx */ 2191 rc = ena_create_io_queues(adapter); 2192 if (unlikely(rc != 0)) { 2193 ena_trace(ENA_ALERT, 2194 "create IO queues failed"); 2195 goto err_io_que; 2196 } 2197 2198 if (unlikely(adapter->link_status)) 2199 if_link_state_change(adapter->ifp, LINK_STATE_UP); 2200 2201 rc = ena_up_complete(adapter); 2202 if (unlikely(rc != 0)) 2203 goto err_up_complete; 2204 2205 counter_u64_add(adapter->dev_stats.interface_up, 1); 2206 2207 ena_update_hwassist(adapter); 2208 2209 if_setdrvflagbits(adapter->ifp, IFF_RUNNING, 2210 IFF_OACTIVE); 2211 2212 callout_reset(&adapter->timer_service, hz, 2213 ena_timer_service, (void *)adapter); 2214 2215 adapter->up = true; 2216 2217 ena_unmask_all_io_irqs(adapter); 2218 } 2219 2220 return (0); 2221 2222 err_up_complete: 2223 ena_destroy_all_io_queues(adapter); 2224 err_io_que: 2225 ena_free_all_rx_resources(adapter); 2226 err_setup_rx: 2227 ena_free_all_tx_resources(adapter); 2228 err_setup_tx: 2229 ena_free_io_irq(adapter); 2230 err_req_irq: 2231 return (rc); 2232 } 2233 2234 #if 0 2235 static uint64_t 2236 ena_get_counter(struct ifnet *ifp, ift_counter cnt) 2237 { 2238 struct ena_adapter *adapter; 2239 struct ena_hw_stats *stats; 2240 2241 adapter = if_getsoftc(ifp); 2242 stats = &adapter->hw_stats; 2243 2244 switch (cnt) { 2245 case IFCOUNTER_IPACKETS: 2246 return (counter_u64_fetch(stats->rx_packets)); 2247 case IFCOUNTER_OPACKETS: 2248 return (counter_u64_fetch(stats->tx_packets)); 2249 case IFCOUNTER_IBYTES: 2250 return (counter_u64_fetch(stats->rx_bytes)); 2251 case IFCOUNTER_OBYTES: 2252 return (counter_u64_fetch(stats->tx_bytes)); 2253 case IFCOUNTER_IQDROPS: 2254 return (counter_u64_fetch(stats->rx_drops)); 2255 default: 2256 return (if_get_counter_default(ifp, cnt)); 2257 } 2258 } 2259 #endif 2260 2261 static int 2262 ena_media_change(struct ifnet *ifp) 2263 { 2264 /* Media Change is not supported by firmware */ 2265 return (0); 2266 } 2267 2268 static void 2269 ena_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2270 { 2271 struct ena_adapter *adapter = if_getsoftc(ifp); 2272 ena_trace(ENA_DBG, "enter"); 2273 2274 mutex_enter(&adapter->global_mtx); 2275 2276 ifmr->ifm_status = IFM_AVALID; 2277 ifmr->ifm_active = IFM_ETHER; 2278 2279 if (!adapter->link_status) { 2280 mutex_exit(&adapter->global_mtx); 2281 ena_trace(ENA_INFO, "link_status = false"); 2282 return; 2283 } 2284 2285 ifmr->ifm_status |= IFM_ACTIVE; 2286 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2287 2288 mutex_exit(&adapter->global_mtx); 2289 } 2290 2291 static int 2292 ena_init(struct ifnet *ifp) 2293 { 2294 struct ena_adapter *adapter = if_getsoftc(ifp); 2295 2296 if (!adapter->up) { 2297 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2298 ena_up(adapter); 2299 rw_exit(&adapter->ioctl_sx); 2300 } 2301 2302 return 0; 2303 } 2304 2305 static int 2306 ena_ioctl(struct ifnet *ifp, u_long command, void *data) 2307 { 2308 struct ena_adapter *adapter; 2309 struct ifreq *ifr; 2310 int rc; 2311 2312 adapter = ifp->if_softc; 2313 ifr = (struct ifreq *)data; 2314 2315 /* 2316 * Acquiring lock to prevent from running up and down routines parallel. 2317 */ 2318 rc = 0; 2319 switch (command) { 2320 case SIOCSIFMTU: 2321 if (ifp->if_mtu == ifr->ifr_mtu) 2322 break; 2323 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2324 ena_down(adapter); 2325 2326 ena_change_mtu(ifp, ifr->ifr_mtu); 2327 2328 rc = ena_up(adapter); 2329 rw_exit(&adapter->ioctl_sx); 2330 break; 2331 2332 case SIOCSIFFLAGS: 2333 if ((ifp->if_flags & IFF_UP) != 0) { 2334 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2335 if ((ifp->if_flags & (IFF_PROMISC | 2336 IFF_ALLMULTI)) != 0) { 2337 device_printf(adapter->pdev, 2338 "ioctl promisc/allmulti\n"); 2339 } 2340 } else { 2341 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2342 rc = ena_up(adapter); 2343 rw_exit(&adapter->ioctl_sx); 2344 } 2345 } else { 2346 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2347 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2348 ena_down(adapter); 2349 rw_exit(&adapter->ioctl_sx); 2350 } 2351 } 2352 break; 2353 2354 case SIOCADDMULTI: 2355 case SIOCDELMULTI: 2356 break; 2357 2358 case SIOCSIFMEDIA: 2359 case SIOCGIFMEDIA: 2360 rc = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 2361 break; 2362 2363 case SIOCSIFCAP: 2364 { 2365 struct ifcapreq *ifcr = data; 2366 int reinit = 0; 2367 2368 if (ifcr->ifcr_capenable != ifp->if_capenable) { 2369 ifp->if_capenable = ifcr->ifcr_capenable; 2370 reinit = 1; 2371 } 2372 2373 if ((reinit != 0) && 2374 ((if_getdrvflags(ifp) & IFF_RUNNING) != 0)) { 2375 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2376 ena_down(adapter); 2377 rc = ena_up(adapter); 2378 rw_exit(&adapter->ioctl_sx); 2379 } 2380 } 2381 2382 break; 2383 default: 2384 rc = ether_ioctl(ifp, command, data); 2385 break; 2386 } 2387 2388 return (rc); 2389 } 2390 2391 static int 2392 ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *feat) 2393 { 2394 int caps = 0; 2395 2396 if ((feat->offload.tx & 2397 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2398 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK | 2399 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)) != 0) 2400 caps |= IFCAP_CSUM_IPv4_Tx; 2401 2402 if ((feat->offload.tx & 2403 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK | 2404 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)) != 0) 2405 caps |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 2406 2407 if ((feat->offload.tx & 2408 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0) 2409 caps |= IFCAP_TSOv4; 2410 2411 if ((feat->offload.tx & 2412 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) != 0) 2413 caps |= IFCAP_TSOv6; 2414 2415 if ((feat->offload.rx_supported & 2416 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK | 2417 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)) != 0) 2418 caps |= IFCAP_CSUM_IPv4_Rx; 2419 2420 if ((feat->offload.rx_supported & 2421 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) != 0) 2422 caps |= IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 2423 2424 caps |= IFCAP_LRO; 2425 2426 return (caps); 2427 } 2428 2429 static void 2430 ena_update_host_info(struct ena_admin_host_info *host_info, struct ifnet *ifp) 2431 { 2432 2433 host_info->supported_network_features[0] = 2434 (uint32_t)if_getcapabilities(ifp); 2435 } 2436 2437 static void 2438 ena_update_hwassist(struct ena_adapter *adapter) 2439 { 2440 struct ifnet *ifp = adapter->ifp; 2441 uint32_t feat = adapter->tx_offload_cap; 2442 int cap = if_getcapenable(ifp); 2443 int flags = 0; 2444 2445 if_clearhwassist(ifp); 2446 2447 if ((cap & (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2448 != 0) { 2449 if ((feat & 2450 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) != 0) 2451 flags |= M_CSUM_IPv4; 2452 if ((feat & 2453 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2454 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)) != 0) 2455 flags |= M_CSUM_TCPv4 | M_CSUM_UDPv4; 2456 } 2457 2458 if ((cap & IFCAP_CSUM_TCPv6_Tx) != 0) 2459 flags |= M_CSUM_TCPv6; 2460 2461 if ((cap & IFCAP_CSUM_UDPv6_Tx) != 0) 2462 flags |= M_CSUM_UDPv6; 2463 2464 if ((cap & IFCAP_TSOv4) != 0) 2465 flags |= M_CSUM_TSOv4; 2466 2467 if ((cap & IFCAP_TSOv6) != 0) 2468 flags |= M_CSUM_TSOv6; 2469 2470 if_sethwassistbits(ifp, flags, 0); 2471 } 2472 2473 static int 2474 ena_setup_ifnet(device_t pdev, struct ena_adapter *adapter, 2475 struct ena_com_dev_get_features_ctx *feat) 2476 { 2477 struct ifnet *ifp; 2478 int caps = 0; 2479 2480 ifp = adapter->ifp = &adapter->sc_ec.ec_if; 2481 if (unlikely(ifp == NULL)) { 2482 ena_trace(ENA_ALERT, "can not allocate ifnet structure\n"); 2483 return (ENXIO); 2484 } 2485 if_initname(ifp, device_xname(pdev), device_unit(pdev)); 2486 if_setdev(ifp, pdev); 2487 if_setsoftc(ifp, adapter); 2488 2489 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2490 if_setinitfn(ifp, ena_init); 2491 if_settransmitfn(ifp, ena_mq_start); 2492 #if 0 2493 if_setqflushfn(ifp, ena_qflush); 2494 #endif 2495 if_setioctlfn(ifp, ena_ioctl); 2496 #if 0 2497 if_setgetcounterfn(ifp, ena_get_counter); 2498 #endif 2499 2500 if_setsendqlen(ifp, adapter->tx_ring_size); 2501 if_setsendqready(ifp); 2502 if_setmtu(ifp, ETHERMTU); 2503 if_setbaudrate(ifp, 0); 2504 /* Zeroize capabilities... */ 2505 if_setcapabilities(ifp, 0); 2506 if_setcapenable(ifp, 0); 2507 /* check hardware support */ 2508 caps = ena_get_dev_offloads(feat); 2509 /* ... and set them */ 2510 if_setcapabilitiesbit(ifp, caps, 0); 2511 adapter->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2512 2513 #if 0 2514 /* TSO parameters */ 2515 /* XXX no limits on NetBSD, guarded by virtue of dmamap load failing */ 2516 ifp->if_hw_tsomax = ENA_TSO_MAXSIZE - 2517 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2518 ifp->if_hw_tsomaxsegcount = adapter->max_tx_sgl_size - 1; 2519 ifp->if_hw_tsomaxsegsize = ENA_TSO_MAXSIZE; 2520 #endif 2521 2522 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2523 if_setcapenable(ifp, if_getcapabilities(ifp)); 2524 2525 /* 2526 * Specify the media types supported by this adapter and register 2527 * callbacks to update media and link information 2528 */ 2529 ifmedia_init(&adapter->media, IFM_IMASK, 2530 ena_media_change, ena_media_status); 2531 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2532 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2533 2534 ether_ifattach(ifp, adapter->mac_addr); 2535 2536 return (0); 2537 } 2538 2539 static void 2540 ena_down(struct ena_adapter *adapter) 2541 { 2542 int rc; 2543 2544 if (adapter->up) { 2545 device_printf(adapter->pdev, "device is going DOWN\n"); 2546 2547 callout_halt(&adapter->timer_service, &adapter->global_mtx); 2548 2549 adapter->up = false; 2550 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, 2551 IFF_RUNNING); 2552 2553 ena_free_io_irq(adapter); 2554 2555 if (adapter->trigger_reset) { 2556 rc = ena_com_dev_reset(adapter->ena_dev, 2557 adapter->reset_reason); 2558 if (unlikely(rc != 0)) 2559 device_printf(adapter->pdev, 2560 "Device reset failed\n"); 2561 } 2562 2563 ena_destroy_all_io_queues(adapter); 2564 2565 ena_free_all_tx_bufs(adapter); 2566 ena_free_all_rx_bufs(adapter); 2567 ena_free_all_tx_resources(adapter); 2568 ena_free_all_rx_resources(adapter); 2569 2570 counter_u64_add(adapter->dev_stats.interface_down, 1); 2571 } 2572 } 2573 2574 static void 2575 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf) 2576 { 2577 struct ena_com_tx_meta *ena_meta; 2578 struct ether_vlan_header *eh; 2579 u32 mss; 2580 bool offload; 2581 uint16_t etype; 2582 int ehdrlen; 2583 struct ip *ip; 2584 int iphlen; 2585 struct tcphdr *th; 2586 2587 offload = false; 2588 ena_meta = &ena_tx_ctx->ena_meta; 2589 2590 #if 0 2591 u32 mss = mbuf->m_pkthdr.tso_segsz; 2592 2593 if (mss != 0) 2594 offload = true; 2595 #else 2596 mss = mbuf->m_pkthdr.len; /* XXX don't have tso_segsz */ 2597 #endif 2598 2599 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) 2600 offload = true; 2601 2602 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 2603 offload = true; 2604 2605 if (!offload) { 2606 ena_tx_ctx->meta_valid = 0; 2607 return; 2608 } 2609 2610 /* Determine where frame payload starts. */ 2611 eh = mtod(mbuf, struct ether_vlan_header *); 2612 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2613 etype = ntohs(eh->evl_proto); 2614 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2615 } else { 2616 etype = htons(eh->evl_encap_proto); 2617 ehdrlen = ETHER_HDR_LEN; 2618 } 2619 2620 ip = (struct ip *)(mbuf->m_data + ehdrlen); 2621 iphlen = ip->ip_hl << 2; 2622 th = (struct tcphdr *)((vaddr_t)ip + iphlen); 2623 2624 if ((mbuf->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 2625 ena_tx_ctx->l3_csum_enable = 1; 2626 } 2627 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 2628 ena_tx_ctx->tso_enable = 1; 2629 ena_meta->l4_hdr_len = (th->th_off); 2630 } 2631 2632 switch (etype) { 2633 case ETHERTYPE_IP: 2634 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 2635 if ((ip->ip_off & htons(IP_DF)) != 0) 2636 ena_tx_ctx->df = 1; 2637 break; 2638 case ETHERTYPE_IPV6: 2639 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 2640 2641 default: 2642 break; 2643 } 2644 2645 if (ip->ip_p == IPPROTO_TCP) { 2646 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 2647 if ((mbuf->m_pkthdr.csum_flags & 2648 (M_CSUM_TCPv4 | M_CSUM_TCPv6)) != 0) 2649 ena_tx_ctx->l4_csum_enable = 1; 2650 else 2651 ena_tx_ctx->l4_csum_enable = 0; 2652 } else if (ip->ip_p == IPPROTO_UDP) { 2653 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 2654 if ((mbuf->m_pkthdr.csum_flags & 2655 (M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2656 ena_tx_ctx->l4_csum_enable = 1; 2657 else 2658 ena_tx_ctx->l4_csum_enable = 0; 2659 } else { 2660 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 2661 ena_tx_ctx->l4_csum_enable = 0; 2662 } 2663 2664 ena_meta->mss = mss; 2665 ena_meta->l3_hdr_len = iphlen; 2666 ena_meta->l3_hdr_offset = ehdrlen; 2667 ena_tx_ctx->meta_valid = 1; 2668 } 2669 2670 static int 2671 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2672 { 2673 struct ena_adapter *adapter; 2674 struct mbuf *collapsed_mbuf; 2675 int num_frags; 2676 2677 adapter = tx_ring->adapter; 2678 num_frags = ena_mbuf_count(*mbuf); 2679 2680 /* One segment must be reserved for configuration descriptor. */ 2681 if (num_frags < adapter->max_tx_sgl_size) 2682 return (0); 2683 counter_u64_add(tx_ring->tx_stats.collapse, 1); 2684 2685 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 2686 adapter->max_tx_sgl_size - 1); 2687 if (unlikely(collapsed_mbuf == NULL)) { 2688 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 2689 return (ENOMEM); 2690 } 2691 2692 /* If mbuf was collapsed succesfully, original mbuf is released. */ 2693 *mbuf = collapsed_mbuf; 2694 2695 return (0); 2696 } 2697 2698 static int 2699 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2700 { 2701 struct ena_adapter *adapter; 2702 struct ena_tx_buffer *tx_info; 2703 struct ena_com_tx_ctx ena_tx_ctx; 2704 struct ena_com_dev *ena_dev; 2705 struct ena_com_buf *ena_buf; 2706 struct ena_com_io_sq* io_sq; 2707 void *push_hdr; 2708 uint16_t next_to_use; 2709 uint16_t req_id; 2710 uint16_t ena_qid; 2711 uint32_t header_len; 2712 int i, rc; 2713 int nb_hw_desc; 2714 2715 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2716 adapter = tx_ring->que->adapter; 2717 ena_dev = adapter->ena_dev; 2718 io_sq = &ena_dev->io_sq_queues[ena_qid]; 2719 2720 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 2721 if (unlikely(rc != 0)) { 2722 ena_trace(ENA_WARNING, 2723 "Failed to collapse mbuf! err: %d", rc); 2724 return (rc); 2725 } 2726 2727 next_to_use = tx_ring->next_to_use; 2728 req_id = tx_ring->free_tx_ids[next_to_use]; 2729 tx_info = &tx_ring->tx_buffer_info[req_id]; 2730 2731 tx_info->mbuf = *mbuf; 2732 tx_info->num_of_bufs = 0; 2733 2734 ena_buf = tx_info->bufs; 2735 2736 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes", (*mbuf)->m_pkthdr.len); 2737 2738 /* 2739 * header_len is just a hint for the device. Because FreeBSD is not 2740 * giving us information about packet header length and it is not 2741 * guaranteed that all packet headers will be in the 1st mbuf, setting 2742 * header_len to 0 is making the device ignore this value and resolve 2743 * header on it's own. 2744 */ 2745 header_len = 0; 2746 push_hdr = NULL; 2747 2748 rc = bus_dmamap_load_mbuf(adapter->sc_dmat, tx_info->map, 2749 *mbuf, BUS_DMA_NOWAIT); 2750 2751 if (unlikely((rc != 0) || (tx_info->map->dm_nsegs == 0))) { 2752 ena_trace(ENA_WARNING, 2753 "dmamap load failed! err: %d nsegs: %d", rc, 2754 tx_info->map->dm_nsegs); 2755 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 2756 tx_info->mbuf = NULL; 2757 if (rc == ENOMEM) 2758 return (ENA_COM_NO_MEM); 2759 else 2760 return (ENA_COM_INVAL); 2761 } 2762 2763 for (i = 0; i < tx_info->map->dm_nsegs; i++) { 2764 ena_buf->len = tx_info->map->dm_segs[i].ds_len; 2765 ena_buf->paddr = tx_info->map->dm_segs[i].ds_addr; 2766 ena_buf++; 2767 } 2768 tx_info->num_of_bufs = tx_info->map->dm_nsegs; 2769 2770 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2771 ena_tx_ctx.ena_bufs = tx_info->bufs; 2772 ena_tx_ctx.push_header = push_hdr; 2773 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2774 ena_tx_ctx.req_id = req_id; 2775 ena_tx_ctx.header_len = header_len; 2776 2777 /* Set flags and meta data */ 2778 ena_tx_csum(&ena_tx_ctx, *mbuf); 2779 /* Prepare the packet's descriptors and send them to device */ 2780 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 2781 if (unlikely(rc != 0)) { 2782 device_printf(adapter->pdev, "failed to prepare tx bufs\n"); 2783 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 2784 goto dma_error; 2785 } 2786 2787 counter_enter(); 2788 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 2789 counter_u64_add_protected(tx_ring->tx_stats.bytes, 2790 (*mbuf)->m_pkthdr.len); 2791 2792 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 2793 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 2794 (*mbuf)->m_pkthdr.len); 2795 counter_exit(); 2796 2797 tx_info->tx_descs = nb_hw_desc; 2798 getbinuptime(&tx_info->timestamp); 2799 tx_info->print_once = true; 2800 2801 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2802 tx_ring->ring_size); 2803 2804 bus_dmamap_sync(adapter->sc_dmat, tx_info->map, 0, 2805 tx_info->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2806 2807 return (0); 2808 2809 dma_error: 2810 tx_info->mbuf = NULL; 2811 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 2812 2813 return (rc); 2814 } 2815 2816 static void 2817 ena_start_xmit(struct ena_ring *tx_ring) 2818 { 2819 struct mbuf *mbuf; 2820 struct ena_adapter *adapter = tx_ring->adapter; 2821 struct ena_com_io_sq* io_sq; 2822 int ena_qid; 2823 int acum_pkts = 0; 2824 int ret = 0; 2825 2826 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2827 return; 2828 2829 if (unlikely(!adapter->link_status)) 2830 return; 2831 2832 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2833 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 2834 2835 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 2836 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 2837 " header csum flags %#jx", 2838 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 2839 2840 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 2841 ENA_TX_CLEANUP_THRESHOLD))) 2842 ena_tx_cleanup(tx_ring); 2843 2844 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 2845 if (ret == ENA_COM_NO_MEM) { 2846 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2847 } else if (ret == ENA_COM_NO_SPACE) { 2848 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2849 } else { 2850 m_freem(mbuf); 2851 drbr_advance(adapter->ifp, tx_ring->br); 2852 } 2853 2854 break; 2855 } 2856 2857 drbr_advance(adapter->ifp, tx_ring->br); 2858 2859 if (unlikely((if_getdrvflags(adapter->ifp) & 2860 IFF_RUNNING) == 0)) 2861 return; 2862 2863 acum_pkts++; 2864 2865 /* 2866 * If there's a BPF listener, bounce a copy of this frame 2867 * to him. 2868 */ 2869 bpf_mtap(adapter->ifp, mbuf, BPF_D_OUT); 2870 2871 if (unlikely(acum_pkts == DB_THRESHOLD)) { 2872 acum_pkts = 0; 2873 wmb(); 2874 /* Trigger the dma engine */ 2875 ena_com_write_sq_doorbell(io_sq); 2876 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2877 } 2878 2879 } 2880 2881 if (likely(acum_pkts != 0)) { 2882 wmb(); 2883 /* Trigger the dma engine */ 2884 ena_com_write_sq_doorbell(io_sq); 2885 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2886 } 2887 2888 if (!ena_com_sq_have_enough_space(io_sq, ENA_TX_CLEANUP_THRESHOLD)) 2889 ena_tx_cleanup(tx_ring); 2890 } 2891 2892 static void 2893 ena_deferred_mq_start(struct work *wk, void *arg) 2894 { 2895 struct ena_ring *tx_ring = (struct ena_ring *)arg; 2896 struct ifnet *ifp = tx_ring->adapter->ifp; 2897 2898 while (!drbr_empty(ifp, tx_ring->br) && 2899 (if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2900 ENA_RING_MTX_LOCK(tx_ring); 2901 ena_start_xmit(tx_ring); 2902 ENA_RING_MTX_UNLOCK(tx_ring); 2903 } 2904 } 2905 2906 static int 2907 ena_mq_start(struct ifnet *ifp, struct mbuf *m) 2908 { 2909 struct ena_adapter *adapter = ifp->if_softc; 2910 struct ena_ring *tx_ring; 2911 int ret, is_drbr_empty; 2912 uint32_t i; 2913 2914 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2915 return (ENODEV); 2916 2917 /* Which queue to use */ 2918 /* 2919 * If everything is setup correctly, it should be the 2920 * same bucket that the current CPU we're on is. 2921 * It should improve performance. 2922 */ 2923 #if 0 2924 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 2925 #ifdef RSS 2926 if (rss_hash2bucket(m->m_pkthdr.flowid, 2927 M_HASHTYPE_GET(m), &i) == 0) { 2928 i = i % adapter->num_queues; 2929 2930 } else 2931 #endif 2932 { 2933 i = m->m_pkthdr.flowid % adapter->num_queues; 2934 } 2935 } else { 2936 #endif 2937 i = cpu_index(curcpu()) % adapter->num_queues; 2938 #if 0 2939 } 2940 #endif 2941 tx_ring = &adapter->tx_ring[i]; 2942 2943 /* Check if drbr is empty before putting packet */ 2944 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 2945 ret = drbr_enqueue(ifp, tx_ring->br, m); 2946 if (unlikely(ret != 0)) { 2947 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 2948 curcpu()); 2949 return (ret); 2950 } 2951 2952 if ((is_drbr_empty != 0) && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 2953 ena_start_xmit(tx_ring); 2954 ENA_RING_MTX_UNLOCK(tx_ring); 2955 } else { 2956 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 2957 curcpu()); 2958 } 2959 2960 return (0); 2961 } 2962 2963 #if 0 2964 static void 2965 ena_qflush(struct ifnet *ifp) 2966 { 2967 struct ena_adapter *adapter = ifp->if_softc; 2968 struct ena_ring *tx_ring = adapter->tx_ring; 2969 int i; 2970 2971 for(i = 0; i < adapter->num_queues; ++i, ++tx_ring) 2972 if (!drbr_empty(ifp, tx_ring->br)) { 2973 ENA_RING_MTX_LOCK(tx_ring); 2974 drbr_flush(ifp, tx_ring->br); 2975 ENA_RING_MTX_UNLOCK(tx_ring); 2976 } 2977 2978 if_qflush(ifp); 2979 } 2980 #endif 2981 2982 static int 2983 ena_calc_io_queue_num(struct pci_attach_args *pa, 2984 struct ena_adapter *adapter, 2985 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2986 { 2987 int io_sq_num, io_cq_num, io_queue_num; 2988 2989 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 2990 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 2991 2992 io_queue_num = min_t(int, mp_ncpus, ENA_MAX_NUM_IO_QUEUES); 2993 io_queue_num = min_t(int, io_queue_num, io_sq_num); 2994 io_queue_num = min_t(int, io_queue_num, io_cq_num); 2995 /* 1 IRQ for for mgmnt and 1 IRQ for each TX/RX pair */ 2996 io_queue_num = min_t(int, io_queue_num, 2997 pci_msix_count(pa->pa_pc, pa->pa_tag) - 1); 2998 #ifdef RSS 2999 io_queue_num = min_t(int, io_queue_num, rss_getnumbuckets()); 3000 #endif 3001 3002 return (io_queue_num); 3003 } 3004 3005 static int 3006 ena_calc_queue_size(struct ena_adapter *adapter, uint16_t *max_tx_sgl_size, 3007 uint16_t *max_rx_sgl_size, struct ena_com_dev_get_features_ctx *feat) 3008 { 3009 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 3010 uint32_t v; 3011 uint32_t q; 3012 3013 queue_size = min_t(uint32_t, queue_size, 3014 feat->max_queues.max_cq_depth); 3015 queue_size = min_t(uint32_t, queue_size, 3016 feat->max_queues.max_sq_depth); 3017 3018 /* round down to the nearest power of 2 */ 3019 v = queue_size; 3020 while (v != 0) { 3021 if (powerof2(queue_size) != 0) 3022 break; 3023 v /= 2; 3024 q = rounddown2(queue_size, v); 3025 if (q != 0) { 3026 queue_size = q; 3027 break; 3028 } 3029 } 3030 3031 if (unlikely(queue_size == 0)) { 3032 device_printf(adapter->pdev, "Invalid queue size\n"); 3033 return (ENA_COM_FAULT); 3034 } 3035 3036 *max_tx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3037 feat->max_queues.max_packet_tx_descs); 3038 *max_rx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3039 feat->max_queues.max_packet_rx_descs); 3040 3041 return (queue_size); 3042 } 3043 3044 #if 0 3045 static int 3046 ena_rss_init_default(struct ena_adapter *adapter) 3047 { 3048 struct ena_com_dev *ena_dev = adapter->ena_dev; 3049 device_t dev = adapter->pdev; 3050 int qid, rc, i; 3051 3052 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3053 if (unlikely(rc != 0)) { 3054 device_printf(dev, "Cannot init indirect table\n"); 3055 return (rc); 3056 } 3057 3058 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3059 #ifdef RSS 3060 qid = rss_get_indirection_to_bucket(i); 3061 qid = qid % adapter->num_queues; 3062 #else 3063 qid = i % adapter->num_queues; 3064 #endif 3065 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3066 ENA_IO_RXQ_IDX(qid)); 3067 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3068 device_printf(dev, "Cannot fill indirect table\n"); 3069 goto err_rss_destroy; 3070 } 3071 } 3072 3073 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3074 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3075 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3076 device_printf(dev, "Cannot fill hash function\n"); 3077 goto err_rss_destroy; 3078 } 3079 3080 rc = ena_com_set_default_hash_ctrl(ena_dev); 3081 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3082 device_printf(dev, "Cannot fill hash control\n"); 3083 goto err_rss_destroy; 3084 } 3085 3086 return (0); 3087 3088 err_rss_destroy: 3089 ena_com_rss_destroy(ena_dev); 3090 return (rc); 3091 } 3092 3093 static void 3094 ena_rss_init_default_deferred(void *arg) 3095 { 3096 struct ena_adapter *adapter; 3097 devclass_t dc; 3098 int max; 3099 int rc; 3100 3101 dc = devclass_find("ena"); 3102 if (unlikely(dc == NULL)) { 3103 ena_trace(ENA_ALERT, "No devclass ena\n"); 3104 return; 3105 } 3106 3107 max = devclass_get_maxunit(dc); 3108 while (max-- >= 0) { 3109 adapter = devclass_get_softc(dc, max); 3110 if (adapter != NULL) { 3111 rc = ena_rss_init_default(adapter); 3112 adapter->rss_support = true; 3113 if (unlikely(rc != 0)) { 3114 device_printf(adapter->pdev, 3115 "WARNING: RSS was not properly initialized," 3116 " it will affect bandwidth\n"); 3117 adapter->rss_support = false; 3118 } 3119 } 3120 } 3121 } 3122 SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL); 3123 #endif 3124 3125 static void 3126 ena_config_host_info(struct ena_com_dev *ena_dev) 3127 { 3128 struct ena_admin_host_info *host_info; 3129 int rc; 3130 3131 /* Allocate only the host info */ 3132 rc = ena_com_allocate_host_info(ena_dev); 3133 if (unlikely(rc != 0)) { 3134 ena_trace(ENA_ALERT, "Cannot allocate host info\n"); 3135 return; 3136 } 3137 3138 host_info = ena_dev->host_attr.host_info; 3139 3140 host_info->os_type = ENA_ADMIN_OS_FREEBSD; 3141 host_info->kernel_ver = osreldate; 3142 3143 snprintf(host_info->kernel_ver_str, sizeof(host_info->kernel_ver_str), 3144 "%d", osreldate); 3145 host_info->os_dist = 0; 3146 strncpy(host_info->os_dist_str, osrelease, 3147 sizeof(host_info->os_dist_str) - 1); 3148 3149 host_info->driver_version = 3150 (DRV_MODULE_VER_MAJOR) | 3151 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 3152 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 3153 3154 rc = ena_com_set_host_attributes(ena_dev); 3155 if (unlikely(rc != 0)) { 3156 if (rc == EOPNOTSUPP) 3157 ena_trace(ENA_WARNING, "Cannot set host attributes\n"); 3158 else 3159 ena_trace(ENA_ALERT, "Cannot set host attributes\n"); 3160 3161 goto err; 3162 } 3163 3164 return; 3165 3166 err: 3167 ena_com_delete_host_info(ena_dev); 3168 } 3169 3170 static int 3171 ena_device_init(struct ena_adapter *adapter, device_t pdev, 3172 struct ena_com_dev_get_features_ctx *get_feat_ctx, int *wd_active) 3173 { 3174 struct ena_com_dev* ena_dev = adapter->ena_dev; 3175 bool readless_supported; 3176 uint32_t aenq_groups; 3177 int dma_width; 3178 int rc; 3179 3180 rc = ena_com_mmio_reg_read_request_init(ena_dev); 3181 if (unlikely(rc != 0)) { 3182 device_printf(pdev, "failed to init mmio read less\n"); 3183 return (rc); 3184 } 3185 3186 /* 3187 * The PCIe configuration space revision id indicate if mmio reg 3188 * read is disabled 3189 */ 3190 const int rev = PCI_REVISION(adapter->sc_pa.pa_class); 3191 readless_supported = ((rev & ENA_MMIO_DISABLE_REG_READ) == 0); 3192 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 3193 3194 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 3195 if (unlikely(rc != 0)) { 3196 device_printf(pdev, "Can not reset device\n"); 3197 goto err_mmio_read_less; 3198 } 3199 3200 rc = ena_com_validate_version(ena_dev); 3201 if (unlikely(rc != 0)) { 3202 device_printf(pdev, "device version is too low\n"); 3203 goto err_mmio_read_less; 3204 } 3205 3206 dma_width = ena_com_get_dma_width(ena_dev); 3207 if (unlikely(dma_width < 0)) { 3208 device_printf(pdev, "Invalid dma width value %d", dma_width); 3209 rc = dma_width; 3210 goto err_mmio_read_less; 3211 } 3212 adapter->dma_width = dma_width; 3213 3214 /* ENA admin level init */ 3215 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 3216 if (unlikely(rc != 0)) { 3217 device_printf(pdev, 3218 "Can not initialize ena admin queue with device\n"); 3219 goto err_mmio_read_less; 3220 } 3221 3222 /* 3223 * To enable the msix interrupts the driver needs to know the number 3224 * of queues. So the driver uses polling mode to retrieve this 3225 * information 3226 */ 3227 ena_com_set_admin_polling_mode(ena_dev, true); 3228 3229 ena_config_host_info(ena_dev); 3230 3231 /* Get Device Attributes */ 3232 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 3233 if (unlikely(rc != 0)) { 3234 device_printf(pdev, 3235 "Cannot get attribute for ena device rc: %d\n", rc); 3236 goto err_admin_init; 3237 } 3238 3239 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT(ENA_ADMIN_KEEP_ALIVE); 3240 3241 aenq_groups &= get_feat_ctx->aenq.supported_groups; 3242 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 3243 if (unlikely(rc != 0)) { 3244 device_printf(pdev, "Cannot configure aenq groups rc: %d\n", rc); 3245 goto err_admin_init; 3246 } 3247 3248 *wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 3249 3250 return (0); 3251 3252 err_admin_init: 3253 ena_com_delete_host_info(ena_dev); 3254 ena_com_admin_destroy(ena_dev); 3255 err_mmio_read_less: 3256 ena_com_mmio_reg_read_request_destroy(ena_dev); 3257 3258 return (rc); 3259 } 3260 3261 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 3262 int io_vectors) 3263 { 3264 struct ena_com_dev *ena_dev = adapter->ena_dev; 3265 int rc; 3266 3267 rc = ena_enable_msix(adapter); 3268 if (unlikely(rc != 0)) { 3269 device_printf(adapter->pdev, "Error with MSI-X enablement\n"); 3270 return (rc); 3271 } 3272 3273 rc = ena_request_mgmnt_irq(adapter); 3274 if (unlikely(rc != 0)) { 3275 device_printf(adapter->pdev, "Cannot setup mgmnt queue intr\n"); 3276 goto err_disable_msix; 3277 } 3278 3279 ena_com_set_admin_polling_mode(ena_dev, false); 3280 3281 ena_com_admin_aenq_enable(ena_dev); 3282 3283 return (0); 3284 3285 err_disable_msix: 3286 ena_disable_msix(adapter); 3287 3288 return (rc); 3289 } 3290 3291 /* Function called on ENA_ADMIN_KEEP_ALIVE event */ 3292 static void ena_keep_alive_wd(void *adapter_data, 3293 struct ena_admin_aenq_entry *aenq_e) 3294 { 3295 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3296 struct ena_admin_aenq_keep_alive_desc *desc; 3297 sbintime_t stime; 3298 uint64_t rx_drops; 3299 3300 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3301 3302 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3303 counter_u64_zero(adapter->hw_stats.rx_drops); 3304 counter_u64_add(adapter->hw_stats.rx_drops, rx_drops); 3305 3306 stime = getsbinuptime(); 3307 (void) atomic_swap_64(&adapter->keep_alive_timestamp, stime); 3308 } 3309 3310 /* Check for keep alive expiration */ 3311 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 3312 { 3313 sbintime_t timestamp, time; 3314 3315 if (adapter->wd_active == 0) 3316 return; 3317 3318 if (likely(adapter->keep_alive_timeout == 0)) 3319 return; 3320 3321 /* FreeBSD uses atomic_load_acq_64() in place of the membar + read */ 3322 membar_sync(); 3323 timestamp = adapter->keep_alive_timestamp; 3324 3325 time = getsbinuptime() - timestamp; 3326 if (unlikely(time > adapter->keep_alive_timeout)) { 3327 device_printf(adapter->pdev, 3328 "Keep alive watchdog timeout.\n"); 3329 counter_u64_add(adapter->dev_stats.wd_expired, 1); 3330 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 3331 adapter->trigger_reset = true; 3332 } 3333 } 3334 3335 /* Check if admin queue is enabled */ 3336 static void check_for_admin_com_state(struct ena_adapter *adapter) 3337 { 3338 if (unlikely(ena_com_get_admin_running_state(adapter->ena_dev) == 3339 false)) { 3340 device_printf(adapter->pdev, 3341 "ENA admin queue is not in running state!\n"); 3342 counter_u64_add(adapter->dev_stats.admin_q_pause, 1); 3343 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 3344 adapter->trigger_reset = true; 3345 } 3346 } 3347 3348 static int 3349 check_missing_comp_in_queue(struct ena_adapter *adapter, 3350 struct ena_ring *tx_ring) 3351 { 3352 struct bintime curtime, time; 3353 struct ena_tx_buffer *tx_buf; 3354 uint32_t missed_tx = 0; 3355 int i; 3356 3357 getbinuptime(&curtime); 3358 3359 for (i = 0; i < tx_ring->ring_size; i++) { 3360 tx_buf = &tx_ring->tx_buffer_info[i]; 3361 3362 if (bintime_isset(&tx_buf->timestamp) == 0) 3363 continue; 3364 3365 time = curtime; 3366 bintime_sub(&time, &tx_buf->timestamp); 3367 3368 /* Check again if packet is still waiting */ 3369 if (unlikely(bttosbt(time) > adapter->missing_tx_timeout)) { 3370 3371 if (!tx_buf->print_once) 3372 ena_trace(ENA_WARNING, "Found a Tx that wasn't " 3373 "completed on time, qid %d, index %d.\n", 3374 tx_ring->qid, i); 3375 3376 tx_buf->print_once = true; 3377 missed_tx++; 3378 counter_u64_add(tx_ring->tx_stats.missing_tx_comp, 1); 3379 3380 if (unlikely(missed_tx > 3381 adapter->missing_tx_threshold)) { 3382 device_printf(adapter->pdev, 3383 "The number of lost tx completion " 3384 "is above the threshold (%d > %d). " 3385 "Reset the device\n", 3386 missed_tx, adapter->missing_tx_threshold); 3387 adapter->reset_reason = 3388 ENA_REGS_RESET_MISS_TX_CMPL; 3389 adapter->trigger_reset = true; 3390 return (EIO); 3391 } 3392 } 3393 } 3394 3395 return (0); 3396 } 3397 3398 /* 3399 * Check for TX which were not completed on time. 3400 * Timeout is defined by "missing_tx_timeout". 3401 * Reset will be performed if number of incompleted 3402 * transactions exceeds "missing_tx_threshold". 3403 */ 3404 static void 3405 check_for_missing_tx_completions(struct ena_adapter *adapter) 3406 { 3407 struct ena_ring *tx_ring; 3408 int i, budget, rc; 3409 3410 /* Make sure the driver doesn't turn the device in other process */ 3411 rmb(); 3412 3413 if (!adapter->up) 3414 return; 3415 3416 if (adapter->trigger_reset) 3417 return; 3418 3419 if (adapter->missing_tx_timeout == 0) 3420 return; 3421 3422 budget = adapter->missing_tx_max_queues; 3423 3424 for (i = adapter->next_monitored_tx_qid; i < adapter->num_queues; i++) { 3425 tx_ring = &adapter->tx_ring[i]; 3426 3427 rc = check_missing_comp_in_queue(adapter, tx_ring); 3428 if (unlikely(rc != 0)) 3429 return; 3430 3431 budget--; 3432 if (budget == 0) { 3433 i++; 3434 break; 3435 } 3436 } 3437 3438 adapter->next_monitored_tx_qid = i % adapter->num_queues; 3439 } 3440 3441 /* trigger deferred rx cleanup after 2 consecutive detections */ 3442 #define EMPTY_RX_REFILL 2 3443 /* For the rare case where the device runs out of Rx descriptors and the 3444 * msix handler failed to refill new Rx descriptors (due to a lack of memory 3445 * for example). 3446 * This case will lead to a deadlock: 3447 * The device won't send interrupts since all the new Rx packets will be dropped 3448 * The msix handler won't allocate new Rx descriptors so the device won't be 3449 * able to send new packets. 3450 * 3451 * When such a situation is detected - execute rx cleanup task in another thread 3452 */ 3453 static void 3454 check_for_empty_rx_ring(struct ena_adapter *adapter) 3455 { 3456 struct ena_ring *rx_ring; 3457 int i, refill_required; 3458 3459 if (!adapter->up) 3460 return; 3461 3462 if (adapter->trigger_reset) 3463 return; 3464 3465 for (i = 0; i < adapter->num_queues; i++) { 3466 rx_ring = &adapter->rx_ring[i]; 3467 3468 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 3469 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 3470 rx_ring->empty_rx_queue++; 3471 3472 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 3473 counter_u64_add(rx_ring->rx_stats.empty_rx_ring, 3474 1); 3475 3476 device_printf(adapter->pdev, 3477 "trigger refill for ring %d\n", i); 3478 3479 workqueue_enqueue(rx_ring->cmpl_tq, 3480 &rx_ring->cmpl_task, curcpu()); 3481 rx_ring->empty_rx_queue = 0; 3482 } 3483 } else { 3484 rx_ring->empty_rx_queue = 0; 3485 } 3486 } 3487 } 3488 3489 static void 3490 ena_timer_service(void *data) 3491 { 3492 struct ena_adapter *adapter = (struct ena_adapter *)data; 3493 struct ena_admin_host_info *host_info = 3494 adapter->ena_dev->host_attr.host_info; 3495 3496 check_for_missing_keep_alive(adapter); 3497 3498 check_for_admin_com_state(adapter); 3499 3500 check_for_missing_tx_completions(adapter); 3501 3502 check_for_empty_rx_ring(adapter); 3503 3504 if (host_info != NULL) 3505 ena_update_host_info(host_info, adapter->ifp); 3506 3507 if (unlikely(adapter->trigger_reset)) { 3508 device_printf(adapter->pdev, "Trigger reset is on\n"); 3509 workqueue_enqueue(adapter->reset_tq, &adapter->reset_task, 3510 curcpu()); 3511 return; 3512 } 3513 3514 /* 3515 * Schedule another timeout one second from now. 3516 */ 3517 callout_schedule(&adapter->timer_service, hz); 3518 } 3519 3520 static void 3521 ena_reset_task(struct work *wk, void *arg) 3522 { 3523 struct ena_com_dev_get_features_ctx get_feat_ctx; 3524 struct ena_adapter *adapter = (struct ena_adapter *)arg; 3525 struct ena_com_dev *ena_dev = adapter->ena_dev; 3526 bool dev_up; 3527 int rc; 3528 3529 if (unlikely(!adapter->trigger_reset)) { 3530 device_printf(adapter->pdev, 3531 "device reset scheduled but trigger_reset is off\n"); 3532 return; 3533 } 3534 3535 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3536 3537 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3538 3539 dev_up = adapter->up; 3540 3541 ena_com_set_admin_running_state(ena_dev, false); 3542 ena_down(adapter); 3543 ena_free_mgmnt_irq(adapter); 3544 ena_disable_msix(adapter); 3545 ena_com_abort_admin_commands(ena_dev); 3546 ena_com_wait_for_abort_completion(ena_dev); 3547 ena_com_admin_destroy(ena_dev); 3548 ena_com_mmio_reg_read_request_destroy(ena_dev); 3549 3550 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3551 adapter->trigger_reset = false; 3552 3553 /* Finished destroy part. Restart the device */ 3554 rc = ena_device_init(adapter, adapter->pdev, &get_feat_ctx, 3555 &adapter->wd_active); 3556 if (unlikely(rc != 0)) { 3557 device_printf(adapter->pdev, 3558 "ENA device init failed! (err: %d)\n", rc); 3559 goto err_dev_free; 3560 } 3561 3562 /* XXX dealloc and realloc MSI-X, probably a waste */ 3563 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 3564 adapter->num_queues); 3565 if (unlikely(rc != 0)) { 3566 device_printf(adapter->pdev, "Enable MSI-X failed\n"); 3567 goto err_com_free; 3568 } 3569 3570 /* If the interface was up before the reset bring it up */ 3571 if (dev_up) { 3572 rc = ena_up(adapter); 3573 if (unlikely(rc != 0)) { 3574 device_printf(adapter->pdev, 3575 "Failed to create I/O queues\n"); 3576 goto err_msix_free; 3577 } 3578 } 3579 3580 callout_reset(&adapter->timer_service, hz, 3581 ena_timer_service, (void *)adapter); 3582 3583 rw_exit(&adapter->ioctl_sx); 3584 3585 return; 3586 3587 err_msix_free: 3588 ena_free_mgmnt_irq(adapter); 3589 ena_disable_msix(adapter); 3590 err_com_free: 3591 ena_com_admin_destroy(ena_dev); 3592 err_dev_free: 3593 device_printf(adapter->pdev, "ENA reset failed!\n"); 3594 adapter->running = false; 3595 rw_exit(&adapter->ioctl_sx); 3596 } 3597 3598 /** 3599 * ena_attach - Device Initialization Routine 3600 * @pdev: device information struct 3601 * 3602 * Returns 0 on success, otherwise on failure. 3603 * 3604 * ena_attach initializes an adapter identified by a device structure. 3605 * The OS initialization, configuring of the adapter private structure, 3606 * and a hardware reset occur. 3607 **/ 3608 static void 3609 ena_attach(device_t parent, device_t self, void *aux) 3610 { 3611 struct pci_attach_args *pa = aux; 3612 struct ena_com_dev_get_features_ctx get_feat_ctx; 3613 static int version_printed; 3614 struct ena_adapter *adapter = device_private(parent); 3615 struct ena_com_dev *ena_dev = NULL; 3616 uint16_t tx_sgl_size = 0; 3617 uint16_t rx_sgl_size = 0; 3618 pcireg_t reg; 3619 int io_queue_num; 3620 int queue_size; 3621 int rc; 3622 3623 adapter->pdev = self; 3624 adapter->ifp = &adapter->sc_ec.ec_if; 3625 adapter->sc_pa = *pa; /* used after attach for adapter reset too */ 3626 3627 if (pci_dma64_available(pa)) 3628 adapter->sc_dmat = pa->pa_dmat64; 3629 else 3630 adapter->sc_dmat = pa->pa_dmat; 3631 3632 pci_aprint_devinfo(pa, NULL); 3633 3634 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3635 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) { 3636 reg |= PCI_COMMAND_MASTER_ENABLE; 3637 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 3638 } 3639 3640 mutex_init(&adapter->global_mtx, MUTEX_DEFAULT, IPL_NET); 3641 rw_init(&adapter->ioctl_sx); 3642 3643 /* Set up the timer service */ 3644 adapter->keep_alive_timeout = DEFAULT_KEEP_ALIVE_TO; 3645 adapter->missing_tx_timeout = DEFAULT_TX_CMP_TO; 3646 adapter->missing_tx_max_queues = DEFAULT_TX_MONITORED_QUEUES; 3647 adapter->missing_tx_threshold = DEFAULT_TX_CMP_THRESHOLD; 3648 3649 if (version_printed++ == 0) 3650 device_printf(parent, "%s\n", ena_version); 3651 3652 rc = ena_allocate_pci_resources(pa, adapter); 3653 if (unlikely(rc != 0)) { 3654 device_printf(parent, "PCI resource allocation failed!\n"); 3655 ena_free_pci_resources(adapter); 3656 return; 3657 } 3658 3659 /* Allocate memory for ena_dev structure */ 3660 ena_dev = malloc(sizeof(struct ena_com_dev), M_DEVBUF, 3661 M_WAITOK | M_ZERO); 3662 3663 adapter->ena_dev = ena_dev; 3664 ena_dev->dmadev = self; 3665 ena_dev->bus = malloc(sizeof(struct ena_bus), M_DEVBUF, 3666 M_WAITOK | M_ZERO); 3667 3668 /* Store register resources */ 3669 ((struct ena_bus*)(ena_dev->bus))->reg_bar_t = adapter->sc_btag; 3670 ((struct ena_bus*)(ena_dev->bus))->reg_bar_h = adapter->sc_bhandle; 3671 3672 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3673 3674 /* Device initialization */ 3675 rc = ena_device_init(adapter, self, &get_feat_ctx, &adapter->wd_active); 3676 if (unlikely(rc != 0)) { 3677 device_printf(self, "ENA device init failed! (err: %d)\n", rc); 3678 rc = ENXIO; 3679 goto err_bus_free; 3680 } 3681 3682 adapter->keep_alive_timestamp = getsbinuptime(); 3683 3684 adapter->tx_offload_cap = get_feat_ctx.offload.tx; 3685 3686 /* Set for sure that interface is not up */ 3687 adapter->up = false; 3688 3689 memcpy(adapter->mac_addr, get_feat_ctx.dev_attr.mac_addr, 3690 ETHER_ADDR_LEN); 3691 3692 /* calculate IO queue number to create */ 3693 io_queue_num = ena_calc_io_queue_num(pa, adapter, &get_feat_ctx); 3694 3695 ENA_ASSERT(io_queue_num > 0, "Invalid queue number: %d\n", 3696 io_queue_num); 3697 adapter->num_queues = io_queue_num; 3698 3699 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 3700 3701 /* calculatre ring sizes */ 3702 queue_size = ena_calc_queue_size(adapter,&tx_sgl_size, 3703 &rx_sgl_size, &get_feat_ctx); 3704 if (unlikely((queue_size <= 0) || (io_queue_num <= 0))) { 3705 rc = ENA_COM_FAULT; 3706 goto err_com_free; 3707 } 3708 3709 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3710 3711 adapter->tx_ring_size = queue_size; 3712 adapter->rx_ring_size = queue_size; 3713 3714 adapter->max_tx_sgl_size = tx_sgl_size; 3715 adapter->max_rx_sgl_size = rx_sgl_size; 3716 3717 #if 0 3718 /* set up dma tags for rx and tx buffers */ 3719 rc = ena_setup_tx_dma_tag(adapter); 3720 if (unlikely(rc != 0)) { 3721 device_printf(self, "Failed to create TX DMA tag\n"); 3722 goto err_com_free; 3723 } 3724 3725 rc = ena_setup_rx_dma_tag(adapter); 3726 if (unlikely(rc != 0)) { 3727 device_printf(self, "Failed to create RX DMA tag\n"); 3728 goto err_tx_tag_free; 3729 } 3730 #endif 3731 3732 /* initialize rings basic information */ 3733 device_printf(self, "initalize %d io queues\n", io_queue_num); 3734 ena_init_io_rings(adapter); 3735 3736 /* setup network interface */ 3737 rc = ena_setup_ifnet(self, adapter, &get_feat_ctx); 3738 if (unlikely(rc != 0)) { 3739 device_printf(self, "Error with network interface setup\n"); 3740 goto err_io_free; 3741 } 3742 3743 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3744 if (unlikely(rc != 0)) { 3745 device_printf(self, 3746 "Failed to enable and set the admin interrupts\n"); 3747 goto err_ifp_free; 3748 } 3749 3750 /* Initialize reset task queue */ 3751 rc = workqueue_create(&adapter->reset_tq, "ena_reset_enqueue", 3752 ena_reset_task, adapter, 0, IPL_NET, 0); 3753 if (unlikely(rc != 0)) { 3754 ena_trace(ENA_ALERT, 3755 "Unable to create workqueue for reset task\n"); 3756 goto err_ifp_free; 3757 } 3758 3759 /* Initialize statistics */ 3760 ena_alloc_counters_dev(&adapter->dev_stats, io_queue_num); 3761 ena_alloc_counters_hwstats(&adapter->hw_stats, io_queue_num); 3762 #if 0 3763 ena_sysctl_add_nodes(adapter); 3764 #endif 3765 3766 /* Tell the stack that the interface is not active */ 3767 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, IFF_RUNNING); 3768 3769 adapter->running = true; 3770 return; 3771 3772 err_ifp_free: 3773 if_detach(adapter->ifp); 3774 if_free(adapter->ifp); 3775 err_io_free: 3776 ena_free_all_io_rings_resources(adapter); 3777 #if 0 3778 ena_free_rx_dma_tag(adapter); 3779 err_tx_tag_free: 3780 ena_free_tx_dma_tag(adapter); 3781 #endif 3782 err_com_free: 3783 ena_com_admin_destroy(ena_dev); 3784 ena_com_delete_host_info(ena_dev); 3785 ena_com_mmio_reg_read_request_destroy(ena_dev); 3786 err_bus_free: 3787 free(ena_dev->bus, M_DEVBUF); 3788 free(ena_dev, M_DEVBUF); 3789 ena_free_pci_resources(adapter); 3790 } 3791 3792 /** 3793 * ena_detach - Device Removal Routine 3794 * @pdev: device information struct 3795 * 3796 * ena_detach is called by the device subsystem to alert the driver 3797 * that it should release a PCI device. 3798 **/ 3799 static int 3800 ena_detach(device_t pdev, int flags) 3801 { 3802 struct ena_adapter *adapter = device_private(pdev); 3803 struct ena_com_dev *ena_dev = adapter->ena_dev; 3804 #if 0 3805 int rc; 3806 #endif 3807 3808 /* Make sure VLANS are not using driver */ 3809 if (VLAN_ATTACHED(&adapter->sc_ec)) { 3810 device_printf(adapter->pdev ,"VLAN is in use, detach first\n"); 3811 return (EBUSY); 3812 } 3813 3814 /* Free reset task and callout */ 3815 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3816 workqueue_wait(adapter->reset_tq, &adapter->reset_task); 3817 workqueue_destroy(adapter->reset_tq); 3818 adapter->reset_tq = NULL; 3819 3820 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3821 ena_down(adapter); 3822 rw_exit(&adapter->ioctl_sx); 3823 3824 if (adapter->ifp != NULL) { 3825 ether_ifdetach(adapter->ifp); 3826 if_free(adapter->ifp); 3827 } 3828 3829 ena_free_all_io_rings_resources(adapter); 3830 3831 ena_free_counters((struct evcnt *)&adapter->hw_stats, 3832 sizeof(struct ena_hw_stats)); 3833 ena_free_counters((struct evcnt *)&adapter->dev_stats, 3834 sizeof(struct ena_stats_dev)); 3835 3836 if (likely(adapter->rss_support)) 3837 ena_com_rss_destroy(ena_dev); 3838 3839 #if 0 3840 rc = ena_free_rx_dma_tag(adapter); 3841 if (unlikely(rc != 0)) 3842 device_printf(adapter->pdev, 3843 "Unmapped RX DMA tag associations\n"); 3844 3845 rc = ena_free_tx_dma_tag(adapter); 3846 if (unlikely(rc != 0)) 3847 device_printf(adapter->pdev, 3848 "Unmapped TX DMA tag associations\n"); 3849 #endif 3850 3851 /* Reset the device only if the device is running. */ 3852 if (adapter->running) 3853 ena_com_dev_reset(ena_dev, adapter->reset_reason); 3854 3855 ena_com_delete_host_info(ena_dev); 3856 3857 ena_free_irqs(adapter); 3858 3859 ena_com_abort_admin_commands(ena_dev); 3860 3861 ena_com_wait_for_abort_completion(ena_dev); 3862 3863 ena_com_admin_destroy(ena_dev); 3864 3865 ena_com_mmio_reg_read_request_destroy(ena_dev); 3866 3867 ena_free_pci_resources(adapter); 3868 3869 mutex_destroy(&adapter->global_mtx); 3870 rw_destroy(&adapter->ioctl_sx); 3871 3872 if (ena_dev->bus != NULL) 3873 free(ena_dev->bus, M_DEVBUF); 3874 3875 if (ena_dev != NULL) 3876 free(ena_dev, M_DEVBUF); 3877 3878 return 0; 3879 } 3880 3881 /****************************************************************************** 3882 ******************************** AENQ Handlers ******************************* 3883 *****************************************************************************/ 3884 /** 3885 * ena_update_on_link_change: 3886 * Notify the network interface about the change in link status 3887 **/ 3888 static void 3889 ena_update_on_link_change(void *adapter_data, 3890 struct ena_admin_aenq_entry *aenq_e) 3891 { 3892 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3893 struct ena_admin_aenq_link_change_desc *aenq_desc; 3894 int status; 3895 struct ifnet *ifp; 3896 3897 aenq_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3898 ifp = adapter->ifp; 3899 status = aenq_desc->flags & 3900 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3901 3902 if (status != 0) { 3903 device_printf(adapter->pdev, "link is UP\n"); 3904 if_link_state_change(ifp, LINK_STATE_UP); 3905 } else if (status == 0) { 3906 device_printf(adapter->pdev, "link is DOWN\n"); 3907 if_link_state_change(ifp, LINK_STATE_DOWN); 3908 } else { 3909 device_printf(adapter->pdev, "invalid value recvd\n"); 3910 BUG(); 3911 } 3912 3913 adapter->link_status = status; 3914 } 3915 3916 /** 3917 * This handler will called for unknown event group or unimplemented handlers 3918 **/ 3919 static void 3920 unimplemented_aenq_handler(void *data, 3921 struct ena_admin_aenq_entry *aenq_e) 3922 { 3923 return; 3924 } 3925 3926 static struct ena_aenq_handlers aenq_handlers = { 3927 .handlers = { 3928 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3929 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 3930 }, 3931 .unimplemented_handler = unimplemented_aenq_handler 3932 }; 3933 3934 #ifdef __FreeBSD__ 3935 /********************************************************************* 3936 * FreeBSD Device Interface Entry Points 3937 *********************************************************************/ 3938 3939 static device_method_t ena_methods[] = { 3940 /* Device interface */ 3941 DEVMETHOD(device_probe, ena_probe), 3942 DEVMETHOD(device_attach, ena_attach), 3943 DEVMETHOD(device_detach, ena_detach), 3944 DEVMETHOD_END 3945 }; 3946 3947 static driver_t ena_driver = { 3948 "ena", ena_methods, sizeof(struct ena_adapter), 3949 }; 3950 3951 devclass_t ena_devclass; 3952 DRIVER_MODULE(ena, pci, ena_driver, ena_devclass, 0, 0); 3953 MODULE_DEPEND(ena, pci, 1, 1, 1); 3954 MODULE_DEPEND(ena, ether, 1, 1, 1); 3955 3956 /*********************************************************************/ 3957 #endif /* __FreeBSD__ */ 3958 3959 #ifdef __NetBSD__ 3960 CFATTACH_DECL_NEW(ena, sizeof(struct ena_adapter), ena_probe, ena_attach, 3961 ena_detach, NULL); 3962 #endif /* __NetBSD */ 3963