1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifdef _KERNEL_OPT 32 #include "opt_net_mpsafe.h" 33 #endif 34 35 #include <sys/cdefs.h> 36 #if 0 37 __FBSDID("$FreeBSD: head/sys/dev/ena/ena.c 333456 2018-05-10 09:37:54Z mw $"); 38 #endif 39 __KERNEL_RCSID(0, "$NetBSD: if_ena.c,v 1.27 2021/01/23 11:50:30 jmcneill Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/kthread.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/time.h> 54 #include <sys/workqueue.h> 55 #include <sys/callout.h> 56 #include <sys/interrupt.h> 57 #include <sys/cpu.h> 58 59 #include <net/if_ether.h> 60 #include <net/if_vlanvar.h> 61 62 #include <dev/pci/if_enavar.h> 63 64 #ifdef NET_MPSAFE 65 #define WQ_FLAGS WQ_MPSAFE 66 #define CALLOUT_FLAGS CALLOUT_MPSAFE 67 #else 68 #define WQ_FLAGS 0 69 #define CALLOUT_FLAGS 0 70 #endif 71 72 /********************************************************* 73 * Function prototypes 74 *********************************************************/ 75 static int ena_probe(device_t, cfdata_t, void *); 76 static int ena_intr_msix_mgmnt(void *); 77 static int ena_allocate_pci_resources(struct pci_attach_args *, 78 struct ena_adapter *); 79 static void ena_free_pci_resources(struct ena_adapter *); 80 static int ena_change_mtu(struct ifnet *, int); 81 static void ena_init_io_rings_common(struct ena_adapter *, 82 struct ena_ring *, uint16_t); 83 static void ena_init_io_rings(struct ena_adapter *); 84 static void ena_free_io_ring_resources(struct ena_adapter *, unsigned int); 85 static void ena_free_all_io_rings_resources(struct ena_adapter *); 86 #if 0 87 static int ena_setup_tx_dma_tag(struct ena_adapter *); 88 static int ena_free_tx_dma_tag(struct ena_adapter *); 89 static int ena_setup_rx_dma_tag(struct ena_adapter *); 90 static int ena_free_rx_dma_tag(struct ena_adapter *); 91 #endif 92 static int ena_setup_tx_resources(struct ena_adapter *, int); 93 static void ena_free_tx_resources(struct ena_adapter *, int); 94 static int ena_setup_all_tx_resources(struct ena_adapter *); 95 static void ena_free_all_tx_resources(struct ena_adapter *); 96 static inline int validate_rx_req_id(struct ena_ring *, uint16_t); 97 static int ena_setup_rx_resources(struct ena_adapter *, unsigned int); 98 static void ena_free_rx_resources(struct ena_adapter *, unsigned int); 99 static int ena_setup_all_rx_resources(struct ena_adapter *); 100 static void ena_free_all_rx_resources(struct ena_adapter *); 101 static inline int ena_alloc_rx_mbuf(struct ena_adapter *, struct ena_ring *, 102 struct ena_rx_buffer *); 103 static void ena_free_rx_mbuf(struct ena_adapter *, struct ena_ring *, 104 struct ena_rx_buffer *); 105 static int ena_refill_rx_bufs(struct ena_ring *, uint32_t); 106 static void ena_free_rx_bufs(struct ena_adapter *, unsigned int); 107 static void ena_refill_all_rx_bufs(struct ena_adapter *); 108 static void ena_free_all_rx_bufs(struct ena_adapter *); 109 static void ena_free_tx_bufs(struct ena_adapter *, unsigned int); 110 static void ena_free_all_tx_bufs(struct ena_adapter *); 111 static void ena_destroy_all_tx_queues(struct ena_adapter *); 112 static void ena_destroy_all_rx_queues(struct ena_adapter *); 113 static void ena_destroy_all_io_queues(struct ena_adapter *); 114 static int ena_create_io_queues(struct ena_adapter *); 115 static int ena_tx_cleanup(struct ena_ring *); 116 static void ena_deferred_rx_cleanup(struct work *, void *); 117 static int ena_rx_cleanup(struct ena_ring *); 118 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 119 #if 0 120 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 121 struct mbuf *); 122 #endif 123 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 124 struct ena_com_rx_ctx *, uint16_t *); 125 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 126 struct mbuf *); 127 static int ena_handle_msix(void *); 128 static int ena_enable_msix(struct ena_adapter *); 129 static int ena_request_mgmnt_irq(struct ena_adapter *); 130 static int ena_request_io_irq(struct ena_adapter *); 131 static void ena_free_mgmnt_irq(struct ena_adapter *); 132 static void ena_free_io_irq(struct ena_adapter *); 133 static void ena_free_irqs(struct ena_adapter*); 134 static void ena_disable_msix(struct ena_adapter *); 135 static void ena_unmask_all_io_irqs(struct ena_adapter *); 136 static int ena_rss_configure(struct ena_adapter *); 137 static int ena_up_complete(struct ena_adapter *); 138 static int ena_up(struct ena_adapter *); 139 static void ena_down(struct ena_adapter *); 140 #if 0 141 static uint64_t ena_get_counter(struct ifnet *, ift_counter); 142 #endif 143 static int ena_media_change(struct ifnet *); 144 static void ena_media_status(struct ifnet *, struct ifmediareq *); 145 static int ena_init(struct ifnet *); 146 static int ena_ioctl(struct ifnet *, u_long, void *); 147 static int ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *); 148 static void ena_update_host_info(struct ena_admin_host_info *, struct ifnet *); 149 static void ena_update_hwassist(struct ena_adapter *); 150 static int ena_setup_ifnet(device_t, struct ena_adapter *, 151 struct ena_com_dev_get_features_ctx *); 152 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *); 153 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 154 struct mbuf **mbuf); 155 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 156 static void ena_start_xmit(struct ena_ring *); 157 static int ena_mq_start(struct ifnet *, struct mbuf *); 158 static void ena_deferred_mq_start(struct work *, void *); 159 #if 0 160 static void ena_qflush(struct ifnet *); 161 #endif 162 static int ena_calc_io_queue_num(struct pci_attach_args *, 163 struct ena_adapter *, struct ena_com_dev_get_features_ctx *); 164 static int ena_calc_queue_size(struct ena_adapter *, uint16_t *, 165 uint16_t *, struct ena_com_dev_get_features_ctx *); 166 #if 0 167 static int ena_rss_init_default(struct ena_adapter *); 168 static void ena_rss_init_default_deferred(void *); 169 #endif 170 static void ena_config_host_info(struct ena_com_dev *); 171 static void ena_attach(device_t, device_t, void *); 172 static int ena_detach(device_t, int); 173 static int ena_device_init(struct ena_adapter *, device_t, 174 struct ena_com_dev_get_features_ctx *, int *); 175 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *, 176 int); 177 static void ena_update_on_link_change(void *, struct ena_admin_aenq_entry *); 178 static void unimplemented_aenq_handler(void *, 179 struct ena_admin_aenq_entry *); 180 static void ena_timer_service(void *); 181 182 static const char ena_version[] = 183 DEVICE_NAME DRV_MODULE_NAME " v" DRV_MODULE_VERSION; 184 185 #if 0 186 static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD, 0, "ENA driver parameters"); 187 #endif 188 189 /* 190 * Tuneable number of buffers in the buf-ring (drbr) 191 */ 192 static int ena_buf_ring_size = 4096; 193 #if 0 194 SYSCTL_INT(_hw_ena, OID_AUTO, buf_ring_size, CTLFLAG_RWTUN, 195 &ena_buf_ring_size, 0, "Size of the bufring"); 196 #endif 197 198 /* 199 * Logging level for changing verbosity of the output 200 */ 201 int ena_log_level = ENA_ALERT | ENA_WARNING; 202 #if 0 203 SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, 204 &ena_log_level, 0, "Logging level indicating verbosity of the logs"); 205 #endif 206 207 static const ena_vendor_info_t ena_vendor_info_array[] = { 208 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_PF, 0}, 209 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_PF, 0}, 210 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_VF, 0}, 211 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_VF, 0}, 212 /* Last entry */ 213 { 0, 0, 0 } 214 }; 215 216 /* 217 * Contains pointers to event handlers, e.g. link state chage. 218 */ 219 static struct ena_aenq_handlers aenq_handlers; 220 221 int 222 ena_dma_alloc(device_t dmadev, bus_size_t size, 223 ena_mem_handle_t *dma , int mapflags) 224 { 225 struct ena_adapter *adapter = device_private(dmadev); 226 uint32_t maxsize; 227 bus_dma_segment_t seg; 228 int error, nsegs; 229 230 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; 231 232 #if 0 233 /* XXX what is this needed for ? */ 234 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); 235 if (unlikely(dma_space_addr == 0)) 236 dma_space_addr = BUS_SPACE_MAXADDR; 237 #endif 238 239 dma->tag = adapter->sc_dmat; 240 241 if ((error = bus_dmamap_create(dma->tag, maxsize, 1, maxsize, 0, 242 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->map)) != 0) { 243 ena_trace(ENA_ALERT, "bus_dmamap_create(%ju) failed: %d\n", 244 (uintmax_t)maxsize, error); 245 goto fail_create; 246 } 247 248 error = bus_dmamem_alloc(dma->tag, maxsize, 8, 0, &seg, 1, &nsegs, 249 BUS_DMA_ALLOCNOW); 250 if (error) { 251 ena_trace(ENA_ALERT, "bus_dmamem_alloc(%ju) failed: %d\n", 252 (uintmax_t)maxsize, error); 253 goto fail_alloc; 254 } 255 256 error = bus_dmamem_map(dma->tag, &seg, nsegs, maxsize, 257 &dma->vaddr, BUS_DMA_COHERENT); 258 if (error) { 259 ena_trace(ENA_ALERT, "bus_dmamem_map(%ju) failed: %d\n", 260 (uintmax_t)maxsize, error); 261 goto fail_map; 262 } 263 memset(dma->vaddr, 0, maxsize); 264 265 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 266 maxsize, NULL, mapflags); 267 if (error) { 268 ena_trace(ENA_ALERT, ": bus_dmamap_load failed: %d\n", error); 269 goto fail_load; 270 } 271 dma->paddr = dma->map->dm_segs[0].ds_addr; 272 273 return (0); 274 275 fail_load: 276 bus_dmamem_unmap(dma->tag, dma->vaddr, maxsize); 277 fail_map: 278 bus_dmamem_free(dma->tag, &seg, nsegs); 279 fail_alloc: 280 bus_dmamap_destroy(adapter->sc_dmat, dma->map); 281 fail_create: 282 return (error); 283 } 284 285 static int 286 ena_allocate_pci_resources(struct pci_attach_args *pa, 287 struct ena_adapter *adapter) 288 { 289 pcireg_t memtype, reg; 290 bus_addr_t memaddr; 291 bus_size_t mapsize; 292 int flags, error; 293 int msixoff; 294 295 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ENA_REG_BAR); 296 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 297 aprint_error_dev(adapter->pdev, "invalid type (type=0x%x)\n", 298 memtype); 299 return ENXIO; 300 } 301 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 302 if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) || 303 ((reg & PCI_COMMAND_MEM_ENABLE) == 0)) { 304 /* 305 * Enable address decoding for memory range in case BIOS or 306 * UEFI didn't set it. 307 */ 308 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 309 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 310 reg); 311 } 312 313 adapter->sc_btag = pa->pa_memt; 314 error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, ENA_REG_BAR, 315 memtype, &memaddr, &mapsize, &flags); 316 if (error) { 317 aprint_error_dev(adapter->pdev, "can't get map info\n"); 318 return ENXIO; 319 } 320 321 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 322 NULL)) { 323 pcireg_t msixtbl; 324 uint32_t table_offset; 325 int bir; 326 327 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 328 msixoff + PCI_MSIX_TBLOFFSET); 329 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 330 bir = msixtbl & PCI_MSIX_TBLBIR_MASK; 331 if (bir == PCI_MAPREG_NUM(ENA_REG_BAR)) 332 mapsize = table_offset; 333 } 334 335 error = bus_space_map(adapter->sc_btag, memaddr, mapsize, flags, 336 &adapter->sc_bhandle); 337 if (error != 0) { 338 aprint_error_dev(adapter->pdev, 339 "can't map mem space (error=%d)\n", error); 340 return ENXIO; 341 } 342 343 return (0); 344 } 345 346 static void 347 ena_free_pci_resources(struct ena_adapter *adapter) 348 { 349 /* Nothing to do */ 350 } 351 352 static int 353 ena_probe(device_t parent, cfdata_t match, void *aux) 354 { 355 struct pci_attach_args *pa = aux; 356 const ena_vendor_info_t *ent; 357 358 for (int i = 0; i < __arraycount(ena_vendor_info_array); i++) { 359 ent = &ena_vendor_info_array[i]; 360 361 if ((PCI_VENDOR(pa->pa_id) == ent->vendor_id) && 362 (PCI_PRODUCT(pa->pa_id) == ent->device_id)) { 363 return 1; 364 } 365 } 366 367 return 0; 368 } 369 370 static int 371 ena_change_mtu(struct ifnet *ifp, int new_mtu) 372 { 373 struct ena_adapter *adapter = if_getsoftc(ifp); 374 int rc; 375 376 if ((new_mtu > adapter->max_mtu) || (new_mtu < ENA_MIN_MTU)) { 377 device_printf(adapter->pdev, "Invalid MTU setting. " 378 "new_mtu: %d max mtu: %d min mtu: %d\n", 379 new_mtu, adapter->max_mtu, ENA_MIN_MTU); 380 return (EINVAL); 381 } 382 383 rc = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 384 if (likely(rc == 0)) { 385 ena_trace(ENA_DBG, "set MTU to %d\n", new_mtu); 386 if_setmtu(ifp, new_mtu); 387 } else { 388 device_printf(adapter->pdev, "Failed to set MTU to %d\n", 389 new_mtu); 390 } 391 392 return (rc); 393 } 394 395 #define EVCNT_INIT(st, f) \ 396 do { \ 397 evcnt_attach_dynamic(&st->f, EVCNT_TYPE_MISC, NULL, \ 398 st->name, #f); \ 399 } while (0) 400 401 static inline void 402 ena_alloc_counters_rx(struct ena_stats_rx *st, int queue) 403 { 404 snprintf(st->name, sizeof(st->name), "ena rxq%d", queue); 405 406 EVCNT_INIT(st, cnt); 407 EVCNT_INIT(st, bytes); 408 EVCNT_INIT(st, refil_partial); 409 EVCNT_INIT(st, bad_csum); 410 EVCNT_INIT(st, mjum_alloc_fail); 411 EVCNT_INIT(st, mbuf_alloc_fail); 412 EVCNT_INIT(st, dma_mapping_err); 413 EVCNT_INIT(st, bad_desc_num); 414 EVCNT_INIT(st, bad_req_id); 415 EVCNT_INIT(st, empty_rx_ring); 416 417 /* Make sure all code is updated when new fields added */ 418 CTASSERT(offsetof(struct ena_stats_rx, empty_rx_ring) 419 + sizeof(st->empty_rx_ring) == sizeof(*st)); 420 } 421 422 static inline void 423 ena_alloc_counters_tx(struct ena_stats_tx *st, int queue) 424 { 425 snprintf(st->name, sizeof(st->name), "ena txq%d", queue); 426 427 EVCNT_INIT(st, cnt); 428 EVCNT_INIT(st, bytes); 429 EVCNT_INIT(st, prepare_ctx_err); 430 EVCNT_INIT(st, dma_mapping_err); 431 EVCNT_INIT(st, doorbells); 432 EVCNT_INIT(st, missing_tx_comp); 433 EVCNT_INIT(st, bad_req_id); 434 EVCNT_INIT(st, collapse); 435 EVCNT_INIT(st, collapse_err); 436 437 /* Make sure all code is updated when new fields added */ 438 CTASSERT(offsetof(struct ena_stats_tx, collapse_err) 439 + sizeof(st->collapse_err) == sizeof(*st)); 440 } 441 442 static inline void 443 ena_alloc_counters_dev(struct ena_stats_dev *st, int queue) 444 { 445 snprintf(st->name, sizeof(st->name), "ena dev ioq%d", queue); 446 447 EVCNT_INIT(st, wd_expired); 448 EVCNT_INIT(st, interface_up); 449 EVCNT_INIT(st, interface_down); 450 EVCNT_INIT(st, admin_q_pause); 451 452 /* Make sure all code is updated when new fields added */ 453 CTASSERT(offsetof(struct ena_stats_dev, admin_q_pause) 454 + sizeof(st->admin_q_pause) == sizeof(*st)); 455 } 456 457 static inline void 458 ena_alloc_counters_hwstats(struct ena_hw_stats *st, int queue) 459 { 460 snprintf(st->name, sizeof(st->name), "ena hw ioq%d", queue); 461 462 EVCNT_INIT(st, rx_packets); 463 EVCNT_INIT(st, tx_packets); 464 EVCNT_INIT(st, rx_bytes); 465 EVCNT_INIT(st, tx_bytes); 466 EVCNT_INIT(st, rx_drops); 467 468 /* Make sure all code is updated when new fields added */ 469 CTASSERT(offsetof(struct ena_hw_stats, rx_drops) 470 + sizeof(st->rx_drops) == sizeof(*st)); 471 } 472 static inline void 473 ena_free_counters(struct evcnt *begin, int size, int offset) 474 { 475 struct evcnt *end = (struct evcnt *)((char *)begin + size); 476 begin = (struct evcnt *)((char *)begin + offset); 477 478 for (; begin < end; ++begin) 479 counter_u64_free(*begin); 480 } 481 482 static inline void 483 ena_reset_counters(struct evcnt *begin, int size, int offset) 484 { 485 struct evcnt *end = (struct evcnt *)((char *)begin + size); 486 begin = (struct evcnt *)((char *)begin + offset); 487 488 for (; begin < end; ++begin) 489 counter_u64_zero(*begin); 490 } 491 492 static void 493 ena_init_io_rings_common(struct ena_adapter *adapter, struct ena_ring *ring, 494 uint16_t qid) 495 { 496 497 ring->qid = qid; 498 ring->adapter = adapter; 499 ring->ena_dev = adapter->ena_dev; 500 } 501 502 static void 503 ena_init_io_rings(struct ena_adapter *adapter) 504 { 505 struct ena_com_dev *ena_dev; 506 struct ena_ring *txr, *rxr; 507 struct ena_que *que; 508 int i; 509 510 ena_dev = adapter->ena_dev; 511 512 for (i = 0; i < adapter->num_queues; i++) { 513 txr = &adapter->tx_ring[i]; 514 rxr = &adapter->rx_ring[i]; 515 516 /* TX/RX common ring state */ 517 ena_init_io_rings_common(adapter, txr, i); 518 ena_init_io_rings_common(adapter, rxr, i); 519 520 /* TX specific ring state */ 521 txr->ring_size = adapter->tx_ring_size; 522 txr->tx_max_header_size = ena_dev->tx_max_header_size; 523 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 524 txr->smoothed_interval = 525 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 526 527 /* Allocate a buf ring */ 528 txr->br = buf_ring_alloc(ena_buf_ring_size, M_DEVBUF, 529 M_WAITOK, &txr->ring_mtx); 530 531 /* Alloc TX statistics. */ 532 ena_alloc_counters_tx(&txr->tx_stats, i); 533 534 /* RX specific ring state */ 535 rxr->ring_size = adapter->rx_ring_size; 536 rxr->smoothed_interval = 537 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 538 539 /* Alloc RX statistics. */ 540 ena_alloc_counters_rx(&rxr->rx_stats, i); 541 542 /* Initialize locks */ 543 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 544 device_xname(adapter->pdev), i); 545 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 546 device_xname(adapter->pdev), i); 547 548 mutex_init(&txr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 549 mutex_init(&rxr->ring_mtx, MUTEX_DEFAULT, IPL_NET); 550 551 que = &adapter->que[i]; 552 que->adapter = adapter; 553 que->id = i; 554 que->tx_ring = txr; 555 que->rx_ring = rxr; 556 557 txr->que = que; 558 rxr->que = que; 559 560 rxr->empty_rx_queue = 0; 561 } 562 } 563 564 static void 565 ena_free_io_ring_resources(struct ena_adapter *adapter, unsigned int qid) 566 { 567 struct ena_ring *txr = &adapter->tx_ring[qid]; 568 struct ena_ring *rxr = &adapter->rx_ring[qid]; 569 570 ena_free_counters((struct evcnt *)&txr->tx_stats, 571 sizeof(txr->tx_stats), offsetof(struct ena_stats_tx, cnt)); 572 ena_free_counters((struct evcnt *)&rxr->rx_stats, 573 sizeof(rxr->rx_stats), offsetof(struct ena_stats_rx, cnt)); 574 575 ENA_RING_MTX_LOCK(txr); 576 drbr_free(txr->br, M_DEVBUF); 577 ENA_RING_MTX_UNLOCK(txr); 578 579 mutex_destroy(&txr->ring_mtx); 580 mutex_destroy(&rxr->ring_mtx); 581 } 582 583 static void 584 ena_free_all_io_rings_resources(struct ena_adapter *adapter) 585 { 586 int i; 587 588 for (i = 0; i < adapter->num_queues; i++) 589 ena_free_io_ring_resources(adapter, i); 590 591 } 592 593 #if 0 594 static int 595 ena_setup_tx_dma_tag(struct ena_adapter *adapter) 596 { 597 int ret; 598 599 /* Create DMA tag for Tx buffers */ 600 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), 601 1, 0, /* alignment, bounds */ 602 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 603 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 604 NULL, NULL, /* filter, filterarg */ 605 ENA_TSO_MAXSIZE, /* maxsize */ 606 adapter->max_tx_sgl_size - 1, /* nsegments */ 607 ENA_TSO_MAXSIZE, /* maxsegsize */ 608 0, /* flags */ 609 NULL, /* lockfunc */ 610 NULL, /* lockfuncarg */ 611 &adapter->tx_buf_tag); 612 613 return (ret); 614 } 615 #endif 616 617 #if 0 618 static int 619 ena_setup_rx_dma_tag(struct ena_adapter *adapter) 620 { 621 int ret; 622 623 /* Create DMA tag for Rx buffers*/ 624 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */ 625 1, 0, /* alignment, bounds */ 626 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 627 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 628 NULL, NULL, /* filter, filterarg */ 629 MJUM16BYTES, /* maxsize */ 630 adapter->max_rx_sgl_size, /* nsegments */ 631 MJUM16BYTES, /* maxsegsize */ 632 0, /* flags */ 633 NULL, /* lockfunc */ 634 NULL, /* lockarg */ 635 &adapter->rx_buf_tag); 636 637 return (ret); 638 } 639 #endif 640 641 /** 642 * ena_setup_tx_resources - allocate Tx resources (Descriptors) 643 * @adapter: network interface device structure 644 * @qid: queue index 645 * 646 * Returns 0 on success, otherwise on failure. 647 **/ 648 static int 649 ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 650 { 651 struct ena_que *que = &adapter->que[qid]; 652 struct ena_ring *tx_ring = que->tx_ring; 653 int size, i, err; 654 #ifdef RSS 655 cpuset_t cpu_mask; 656 #endif 657 658 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 659 tx_ring->tx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 660 661 size = sizeof(uint16_t) * tx_ring->ring_size; 662 tx_ring->free_tx_ids = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 663 664 /* Req id stack for TX OOO completions */ 665 for (i = 0; i < tx_ring->ring_size; i++) 666 tx_ring->free_tx_ids[i] = i; 667 668 /* Reset TX statistics. */ 669 ena_reset_counters((struct evcnt *)&tx_ring->tx_stats, 670 sizeof(tx_ring->tx_stats), 671 offsetof(struct ena_stats_tx, cnt)); 672 673 tx_ring->next_to_use = 0; 674 tx_ring->next_to_clean = 0; 675 676 /* Make sure that drbr is empty */ 677 ENA_RING_MTX_LOCK(tx_ring); 678 drbr_flush(adapter->ifp, tx_ring->br); 679 ENA_RING_MTX_UNLOCK(tx_ring); 680 681 /* ... and create the buffer DMA maps */ 682 for (i = 0; i < tx_ring->ring_size; i++) { 683 err = bus_dmamap_create(adapter->sc_dmat, 684 ENA_TSO_MAXSIZE, adapter->max_tx_sgl_size - 1, 685 ENA_TSO_MAXSIZE, 0, 0, 686 &tx_ring->tx_buffer_info[i].map); 687 if (unlikely(err != 0)) { 688 ena_trace(ENA_ALERT, 689 "Unable to create Tx DMA map for buffer %d\n", i); 690 goto err_buf_info_unmap; 691 } 692 } 693 694 /* Allocate workqueues */ 695 int rc = workqueue_create(&tx_ring->enqueue_tq, "ena_tx_enq", 696 ena_deferred_mq_start, tx_ring, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 697 if (unlikely(rc != 0)) { 698 ena_trace(ENA_ALERT, 699 "Unable to create workqueue for enqueue task\n"); 700 i = tx_ring->ring_size; 701 goto err_buf_info_unmap; 702 } 703 704 #if 0 705 /* RSS set cpu for thread */ 706 #ifdef RSS 707 CPU_SETOF(que->cpu, &cpu_mask); 708 taskqueue_start_threads_cpuset(&tx_ring->enqueue_tq, 1, IPL_NET, 709 &cpu_mask, "%s tx_ring enq (bucket %d)", 710 device_xname(adapter->pdev), que->cpu); 711 #else /* RSS */ 712 taskqueue_start_threads(&tx_ring->enqueue_tq, 1, IPL_NET, 713 "%s txeq %d", device_xname(adapter->pdev), que->cpu); 714 #endif /* RSS */ 715 #endif 716 717 return (0); 718 719 err_buf_info_unmap: 720 while (i--) { 721 bus_dmamap_destroy(adapter->sc_dmat, 722 tx_ring->tx_buffer_info[i].map); 723 } 724 free(tx_ring->free_tx_ids, M_DEVBUF); 725 tx_ring->free_tx_ids = NULL; 726 free(tx_ring->tx_buffer_info, M_DEVBUF); 727 tx_ring->tx_buffer_info = NULL; 728 729 return (ENOMEM); 730 } 731 732 /** 733 * ena_free_tx_resources - Free Tx Resources per Queue 734 * @adapter: network interface device structure 735 * @qid: queue index 736 * 737 * Free all transmit software resources 738 **/ 739 static void 740 ena_free_tx_resources(struct ena_adapter *adapter, int qid) 741 { 742 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 743 744 workqueue_wait(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 745 workqueue_destroy(tx_ring->enqueue_tq); 746 tx_ring->enqueue_tq = NULL; 747 748 ENA_RING_MTX_LOCK(tx_ring); 749 /* Flush buffer ring, */ 750 drbr_flush(adapter->ifp, tx_ring->br); 751 752 /* Free buffer DMA maps, */ 753 for (int i = 0; i < tx_ring->ring_size; i++) { 754 m_freem(tx_ring->tx_buffer_info[i].mbuf); 755 tx_ring->tx_buffer_info[i].mbuf = NULL; 756 bus_dmamap_unload(adapter->sc_dmat, 757 tx_ring->tx_buffer_info[i].map); 758 bus_dmamap_destroy(adapter->sc_dmat, 759 tx_ring->tx_buffer_info[i].map); 760 } 761 ENA_RING_MTX_UNLOCK(tx_ring); 762 763 /* And free allocated memory. */ 764 free(tx_ring->tx_buffer_info, M_DEVBUF); 765 tx_ring->tx_buffer_info = NULL; 766 767 free(tx_ring->free_tx_ids, M_DEVBUF); 768 tx_ring->free_tx_ids = NULL; 769 } 770 771 /** 772 * ena_setup_all_tx_resources - allocate all queues Tx resources 773 * @adapter: network interface device structure 774 * 775 * Returns 0 on success, otherwise on failure. 776 **/ 777 static int 778 ena_setup_all_tx_resources(struct ena_adapter *adapter) 779 { 780 int i, rc; 781 782 for (i = 0; i < adapter->num_queues; i++) { 783 rc = ena_setup_tx_resources(adapter, i); 784 if (rc != 0) { 785 device_printf(adapter->pdev, 786 "Allocation for Tx Queue %u failed\n", i); 787 goto err_setup_tx; 788 } 789 } 790 791 return (0); 792 793 err_setup_tx: 794 /* Rewind the index freeing the rings as we go */ 795 while (i--) 796 ena_free_tx_resources(adapter, i); 797 return (rc); 798 } 799 800 /** 801 * ena_free_all_tx_resources - Free Tx Resources for All Queues 802 * @adapter: network interface device structure 803 * 804 * Free all transmit software resources 805 **/ 806 static void 807 ena_free_all_tx_resources(struct ena_adapter *adapter) 808 { 809 int i; 810 811 for (i = 0; i < adapter->num_queues; i++) 812 ena_free_tx_resources(adapter, i); 813 } 814 815 static inline int 816 validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 817 { 818 if (likely(req_id < rx_ring->ring_size)) 819 return (0); 820 821 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 822 req_id); 823 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 824 825 /* Trigger device reset */ 826 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 827 rx_ring->adapter->trigger_reset = true; 828 829 return (EFAULT); 830 } 831 832 /** 833 * ena_setup_rx_resources - allocate Rx resources (Descriptors) 834 * @adapter: network interface device structure 835 * @qid: queue index 836 * 837 * Returns 0 on success, otherwise on failure. 838 **/ 839 static int 840 ena_setup_rx_resources(struct ena_adapter *adapter, unsigned int qid) 841 { 842 struct ena_que *que = &adapter->que[qid]; 843 struct ena_ring *rx_ring = que->rx_ring; 844 int size, err, i; 845 #ifdef RSS 846 cpuset_t cpu_mask; 847 #endif 848 849 size = sizeof(struct ena_rx_buffer) * rx_ring->ring_size; 850 851 /* 852 * Alloc extra element so in rx path 853 * we can always prefetch rx_info + 1 854 */ 855 size += sizeof(struct ena_rx_buffer); 856 857 rx_ring->rx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 858 859 size = sizeof(uint16_t) * rx_ring->ring_size; 860 rx_ring->free_rx_ids = malloc(size, M_DEVBUF, M_WAITOK); 861 862 for (i = 0; i < rx_ring->ring_size; i++) 863 rx_ring->free_rx_ids[i] = i; 864 865 /* Reset RX statistics. */ 866 ena_reset_counters((struct evcnt *)&rx_ring->rx_stats, 867 sizeof(rx_ring->rx_stats), 868 offsetof(struct ena_stats_rx, cnt)); 869 870 rx_ring->next_to_clean = 0; 871 rx_ring->next_to_use = 0; 872 873 /* ... and create the buffer DMA maps */ 874 for (i = 0; i < rx_ring->ring_size; i++) { 875 err = bus_dmamap_create(adapter->sc_dmat, 876 MJUM16BYTES, adapter->max_rx_sgl_size, MJUM16BYTES, 877 0, 0, 878 &(rx_ring->rx_buffer_info[i].map)); 879 if (err != 0) { 880 ena_trace(ENA_ALERT, 881 "Unable to create Rx DMA map for buffer %d\n", i); 882 goto err_buf_info_unmap; 883 } 884 } 885 886 #ifdef LRO 887 /* Create LRO for the ring */ 888 if ((adapter->ifp->if_capenable & IFCAP_LRO) != 0) { 889 int err = tcp_lro_init(&rx_ring->lro); 890 if (err != 0) { 891 device_printf(adapter->pdev, 892 "LRO[%d] Initialization failed!\n", qid); 893 } else { 894 ena_trace(ENA_INFO, 895 "RX Soft LRO[%d] Initialized\n", qid); 896 rx_ring->lro.ifp = adapter->ifp; 897 } 898 } 899 #endif 900 901 /* Allocate workqueues */ 902 int rc = workqueue_create(&rx_ring->cmpl_tq, "ena_rx_comp", 903 ena_deferred_rx_cleanup, rx_ring, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 904 if (unlikely(rc != 0)) { 905 ena_trace(ENA_ALERT, 906 "Unable to create workqueue for RX completion task\n"); 907 goto err_buf_info_unmap; 908 } 909 910 #if 0 911 /* RSS set cpu for thread */ 912 #ifdef RSS 913 CPU_SETOF(que->cpu, &cpu_mask); 914 taskqueue_start_threads_cpuset(&rx_ring->cmpl_tq, 1, IPL_NET, &cpu_mask, 915 "%s rx_ring cmpl (bucket %d)", 916 device_xname(adapter->pdev), que->cpu); 917 #else 918 taskqueue_start_threads(&rx_ring->cmpl_tq, 1, IPL_NET, 919 "%s rx_ring cmpl %d", device_xname(adapter->pdev), que->cpu); 920 #endif 921 #endif 922 923 return (0); 924 925 err_buf_info_unmap: 926 while (i--) { 927 bus_dmamap_destroy(adapter->sc_dmat, 928 rx_ring->rx_buffer_info[i].map); 929 } 930 931 free(rx_ring->free_rx_ids, M_DEVBUF); 932 rx_ring->free_rx_ids = NULL; 933 free(rx_ring->rx_buffer_info, M_DEVBUF); 934 rx_ring->rx_buffer_info = NULL; 935 return (ENOMEM); 936 } 937 938 /** 939 * ena_free_rx_resources - Free Rx Resources 940 * @adapter: network interface device structure 941 * @qid: queue index 942 * 943 * Free all receive software resources 944 **/ 945 static void 946 ena_free_rx_resources(struct ena_adapter *adapter, unsigned int qid) 947 { 948 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 949 950 workqueue_wait(rx_ring->cmpl_tq, &rx_ring->cmpl_task); 951 workqueue_destroy(rx_ring->cmpl_tq); 952 rx_ring->cmpl_tq = NULL; 953 954 /* Free buffer DMA maps, */ 955 for (int i = 0; i < rx_ring->ring_size; i++) { 956 m_freem(rx_ring->rx_buffer_info[i].mbuf); 957 rx_ring->rx_buffer_info[i].mbuf = NULL; 958 bus_dmamap_unload(adapter->sc_dmat, 959 rx_ring->rx_buffer_info[i].map); 960 bus_dmamap_destroy(adapter->sc_dmat, 961 rx_ring->rx_buffer_info[i].map); 962 } 963 964 #ifdef LRO 965 /* free LRO resources, */ 966 tcp_lro_free(&rx_ring->lro); 967 #endif 968 969 /* free allocated memory */ 970 free(rx_ring->rx_buffer_info, M_DEVBUF); 971 rx_ring->rx_buffer_info = NULL; 972 973 free(rx_ring->free_rx_ids, M_DEVBUF); 974 rx_ring->free_rx_ids = NULL; 975 } 976 977 /** 978 * ena_setup_all_rx_resources - allocate all queues Rx resources 979 * @adapter: network interface device structure 980 * 981 * Returns 0 on success, otherwise on failure. 982 **/ 983 static int 984 ena_setup_all_rx_resources(struct ena_adapter *adapter) 985 { 986 int i, rc = 0; 987 988 for (i = 0; i < adapter->num_queues; i++) { 989 rc = ena_setup_rx_resources(adapter, i); 990 if (rc != 0) { 991 device_printf(adapter->pdev, 992 "Allocation for Rx Queue %u failed\n", i); 993 goto err_setup_rx; 994 } 995 } 996 return (0); 997 998 err_setup_rx: 999 /* rewind the index freeing the rings as we go */ 1000 while (i--) 1001 ena_free_rx_resources(adapter, i); 1002 return (rc); 1003 } 1004 1005 /** 1006 * ena_free_all_rx_resources - Free Rx resources for all queues 1007 * @adapter: network interface device structure 1008 * 1009 * Free all receive software resources 1010 **/ 1011 static void 1012 ena_free_all_rx_resources(struct ena_adapter *adapter) 1013 { 1014 int i; 1015 1016 for (i = 0; i < adapter->num_queues; i++) 1017 ena_free_rx_resources(adapter, i); 1018 } 1019 1020 static inline int 1021 ena_alloc_rx_mbuf(struct ena_adapter *adapter, 1022 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 1023 { 1024 struct ena_com_buf *ena_buf; 1025 int error; 1026 int mlen; 1027 1028 /* if previous allocated frag is not used */ 1029 if (unlikely(rx_info->mbuf != NULL)) 1030 return (0); 1031 1032 /* Get mbuf using UMA allocator */ 1033 rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); 1034 1035 if (unlikely(rx_info->mbuf == NULL)) { 1036 counter_u64_add(rx_ring->rx_stats.mjum_alloc_fail, 1); 1037 rx_info->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1038 if (unlikely(rx_info->mbuf == NULL)) { 1039 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1040 return (ENOMEM); 1041 } 1042 mlen = MCLBYTES; 1043 } else { 1044 mlen = MJUM16BYTES; 1045 } 1046 /* Set mbuf length*/ 1047 rx_info->mbuf->m_pkthdr.len = rx_info->mbuf->m_len = mlen; 1048 1049 /* Map packets for DMA */ 1050 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1051 "Using tag %p for buffers' DMA mapping, mbuf %p len: %d", 1052 adapter->sc_dmat,rx_info->mbuf, rx_info->mbuf->m_len); 1053 error = bus_dmamap_load_mbuf(adapter->sc_dmat, rx_info->map, 1054 rx_info->mbuf, BUS_DMA_NOWAIT); 1055 if (unlikely((error != 0) || (rx_info->map->dm_nsegs != 1))) { 1056 ena_trace(ENA_WARNING, "failed to map mbuf, error: %d, " 1057 "nsegs: %d\n", error, rx_info->map->dm_nsegs); 1058 counter_u64_add(rx_ring->rx_stats.dma_mapping_err, 1); 1059 goto exit; 1060 1061 } 1062 1063 bus_dmamap_sync(adapter->sc_dmat, rx_info->map, 0, 1064 rx_info->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1065 1066 ena_buf = &rx_info->ena_buf; 1067 ena_buf->paddr = rx_info->map->dm_segs[0].ds_addr; 1068 ena_buf->len = mlen; 1069 1070 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 1071 "ALLOC RX BUF: mbuf %p, rx_info %p, len %d, paddr %#jx\n", 1072 rx_info->mbuf, rx_info,ena_buf->len, (uintmax_t)ena_buf->paddr); 1073 1074 return (0); 1075 1076 exit: 1077 m_freem(rx_info->mbuf); 1078 rx_info->mbuf = NULL; 1079 return (EFAULT); 1080 } 1081 1082 static void 1083 ena_free_rx_mbuf(struct ena_adapter *adapter, struct ena_ring *rx_ring, 1084 struct ena_rx_buffer *rx_info) 1085 { 1086 1087 if (rx_info->mbuf == NULL) { 1088 ena_trace(ENA_WARNING, "Trying to free unallocated buffer\n"); 1089 return; 1090 } 1091 1092 bus_dmamap_unload(adapter->sc_dmat, rx_info->map); 1093 m_freem(rx_info->mbuf); 1094 rx_info->mbuf = NULL; 1095 } 1096 1097 /** 1098 * ena_refill_rx_bufs - Refills ring with descriptors 1099 * @rx_ring: the ring which we want to feed with free descriptors 1100 * @num: number of descriptors to refill 1101 * Refills the ring with newly allocated DMA-mapped mbufs for receiving 1102 **/ 1103 static int 1104 ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num) 1105 { 1106 struct ena_adapter *adapter = rx_ring->adapter; 1107 uint16_t next_to_use, req_id; 1108 uint32_t i; 1109 int rc; 1110 1111 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, "refill qid: %d", 1112 rx_ring->qid); 1113 1114 next_to_use = rx_ring->next_to_use; 1115 1116 for (i = 0; i < num; i++) { 1117 struct ena_rx_buffer *rx_info; 1118 1119 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, 1120 "RX buffer - next to use: %d", next_to_use); 1121 1122 req_id = rx_ring->free_rx_ids[next_to_use]; 1123 rc = validate_rx_req_id(rx_ring, req_id); 1124 if (unlikely(rc != 0)) 1125 break; 1126 1127 rx_info = &rx_ring->rx_buffer_info[req_id]; 1128 1129 rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info); 1130 if (unlikely(rc != 0)) { 1131 ena_trace(ENA_WARNING, 1132 "failed to alloc buffer for rx queue %d\n", 1133 rx_ring->qid); 1134 break; 1135 } 1136 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 1137 &rx_info->ena_buf, req_id); 1138 if (unlikely(rc != 0)) { 1139 ena_trace(ENA_WARNING, 1140 "failed to add buffer for rx queue %d\n", 1141 rx_ring->qid); 1142 break; 1143 } 1144 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 1145 rx_ring->ring_size); 1146 } 1147 1148 if (unlikely(i < num)) { 1149 counter_u64_add(rx_ring->rx_stats.refil_partial, 1); 1150 ena_trace(ENA_WARNING, 1151 "refilled rx qid %d with only %d mbufs (from %d)\n", 1152 rx_ring->qid, i, num); 1153 } 1154 1155 if (likely(i != 0)) { 1156 wmb(); 1157 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 1158 } 1159 rx_ring->next_to_use = next_to_use; 1160 return (i); 1161 } 1162 1163 static void 1164 ena_free_rx_bufs(struct ena_adapter *adapter, unsigned int qid) 1165 { 1166 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 1167 unsigned int i; 1168 1169 for (i = 0; i < rx_ring->ring_size; i++) { 1170 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 1171 1172 if (rx_info->mbuf != NULL) 1173 ena_free_rx_mbuf(adapter, rx_ring, rx_info); 1174 } 1175 } 1176 1177 /** 1178 * ena_refill_all_rx_bufs - allocate all queues Rx buffers 1179 * @adapter: network interface device structure 1180 * 1181 */ 1182 static void 1183 ena_refill_all_rx_bufs(struct ena_adapter *adapter) 1184 { 1185 struct ena_ring *rx_ring; 1186 int i, rc, bufs_num; 1187 1188 for (i = 0; i < adapter->num_queues; i++) { 1189 rx_ring = &adapter->rx_ring[i]; 1190 bufs_num = rx_ring->ring_size - 1; 1191 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 1192 1193 if (unlikely(rc != bufs_num)) 1194 ena_trace(ENA_WARNING, "refilling Queue %d failed. " 1195 "Allocated %d buffers from: %d\n", i, rc, bufs_num); 1196 } 1197 } 1198 1199 static void 1200 ena_free_all_rx_bufs(struct ena_adapter *adapter) 1201 { 1202 int i; 1203 1204 for (i = 0; i < adapter->num_queues; i++) 1205 ena_free_rx_bufs(adapter, i); 1206 } 1207 1208 /** 1209 * ena_free_tx_bufs - Free Tx Buffers per Queue 1210 * @adapter: network interface device structure 1211 * @qid: queue index 1212 **/ 1213 static void 1214 ena_free_tx_bufs(struct ena_adapter *adapter, unsigned int qid) 1215 { 1216 bool print_once = true; 1217 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 1218 1219 ENA_RING_MTX_LOCK(tx_ring); 1220 for (int i = 0; i < tx_ring->ring_size; i++) { 1221 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 1222 1223 if (tx_info->mbuf == NULL) 1224 continue; 1225 1226 if (print_once) { 1227 device_printf(adapter->pdev, 1228 "free uncompleted tx mbuf qid %d idx 0x%x", 1229 qid, i); 1230 print_once = false; 1231 } else { 1232 ena_trace(ENA_DBG, 1233 "free uncompleted tx mbuf qid %d idx 0x%x", 1234 qid, i); 1235 } 1236 1237 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1238 m_free(tx_info->mbuf); 1239 tx_info->mbuf = NULL; 1240 } 1241 ENA_RING_MTX_UNLOCK(tx_ring); 1242 } 1243 1244 static void 1245 ena_free_all_tx_bufs(struct ena_adapter *adapter) 1246 { 1247 1248 for (int i = 0; i < adapter->num_queues; i++) 1249 ena_free_tx_bufs(adapter, i); 1250 } 1251 1252 static void 1253 ena_destroy_all_tx_queues(struct ena_adapter *adapter) 1254 { 1255 uint16_t ena_qid; 1256 int i; 1257 1258 for (i = 0; i < adapter->num_queues; i++) { 1259 ena_qid = ENA_IO_TXQ_IDX(i); 1260 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1261 } 1262 } 1263 1264 static void 1265 ena_destroy_all_rx_queues(struct ena_adapter *adapter) 1266 { 1267 uint16_t ena_qid; 1268 int i; 1269 1270 for (i = 0; i < adapter->num_queues; i++) { 1271 ena_qid = ENA_IO_RXQ_IDX(i); 1272 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1273 } 1274 } 1275 1276 static void 1277 ena_destroy_all_io_queues(struct ena_adapter *adapter) 1278 { 1279 ena_destroy_all_tx_queues(adapter); 1280 ena_destroy_all_rx_queues(adapter); 1281 } 1282 1283 static inline int 1284 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 1285 { 1286 struct ena_adapter *adapter = tx_ring->adapter; 1287 struct ena_tx_buffer *tx_info = NULL; 1288 1289 if (likely(req_id < tx_ring->ring_size)) { 1290 tx_info = &tx_ring->tx_buffer_info[req_id]; 1291 if (tx_info->mbuf != NULL) 1292 return (0); 1293 } 1294 1295 if (tx_info->mbuf == NULL) 1296 device_printf(adapter->pdev, 1297 "tx_info doesn't have valid mbuf\n"); 1298 else 1299 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 1300 1301 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 1302 1303 return (EFAULT); 1304 } 1305 1306 static int 1307 ena_create_io_queues(struct ena_adapter *adapter) 1308 { 1309 struct ena_com_dev *ena_dev = adapter->ena_dev; 1310 struct ena_com_create_io_ctx ctx; 1311 struct ena_ring *ring; 1312 uint16_t ena_qid; 1313 uint32_t msix_vector; 1314 int rc, i; 1315 1316 /* Create TX queues */ 1317 for (i = 0; i < adapter->num_queues; i++) { 1318 msix_vector = ENA_IO_IRQ_IDX(i); 1319 ena_qid = ENA_IO_TXQ_IDX(i); 1320 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1321 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1322 ctx.queue_size = adapter->tx_ring_size; 1323 ctx.msix_vector = msix_vector; 1324 ctx.qid = ena_qid; 1325 rc = ena_com_create_io_queue(ena_dev, &ctx); 1326 if (rc != 0) { 1327 device_printf(adapter->pdev, 1328 "Failed to create io TX queue #%d rc: %d\n", i, rc); 1329 goto err_tx; 1330 } 1331 ring = &adapter->tx_ring[i]; 1332 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1333 &ring->ena_com_io_sq, 1334 &ring->ena_com_io_cq); 1335 if (rc != 0) { 1336 device_printf(adapter->pdev, 1337 "Failed to get TX queue handlers. TX queue num" 1338 " %d rc: %d\n", i, rc); 1339 ena_com_destroy_io_queue(ena_dev, ena_qid); 1340 goto err_tx; 1341 } 1342 } 1343 1344 /* Create RX queues */ 1345 for (i = 0; i < adapter->num_queues; i++) { 1346 msix_vector = ENA_IO_IRQ_IDX(i); 1347 ena_qid = ENA_IO_RXQ_IDX(i); 1348 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1349 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1350 ctx.queue_size = adapter->rx_ring_size; 1351 ctx.msix_vector = msix_vector; 1352 ctx.qid = ena_qid; 1353 rc = ena_com_create_io_queue(ena_dev, &ctx); 1354 if (unlikely(rc != 0)) { 1355 device_printf(adapter->pdev, 1356 "Failed to create io RX queue[%d] rc: %d\n", i, rc); 1357 goto err_rx; 1358 } 1359 1360 ring = &adapter->rx_ring[i]; 1361 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1362 &ring->ena_com_io_sq, 1363 &ring->ena_com_io_cq); 1364 if (unlikely(rc != 0)) { 1365 device_printf(adapter->pdev, 1366 "Failed to get RX queue handlers. RX queue num" 1367 " %d rc: %d\n", i, rc); 1368 ena_com_destroy_io_queue(ena_dev, ena_qid); 1369 goto err_rx; 1370 } 1371 } 1372 1373 return (0); 1374 1375 err_rx: 1376 while (i--) 1377 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1378 i = adapter->num_queues; 1379 err_tx: 1380 while (i--) 1381 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1382 1383 return (ENXIO); 1384 } 1385 1386 /** 1387 * ena_tx_cleanup - clear sent packets and corresponding descriptors 1388 * @tx_ring: ring for which we want to clean packets 1389 * 1390 * Once packets are sent, we ask the device in a loop for no longer used 1391 * descriptors. We find the related mbuf chain in a map (index in an array) 1392 * and free it, then update ring state. 1393 * This is performed in "endless" loop, updating ring pointers every 1394 * TX_COMMIT. The first check of free descriptor is performed before the actual 1395 * loop, then repeated at the loop end. 1396 **/ 1397 static int 1398 ena_tx_cleanup(struct ena_ring *tx_ring) 1399 { 1400 struct ena_adapter *adapter; 1401 struct ena_com_io_cq* io_cq; 1402 uint16_t next_to_clean; 1403 uint16_t req_id; 1404 uint16_t ena_qid; 1405 unsigned int total_done = 0; 1406 int rc; 1407 int commit = TX_COMMIT; 1408 int budget = TX_BUDGET; 1409 int work_done; 1410 1411 adapter = tx_ring->que->adapter; 1412 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1413 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1414 next_to_clean = tx_ring->next_to_clean; 1415 1416 do { 1417 struct ena_tx_buffer *tx_info; 1418 struct mbuf *mbuf; 1419 1420 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 1421 if (unlikely(rc != 0)) 1422 break; 1423 1424 rc = validate_tx_req_id(tx_ring, req_id); 1425 if (unlikely(rc != 0)) 1426 break; 1427 1428 tx_info = &tx_ring->tx_buffer_info[req_id]; 1429 1430 mbuf = tx_info->mbuf; 1431 1432 tx_info->mbuf = NULL; 1433 bintime_clear(&tx_info->timestamp); 1434 1435 if (likely(tx_info->num_of_bufs != 0)) { 1436 /* Map is no longer required */ 1437 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 1438 } 1439 1440 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed", 1441 tx_ring->qid, mbuf); 1442 1443 m_freem(mbuf); 1444 1445 total_done += tx_info->tx_descs; 1446 1447 tx_ring->free_tx_ids[next_to_clean] = req_id; 1448 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 1449 tx_ring->ring_size); 1450 1451 if (unlikely(--commit == 0)) { 1452 commit = TX_COMMIT; 1453 /* update ring state every TX_COMMIT descriptor */ 1454 tx_ring->next_to_clean = next_to_clean; 1455 ena_com_comp_ack( 1456 &adapter->ena_dev->io_sq_queues[ena_qid], 1457 total_done); 1458 ena_com_update_dev_comp_head(io_cq); 1459 total_done = 0; 1460 } 1461 } while (likely(--budget)); 1462 1463 work_done = TX_BUDGET - budget; 1464 1465 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d", 1466 tx_ring->qid, work_done); 1467 1468 /* If there is still something to commit update ring state */ 1469 if (likely(commit != TX_COMMIT)) { 1470 tx_ring->next_to_clean = next_to_clean; 1471 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 1472 total_done); 1473 ena_com_update_dev_comp_head(io_cq); 1474 } 1475 1476 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 1477 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, NULL); 1478 1479 return (work_done); 1480 } 1481 1482 #if 0 1483 static void 1484 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1485 struct mbuf *mbuf) 1486 { 1487 struct ena_adapter *adapter = rx_ring->adapter; 1488 1489 if (likely(adapter->rss_support)) { 1490 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 1491 1492 if (ena_rx_ctx->frag && 1493 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 1494 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1495 return; 1496 } 1497 1498 switch (ena_rx_ctx->l3_proto) { 1499 case ENA_ETH_IO_L3_PROTO_IPV4: 1500 switch (ena_rx_ctx->l4_proto) { 1501 case ENA_ETH_IO_L4_PROTO_TCP: 1502 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 1503 break; 1504 case ENA_ETH_IO_L4_PROTO_UDP: 1505 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 1506 break; 1507 default: 1508 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 1509 } 1510 break; 1511 case ENA_ETH_IO_L3_PROTO_IPV6: 1512 switch (ena_rx_ctx->l4_proto) { 1513 case ENA_ETH_IO_L4_PROTO_TCP: 1514 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 1515 break; 1516 case ENA_ETH_IO_L4_PROTO_UDP: 1517 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 1518 break; 1519 default: 1520 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 1521 } 1522 break; 1523 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 1524 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1525 break; 1526 default: 1527 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1528 } 1529 } else { 1530 mbuf->m_pkthdr.flowid = rx_ring->qid; 1531 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1532 } 1533 } 1534 #endif 1535 1536 /** 1537 * ena_rx_mbuf - assemble mbuf from descriptors 1538 * @rx_ring: ring for which we want to clean packets 1539 * @ena_bufs: buffer info 1540 * @ena_rx_ctx: metadata for this packet(s) 1541 * @next_to_clean: ring pointer, will be updated only upon success 1542 * 1543 **/ 1544 static struct mbuf* 1545 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 1546 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 1547 { 1548 struct mbuf *mbuf; 1549 struct ena_rx_buffer *rx_info; 1550 struct ena_adapter *adapter; 1551 unsigned int descs = ena_rx_ctx->descs; 1552 uint16_t ntc, len, req_id, buf = 0; 1553 1554 ntc = *next_to_clean; 1555 adapter = rx_ring->adapter; 1556 rx_info = &rx_ring->rx_buffer_info[ntc]; 1557 1558 if (unlikely(rx_info->mbuf == NULL)) { 1559 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1560 return (NULL); 1561 } 1562 1563 len = ena_bufs[buf].len; 1564 req_id = ena_bufs[buf].req_id; 1565 rx_info = &rx_ring->rx_buffer_info[req_id]; 1566 1567 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx", 1568 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 1569 1570 mbuf = rx_info->mbuf; 1571 KASSERT(mbuf->m_flags & M_PKTHDR); 1572 mbuf->m_pkthdr.len = len; 1573 mbuf->m_len = len; 1574 m_set_rcvif(mbuf, rx_ring->que->adapter->ifp); 1575 1576 /* Fill mbuf with hash key and it's interpretation for optimization */ 1577 #if 0 1578 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 1579 #endif 1580 1581 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf %p, flags=0x%x, len: %d", 1582 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 1583 1584 /* DMA address is not needed anymore, unmap it */ 1585 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1586 1587 rx_info->mbuf = NULL; 1588 rx_ring->free_rx_ids[ntc] = req_id; 1589 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1590 1591 /* 1592 * While we have more than 1 descriptors for one rcvd packet, append 1593 * other mbufs to the main one 1594 */ 1595 while (--descs) { 1596 ++buf; 1597 len = ena_bufs[buf].len; 1598 req_id = ena_bufs[buf].req_id; 1599 rx_info = &rx_ring->rx_buffer_info[req_id]; 1600 1601 if (unlikely(rx_info->mbuf == NULL)) { 1602 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1603 /* 1604 * If one of the required mbufs was not allocated yet, 1605 * we can break there. 1606 * All earlier used descriptors will be reallocated 1607 * later and not used mbufs can be reused. 1608 * The next_to_clean pointer will not be updated in case 1609 * of an error, so caller should advance it manually 1610 * in error handling routine to keep it up to date 1611 * with hw ring. 1612 */ 1613 m_freem(mbuf); 1614 return (NULL); 1615 } 1616 1617 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 1618 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1619 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p", 1620 mbuf); 1621 } 1622 1623 ena_trace(ENA_DBG | ENA_RXPTH, 1624 "rx mbuf updated. len %d", mbuf->m_pkthdr.len); 1625 1626 /* Free already appended mbuf, it won't be useful anymore */ 1627 bus_dmamap_unload(rx_ring->adapter->sc_dmat, rx_info->map); 1628 m_freem(rx_info->mbuf); 1629 rx_info->mbuf = NULL; 1630 1631 rx_ring->free_rx_ids[ntc] = req_id; 1632 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1633 } 1634 1635 *next_to_clean = ntc; 1636 1637 return (mbuf); 1638 } 1639 1640 /** 1641 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 1642 **/ 1643 static inline void 1644 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1645 struct mbuf *mbuf) 1646 { 1647 1648 /* IPv4 */ 1649 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) { 1650 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1651 if (ena_rx_ctx->l3_csum_err) { 1652 /* ipv4 checksum error */ 1653 mbuf->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1654 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1655 ena_trace(ENA_DBG, "RX IPv4 header checksum error"); 1656 return; 1657 } 1658 1659 /* TCP/UDP */ 1660 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1661 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1662 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv4 : M_CSUM_UDPv4; 1663 if (ena_rx_ctx->l4_csum_err) { 1664 /* TCP/UDP checksum error */ 1665 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1666 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1667 ena_trace(ENA_DBG, "RX L4 checksum error"); 1668 } 1669 } 1670 } 1671 /* IPv6 */ 1672 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) { 1673 /* TCP/UDP */ 1674 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1675 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1676 mbuf->m_pkthdr.csum_flags |= (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ? M_CSUM_TCPv6 : M_CSUM_UDPv6; 1677 if (ena_rx_ctx->l4_csum_err) { 1678 /* TCP/UDP checksum error */ 1679 mbuf->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1680 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1681 ena_trace(ENA_DBG, "RX L4 checksum error"); 1682 } 1683 } 1684 } 1685 } 1686 1687 static void 1688 ena_deferred_rx_cleanup(struct work *wk, void *arg) 1689 { 1690 struct ena_ring *rx_ring = arg; 1691 int budget = CLEAN_BUDGET; 1692 1693 atomic_swap_uint(&rx_ring->task_pending, 0); 1694 1695 ENA_RING_MTX_LOCK(rx_ring); 1696 /* 1697 * If deferred task was executed, perform cleanup of all awaiting 1698 * descs (or until given budget is depleted to avoid infinite loop). 1699 */ 1700 while (likely(budget--)) { 1701 if (ena_rx_cleanup(rx_ring) == 0) 1702 break; 1703 } 1704 ENA_RING_MTX_UNLOCK(rx_ring); 1705 } 1706 1707 /** 1708 * ena_rx_cleanup - handle rx irq 1709 * @arg: ring for which irq is being handled 1710 **/ 1711 static int 1712 ena_rx_cleanup(struct ena_ring *rx_ring) 1713 { 1714 struct ena_adapter *adapter; 1715 struct mbuf *mbuf; 1716 struct ena_com_rx_ctx ena_rx_ctx; 1717 struct ena_com_io_cq* io_cq; 1718 struct ena_com_io_sq* io_sq; 1719 struct ifnet *ifp; 1720 uint16_t ena_qid; 1721 uint16_t next_to_clean; 1722 uint32_t refill_required; 1723 uint32_t refill_threshold; 1724 uint32_t do_if_input = 0; 1725 unsigned int qid; 1726 int rc, i; 1727 int budget = RX_BUDGET; 1728 1729 adapter = rx_ring->que->adapter; 1730 ifp = adapter->ifp; 1731 qid = rx_ring->que->id; 1732 ena_qid = ENA_IO_RXQ_IDX(qid); 1733 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1734 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1735 next_to_clean = rx_ring->next_to_clean; 1736 1737 ena_trace(ENA_DBG, "rx: qid %d", qid); 1738 1739 do { 1740 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1741 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 1742 ena_rx_ctx.descs = 0; 1743 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 1744 1745 if (unlikely(rc != 0)) 1746 goto error; 1747 1748 if (unlikely(ena_rx_ctx.descs == 0)) 1749 break; 1750 1751 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 1752 "descs #: %d l3 proto %d l4 proto %d hash: %x", 1753 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1754 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1755 1756 /* Receive mbuf from the ring */ 1757 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 1758 &ena_rx_ctx, &next_to_clean); 1759 1760 /* Exit if we failed to retrieve a buffer */ 1761 if (unlikely(mbuf == NULL)) { 1762 for (i = 0; i < ena_rx_ctx.descs; ++i) { 1763 rx_ring->free_rx_ids[next_to_clean] = 1764 rx_ring->ena_bufs[i].req_id; 1765 next_to_clean = 1766 ENA_RX_RING_IDX_NEXT(next_to_clean, 1767 rx_ring->ring_size); 1768 1769 } 1770 break; 1771 } 1772 1773 if (((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) || 1774 ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) || 1775 ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) || 1776 ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) || 1777 ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0)) { 1778 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 1779 } 1780 1781 counter_enter(); 1782 counter_u64_add_protected(rx_ring->rx_stats.bytes, 1783 mbuf->m_pkthdr.len); 1784 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 1785 mbuf->m_pkthdr.len); 1786 counter_exit(); 1787 /* 1788 * LRO is only for IP/TCP packets and TCP checksum of the packet 1789 * should be computed by hardware. 1790 */ 1791 do_if_input = 1; 1792 #ifdef LRO 1793 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 1794 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 1795 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 1796 /* 1797 * Send to the stack if: 1798 * - LRO not enabled, or 1799 * - no LRO resources, or 1800 * - lro enqueue fails 1801 */ 1802 if ((rx_ring->lro.lro_cnt != 0) && 1803 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 1804 do_if_input = 0; 1805 } 1806 #endif 1807 if (do_if_input != 0) { 1808 ena_trace(ENA_DBG | ENA_RXPTH, 1809 "calling if_input() with mbuf %p", mbuf); 1810 if_percpuq_enqueue(ifp->if_percpuq, mbuf); 1811 } 1812 1813 counter_enter(); 1814 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 1815 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 1816 counter_exit(); 1817 } while (--budget); 1818 1819 rx_ring->next_to_clean = next_to_clean; 1820 1821 refill_required = ena_com_free_desc(io_sq); 1822 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1823 1824 if (refill_required > refill_threshold) { 1825 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1826 ena_refill_rx_bufs(rx_ring, refill_required); 1827 } 1828 1829 #ifdef LRO 1830 tcp_lro_flush_all(&rx_ring->lro); 1831 #endif 1832 1833 return (RX_BUDGET - budget); 1834 1835 error: 1836 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 1837 return (RX_BUDGET - budget); 1838 } 1839 1840 /********************************************************************* 1841 * 1842 * MSIX & Interrupt Service routine 1843 * 1844 **********************************************************************/ 1845 1846 /** 1847 * ena_handle_msix - MSIX Interrupt Handler for admin/async queue 1848 * @arg: interrupt number 1849 **/ 1850 static int 1851 ena_intr_msix_mgmnt(void *arg) 1852 { 1853 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1854 1855 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1856 if (likely(adapter->running)) 1857 ena_com_aenq_intr_handler(adapter->ena_dev, arg); 1858 1859 return 1; 1860 } 1861 1862 /** 1863 * ena_handle_msix - MSIX Interrupt Handler for Tx/Rx 1864 * @arg: interrupt number 1865 **/ 1866 static int 1867 ena_handle_msix(void *arg) 1868 { 1869 struct ena_que *que = arg; 1870 struct ena_adapter *adapter = que->adapter; 1871 struct ifnet *ifp = adapter->ifp; 1872 struct ena_ring *tx_ring; 1873 struct ena_ring *rx_ring; 1874 struct ena_com_io_cq* io_cq; 1875 struct ena_eth_io_intr_reg intr_reg; 1876 int qid, ena_qid; 1877 int txc, rxc, i; 1878 1879 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1880 return 0; 1881 1882 ena_trace(ENA_DBG, "MSI-X TX/RX routine"); 1883 1884 tx_ring = que->tx_ring; 1885 rx_ring = que->rx_ring; 1886 qid = que->id; 1887 ena_qid = ENA_IO_TXQ_IDX(qid); 1888 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1889 1890 for (i = 0; i < CLEAN_BUDGET; ++i) { 1891 /* 1892 * If lock cannot be acquired, then deferred cleanup task was 1893 * being executed and rx ring is being cleaned up in 1894 * another thread. 1895 */ 1896 if (likely(ENA_RING_MTX_TRYLOCK(rx_ring) != 0)) { 1897 rxc = ena_rx_cleanup(rx_ring); 1898 ENA_RING_MTX_UNLOCK(rx_ring); 1899 } else { 1900 rxc = 0; 1901 } 1902 1903 /* Protection from calling ena_tx_cleanup from ena_start_xmit */ 1904 ENA_RING_MTX_LOCK(tx_ring); 1905 txc = ena_tx_cleanup(tx_ring); 1906 ENA_RING_MTX_UNLOCK(tx_ring); 1907 1908 if (unlikely((if_getdrvflags(ifp) & IFF_RUNNING) == 0)) 1909 return 0; 1910 1911 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 1912 break; 1913 } 1914 1915 /* Signal that work is done and unmask interrupt */ 1916 ena_com_update_intr_reg(&intr_reg, 1917 RX_IRQ_INTERVAL, 1918 TX_IRQ_INTERVAL, 1919 true); 1920 ena_com_unmask_intr(io_cq, &intr_reg); 1921 1922 return 1; 1923 } 1924 1925 static int 1926 ena_enable_msix(struct ena_adapter *adapter) 1927 { 1928 int msix_req; 1929 int counts[PCI_INTR_TYPE_SIZE]; 1930 int max_type; 1931 1932 /* Reserved the max msix vectors we might need */ 1933 msix_req = ENA_MAX_MSIX_VEC(adapter->num_queues); 1934 1935 counts[PCI_INTR_TYPE_INTX] = 0; 1936 counts[PCI_INTR_TYPE_MSI] = 0; 1937 counts[PCI_INTR_TYPE_MSIX] = msix_req; 1938 max_type = PCI_INTR_TYPE_MSIX; 1939 1940 if (pci_intr_alloc(&adapter->sc_pa, &adapter->sc_intrs, counts, 1941 max_type) != 0) { 1942 aprint_error_dev(adapter->pdev, 1943 "failed to allocate interrupt\n"); 1944 return ENOSPC; 1945 } 1946 1947 adapter->sc_nintrs = counts[PCI_INTR_TYPE_MSIX]; 1948 1949 if (counts[PCI_INTR_TYPE_MSIX] != msix_req) { 1950 device_printf(adapter->pdev, 1951 "Enable only %d MSI-x (out of %d), reduce " 1952 "the number of queues\n", adapter->sc_nintrs, msix_req); 1953 adapter->num_queues = adapter->sc_nintrs - ENA_ADMIN_MSIX_VEC; 1954 } 1955 1956 return 0; 1957 } 1958 1959 #if 0 1960 static void 1961 ena_setup_io_intr(struct ena_adapter *adapter) 1962 { 1963 static int last_bind_cpu = -1; 1964 int irq_idx; 1965 1966 for (int i = 0; i < adapter->num_queues; i++) { 1967 irq_idx = ENA_IO_IRQ_IDX(i); 1968 1969 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1970 "%s-TxRx-%d", device_xname(adapter->pdev), i); 1971 adapter->irq_tbl[irq_idx].handler = ena_handle_msix; 1972 adapter->irq_tbl[irq_idx].data = &adapter->que[i]; 1973 adapter->irq_tbl[irq_idx].vector = 1974 adapter->msix_entries[irq_idx].vector; 1975 ena_trace(ENA_INFO | ENA_IOQ, "ena_setup_io_intr vector: %d\n", 1976 adapter->msix_entries[irq_idx].vector); 1977 #ifdef RSS 1978 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1979 rss_getcpu(i % rss_getnumbuckets()); 1980 #else 1981 /* 1982 * We still want to bind rings to the corresponding cpu 1983 * using something similar to the RSS round-robin technique. 1984 */ 1985 if (unlikely(last_bind_cpu < 0)) 1986 last_bind_cpu = CPU_FIRST(); 1987 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1988 last_bind_cpu; 1989 last_bind_cpu = CPU_NEXT(last_bind_cpu); 1990 #endif 1991 } 1992 } 1993 #endif 1994 1995 static int 1996 ena_request_mgmnt_irq(struct ena_adapter *adapter) 1997 { 1998 const char *intrstr; 1999 char intrbuf[PCI_INTRSTR_LEN]; 2000 char intr_xname[INTRDEVNAMEBUF]; 2001 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 2002 const int irq_slot = ENA_MGMNT_IRQ_IDX; 2003 2004 KASSERT(adapter->sc_intrs != NULL); 2005 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 2006 2007 snprintf(intr_xname, sizeof(intr_xname), "%s mgmnt", 2008 device_xname(adapter->pdev)); 2009 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 2010 intrbuf, sizeof(intrbuf)); 2011 2012 adapter->sc_ihs[irq_slot] = pci_intr_establish_xname( 2013 pc, adapter->sc_intrs[irq_slot], 2014 IPL_NET, ena_intr_msix_mgmnt, adapter, intr_xname); 2015 2016 if (adapter->sc_ihs[irq_slot] == NULL) { 2017 device_printf(adapter->pdev, "failed to register " 2018 "interrupt handler for MGMNT irq %s\n", 2019 intrstr); 2020 return ENOMEM; 2021 } 2022 2023 aprint_normal_dev(adapter->pdev, 2024 "for MGMNT interrupting at %s\n", intrstr); 2025 2026 return 0; 2027 } 2028 2029 static int 2030 ena_request_io_irq(struct ena_adapter *adapter) 2031 { 2032 const char *intrstr; 2033 char intrbuf[PCI_INTRSTR_LEN]; 2034 char intr_xname[INTRDEVNAMEBUF]; 2035 pci_chipset_tag_t pc = adapter->sc_pa.pa_pc; 2036 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2037 void *vih; 2038 kcpuset_t *affinity; 2039 int i; 2040 2041 KASSERT(adapter->sc_intrs != NULL); 2042 2043 kcpuset_create(&affinity, false); 2044 2045 for (i = 0; i < adapter->num_queues; i++) { 2046 int irq_slot = i + irq_off; 2047 int affinity_to = (irq_slot) % ncpu; 2048 2049 KASSERT((void *)adapter->sc_intrs[irq_slot] != NULL); 2050 KASSERT(adapter->sc_ihs[irq_slot] == NULL); 2051 2052 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 2053 device_xname(adapter->pdev), i); 2054 intrstr = pci_intr_string(pc, adapter->sc_intrs[irq_slot], 2055 intrbuf, sizeof(intrbuf)); 2056 2057 vih = pci_intr_establish_xname(adapter->sc_pa.pa_pc, 2058 adapter->sc_intrs[irq_slot], IPL_NET, 2059 ena_handle_msix, &adapter->que[i], intr_xname); 2060 2061 if (adapter->sc_ihs[ENA_MGMNT_IRQ_IDX] == NULL) { 2062 device_printf(adapter->pdev, "failed to register " 2063 "interrupt handler for IO queue %d irq %s\n", 2064 i, intrstr); 2065 goto err; 2066 } 2067 2068 kcpuset_zero(affinity); 2069 /* Round-robin affinity */ 2070 kcpuset_set(affinity, affinity_to); 2071 int error = interrupt_distribute(vih, affinity, NULL); 2072 if (error == 0) { 2073 aprint_normal_dev(adapter->pdev, 2074 "for IO queue %d interrupting at %s" 2075 " affinity to %u\n", i, intrstr, affinity_to); 2076 } else { 2077 aprint_normal_dev(adapter->pdev, 2078 "for IO queue %d interrupting at %s\n", i, intrstr); 2079 } 2080 2081 adapter->sc_ihs[irq_slot] = vih; 2082 2083 #ifdef RSS 2084 ena_trace(ENA_INFO, "queue %d - RSS bucket %d\n", 2085 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2086 #else 2087 ena_trace(ENA_INFO, "queue %d - cpu %d\n", 2088 i - ENA_IO_IRQ_FIRST_IDX, affinity_to); 2089 #endif 2090 } 2091 2092 kcpuset_destroy(affinity); 2093 return 0; 2094 2095 err: 2096 kcpuset_destroy(affinity); 2097 2098 for (i--; i >= 0; i--) { 2099 int irq_slot __diagused = i + irq_off; 2100 KASSERT(adapter->sc_ihs[irq_slot] != NULL); 2101 pci_intr_disestablish(adapter->sc_pa.pa_pc, adapter->sc_ihs[i]); 2102 adapter->sc_ihs[i] = NULL; 2103 } 2104 2105 return ENOSPC; 2106 } 2107 2108 static void 2109 ena_free_mgmnt_irq(struct ena_adapter *adapter) 2110 { 2111 const int irq_slot = ENA_MGMNT_IRQ_IDX; 2112 2113 if (adapter->sc_ihs[irq_slot]) { 2114 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2115 adapter->sc_ihs[irq_slot]); 2116 adapter->sc_ihs[irq_slot] = NULL; 2117 } 2118 } 2119 2120 static void 2121 ena_free_io_irq(struct ena_adapter *adapter) 2122 { 2123 const int irq_off = ENA_IO_IRQ_FIRST_IDX; 2124 2125 for (int i = 0; i < adapter->num_queues; i++) { 2126 int irq_slot = i + irq_off; 2127 2128 if (adapter->sc_ihs[irq_slot]) { 2129 pci_intr_disestablish(adapter->sc_pa.pa_pc, 2130 adapter->sc_ihs[i]); 2131 adapter->sc_ihs[i] = NULL; 2132 } 2133 } 2134 } 2135 2136 static void 2137 ena_free_irqs(struct ena_adapter* adapter) 2138 { 2139 2140 ena_free_io_irq(adapter); 2141 ena_free_mgmnt_irq(adapter); 2142 ena_disable_msix(adapter); 2143 } 2144 2145 static void 2146 ena_disable_msix(struct ena_adapter *adapter) 2147 { 2148 pci_intr_release(adapter->sc_pa.pa_pc, adapter->sc_intrs, 2149 adapter->sc_nintrs); 2150 } 2151 2152 static void 2153 ena_unmask_all_io_irqs(struct ena_adapter *adapter) 2154 { 2155 struct ena_com_io_cq* io_cq; 2156 struct ena_eth_io_intr_reg intr_reg; 2157 uint16_t ena_qid; 2158 int i; 2159 2160 /* Unmask interrupts for all queues */ 2161 for (i = 0; i < adapter->num_queues; i++) { 2162 ena_qid = ENA_IO_TXQ_IDX(i); 2163 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 2164 ena_com_update_intr_reg(&intr_reg, 0, 0, true); 2165 ena_com_unmask_intr(io_cq, &intr_reg); 2166 } 2167 } 2168 2169 /* Configure the Rx forwarding */ 2170 static int 2171 ena_rss_configure(struct ena_adapter *adapter) 2172 { 2173 struct ena_com_dev *ena_dev = adapter->ena_dev; 2174 int rc; 2175 2176 /* Set indirect table */ 2177 rc = ena_com_indirect_table_set(ena_dev); 2178 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2179 return (rc); 2180 2181 /* Configure hash function (if supported) */ 2182 rc = ena_com_set_hash_function(ena_dev); 2183 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2184 return (rc); 2185 2186 /* Configure hash inputs (if supported) */ 2187 rc = ena_com_set_hash_ctrl(ena_dev); 2188 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2189 return (rc); 2190 2191 return (0); 2192 } 2193 2194 static int 2195 ena_up_complete(struct ena_adapter *adapter) 2196 { 2197 int rc; 2198 2199 if (likely(adapter->rss_support)) { 2200 rc = ena_rss_configure(adapter); 2201 if (rc != 0) 2202 return (rc); 2203 } 2204 2205 rc = ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu); 2206 if (unlikely(rc != 0)) 2207 return (rc); 2208 2209 ena_refill_all_rx_bufs(adapter); 2210 ena_reset_counters((struct evcnt *)&adapter->hw_stats, 2211 sizeof(adapter->hw_stats), 2212 offsetof(struct ena_hw_stats, rx_packets)); 2213 2214 return (0); 2215 } 2216 2217 static int 2218 ena_up(struct ena_adapter *adapter) 2219 { 2220 int rc = 0; 2221 2222 #if 0 2223 if (unlikely(device_is_attached(adapter->pdev) == 0)) { 2224 device_printf(adapter->pdev, "device is not attached!\n"); 2225 return (ENXIO); 2226 } 2227 #endif 2228 2229 if (unlikely(!adapter->running)) { 2230 device_printf(adapter->pdev, "device is not running!\n"); 2231 return (ENXIO); 2232 } 2233 2234 if (!adapter->up) { 2235 device_printf(adapter->pdev, "device is going UP\n"); 2236 2237 /* setup interrupts for IO queues */ 2238 rc = ena_request_io_irq(adapter); 2239 if (unlikely(rc != 0)) { 2240 ena_trace(ENA_ALERT, "err_req_irq"); 2241 goto err_req_irq; 2242 } 2243 2244 /* allocate transmit descriptors */ 2245 rc = ena_setup_all_tx_resources(adapter); 2246 if (unlikely(rc != 0)) { 2247 ena_trace(ENA_ALERT, "err_setup_tx"); 2248 goto err_setup_tx; 2249 } 2250 2251 /* allocate receive descriptors */ 2252 rc = ena_setup_all_rx_resources(adapter); 2253 if (unlikely(rc != 0)) { 2254 ena_trace(ENA_ALERT, "err_setup_rx"); 2255 goto err_setup_rx; 2256 } 2257 2258 /* create IO queues for Rx & Tx */ 2259 rc = ena_create_io_queues(adapter); 2260 if (unlikely(rc != 0)) { 2261 ena_trace(ENA_ALERT, 2262 "create IO queues failed"); 2263 goto err_io_que; 2264 } 2265 2266 if (unlikely(adapter->link_status)) 2267 if_link_state_change(adapter->ifp, LINK_STATE_UP); 2268 2269 rc = ena_up_complete(adapter); 2270 if (unlikely(rc != 0)) 2271 goto err_up_complete; 2272 2273 counter_u64_add(adapter->dev_stats.interface_up, 1); 2274 2275 ena_update_hwassist(adapter); 2276 2277 if_setdrvflagbits(adapter->ifp, IFF_RUNNING, 2278 IFF_OACTIVE); 2279 2280 callout_schedule(&adapter->timer_service, hz); 2281 2282 adapter->up = true; 2283 2284 ena_unmask_all_io_irqs(adapter); 2285 } 2286 2287 return (0); 2288 2289 err_up_complete: 2290 ena_destroy_all_io_queues(adapter); 2291 err_io_que: 2292 ena_free_all_rx_resources(adapter); 2293 err_setup_rx: 2294 ena_free_all_tx_resources(adapter); 2295 err_setup_tx: 2296 ena_free_io_irq(adapter); 2297 err_req_irq: 2298 return (rc); 2299 } 2300 2301 #if 0 2302 static uint64_t 2303 ena_get_counter(struct ifnet *ifp, ift_counter cnt) 2304 { 2305 struct ena_adapter *adapter; 2306 struct ena_hw_stats *stats; 2307 2308 adapter = if_getsoftc(ifp); 2309 stats = &adapter->hw_stats; 2310 2311 switch (cnt) { 2312 case IFCOUNTER_IPACKETS: 2313 return (counter_u64_fetch(stats->rx_packets)); 2314 case IFCOUNTER_OPACKETS: 2315 return (counter_u64_fetch(stats->tx_packets)); 2316 case IFCOUNTER_IBYTES: 2317 return (counter_u64_fetch(stats->rx_bytes)); 2318 case IFCOUNTER_OBYTES: 2319 return (counter_u64_fetch(stats->tx_bytes)); 2320 case IFCOUNTER_IQDROPS: 2321 return (counter_u64_fetch(stats->rx_drops)); 2322 default: 2323 return (if_get_counter_default(ifp, cnt)); 2324 } 2325 } 2326 #endif 2327 2328 static int 2329 ena_media_change(struct ifnet *ifp) 2330 { 2331 /* Media Change is not supported by firmware */ 2332 return (0); 2333 } 2334 2335 static void 2336 ena_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2337 { 2338 struct ena_adapter *adapter = if_getsoftc(ifp); 2339 ena_trace(ENA_DBG, "enter"); 2340 2341 mutex_enter(&adapter->global_mtx); 2342 2343 ifmr->ifm_status = IFM_AVALID; 2344 ifmr->ifm_active = IFM_ETHER; 2345 2346 if (!adapter->link_status) { 2347 mutex_exit(&adapter->global_mtx); 2348 ena_trace(ENA_INFO, "link_status = false"); 2349 return; 2350 } 2351 2352 ifmr->ifm_status |= IFM_ACTIVE; 2353 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2354 2355 mutex_exit(&adapter->global_mtx); 2356 } 2357 2358 static int 2359 ena_init(struct ifnet *ifp) 2360 { 2361 struct ena_adapter *adapter = if_getsoftc(ifp); 2362 2363 if (!adapter->up) { 2364 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2365 ena_up(adapter); 2366 rw_exit(&adapter->ioctl_sx); 2367 } 2368 2369 return 0; 2370 } 2371 2372 static int 2373 ena_ioctl(struct ifnet *ifp, u_long command, void *data) 2374 { 2375 struct ena_adapter *adapter; 2376 struct ifreq *ifr; 2377 int rc; 2378 2379 adapter = ifp->if_softc; 2380 ifr = (struct ifreq *)data; 2381 2382 /* 2383 * Acquiring lock to prevent from running up and down routines parallel. 2384 */ 2385 rc = 0; 2386 switch (command) { 2387 case SIOCSIFMTU: 2388 if (ifp->if_mtu == ifr->ifr_mtu) 2389 break; 2390 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2391 ena_down(adapter); 2392 2393 ena_change_mtu(ifp, ifr->ifr_mtu); 2394 2395 rc = ena_up(adapter); 2396 rw_exit(&adapter->ioctl_sx); 2397 break; 2398 2399 case SIOCSIFFLAGS: 2400 if ((ifp->if_flags & IFF_UP) != 0) { 2401 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2402 if ((ifp->if_flags & (IFF_PROMISC | 2403 IFF_ALLMULTI)) != 0) { 2404 device_printf(adapter->pdev, 2405 "ioctl promisc/allmulti\n"); 2406 } 2407 } else { 2408 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2409 rc = ena_up(adapter); 2410 rw_exit(&adapter->ioctl_sx); 2411 } 2412 } else { 2413 if ((if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2414 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2415 ena_down(adapter); 2416 rw_exit(&adapter->ioctl_sx); 2417 } 2418 } 2419 break; 2420 2421 case SIOCADDMULTI: 2422 case SIOCDELMULTI: 2423 break; 2424 2425 case SIOCSIFCAP: 2426 { 2427 struct ifcapreq *ifcr = data; 2428 int reinit = 0; 2429 2430 if (ifcr->ifcr_capenable != ifp->if_capenable) { 2431 ifp->if_capenable = ifcr->ifcr_capenable; 2432 reinit = 1; 2433 } 2434 2435 if ((reinit != 0) && 2436 ((if_getdrvflags(ifp) & IFF_RUNNING) != 0)) { 2437 rw_enter(&adapter->ioctl_sx, RW_WRITER); 2438 ena_down(adapter); 2439 rc = ena_up(adapter); 2440 rw_exit(&adapter->ioctl_sx); 2441 } 2442 } 2443 2444 break; 2445 default: 2446 rc = ether_ioctl(ifp, command, data); 2447 break; 2448 } 2449 2450 return (rc); 2451 } 2452 2453 static int 2454 ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *feat) 2455 { 2456 int caps = 0; 2457 2458 if ((feat->offload.tx & 2459 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2460 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK | 2461 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)) != 0) 2462 caps |= IFCAP_CSUM_IPv4_Tx; 2463 2464 if ((feat->offload.tx & 2465 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK | 2466 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)) != 0) 2467 caps |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 2468 2469 if ((feat->offload.tx & 2470 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0) 2471 caps |= IFCAP_TSOv4; 2472 2473 if ((feat->offload.tx & 2474 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) != 0) 2475 caps |= IFCAP_TSOv6; 2476 2477 if ((feat->offload.rx_supported & 2478 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK | 2479 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)) != 0) 2480 caps |= IFCAP_CSUM_IPv4_Rx; 2481 2482 if ((feat->offload.rx_supported & 2483 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) != 0) 2484 caps |= IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 2485 2486 caps |= IFCAP_LRO; 2487 2488 return (caps); 2489 } 2490 2491 static void 2492 ena_update_host_info(struct ena_admin_host_info *host_info, struct ifnet *ifp) 2493 { 2494 2495 host_info->supported_network_features[0] = 2496 (uint32_t)if_getcapabilities(ifp); 2497 } 2498 2499 static void 2500 ena_update_hwassist(struct ena_adapter *adapter) 2501 { 2502 struct ifnet *ifp = adapter->ifp; 2503 uint32_t feat = adapter->tx_offload_cap; 2504 int cap = if_getcapenable(ifp); 2505 int flags = 0; 2506 2507 if_clearhwassist(ifp); 2508 2509 if ((cap & (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2510 != 0) { 2511 if ((feat & 2512 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) != 0) 2513 flags |= M_CSUM_IPv4; 2514 if ((feat & 2515 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2516 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)) != 0) 2517 flags |= M_CSUM_TCPv4 | M_CSUM_UDPv4; 2518 } 2519 2520 if ((cap & IFCAP_CSUM_TCPv6_Tx) != 0) 2521 flags |= M_CSUM_TCPv6; 2522 2523 if ((cap & IFCAP_CSUM_UDPv6_Tx) != 0) 2524 flags |= M_CSUM_UDPv6; 2525 2526 if ((cap & IFCAP_TSOv4) != 0) 2527 flags |= M_CSUM_TSOv4; 2528 2529 if ((cap & IFCAP_TSOv6) != 0) 2530 flags |= M_CSUM_TSOv6; 2531 2532 if_sethwassistbits(ifp, flags, 0); 2533 } 2534 2535 static int 2536 ena_setup_ifnet(device_t pdev, struct ena_adapter *adapter, 2537 struct ena_com_dev_get_features_ctx *feat) 2538 { 2539 struct ifnet *ifp; 2540 int caps = 0; 2541 2542 ifp = adapter->ifp = &adapter->sc_ec.ec_if; 2543 if (unlikely(ifp == NULL)) { 2544 ena_trace(ENA_ALERT, "can not allocate ifnet structure\n"); 2545 return (ENXIO); 2546 } 2547 if_initname(ifp, "ena", device_unit(pdev)); 2548 if_setdev(ifp, pdev); 2549 if_setsoftc(ifp, adapter); 2550 2551 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2552 if_setinitfn(ifp, ena_init); 2553 if_settransmitfn(ifp, ena_mq_start); 2554 #if 0 2555 if_setqflushfn(ifp, ena_qflush); 2556 #endif 2557 if_setioctlfn(ifp, ena_ioctl); 2558 #if 0 2559 if_setgetcounterfn(ifp, ena_get_counter); 2560 #endif 2561 2562 if_setsendqlen(ifp, adapter->tx_ring_size); 2563 if_setsendqready(ifp); 2564 if_setmtu(ifp, ETHERMTU); 2565 if_setbaudrate(ifp, 0); 2566 /* Zeroize capabilities... */ 2567 if_setcapabilities(ifp, 0); 2568 if_setcapenable(ifp, 0); 2569 /* check hardware support */ 2570 caps = ena_get_dev_offloads(feat); 2571 /* ... and set them */ 2572 if_setcapabilitiesbit(ifp, caps, 0); 2573 adapter->sc_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2574 2575 #if 0 2576 /* TSO parameters */ 2577 /* XXX no limits on NetBSD, guarded by virtue of dmamap load failing */ 2578 ifp->if_hw_tsomax = ENA_TSO_MAXSIZE - 2579 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2580 ifp->if_hw_tsomaxsegcount = adapter->max_tx_sgl_size - 1; 2581 ifp->if_hw_tsomaxsegsize = ENA_TSO_MAXSIZE; 2582 #endif 2583 2584 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2585 if_setcapenable(ifp, if_getcapabilities(ifp)); 2586 2587 /* 2588 * Specify the media types supported by this adapter and register 2589 * callbacks to update media and link information 2590 */ 2591 adapter->sc_ec.ec_ifmedia = &adapter->media; 2592 ifmedia_init(&adapter->media, IFM_IMASK, 2593 ena_media_change, ena_media_status); 2594 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2595 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2596 2597 if_attach(ifp); 2598 if_deferred_start_init(ifp, NULL); 2599 2600 ether_ifattach(ifp, adapter->mac_addr); 2601 2602 return (0); 2603 } 2604 2605 static void 2606 ena_down(struct ena_adapter *adapter) 2607 { 2608 int rc; 2609 2610 if (adapter->up) { 2611 device_printf(adapter->pdev, "device is going DOWN\n"); 2612 2613 callout_halt(&adapter->timer_service, &adapter->global_mtx); 2614 2615 adapter->up = false; 2616 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, 2617 IFF_RUNNING); 2618 2619 ena_free_io_irq(adapter); 2620 2621 if (adapter->trigger_reset) { 2622 rc = ena_com_dev_reset(adapter->ena_dev, 2623 adapter->reset_reason); 2624 if (unlikely(rc != 0)) 2625 device_printf(adapter->pdev, 2626 "Device reset failed\n"); 2627 } 2628 2629 ena_destroy_all_io_queues(adapter); 2630 2631 ena_free_all_tx_bufs(adapter); 2632 ena_free_all_rx_bufs(adapter); 2633 ena_free_all_tx_resources(adapter); 2634 ena_free_all_rx_resources(adapter); 2635 2636 counter_u64_add(adapter->dev_stats.interface_down, 1); 2637 } 2638 } 2639 2640 static void 2641 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf) 2642 { 2643 struct ena_com_tx_meta *ena_meta; 2644 struct ether_vlan_header *eh; 2645 u32 mss; 2646 bool offload; 2647 uint16_t etype; 2648 int ehdrlen; 2649 struct ip *ip; 2650 int iphlen; 2651 struct tcphdr *th; 2652 2653 offload = false; 2654 ena_meta = &ena_tx_ctx->ena_meta; 2655 2656 #if 0 2657 u32 mss = mbuf->m_pkthdr.tso_segsz; 2658 2659 if (mss != 0) 2660 offload = true; 2661 #else 2662 mss = mbuf->m_pkthdr.len; /* XXX don't have tso_segsz */ 2663 #endif 2664 2665 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) 2666 offload = true; 2667 2668 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 2669 offload = true; 2670 2671 if (!offload) { 2672 ena_tx_ctx->meta_valid = 0; 2673 return; 2674 } 2675 2676 /* Determine where frame payload starts. */ 2677 eh = mtod(mbuf, struct ether_vlan_header *); 2678 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2679 etype = ntohs(eh->evl_proto); 2680 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2681 } else { 2682 etype = htons(eh->evl_encap_proto); 2683 ehdrlen = ETHER_HDR_LEN; 2684 } 2685 2686 ip = (struct ip *)(mbuf->m_data + ehdrlen); 2687 iphlen = ip->ip_hl << 2; 2688 th = (struct tcphdr *)((vaddr_t)ip + iphlen); 2689 2690 if ((mbuf->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 2691 ena_tx_ctx->l3_csum_enable = 1; 2692 } 2693 if ((mbuf->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 2694 ena_tx_ctx->tso_enable = 1; 2695 ena_meta->l4_hdr_len = (th->th_off); 2696 } 2697 2698 switch (etype) { 2699 case ETHERTYPE_IP: 2700 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 2701 if ((ip->ip_off & htons(IP_DF)) != 0) 2702 ena_tx_ctx->df = 1; 2703 break; 2704 case ETHERTYPE_IPV6: 2705 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 2706 2707 default: 2708 break; 2709 } 2710 2711 if (ip->ip_p == IPPROTO_TCP) { 2712 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 2713 if ((mbuf->m_pkthdr.csum_flags & 2714 (M_CSUM_TCPv4 | M_CSUM_TCPv6)) != 0) 2715 ena_tx_ctx->l4_csum_enable = 1; 2716 else 2717 ena_tx_ctx->l4_csum_enable = 0; 2718 } else if (ip->ip_p == IPPROTO_UDP) { 2719 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 2720 if ((mbuf->m_pkthdr.csum_flags & 2721 (M_CSUM_UDPv4 | M_CSUM_UDPv6)) != 0) 2722 ena_tx_ctx->l4_csum_enable = 1; 2723 else 2724 ena_tx_ctx->l4_csum_enable = 0; 2725 } else { 2726 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 2727 ena_tx_ctx->l4_csum_enable = 0; 2728 } 2729 2730 ena_meta->mss = mss; 2731 ena_meta->l3_hdr_len = iphlen; 2732 ena_meta->l3_hdr_offset = ehdrlen; 2733 ena_tx_ctx->meta_valid = 1; 2734 } 2735 2736 static int 2737 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2738 { 2739 struct ena_adapter *adapter; 2740 struct mbuf *collapsed_mbuf; 2741 int num_frags; 2742 2743 adapter = tx_ring->adapter; 2744 num_frags = ena_mbuf_count(*mbuf); 2745 2746 /* One segment must be reserved for configuration descriptor. */ 2747 if (num_frags < adapter->max_tx_sgl_size) 2748 return (0); 2749 counter_u64_add(tx_ring->tx_stats.collapse, 1); 2750 2751 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 2752 adapter->max_tx_sgl_size - 1); 2753 if (unlikely(collapsed_mbuf == NULL)) { 2754 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 2755 return (ENOMEM); 2756 } 2757 2758 /* If mbuf was collapsed succesfully, original mbuf is released. */ 2759 *mbuf = collapsed_mbuf; 2760 2761 return (0); 2762 } 2763 2764 static int 2765 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2766 { 2767 struct ena_adapter *adapter; 2768 struct ena_tx_buffer *tx_info; 2769 struct ena_com_tx_ctx ena_tx_ctx; 2770 struct ena_com_dev *ena_dev; 2771 struct ena_com_buf *ena_buf; 2772 struct ena_com_io_sq* io_sq; 2773 void *push_hdr; 2774 uint16_t next_to_use; 2775 uint16_t req_id; 2776 uint16_t ena_qid; 2777 uint32_t header_len; 2778 int i, rc; 2779 int nb_hw_desc; 2780 2781 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2782 adapter = tx_ring->que->adapter; 2783 ena_dev = adapter->ena_dev; 2784 io_sq = &ena_dev->io_sq_queues[ena_qid]; 2785 2786 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 2787 if (unlikely(rc != 0)) { 2788 ena_trace(ENA_WARNING, 2789 "Failed to collapse mbuf! err: %d", rc); 2790 return (rc); 2791 } 2792 2793 next_to_use = tx_ring->next_to_use; 2794 req_id = tx_ring->free_tx_ids[next_to_use]; 2795 tx_info = &tx_ring->tx_buffer_info[req_id]; 2796 2797 tx_info->mbuf = *mbuf; 2798 tx_info->num_of_bufs = 0; 2799 2800 ena_buf = tx_info->bufs; 2801 2802 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes", (*mbuf)->m_pkthdr.len); 2803 2804 /* 2805 * header_len is just a hint for the device. Because FreeBSD is not 2806 * giving us information about packet header length and it is not 2807 * guaranteed that all packet headers will be in the 1st mbuf, setting 2808 * header_len to 0 is making the device ignore this value and resolve 2809 * header on it's own. 2810 */ 2811 header_len = 0; 2812 push_hdr = NULL; 2813 2814 rc = bus_dmamap_load_mbuf(adapter->sc_dmat, tx_info->map, 2815 *mbuf, BUS_DMA_NOWAIT); 2816 2817 if (unlikely((rc != 0) || (tx_info->map->dm_nsegs == 0))) { 2818 ena_trace(ENA_WARNING, 2819 "dmamap load failed! err: %d nsegs: %d", rc, 2820 tx_info->map->dm_nsegs); 2821 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 2822 tx_info->mbuf = NULL; 2823 if (rc == ENOMEM) 2824 return (ENA_COM_NO_MEM); 2825 else 2826 return (ENA_COM_INVAL); 2827 } 2828 2829 for (i = 0; i < tx_info->map->dm_nsegs; i++) { 2830 ena_buf->len = tx_info->map->dm_segs[i].ds_len; 2831 ena_buf->paddr = tx_info->map->dm_segs[i].ds_addr; 2832 ena_buf++; 2833 } 2834 tx_info->num_of_bufs = tx_info->map->dm_nsegs; 2835 2836 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2837 ena_tx_ctx.ena_bufs = tx_info->bufs; 2838 ena_tx_ctx.push_header = push_hdr; 2839 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2840 ena_tx_ctx.req_id = req_id; 2841 ena_tx_ctx.header_len = header_len; 2842 2843 /* Set flags and meta data */ 2844 ena_tx_csum(&ena_tx_ctx, *mbuf); 2845 /* Prepare the packet's descriptors and send them to device */ 2846 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 2847 if (unlikely(rc != 0)) { 2848 device_printf(adapter->pdev, "failed to prepare tx bufs\n"); 2849 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 2850 goto dma_error; 2851 } 2852 2853 counter_enter(); 2854 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 2855 counter_u64_add_protected(tx_ring->tx_stats.bytes, 2856 (*mbuf)->m_pkthdr.len); 2857 2858 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 2859 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 2860 (*mbuf)->m_pkthdr.len); 2861 counter_exit(); 2862 2863 tx_info->tx_descs = nb_hw_desc; 2864 getbinuptime(&tx_info->timestamp); 2865 tx_info->print_once = true; 2866 2867 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2868 tx_ring->ring_size); 2869 2870 bus_dmamap_sync(adapter->sc_dmat, tx_info->map, 0, 2871 tx_info->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2872 2873 return (0); 2874 2875 dma_error: 2876 tx_info->mbuf = NULL; 2877 bus_dmamap_unload(adapter->sc_dmat, tx_info->map); 2878 2879 return (rc); 2880 } 2881 2882 static void 2883 ena_start_xmit(struct ena_ring *tx_ring) 2884 { 2885 struct mbuf *mbuf; 2886 struct ena_adapter *adapter = tx_ring->adapter; 2887 struct ena_com_io_sq* io_sq; 2888 int ena_qid; 2889 int acum_pkts = 0; 2890 int ret = 0; 2891 2892 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2893 return; 2894 2895 if (unlikely(!adapter->link_status)) 2896 return; 2897 2898 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2899 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 2900 2901 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 2902 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 2903 " header csum flags %#jx", 2904 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 2905 2906 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 2907 ENA_TX_CLEANUP_THRESHOLD))) 2908 ena_tx_cleanup(tx_ring); 2909 2910 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 2911 if (ret == ENA_COM_NO_MEM) { 2912 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2913 } else if (ret == ENA_COM_NO_SPACE) { 2914 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2915 } else { 2916 m_freem(mbuf); 2917 drbr_advance(adapter->ifp, tx_ring->br); 2918 } 2919 2920 break; 2921 } 2922 2923 drbr_advance(adapter->ifp, tx_ring->br); 2924 2925 if (unlikely((if_getdrvflags(adapter->ifp) & 2926 IFF_RUNNING) == 0)) 2927 return; 2928 2929 acum_pkts++; 2930 2931 /* 2932 * If there's a BPF listener, bounce a copy of this frame 2933 * to him. 2934 */ 2935 bpf_mtap(adapter->ifp, mbuf, BPF_D_OUT); 2936 2937 if (unlikely(acum_pkts == DB_THRESHOLD)) { 2938 acum_pkts = 0; 2939 wmb(); 2940 /* Trigger the dma engine */ 2941 ena_com_write_sq_doorbell(io_sq); 2942 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2943 } 2944 2945 } 2946 2947 if (likely(acum_pkts != 0)) { 2948 wmb(); 2949 /* Trigger the dma engine */ 2950 ena_com_write_sq_doorbell(io_sq); 2951 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2952 } 2953 2954 if (!ena_com_sq_have_enough_space(io_sq, ENA_TX_CLEANUP_THRESHOLD)) 2955 ena_tx_cleanup(tx_ring); 2956 } 2957 2958 static void 2959 ena_deferred_mq_start(struct work *wk, void *arg) 2960 { 2961 struct ena_ring *tx_ring = (struct ena_ring *)arg; 2962 struct ifnet *ifp = tx_ring->adapter->ifp; 2963 2964 atomic_swap_uint(&tx_ring->task_pending, 0); 2965 2966 while (!drbr_empty(ifp, tx_ring->br) && 2967 (if_getdrvflags(ifp) & IFF_RUNNING) != 0) { 2968 ENA_RING_MTX_LOCK(tx_ring); 2969 ena_start_xmit(tx_ring); 2970 ENA_RING_MTX_UNLOCK(tx_ring); 2971 } 2972 } 2973 2974 static int 2975 ena_mq_start(struct ifnet *ifp, struct mbuf *m) 2976 { 2977 struct ena_adapter *adapter = ifp->if_softc; 2978 struct ena_ring *tx_ring; 2979 int ret, is_drbr_empty; 2980 uint32_t i; 2981 2982 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_RUNNING) == 0)) 2983 return (ENODEV); 2984 2985 /* Which queue to use */ 2986 /* 2987 * If everything is setup correctly, it should be the 2988 * same bucket that the current CPU we're on is. 2989 * It should improve performance. 2990 */ 2991 #if 0 2992 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 2993 #ifdef RSS 2994 if (rss_hash2bucket(m->m_pkthdr.flowid, 2995 M_HASHTYPE_GET(m), &i) == 0) { 2996 i = i % adapter->num_queues; 2997 2998 } else 2999 #endif 3000 { 3001 i = m->m_pkthdr.flowid % adapter->num_queues; 3002 } 3003 } else { 3004 #endif 3005 i = cpu_index(curcpu()) % adapter->num_queues; 3006 #if 0 3007 } 3008 #endif 3009 tx_ring = &adapter->tx_ring[i]; 3010 3011 /* Check if drbr is empty before putting packet */ 3012 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 3013 ret = drbr_enqueue(ifp, tx_ring->br, m); 3014 if (unlikely(ret != 0)) { 3015 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 3016 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 3017 curcpu()); 3018 return (ret); 3019 } 3020 3021 if ((is_drbr_empty != 0) && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 3022 ena_start_xmit(tx_ring); 3023 ENA_RING_MTX_UNLOCK(tx_ring); 3024 } else { 3025 if (atomic_cas_uint(&tx_ring->task_pending, 0, 1) == 0) 3026 workqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 3027 curcpu()); 3028 } 3029 3030 return (0); 3031 } 3032 3033 #if 0 3034 static void 3035 ena_qflush(struct ifnet *ifp) 3036 { 3037 struct ena_adapter *adapter = ifp->if_softc; 3038 struct ena_ring *tx_ring = adapter->tx_ring; 3039 int i; 3040 3041 for(i = 0; i < adapter->num_queues; ++i, ++tx_ring) 3042 if (!drbr_empty(ifp, tx_ring->br)) { 3043 ENA_RING_MTX_LOCK(tx_ring); 3044 drbr_flush(ifp, tx_ring->br); 3045 ENA_RING_MTX_UNLOCK(tx_ring); 3046 } 3047 3048 if_qflush(ifp); 3049 } 3050 #endif 3051 3052 static int 3053 ena_calc_io_queue_num(struct pci_attach_args *pa, 3054 struct ena_adapter *adapter, 3055 struct ena_com_dev_get_features_ctx *get_feat_ctx) 3056 { 3057 int io_sq_num, io_cq_num, io_queue_num; 3058 3059 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 3060 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 3061 3062 io_queue_num = min_t(int, mp_ncpus, ENA_MAX_NUM_IO_QUEUES); 3063 io_queue_num = min_t(int, io_queue_num, io_sq_num); 3064 io_queue_num = min_t(int, io_queue_num, io_cq_num); 3065 /* 1 IRQ for for mgmnt and 1 IRQ for each TX/RX pair */ 3066 io_queue_num = min_t(int, io_queue_num, 3067 pci_msix_count(pa->pa_pc, pa->pa_tag) - 1); 3068 #ifdef RSS 3069 io_queue_num = min_t(int, io_queue_num, rss_getnumbuckets()); 3070 #endif 3071 3072 return (io_queue_num); 3073 } 3074 3075 static int 3076 ena_calc_queue_size(struct ena_adapter *adapter, uint16_t *max_tx_sgl_size, 3077 uint16_t *max_rx_sgl_size, struct ena_com_dev_get_features_ctx *feat) 3078 { 3079 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 3080 uint32_t v; 3081 uint32_t q; 3082 3083 queue_size = min_t(uint32_t, queue_size, 3084 feat->max_queues.max_cq_depth); 3085 queue_size = min_t(uint32_t, queue_size, 3086 feat->max_queues.max_sq_depth); 3087 3088 /* round down to the nearest power of 2 */ 3089 v = queue_size; 3090 while (v != 0) { 3091 if (powerof2(queue_size) != 0) 3092 break; 3093 v /= 2; 3094 q = rounddown2(queue_size, v); 3095 if (q != 0) { 3096 queue_size = q; 3097 break; 3098 } 3099 } 3100 3101 if (unlikely(queue_size == 0)) { 3102 device_printf(adapter->pdev, "Invalid queue size\n"); 3103 return (ENA_COM_FAULT); 3104 } 3105 3106 *max_tx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3107 feat->max_queues.max_packet_tx_descs); 3108 *max_rx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3109 feat->max_queues.max_packet_rx_descs); 3110 3111 return (queue_size); 3112 } 3113 3114 #if 0 3115 static int 3116 ena_rss_init_default(struct ena_adapter *adapter) 3117 { 3118 struct ena_com_dev *ena_dev = adapter->ena_dev; 3119 device_t dev = adapter->pdev; 3120 int qid, rc, i; 3121 3122 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3123 if (unlikely(rc != 0)) { 3124 device_printf(dev, "Cannot init indirect table\n"); 3125 return (rc); 3126 } 3127 3128 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3129 #ifdef RSS 3130 qid = rss_get_indirection_to_bucket(i); 3131 qid = qid % adapter->num_queues; 3132 #else 3133 qid = i % adapter->num_queues; 3134 #endif 3135 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3136 ENA_IO_RXQ_IDX(qid)); 3137 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3138 device_printf(dev, "Cannot fill indirect table\n"); 3139 goto err_rss_destroy; 3140 } 3141 } 3142 3143 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3144 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3145 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3146 device_printf(dev, "Cannot fill hash function\n"); 3147 goto err_rss_destroy; 3148 } 3149 3150 rc = ena_com_set_default_hash_ctrl(ena_dev); 3151 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3152 device_printf(dev, "Cannot fill hash control\n"); 3153 goto err_rss_destroy; 3154 } 3155 3156 return (0); 3157 3158 err_rss_destroy: 3159 ena_com_rss_destroy(ena_dev); 3160 return (rc); 3161 } 3162 3163 static void 3164 ena_rss_init_default_deferred(void *arg) 3165 { 3166 struct ena_adapter *adapter; 3167 devclass_t dc; 3168 int max; 3169 int rc; 3170 3171 dc = devclass_find("ena"); 3172 if (unlikely(dc == NULL)) { 3173 ena_trace(ENA_ALERT, "No devclass ena\n"); 3174 return; 3175 } 3176 3177 max = devclass_get_maxunit(dc); 3178 while (max-- >= 0) { 3179 adapter = devclass_get_softc(dc, max); 3180 if (adapter != NULL) { 3181 rc = ena_rss_init_default(adapter); 3182 adapter->rss_support = true; 3183 if (unlikely(rc != 0)) { 3184 device_printf(adapter->pdev, 3185 "WARNING: RSS was not properly initialized," 3186 " it will affect bandwidth\n"); 3187 adapter->rss_support = false; 3188 } 3189 } 3190 } 3191 } 3192 SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL); 3193 #endif 3194 3195 static void 3196 ena_config_host_info(struct ena_com_dev *ena_dev) 3197 { 3198 struct ena_admin_host_info *host_info; 3199 int rc; 3200 3201 /* Allocate only the host info */ 3202 rc = ena_com_allocate_host_info(ena_dev); 3203 if (unlikely(rc != 0)) { 3204 ena_trace(ENA_ALERT, "Cannot allocate host info\n"); 3205 return; 3206 } 3207 3208 host_info = ena_dev->host_attr.host_info; 3209 3210 host_info->os_type = ENA_ADMIN_OS_FREEBSD; 3211 host_info->kernel_ver = osreldate; 3212 3213 snprintf(host_info->kernel_ver_str, sizeof(host_info->kernel_ver_str), 3214 "%d", osreldate); 3215 host_info->os_dist = 0; 3216 strncpy(host_info->os_dist_str, osrelease, 3217 sizeof(host_info->os_dist_str) - 1); 3218 3219 host_info->driver_version = 3220 (DRV_MODULE_VER_MAJOR) | 3221 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 3222 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 3223 3224 rc = ena_com_set_host_attributes(ena_dev); 3225 if (unlikely(rc != 0)) { 3226 if (rc == EOPNOTSUPP) 3227 ena_trace(ENA_WARNING, "Cannot set host attributes\n"); 3228 else 3229 ena_trace(ENA_ALERT, "Cannot set host attributes\n"); 3230 3231 goto err; 3232 } 3233 3234 return; 3235 3236 err: 3237 ena_com_delete_host_info(ena_dev); 3238 } 3239 3240 static int 3241 ena_device_init(struct ena_adapter *adapter, device_t pdev, 3242 struct ena_com_dev_get_features_ctx *get_feat_ctx, int *wd_active) 3243 { 3244 struct ena_com_dev* ena_dev = adapter->ena_dev; 3245 bool readless_supported; 3246 uint32_t aenq_groups; 3247 int dma_width; 3248 int rc; 3249 3250 rc = ena_com_mmio_reg_read_request_init(ena_dev); 3251 if (unlikely(rc != 0)) { 3252 device_printf(pdev, "failed to init mmio read less\n"); 3253 return (rc); 3254 } 3255 3256 /* 3257 * The PCIe configuration space revision id indicate if mmio reg 3258 * read is disabled 3259 */ 3260 const int rev = PCI_REVISION(adapter->sc_pa.pa_class); 3261 readless_supported = ((rev & ENA_MMIO_DISABLE_REG_READ) == 0); 3262 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 3263 3264 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 3265 if (unlikely(rc != 0)) { 3266 device_printf(pdev, "Can not reset device\n"); 3267 goto err_mmio_read_less; 3268 } 3269 3270 rc = ena_com_validate_version(ena_dev); 3271 if (unlikely(rc != 0)) { 3272 device_printf(pdev, "device version is too low\n"); 3273 goto err_mmio_read_less; 3274 } 3275 3276 dma_width = ena_com_get_dma_width(ena_dev); 3277 if (unlikely(dma_width < 0)) { 3278 device_printf(pdev, "Invalid dma width value %d", dma_width); 3279 rc = dma_width; 3280 goto err_mmio_read_less; 3281 } 3282 adapter->dma_width = dma_width; 3283 3284 /* ENA admin level init */ 3285 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 3286 if (unlikely(rc != 0)) { 3287 device_printf(pdev, 3288 "Can not initialize ena admin queue with device\n"); 3289 goto err_mmio_read_less; 3290 } 3291 3292 /* 3293 * To enable the msix interrupts the driver needs to know the number 3294 * of queues. So the driver uses polling mode to retrieve this 3295 * information 3296 */ 3297 ena_com_set_admin_polling_mode(ena_dev, true); 3298 3299 ena_config_host_info(ena_dev); 3300 3301 /* Get Device Attributes */ 3302 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 3303 if (unlikely(rc != 0)) { 3304 device_printf(pdev, 3305 "Cannot get attribute for ena device rc: %d\n", rc); 3306 goto err_admin_init; 3307 } 3308 3309 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | BIT(ENA_ADMIN_KEEP_ALIVE); 3310 3311 aenq_groups &= get_feat_ctx->aenq.supported_groups; 3312 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 3313 if (unlikely(rc != 0)) { 3314 device_printf(pdev, "Cannot configure aenq groups rc: %d\n", rc); 3315 goto err_admin_init; 3316 } 3317 3318 *wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 3319 3320 return (0); 3321 3322 err_admin_init: 3323 ena_com_delete_host_info(ena_dev); 3324 ena_com_admin_destroy(ena_dev); 3325 err_mmio_read_less: 3326 ena_com_mmio_reg_read_request_destroy(ena_dev); 3327 3328 return (rc); 3329 } 3330 3331 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 3332 int io_vectors) 3333 { 3334 struct ena_com_dev *ena_dev = adapter->ena_dev; 3335 int rc; 3336 3337 rc = ena_enable_msix(adapter); 3338 if (unlikely(rc != 0)) { 3339 device_printf(adapter->pdev, "Error with MSI-X enablement\n"); 3340 return (rc); 3341 } 3342 3343 rc = ena_request_mgmnt_irq(adapter); 3344 if (unlikely(rc != 0)) { 3345 device_printf(adapter->pdev, "Cannot setup mgmnt queue intr\n"); 3346 goto err_disable_msix; 3347 } 3348 3349 ena_com_set_admin_polling_mode(ena_dev, false); 3350 3351 ena_com_admin_aenq_enable(ena_dev); 3352 3353 return (0); 3354 3355 err_disable_msix: 3356 ena_disable_msix(adapter); 3357 3358 return (rc); 3359 } 3360 3361 /* Function called on ENA_ADMIN_KEEP_ALIVE event */ 3362 static void ena_keep_alive_wd(void *adapter_data, 3363 struct ena_admin_aenq_entry *aenq_e) 3364 { 3365 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3366 struct ena_admin_aenq_keep_alive_desc *desc; 3367 uint64_t rx_drops; 3368 3369 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3370 3371 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3372 counter_u64_zero(adapter->hw_stats.rx_drops); 3373 counter_u64_add(adapter->hw_stats.rx_drops, rx_drops); 3374 3375 atomic_store_release(&adapter->keep_alive_timestamp, getsbinuptime()); 3376 } 3377 3378 /* Check for keep alive expiration */ 3379 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 3380 { 3381 sbintime_t timestamp, time; 3382 3383 if (adapter->wd_active == 0) 3384 return; 3385 3386 if (likely(adapter->keep_alive_timeout == 0)) 3387 return; 3388 3389 timestamp = atomic_load_acquire(&adapter->keep_alive_timestamp); 3390 3391 time = getsbinuptime() - timestamp; 3392 if (unlikely(time > adapter->keep_alive_timeout)) { 3393 device_printf(adapter->pdev, 3394 "Keep alive watchdog timeout.\n"); 3395 counter_u64_add(adapter->dev_stats.wd_expired, 1); 3396 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 3397 adapter->trigger_reset = true; 3398 } 3399 } 3400 3401 /* Check if admin queue is enabled */ 3402 static void check_for_admin_com_state(struct ena_adapter *adapter) 3403 { 3404 if (unlikely(ena_com_get_admin_running_state(adapter->ena_dev) == 3405 false)) { 3406 device_printf(adapter->pdev, 3407 "ENA admin queue is not in running state!\n"); 3408 counter_u64_add(adapter->dev_stats.admin_q_pause, 1); 3409 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 3410 adapter->trigger_reset = true; 3411 } 3412 } 3413 3414 static int 3415 check_missing_comp_in_queue(struct ena_adapter *adapter, 3416 struct ena_ring *tx_ring) 3417 { 3418 struct bintime curtime, time; 3419 struct ena_tx_buffer *tx_buf; 3420 uint32_t missed_tx = 0; 3421 int i; 3422 3423 getbinuptime(&curtime); 3424 3425 for (i = 0; i < tx_ring->ring_size; i++) { 3426 tx_buf = &tx_ring->tx_buffer_info[i]; 3427 3428 if (bintime_isset(&tx_buf->timestamp) == 0) 3429 continue; 3430 3431 time = curtime; 3432 bintime_sub(&time, &tx_buf->timestamp); 3433 3434 /* Check again if packet is still waiting */ 3435 if (unlikely(bttosbt(time) > adapter->missing_tx_timeout)) { 3436 3437 if (!tx_buf->print_once) 3438 ena_trace(ENA_WARNING, "Found a Tx that wasn't " 3439 "completed on time, qid %d, index %d.\n", 3440 tx_ring->qid, i); 3441 3442 tx_buf->print_once = true; 3443 missed_tx++; 3444 counter_u64_add(tx_ring->tx_stats.missing_tx_comp, 1); 3445 3446 if (unlikely(missed_tx > 3447 adapter->missing_tx_threshold)) { 3448 device_printf(adapter->pdev, 3449 "The number of lost tx completion " 3450 "is above the threshold (%d > %d). " 3451 "Reset the device\n", 3452 missed_tx, adapter->missing_tx_threshold); 3453 adapter->reset_reason = 3454 ENA_REGS_RESET_MISS_TX_CMPL; 3455 adapter->trigger_reset = true; 3456 return (EIO); 3457 } 3458 } 3459 } 3460 3461 return (0); 3462 } 3463 3464 /* 3465 * Check for TX which were not completed on time. 3466 * Timeout is defined by "missing_tx_timeout". 3467 * Reset will be performed if number of incompleted 3468 * transactions exceeds "missing_tx_threshold". 3469 */ 3470 static void 3471 check_for_missing_tx_completions(struct ena_adapter *adapter) 3472 { 3473 struct ena_ring *tx_ring; 3474 int i, budget, rc; 3475 3476 /* Make sure the driver doesn't turn the device in other process */ 3477 rmb(); 3478 3479 if (!adapter->up) 3480 return; 3481 3482 if (adapter->trigger_reset) 3483 return; 3484 3485 if (adapter->missing_tx_timeout == 0) 3486 return; 3487 3488 budget = adapter->missing_tx_max_queues; 3489 3490 for (i = adapter->next_monitored_tx_qid; i < adapter->num_queues; i++) { 3491 tx_ring = &adapter->tx_ring[i]; 3492 3493 rc = check_missing_comp_in_queue(adapter, tx_ring); 3494 if (unlikely(rc != 0)) 3495 return; 3496 3497 budget--; 3498 if (budget == 0) { 3499 i++; 3500 break; 3501 } 3502 } 3503 3504 adapter->next_monitored_tx_qid = i % adapter->num_queues; 3505 } 3506 3507 /* trigger deferred rx cleanup after 2 consecutive detections */ 3508 #define EMPTY_RX_REFILL 2 3509 /* For the rare case where the device runs out of Rx descriptors and the 3510 * msix handler failed to refill new Rx descriptors (due to a lack of memory 3511 * for example). 3512 * This case will lead to a deadlock: 3513 * The device won't send interrupts since all the new Rx packets will be dropped 3514 * The msix handler won't allocate new Rx descriptors so the device won't be 3515 * able to send new packets. 3516 * 3517 * When such a situation is detected - execute rx cleanup task in another thread 3518 */ 3519 static void 3520 check_for_empty_rx_ring(struct ena_adapter *adapter) 3521 { 3522 struct ena_ring *rx_ring; 3523 int i, refill_required; 3524 3525 if (!adapter->up) 3526 return; 3527 3528 if (adapter->trigger_reset) 3529 return; 3530 3531 for (i = 0; i < adapter->num_queues; i++) { 3532 rx_ring = &adapter->rx_ring[i]; 3533 3534 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 3535 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 3536 rx_ring->empty_rx_queue++; 3537 3538 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 3539 counter_u64_add(rx_ring->rx_stats.empty_rx_ring, 3540 1); 3541 3542 device_printf(adapter->pdev, 3543 "trigger refill for ring %d\n", i); 3544 3545 if (atomic_cas_uint(&rx_ring->task_pending, 0, 1) == 0) 3546 workqueue_enqueue(rx_ring->cmpl_tq, 3547 &rx_ring->cmpl_task, curcpu()); 3548 rx_ring->empty_rx_queue = 0; 3549 } 3550 } else { 3551 rx_ring->empty_rx_queue = 0; 3552 } 3553 } 3554 } 3555 3556 static void 3557 ena_timer_service(void *data) 3558 { 3559 struct ena_adapter *adapter = (struct ena_adapter *)data; 3560 struct ena_admin_host_info *host_info = 3561 adapter->ena_dev->host_attr.host_info; 3562 3563 check_for_missing_keep_alive(adapter); 3564 3565 check_for_admin_com_state(adapter); 3566 3567 check_for_missing_tx_completions(adapter); 3568 3569 check_for_empty_rx_ring(adapter); 3570 3571 if (host_info != NULL) 3572 ena_update_host_info(host_info, adapter->ifp); 3573 3574 if (unlikely(adapter->trigger_reset)) { 3575 device_printf(adapter->pdev, "Trigger reset is on\n"); 3576 workqueue_enqueue(adapter->reset_tq, &adapter->reset_task, 3577 curcpu()); 3578 return; 3579 } 3580 3581 /* 3582 * Schedule another timeout one second from now. 3583 */ 3584 callout_schedule(&adapter->timer_service, hz); 3585 } 3586 3587 static void 3588 ena_reset_task(struct work *wk, void *arg) 3589 { 3590 struct ena_com_dev_get_features_ctx get_feat_ctx; 3591 struct ena_adapter *adapter = (struct ena_adapter *)arg; 3592 struct ena_com_dev *ena_dev = adapter->ena_dev; 3593 bool dev_up; 3594 int rc; 3595 3596 if (unlikely(!adapter->trigger_reset)) { 3597 device_printf(adapter->pdev, 3598 "device reset scheduled but trigger_reset is off\n"); 3599 return; 3600 } 3601 3602 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3603 3604 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3605 3606 dev_up = adapter->up; 3607 3608 ena_com_set_admin_running_state(ena_dev, false); 3609 ena_down(adapter); 3610 ena_free_mgmnt_irq(adapter); 3611 ena_disable_msix(adapter); 3612 ena_com_abort_admin_commands(ena_dev); 3613 ena_com_wait_for_abort_completion(ena_dev); 3614 ena_com_admin_destroy(ena_dev); 3615 ena_com_mmio_reg_read_request_destroy(ena_dev); 3616 3617 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3618 adapter->trigger_reset = false; 3619 3620 /* Finished destroy part. Restart the device */ 3621 rc = ena_device_init(adapter, adapter->pdev, &get_feat_ctx, 3622 &adapter->wd_active); 3623 if (unlikely(rc != 0)) { 3624 device_printf(adapter->pdev, 3625 "ENA device init failed! (err: %d)\n", rc); 3626 goto err_dev_free; 3627 } 3628 3629 /* XXX dealloc and realloc MSI-X, probably a waste */ 3630 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 3631 adapter->num_queues); 3632 if (unlikely(rc != 0)) { 3633 device_printf(adapter->pdev, "Enable MSI-X failed\n"); 3634 goto err_com_free; 3635 } 3636 3637 /* If the interface was up before the reset bring it up */ 3638 if (dev_up) { 3639 rc = ena_up(adapter); 3640 if (unlikely(rc != 0)) { 3641 device_printf(adapter->pdev, 3642 "Failed to create I/O queues\n"); 3643 goto err_msix_free; 3644 } 3645 } 3646 3647 callout_schedule(&adapter->timer_service, hz); 3648 3649 rw_exit(&adapter->ioctl_sx); 3650 3651 return; 3652 3653 err_msix_free: 3654 ena_free_mgmnt_irq(adapter); 3655 ena_disable_msix(adapter); 3656 err_com_free: 3657 ena_com_admin_destroy(ena_dev); 3658 err_dev_free: 3659 device_printf(adapter->pdev, "ENA reset failed!\n"); 3660 adapter->running = false; 3661 rw_exit(&adapter->ioctl_sx); 3662 } 3663 3664 /** 3665 * ena_attach - Device Initialization Routine 3666 * @pdev: device information struct 3667 * 3668 * Returns 0 on success, otherwise on failure. 3669 * 3670 * ena_attach initializes an adapter identified by a device structure. 3671 * The OS initialization, configuring of the adapter private structure, 3672 * and a hardware reset occur. 3673 **/ 3674 static void 3675 ena_attach(device_t parent, device_t self, void *aux) 3676 { 3677 struct pci_attach_args *pa = aux; 3678 struct ena_com_dev_get_features_ctx get_feat_ctx; 3679 static int version_printed; 3680 struct ena_adapter *adapter = device_private(self); 3681 struct ena_com_dev *ena_dev = NULL; 3682 uint16_t tx_sgl_size = 0; 3683 uint16_t rx_sgl_size = 0; 3684 pcireg_t reg; 3685 int io_queue_num; 3686 int queue_size; 3687 int rc; 3688 3689 adapter->pdev = self; 3690 adapter->ifp = &adapter->sc_ec.ec_if; 3691 adapter->sc_pa = *pa; /* used after attach for adapter reset too */ 3692 3693 if (pci_dma64_available(pa)) 3694 adapter->sc_dmat = pa->pa_dmat64; 3695 else 3696 adapter->sc_dmat = pa->pa_dmat; 3697 3698 pci_aprint_devinfo(pa, NULL); 3699 3700 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3701 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) { 3702 reg |= PCI_COMMAND_MASTER_ENABLE; 3703 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 3704 } 3705 3706 mutex_init(&adapter->global_mtx, MUTEX_DEFAULT, IPL_NET); 3707 rw_init(&adapter->ioctl_sx); 3708 3709 /* Set up the timer service */ 3710 adapter->keep_alive_timeout = DEFAULT_KEEP_ALIVE_TO; 3711 adapter->missing_tx_timeout = DEFAULT_TX_CMP_TO; 3712 adapter->missing_tx_max_queues = DEFAULT_TX_MONITORED_QUEUES; 3713 adapter->missing_tx_threshold = DEFAULT_TX_CMP_THRESHOLD; 3714 3715 if (version_printed++ == 0) 3716 device_printf(parent, "%s\n", ena_version); 3717 3718 rc = ena_allocate_pci_resources(pa, adapter); 3719 if (unlikely(rc != 0)) { 3720 device_printf(parent, "PCI resource allocation failed!\n"); 3721 ena_free_pci_resources(adapter); 3722 return; 3723 } 3724 3725 /* Allocate memory for ena_dev structure */ 3726 ena_dev = malloc(sizeof(struct ena_com_dev), M_DEVBUF, 3727 M_WAITOK | M_ZERO); 3728 3729 adapter->ena_dev = ena_dev; 3730 ena_dev->dmadev = self; 3731 ena_dev->bus = malloc(sizeof(struct ena_bus), M_DEVBUF, 3732 M_WAITOK | M_ZERO); 3733 3734 /* Store register resources */ 3735 ((struct ena_bus*)(ena_dev->bus))->reg_bar_t = adapter->sc_btag; 3736 ((struct ena_bus*)(ena_dev->bus))->reg_bar_h = adapter->sc_bhandle; 3737 3738 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3739 3740 /* Device initialization */ 3741 rc = ena_device_init(adapter, self, &get_feat_ctx, &adapter->wd_active); 3742 if (unlikely(rc != 0)) { 3743 device_printf(self, "ENA device init failed! (err: %d)\n", rc); 3744 rc = ENXIO; 3745 goto err_bus_free; 3746 } 3747 3748 adapter->keep_alive_timestamp = getsbinuptime(); 3749 3750 adapter->tx_offload_cap = get_feat_ctx.offload.tx; 3751 3752 /* Set for sure that interface is not up */ 3753 adapter->up = false; 3754 3755 memcpy(adapter->mac_addr, get_feat_ctx.dev_attr.mac_addr, 3756 ETHER_ADDR_LEN); 3757 3758 /* calculate IO queue number to create */ 3759 io_queue_num = ena_calc_io_queue_num(pa, adapter, &get_feat_ctx); 3760 3761 ENA_ASSERT(io_queue_num > 0, "Invalid queue number: %d\n", 3762 io_queue_num); 3763 adapter->num_queues = io_queue_num; 3764 3765 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 3766 3767 /* calculatre ring sizes */ 3768 queue_size = ena_calc_queue_size(adapter,&tx_sgl_size, 3769 &rx_sgl_size, &get_feat_ctx); 3770 if (unlikely((queue_size <= 0) || (io_queue_num <= 0))) { 3771 rc = ENA_COM_FAULT; 3772 goto err_com_free; 3773 } 3774 3775 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3776 3777 adapter->tx_ring_size = queue_size; 3778 adapter->rx_ring_size = queue_size; 3779 3780 adapter->max_tx_sgl_size = tx_sgl_size; 3781 adapter->max_rx_sgl_size = rx_sgl_size; 3782 3783 #if 0 3784 /* set up dma tags for rx and tx buffers */ 3785 rc = ena_setup_tx_dma_tag(adapter); 3786 if (unlikely(rc != 0)) { 3787 device_printf(self, "Failed to create TX DMA tag\n"); 3788 goto err_com_free; 3789 } 3790 3791 rc = ena_setup_rx_dma_tag(adapter); 3792 if (unlikely(rc != 0)) { 3793 device_printf(self, "Failed to create RX DMA tag\n"); 3794 goto err_tx_tag_free; 3795 } 3796 #endif 3797 3798 /* initialize rings basic information */ 3799 device_printf(self, "initialize %d io queues\n", io_queue_num); 3800 ena_init_io_rings(adapter); 3801 3802 /* setup network interface */ 3803 rc = ena_setup_ifnet(self, adapter, &get_feat_ctx); 3804 if (unlikely(rc != 0)) { 3805 device_printf(self, "Error with network interface setup\n"); 3806 goto err_io_free; 3807 } 3808 3809 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3810 if (unlikely(rc != 0)) { 3811 device_printf(self, 3812 "Failed to enable and set the admin interrupts\n"); 3813 goto err_ifp_free; 3814 } 3815 3816 callout_init(&adapter->timer_service, CALLOUT_FLAGS); 3817 callout_setfunc(&adapter->timer_service, ena_timer_service, adapter); 3818 3819 /* Initialize reset task queue */ 3820 rc = workqueue_create(&adapter->reset_tq, "ena_reset_enq", 3821 ena_reset_task, adapter, 0, IPL_NET, WQ_PERCPU | WQ_FLAGS); 3822 if (unlikely(rc != 0)) { 3823 ena_trace(ENA_ALERT, 3824 "Unable to create workqueue for reset task\n"); 3825 goto err_ifp_free; 3826 } 3827 3828 /* Initialize statistics */ 3829 ena_alloc_counters_dev(&adapter->dev_stats, io_queue_num); 3830 ena_alloc_counters_hwstats(&adapter->hw_stats, io_queue_num); 3831 #if 0 3832 ena_sysctl_add_nodes(adapter); 3833 #endif 3834 3835 /* Tell the stack that the interface is not active */ 3836 if_setdrvflagbits(adapter->ifp, IFF_OACTIVE, IFF_RUNNING); 3837 3838 adapter->running = true; 3839 return; 3840 3841 err_ifp_free: 3842 if_detach(adapter->ifp); 3843 if_free(adapter->ifp); 3844 err_io_free: 3845 ena_free_all_io_rings_resources(adapter); 3846 #if 0 3847 ena_free_rx_dma_tag(adapter); 3848 err_tx_tag_free: 3849 ena_free_tx_dma_tag(adapter); 3850 #endif 3851 err_com_free: 3852 ena_com_admin_destroy(ena_dev); 3853 ena_com_delete_host_info(ena_dev); 3854 ena_com_mmio_reg_read_request_destroy(ena_dev); 3855 err_bus_free: 3856 free(ena_dev->bus, M_DEVBUF); 3857 free(ena_dev, M_DEVBUF); 3858 ena_free_pci_resources(adapter); 3859 } 3860 3861 /** 3862 * ena_detach - Device Removal Routine 3863 * @pdev: device information struct 3864 * 3865 * ena_detach is called by the device subsystem to alert the driver 3866 * that it should release a PCI device. 3867 **/ 3868 static int 3869 ena_detach(device_t pdev, int flags) 3870 { 3871 struct ena_adapter *adapter = device_private(pdev); 3872 struct ena_com_dev *ena_dev = adapter->ena_dev; 3873 #if 0 3874 int rc; 3875 #endif 3876 3877 /* Make sure VLANS are not using driver */ 3878 if (VLAN_ATTACHED(&adapter->sc_ec)) { 3879 device_printf(adapter->pdev ,"VLAN is in use, detach first\n"); 3880 return (EBUSY); 3881 } 3882 3883 /* Free reset task and callout */ 3884 callout_halt(&adapter->timer_service, &adapter->global_mtx); 3885 callout_destroy(&adapter->timer_service); 3886 workqueue_wait(adapter->reset_tq, &adapter->reset_task); 3887 workqueue_destroy(adapter->reset_tq); 3888 adapter->reset_tq = NULL; 3889 3890 rw_enter(&adapter->ioctl_sx, RW_WRITER); 3891 ena_down(adapter); 3892 rw_exit(&adapter->ioctl_sx); 3893 3894 if (adapter->ifp != NULL) { 3895 ether_ifdetach(adapter->ifp); 3896 if_free(adapter->ifp); 3897 } 3898 ifmedia_fini(&adapter->media); 3899 3900 ena_free_all_io_rings_resources(adapter); 3901 3902 ena_free_counters((struct evcnt *)&adapter->hw_stats, 3903 sizeof(struct ena_hw_stats), 3904 offsetof(struct ena_hw_stats, rx_packets)); 3905 ena_free_counters((struct evcnt *)&adapter->dev_stats, 3906 sizeof(struct ena_stats_dev), 3907 offsetof(struct ena_stats_dev, wd_expired)); 3908 3909 if (likely(adapter->rss_support)) 3910 ena_com_rss_destroy(ena_dev); 3911 3912 #if 0 3913 rc = ena_free_rx_dma_tag(adapter); 3914 if (unlikely(rc != 0)) 3915 device_printf(adapter->pdev, 3916 "Unmapped RX DMA tag associations\n"); 3917 3918 rc = ena_free_tx_dma_tag(adapter); 3919 if (unlikely(rc != 0)) 3920 device_printf(adapter->pdev, 3921 "Unmapped TX DMA tag associations\n"); 3922 #endif 3923 3924 /* Reset the device only if the device is running. */ 3925 if (adapter->running) 3926 ena_com_dev_reset(ena_dev, adapter->reset_reason); 3927 3928 ena_com_delete_host_info(ena_dev); 3929 3930 ena_free_irqs(adapter); 3931 3932 ena_com_abort_admin_commands(ena_dev); 3933 3934 ena_com_wait_for_abort_completion(ena_dev); 3935 3936 ena_com_admin_destroy(ena_dev); 3937 3938 ena_com_mmio_reg_read_request_destroy(ena_dev); 3939 3940 ena_free_pci_resources(adapter); 3941 3942 mutex_destroy(&adapter->global_mtx); 3943 rw_destroy(&adapter->ioctl_sx); 3944 3945 if (ena_dev->bus != NULL) 3946 free(ena_dev->bus, M_DEVBUF); 3947 3948 if (ena_dev != NULL) 3949 free(ena_dev, M_DEVBUF); 3950 3951 return 0; 3952 } 3953 3954 /****************************************************************************** 3955 ******************************** AENQ Handlers ******************************* 3956 *****************************************************************************/ 3957 /** 3958 * ena_update_on_link_change: 3959 * Notify the network interface about the change in link status 3960 **/ 3961 static void 3962 ena_update_on_link_change(void *adapter_data, 3963 struct ena_admin_aenq_entry *aenq_e) 3964 { 3965 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3966 struct ena_admin_aenq_link_change_desc *aenq_desc; 3967 int status; 3968 struct ifnet *ifp; 3969 3970 aenq_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3971 ifp = adapter->ifp; 3972 status = aenq_desc->flags & 3973 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3974 3975 if (status != 0) { 3976 device_printf(adapter->pdev, "link is UP\n"); 3977 if_link_state_change(ifp, LINK_STATE_UP); 3978 } else if (status == 0) { 3979 device_printf(adapter->pdev, "link is DOWN\n"); 3980 if_link_state_change(ifp, LINK_STATE_DOWN); 3981 } else { 3982 device_printf(adapter->pdev, "invalid value recvd\n"); 3983 BUG(); 3984 } 3985 3986 adapter->link_status = status; 3987 } 3988 3989 /** 3990 * This handler will called for unknown event group or unimplemented handlers 3991 **/ 3992 static void 3993 unimplemented_aenq_handler(void *data, 3994 struct ena_admin_aenq_entry *aenq_e) 3995 { 3996 return; 3997 } 3998 3999 static struct ena_aenq_handlers aenq_handlers = { 4000 .handlers = { 4001 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 4002 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 4003 }, 4004 .unimplemented_handler = unimplemented_aenq_handler 4005 }; 4006 4007 #ifdef __FreeBSD__ 4008 /********************************************************************* 4009 * FreeBSD Device Interface Entry Points 4010 *********************************************************************/ 4011 4012 static device_method_t ena_methods[] = { 4013 /* Device interface */ 4014 DEVMETHOD(device_probe, ena_probe), 4015 DEVMETHOD(device_attach, ena_attach), 4016 DEVMETHOD(device_detach, ena_detach), 4017 DEVMETHOD_END 4018 }; 4019 4020 static driver_t ena_driver = { 4021 "ena", ena_methods, sizeof(struct ena_adapter), 4022 }; 4023 4024 devclass_t ena_devclass; 4025 DRIVER_MODULE(ena, pci, ena_driver, ena_devclass, 0, 0); 4026 MODULE_DEPEND(ena, pci, 1, 1, 1); 4027 MODULE_DEPEND(ena, ether, 1, 1, 1); 4028 4029 /*********************************************************************/ 4030 #endif /* __FreeBSD__ */ 4031 4032 #ifdef __NetBSD__ 4033 CFATTACH_DECL_NEW(ena, sizeof(struct ena_adapter), ena_probe, ena_attach, 4034 ena_detach, NULL); 4035 #endif /* __NetBSD */ 4036