1 /* $NetBSD: if_dge.c,v 1.31 2010/11/13 13:52:06 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.31 2010/11/13 13:52:06 uebayasi Exp $"); 84 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 99 #if NRND > 0 100 #include <sys/rnd.h> 101 #endif 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #include <net/bpf.h> 109 110 #include <netinet/in.h> /* XXX for struct ip */ 111 #include <netinet/in_systm.h> /* XXX for struct ip */ 112 #include <netinet/ip.h> /* XXX for struct ip */ 113 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_dgereg.h> 128 129 /* 130 * The receive engine may sometimes become off-by-one when writing back 131 * chained descriptors. Avoid this by allocating a large chunk of 132 * memory and use if instead (to avoid chained descriptors). 133 * This only happens with chained descriptors under heavy load. 134 */ 135 #define DGE_OFFBYONE_RXBUG 136 137 #define DGE_EVENT_COUNTERS 138 #define DGE_DEBUG 139 140 #ifdef DGE_DEBUG 141 #define DGE_DEBUG_LINK 0x01 142 #define DGE_DEBUG_TX 0x02 143 #define DGE_DEBUG_RX 0x04 144 #define DGE_DEBUG_CKSUM 0x08 145 int dge_debug = 0; 146 147 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 148 #else 149 #define DPRINTF(x, y) /* nothing */ 150 #endif /* DGE_DEBUG */ 151 152 /* 153 * Transmit descriptor list size. We allow up to 100 DMA segments per 154 * packet (Intel reports of jumbo frame packets with as 155 * many as 80 DMA segments when using 16k buffers). 156 */ 157 #define DGE_NTXSEGS 100 158 #define DGE_IFQUEUELEN 20000 159 #define DGE_TXQUEUELEN 2048 160 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 161 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 162 #define DGE_NTXDESC 1024 163 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 164 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 165 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 166 167 /* 168 * Receive descriptor list size. 169 * Packet is of size MCLBYTES, and for jumbo packets buffers may 170 * be chained. Due to the nature of the card (high-speed), keep this 171 * ring large. With 2k buffers the ring can store 400 jumbo packets, 172 * which at full speed will be received in just under 3ms. 173 */ 174 #define DGE_NRXDESC 2048 175 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 176 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 177 /* 178 * # of descriptors between head and written descriptors. 179 * This is to work-around two erratas. 180 */ 181 #define DGE_RXSPACE 10 182 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 183 /* 184 * Receive descriptor fetch threshholds. These are values recommended 185 * by Intel, do not touch them unless you know what you are doing. 186 */ 187 #define RXDCTL_PTHRESH_VAL 128 188 #define RXDCTL_HTHRESH_VAL 16 189 #define RXDCTL_WTHRESH_VAL 16 190 191 192 /* 193 * Tweakable parameters; default values. 194 */ 195 #define FCRTH 0x30000 /* Send XOFF water mark */ 196 #define FCRTL 0x28000 /* Send XON water mark */ 197 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 198 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 199 200 /* 201 * Control structures are DMA'd to the i82597 chip. We allocate them in 202 * a single clump that maps to a single DMA segment to make serveral things 203 * easier. 204 */ 205 struct dge_control_data { 206 /* 207 * The transmit descriptors. 208 */ 209 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 210 211 /* 212 * The receive descriptors. 213 */ 214 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 215 }; 216 217 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 218 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 219 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 220 221 /* 222 * The DGE interface have a higher max MTU size than normal jumbo frames. 223 */ 224 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 225 226 /* 227 * Software state for transmit jobs. 228 */ 229 struct dge_txsoft { 230 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 231 bus_dmamap_t txs_dmamap; /* our DMA map */ 232 int txs_firstdesc; /* first descriptor in packet */ 233 int txs_lastdesc; /* last descriptor in packet */ 234 int txs_ndesc; /* # of descriptors used */ 235 }; 236 237 /* 238 * Software state for receive buffers. Each descriptor gets a 239 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 240 * more than one buffer, we chain them together. 241 */ 242 struct dge_rxsoft { 243 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 244 bus_dmamap_t rxs_dmamap; /* our DMA map */ 245 }; 246 247 /* 248 * Software state per device. 249 */ 250 struct dge_softc { 251 struct device sc_dev; /* generic device information */ 252 bus_space_tag_t sc_st; /* bus space tag */ 253 bus_space_handle_t sc_sh; /* bus space handle */ 254 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 255 struct ethercom sc_ethercom; /* ethernet common data */ 256 257 int sc_flags; /* flags; see below */ 258 int sc_bus_speed; /* PCI/PCIX bus speed */ 259 int sc_pcix_offset; /* PCIX capability register offset */ 260 261 pci_chipset_tag_t sc_pc; 262 pcitag_t sc_pt; 263 int sc_mmrbc; /* Max PCIX memory read byte count */ 264 265 void *sc_ih; /* interrupt cookie */ 266 267 struct ifmedia sc_media; 268 269 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 270 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 271 272 int sc_align_tweak; 273 274 /* 275 * Software state for the transmit and receive descriptors. 276 */ 277 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 278 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 279 280 /* 281 * Control data structures. 282 */ 283 struct dge_control_data *sc_control_data; 284 #define sc_txdescs sc_control_data->wcd_txdescs 285 #define sc_rxdescs sc_control_data->wcd_rxdescs 286 287 #ifdef DGE_EVENT_COUNTERS 288 /* Event counters. */ 289 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 290 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 291 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 292 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 293 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 294 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 295 struct evcnt sc_ev_linkintr; /* Link interrupts */ 296 297 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 298 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 299 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 300 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 301 302 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 303 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 304 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 305 306 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 307 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 308 #endif /* DGE_EVENT_COUNTERS */ 309 310 int sc_txfree; /* number of free Tx descriptors */ 311 int sc_txnext; /* next ready Tx descriptor */ 312 313 int sc_txsfree; /* number of free Tx jobs */ 314 int sc_txsnext; /* next free Tx job */ 315 int sc_txsdirty; /* dirty Tx jobs */ 316 317 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 318 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 319 320 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 321 int sc_rxdiscard; 322 int sc_rxlen; 323 struct mbuf *sc_rxhead; 324 struct mbuf *sc_rxtail; 325 struct mbuf **sc_rxtailp; 326 327 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 328 uint32_t sc_icr; /* prototype interrupt bits */ 329 uint32_t sc_tctl; /* prototype TCTL register */ 330 uint32_t sc_rctl; /* prototype RCTL register */ 331 332 int sc_mchash_type; /* multicast filter offset */ 333 334 uint16_t sc_eeprom[EEPROM_SIZE]; 335 336 #if NRND > 0 337 rndsource_element_t rnd_source; /* random source */ 338 #endif 339 #ifdef DGE_OFFBYONE_RXBUG 340 void *sc_bugbuf; 341 SLIST_HEAD(, rxbugentry) sc_buglist; 342 bus_dmamap_t sc_bugmap; 343 struct rxbugentry *sc_entry; 344 #endif 345 }; 346 347 #define DGE_RXCHAIN_RESET(sc) \ 348 do { \ 349 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 350 *(sc)->sc_rxtailp = NULL; \ 351 (sc)->sc_rxlen = 0; \ 352 } while (/*CONSTCOND*/0) 353 354 #define DGE_RXCHAIN_LINK(sc, m) \ 355 do { \ 356 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 357 (sc)->sc_rxtailp = &(m)->m_next; \ 358 } while (/*CONSTCOND*/0) 359 360 /* sc_flags */ 361 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 362 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 363 364 #ifdef DGE_EVENT_COUNTERS 365 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 366 #else 367 #define DGE_EVCNT_INCR(ev) /* nothing */ 368 #endif 369 370 #define CSR_READ(sc, reg) \ 371 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 372 #define CSR_WRITE(sc, reg, val) \ 373 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 374 375 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 376 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 377 378 #define DGE_CDTXSYNC(sc, x, n, ops) \ 379 do { \ 380 int __x, __n; \ 381 \ 382 __x = (x); \ 383 __n = (n); \ 384 \ 385 /* If it will wrap around, sync to the end of the ring. */ \ 386 if ((__x + __n) > DGE_NTXDESC) { \ 387 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 388 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 389 (DGE_NTXDESC - __x), (ops)); \ 390 __n -= (DGE_NTXDESC - __x); \ 391 __x = 0; \ 392 } \ 393 \ 394 /* Now sync whatever is left. */ \ 395 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 396 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 397 } while (/*CONSTCOND*/0) 398 399 #define DGE_CDRXSYNC(sc, x, ops) \ 400 do { \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 403 } while (/*CONSTCOND*/0) 404 405 #ifdef DGE_OFFBYONE_RXBUG 406 #define DGE_INIT_RXDESC(sc, x) \ 407 do { \ 408 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 409 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 410 struct mbuf *__m = __rxs->rxs_mbuf; \ 411 \ 412 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 413 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 414 __rxd->dr_baddrh = 0; \ 415 __rxd->dr_len = 0; \ 416 __rxd->dr_cksum = 0; \ 417 __rxd->dr_status = 0; \ 418 __rxd->dr_errors = 0; \ 419 __rxd->dr_special = 0; \ 420 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 421 \ 422 CSR_WRITE((sc), DGE_RDT, (x)); \ 423 } while (/*CONSTCOND*/0) 424 #else 425 #define DGE_INIT_RXDESC(sc, x) \ 426 do { \ 427 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 428 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 429 struct mbuf *__m = __rxs->rxs_mbuf; \ 430 \ 431 /* \ 432 * Note: We scoot the packet forward 2 bytes in the buffer \ 433 * so that the payload after the Ethernet header is aligned \ 434 * to a 4-byte boundary. \ 435 * \ 436 * XXX BRAINDAMAGE ALERT! \ 437 * The stupid chip uses the same size for every buffer, which \ 438 * is set in the Receive Control register. We are using the 2K \ 439 * size option, but what we REALLY want is (2K - 2)! For this \ 440 * reason, we can't "scoot" packets longer than the standard \ 441 * Ethernet MTU. On strict-alignment platforms, if the total \ 442 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 443 * the upper layer copy the headers. \ 444 */ \ 445 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 446 \ 447 __rxd->dr_baddrl = \ 448 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 449 (sc)->sc_align_tweak); \ 450 __rxd->dr_baddrh = 0; \ 451 __rxd->dr_len = 0; \ 452 __rxd->dr_cksum = 0; \ 453 __rxd->dr_status = 0; \ 454 __rxd->dr_errors = 0; \ 455 __rxd->dr_special = 0; \ 456 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 457 \ 458 CSR_WRITE((sc), DGE_RDT, (x)); \ 459 } while (/*CONSTCOND*/0) 460 #endif 461 462 #ifdef DGE_OFFBYONE_RXBUG 463 /* 464 * Allocation constants. Much memory may be used for this. 465 */ 466 #ifndef DGE_BUFFER_SIZE 467 #define DGE_BUFFER_SIZE DGE_MAX_MTU 468 #endif 469 #define DGE_NBUFFERS (4*DGE_NRXDESC) 470 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 471 472 struct rxbugentry { 473 SLIST_ENTRY(rxbugentry) rb_entry; 474 int rb_slot; 475 }; 476 477 static int 478 dge_alloc_rcvmem(struct dge_softc *sc) 479 { 480 char *ptr, *kva; 481 bus_dma_segment_t seg; 482 int i, rseg, state, error; 483 struct rxbugentry *entry; 484 485 state = error = 0; 486 487 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 488 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 489 aprint_error_dev(&sc->sc_dev, "can't alloc rx buffers\n"); 490 return ENOBUFS; 491 } 492 493 state = 1; 494 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, 495 BUS_DMA_NOWAIT)) { 496 aprint_error_dev(&sc->sc_dev, "can't map DMA buffers (%d bytes)\n", 497 (int)DGE_RXMEM); 498 error = ENOBUFS; 499 goto out; 500 } 501 502 state = 2; 503 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 504 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 505 aprint_error_dev(&sc->sc_dev, "can't create DMA map\n"); 506 error = ENOBUFS; 507 goto out; 508 } 509 510 state = 3; 511 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 512 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 513 aprint_error_dev(&sc->sc_dev, "can't load DMA map\n"); 514 error = ENOBUFS; 515 goto out; 516 } 517 518 state = 4; 519 sc->sc_bugbuf = (void *)kva; 520 SLIST_INIT(&sc->sc_buglist); 521 522 /* 523 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 524 * in an array. 525 */ 526 ptr = sc->sc_bugbuf; 527 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 528 M_DEVBUF, M_NOWAIT)) == NULL) { 529 error = ENOBUFS; 530 goto out; 531 } 532 sc->sc_entry = entry; 533 for (i = 0; i < DGE_NBUFFERS; i++) { 534 entry[i].rb_slot = i; 535 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 536 } 537 out: 538 if (error != 0) { 539 switch (state) { 540 case 4: 541 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 542 case 3: 543 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 544 case 2: 545 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 546 case 1: 547 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 548 break; 549 default: 550 break; 551 } 552 } 553 554 return error; 555 } 556 557 /* 558 * Allocate a jumbo buffer. 559 */ 560 static void * 561 dge_getbuf(struct dge_softc *sc) 562 { 563 struct rxbugentry *entry; 564 565 entry = SLIST_FIRST(&sc->sc_buglist); 566 567 if (entry == NULL) { 568 printf("%s: no free RX buffers\n", device_xname(&sc->sc_dev)); 569 return(NULL); 570 } 571 572 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 573 return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 574 } 575 576 /* 577 * Release a jumbo buffer. 578 */ 579 static void 580 dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) 581 { 582 struct rxbugentry *entry; 583 struct dge_softc *sc; 584 int i, s; 585 586 /* Extract the softc struct pointer. */ 587 sc = (struct dge_softc *)arg; 588 589 if (sc == NULL) 590 panic("dge_freebuf: can't find softc pointer!"); 591 592 /* calculate the slot this buffer belongs to */ 593 594 i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; 595 596 if ((i < 0) || (i >= DGE_NBUFFERS)) 597 panic("dge_freebuf: asked to free buffer %d!", i); 598 599 s = splvm(); 600 entry = sc->sc_entry + i; 601 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 602 603 if (__predict_true(m != NULL)) 604 pool_cache_put(mb_cache, m); 605 splx(s); 606 } 607 #endif 608 609 static void dge_start(struct ifnet *); 610 static void dge_watchdog(struct ifnet *); 611 static int dge_ioctl(struct ifnet *, u_long, void *); 612 static int dge_init(struct ifnet *); 613 static void dge_stop(struct ifnet *, int); 614 615 static bool dge_shutdown(device_t, int); 616 617 static void dge_reset(struct dge_softc *); 618 static void dge_rxdrain(struct dge_softc *); 619 static int dge_add_rxbuf(struct dge_softc *, int); 620 621 static void dge_set_filter(struct dge_softc *); 622 623 static int dge_intr(void *); 624 static void dge_txintr(struct dge_softc *); 625 static void dge_rxintr(struct dge_softc *); 626 static void dge_linkintr(struct dge_softc *, uint32_t); 627 628 static int dge_match(device_t, cfdata_t, void *); 629 static void dge_attach(device_t, device_t, void *); 630 631 static int dge_read_eeprom(struct dge_softc *sc); 632 static int dge_eeprom_clockin(struct dge_softc *sc); 633 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 634 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 635 static int dge_xgmii_mediachange(struct ifnet *); 636 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 637 static void dge_xgmii_reset(struct dge_softc *); 638 static void dge_xgmii_writereg(device_t, int, int, int); 639 640 641 CFATTACH_DECL(dge, sizeof(struct dge_softc), 642 dge_match, dge_attach, NULL, NULL); 643 644 #ifdef DGE_EVENT_COUNTERS 645 #if DGE_NTXSEGS > 100 646 #error Update dge_txseg_evcnt_names 647 #endif 648 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 649 #endif /* DGE_EVENT_COUNTERS */ 650 651 static int 652 dge_match(device_t parent, cfdata_t cf, void *aux) 653 { 654 struct pci_attach_args *pa = aux; 655 656 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 657 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82597EX) 658 return (1); 659 660 return (0); 661 } 662 663 static void 664 dge_attach(device_t parent, device_t self, void *aux) 665 { 666 struct dge_softc *sc = device_private(self); 667 struct pci_attach_args *pa = aux; 668 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 669 pci_chipset_tag_t pc = pa->pa_pc; 670 pci_intr_handle_t ih; 671 const char *intrstr = NULL; 672 bus_dma_segment_t seg; 673 int i, rseg, error; 674 uint8_t enaddr[ETHER_ADDR_LEN]; 675 pcireg_t preg, memtype; 676 uint32_t reg; 677 678 sc->sc_dmat = pa->pa_dmat; 679 sc->sc_pc = pa->pa_pc; 680 sc->sc_pt = pa->pa_tag; 681 682 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 683 aprint_naive(": Ethernet controller\n"); 684 aprint_normal(": Intel i82597EX 10GbE-LR Ethernet, rev. %d\n", preg); 685 686 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 687 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 688 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 689 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 690 return; 691 } 692 693 /* Enable bus mastering */ 694 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 695 preg |= PCI_COMMAND_MASTER_ENABLE; 696 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 697 698 /* 699 * Map and establish our interrupt. 700 */ 701 if (pci_intr_map(pa, &ih)) { 702 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 703 return; 704 } 705 intrstr = pci_intr_string(pc, ih); 706 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 707 if (sc->sc_ih == NULL) { 708 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 709 if (intrstr != NULL) 710 aprint_error(" at %s", intrstr); 711 aprint_error("\n"); 712 return; 713 } 714 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 715 716 /* 717 * Determine a few things about the bus we're connected to. 718 */ 719 reg = CSR_READ(sc, DGE_STATUS); 720 if (reg & STATUS_BUS64) 721 sc->sc_flags |= DGE_F_BUS64; 722 723 sc->sc_flags |= DGE_F_PCIX; 724 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 725 PCI_CAP_PCIX, 726 &sc->sc_pcix_offset, NULL) == 0) 727 aprint_error_dev(&sc->sc_dev, "unable to find PCIX " 728 "capability\n"); 729 730 if (sc->sc_flags & DGE_F_PCIX) { 731 switch (reg & STATUS_PCIX_MSK) { 732 case STATUS_PCIX_66: 733 sc->sc_bus_speed = 66; 734 break; 735 case STATUS_PCIX_100: 736 sc->sc_bus_speed = 100; 737 break; 738 case STATUS_PCIX_133: 739 sc->sc_bus_speed = 133; 740 break; 741 default: 742 aprint_error_dev(&sc->sc_dev, 743 "unknown PCIXSPD %d; assuming 66MHz\n", 744 reg & STATUS_PCIX_MSK); 745 sc->sc_bus_speed = 66; 746 } 747 } else 748 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 749 aprint_verbose_dev(&sc->sc_dev, "%d-bit %dMHz %s bus\n", 750 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 751 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 752 753 /* 754 * Allocate the control data structures, and create and load the 755 * DMA map for it. 756 */ 757 if ((error = bus_dmamem_alloc(sc->sc_dmat, 758 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 759 0)) != 0) { 760 aprint_error_dev(&sc->sc_dev, 761 "unable to allocate control data, error = %d\n", 762 error); 763 goto fail_0; 764 } 765 766 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 767 sizeof(struct dge_control_data), (void **)&sc->sc_control_data, 768 0)) != 0) { 769 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 770 error); 771 goto fail_1; 772 } 773 774 if ((error = bus_dmamap_create(sc->sc_dmat, 775 sizeof(struct dge_control_data), 1, 776 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 777 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 778 "error = %d\n", error); 779 goto fail_2; 780 } 781 782 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 783 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 784 0)) != 0) { 785 aprint_error_dev(&sc->sc_dev, 786 "unable to load control data DMA map, error = %d\n", 787 error); 788 goto fail_3; 789 } 790 791 #ifdef DGE_OFFBYONE_RXBUG 792 if (dge_alloc_rcvmem(sc) != 0) 793 return; /* Already complained */ 794 #endif 795 /* 796 * Create the transmit buffer DMA maps. 797 */ 798 for (i = 0; i < DGE_TXQUEUELEN; i++) { 799 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 800 DGE_NTXSEGS, MCLBYTES, 0, 0, 801 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 802 aprint_error_dev(&sc->sc_dev, "unable to create Tx DMA map %d, " 803 "error = %d\n", i, error); 804 goto fail_4; 805 } 806 } 807 808 /* 809 * Create the receive buffer DMA maps. 810 */ 811 for (i = 0; i < DGE_NRXDESC; i++) { 812 #ifdef DGE_OFFBYONE_RXBUG 813 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 814 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 815 #else 816 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 817 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 818 #endif 819 aprint_error_dev(&sc->sc_dev, "unable to create Rx DMA map %d, " 820 "error = %d\n", i, error); 821 goto fail_5; 822 } 823 sc->sc_rxsoft[i].rxs_mbuf = NULL; 824 } 825 826 /* 827 * Set bits in ctrl0 register. 828 * Should get the software defined pins out of EEPROM? 829 */ 830 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 831 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 832 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 833 834 /* 835 * Reset the chip to a known state. 836 */ 837 dge_reset(sc); 838 839 /* 840 * Reset the PHY. 841 */ 842 dge_xgmii_reset(sc); 843 844 /* 845 * Read in EEPROM data. 846 */ 847 if (dge_read_eeprom(sc)) { 848 aprint_error_dev(&sc->sc_dev, "couldn't read EEPROM\n"); 849 return; 850 } 851 852 /* 853 * Get the ethernet address. 854 */ 855 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 856 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 857 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 858 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 859 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 860 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 861 862 aprint_normal_dev(&sc->sc_dev, "Ethernet address %s\n", 863 ether_sprintf(enaddr)); 864 865 /* 866 * Setup media stuff. 867 */ 868 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 869 dge_xgmii_mediastatus); 870 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 871 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 872 873 ifp = &sc->sc_ethercom.ec_if; 874 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 875 ifp->if_softc = sc; 876 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 877 ifp->if_ioctl = dge_ioctl; 878 ifp->if_start = dge_start; 879 ifp->if_watchdog = dge_watchdog; 880 ifp->if_init = dge_init; 881 ifp->if_stop = dge_stop; 882 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 883 IFQ_SET_READY(&ifp->if_snd); 884 885 sc->sc_ethercom.ec_capabilities |= 886 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 887 888 /* 889 * We can perform TCPv4 and UDPv4 checkums in-bound. 890 */ 891 ifp->if_capabilities |= 892 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 893 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 894 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 895 896 /* 897 * Attach the interface. 898 */ 899 if_attach(ifp); 900 ether_ifattach(ifp, enaddr); 901 #if NRND > 0 902 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 903 RND_TYPE_NET, 0); 904 #endif 905 906 #ifdef DGE_EVENT_COUNTERS 907 /* Fix segment event naming */ 908 if (dge_txseg_evcnt_names == NULL) { 909 dge_txseg_evcnt_names = 910 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 911 for (i = 0; i < DGE_NTXSEGS; i++) 912 snprintf((*dge_txseg_evcnt_names)[i], 913 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 914 } 915 916 /* Attach event counters. */ 917 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 918 NULL, device_xname(&sc->sc_dev), "txsstall"); 919 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 920 NULL, device_xname(&sc->sc_dev), "txdstall"); 921 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 922 NULL, device_xname(&sc->sc_dev), "txforceintr"); 923 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 924 NULL, device_xname(&sc->sc_dev), "txdw"); 925 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 926 NULL, device_xname(&sc->sc_dev), "txqe"); 927 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 928 NULL, device_xname(&sc->sc_dev), "rxintr"); 929 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 930 NULL, device_xname(&sc->sc_dev), "linkintr"); 931 932 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 933 NULL, device_xname(&sc->sc_dev), "rxipsum"); 934 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 935 NULL, device_xname(&sc->sc_dev), "rxtusum"); 936 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 937 NULL, device_xname(&sc->sc_dev), "txipsum"); 938 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 939 NULL, device_xname(&sc->sc_dev), "txtusum"); 940 941 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 942 NULL, device_xname(&sc->sc_dev), "txctx init"); 943 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 944 NULL, device_xname(&sc->sc_dev), "txctx hit"); 945 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 946 NULL, device_xname(&sc->sc_dev), "txctx miss"); 947 948 for (i = 0; i < DGE_NTXSEGS; i++) 949 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 950 NULL, device_xname(&sc->sc_dev), (*dge_txseg_evcnt_names)[i]); 951 952 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 953 NULL, device_xname(&sc->sc_dev), "txdrop"); 954 955 #endif /* DGE_EVENT_COUNTERS */ 956 957 /* 958 * Make sure the interface is shutdown during reboot. 959 */ 960 if (pmf_device_register1(self, NULL, NULL, dge_shutdown)) 961 pmf_class_network_register(self, ifp); 962 else 963 aprint_error_dev(self, "couldn't establish power handler\n"); 964 965 return; 966 967 /* 968 * Free any resources we've allocated during the failed attach 969 * attempt. Do this in reverse order and fall through. 970 */ 971 fail_5: 972 for (i = 0; i < DGE_NRXDESC; i++) { 973 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 974 bus_dmamap_destroy(sc->sc_dmat, 975 sc->sc_rxsoft[i].rxs_dmamap); 976 } 977 fail_4: 978 for (i = 0; i < DGE_TXQUEUELEN; i++) { 979 if (sc->sc_txsoft[i].txs_dmamap != NULL) 980 bus_dmamap_destroy(sc->sc_dmat, 981 sc->sc_txsoft[i].txs_dmamap); 982 } 983 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 984 fail_3: 985 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 986 fail_2: 987 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 988 sizeof(struct dge_control_data)); 989 fail_1: 990 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 991 fail_0: 992 return; 993 } 994 995 /* 996 * dge_shutdown: 997 * 998 * Make sure the interface is stopped at reboot time. 999 */ 1000 static bool 1001 dge_shutdown(device_t self, int howto) 1002 { 1003 struct dge_softc *sc; 1004 1005 sc = device_private(self); 1006 dge_stop(&sc->sc_ethercom.ec_if, 1); 1007 1008 return true; 1009 } 1010 1011 /* 1012 * dge_tx_cksum: 1013 * 1014 * Set up TCP/IP checksumming parameters for the 1015 * specified packet. 1016 */ 1017 static int 1018 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1019 { 1020 struct mbuf *m0 = txs->txs_mbuf; 1021 struct dge_ctdes *t; 1022 uint32_t ipcs, tucs; 1023 struct ether_header *eh; 1024 int offset, iphl; 1025 uint8_t fields = 0; 1026 1027 /* 1028 * XXX It would be nice if the mbuf pkthdr had offset 1029 * fields for the protocol headers. 1030 */ 1031 1032 eh = mtod(m0, struct ether_header *); 1033 switch (htons(eh->ether_type)) { 1034 case ETHERTYPE_IP: 1035 offset = ETHER_HDR_LEN; 1036 break; 1037 1038 case ETHERTYPE_VLAN: 1039 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1040 break; 1041 1042 default: 1043 /* 1044 * Don't support this protocol or encapsulation. 1045 */ 1046 *fieldsp = 0; 1047 return (0); 1048 } 1049 1050 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1051 1052 /* 1053 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1054 * offload feature, if we load the context descriptor, we 1055 * MUST provide valid values for IPCSS and TUCSS fields. 1056 */ 1057 1058 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1059 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1060 fields |= TDESC_POPTS_IXSM; 1061 ipcs = DGE_TCPIP_IPCSS(offset) | 1062 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1063 DGE_TCPIP_IPCSE(offset + iphl - 1); 1064 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1065 /* Use the cached value. */ 1066 ipcs = sc->sc_txctx_ipcs; 1067 } else { 1068 /* Just initialize it to the likely value anyway. */ 1069 ipcs = DGE_TCPIP_IPCSS(offset) | 1070 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1071 DGE_TCPIP_IPCSE(offset + iphl - 1); 1072 } 1073 DPRINTF(DGE_DEBUG_CKSUM, 1074 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1075 device_xname(&sc->sc_dev), offset, ipcs)); 1076 1077 offset += iphl; 1078 1079 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1080 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1081 fields |= TDESC_POPTS_TXSM; 1082 tucs = DGE_TCPIP_TUCSS(offset) | 1083 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1084 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1085 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1086 /* Use the cached value. */ 1087 tucs = sc->sc_txctx_tucs; 1088 } else { 1089 /* Just initialize it to a valid TCP context. */ 1090 tucs = DGE_TCPIP_TUCSS(offset) | 1091 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1092 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1093 } 1094 1095 DPRINTF(DGE_DEBUG_CKSUM, 1096 ("%s: CKSUM: offset %d tucs 0x%x\n", 1097 device_xname(&sc->sc_dev), offset, tucs)); 1098 1099 if (sc->sc_txctx_ipcs == ipcs && 1100 sc->sc_txctx_tucs == tucs) { 1101 /* Cached context is fine. */ 1102 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1103 } else { 1104 /* Fill in the context descriptor. */ 1105 #ifdef DGE_EVENT_COUNTERS 1106 if (sc->sc_txctx_ipcs == 0xffffffff && 1107 sc->sc_txctx_tucs == 0xffffffff) 1108 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1109 else 1110 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1111 #endif 1112 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1113 t->dc_tcpip_ipcs = htole32(ipcs); 1114 t->dc_tcpip_tucs = htole32(tucs); 1115 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1116 t->dc_tcpip_seg = 0; 1117 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1118 1119 sc->sc_txctx_ipcs = ipcs; 1120 sc->sc_txctx_tucs = tucs; 1121 1122 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1123 txs->txs_ndesc++; 1124 } 1125 1126 *fieldsp = fields; 1127 1128 return (0); 1129 } 1130 1131 /* 1132 * dge_start: [ifnet interface function] 1133 * 1134 * Start packet transmission on the interface. 1135 */ 1136 static void 1137 dge_start(struct ifnet *ifp) 1138 { 1139 struct dge_softc *sc = ifp->if_softc; 1140 struct mbuf *m0; 1141 struct dge_txsoft *txs; 1142 bus_dmamap_t dmamap; 1143 int error, nexttx, lasttx = -1, ofree, seg; 1144 uint32_t cksumcmd; 1145 uint8_t cksumfields; 1146 1147 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1148 return; 1149 1150 /* 1151 * Remember the previous number of free descriptors. 1152 */ 1153 ofree = sc->sc_txfree; 1154 1155 /* 1156 * Loop through the send queue, setting up transmit descriptors 1157 * until we drain the queue, or use up all available transmit 1158 * descriptors. 1159 */ 1160 for (;;) { 1161 /* Grab a packet off the queue. */ 1162 IFQ_POLL(&ifp->if_snd, m0); 1163 if (m0 == NULL) 1164 break; 1165 1166 DPRINTF(DGE_DEBUG_TX, 1167 ("%s: TX: have packet to transmit: %p\n", 1168 device_xname(&sc->sc_dev), m0)); 1169 1170 /* Get a work queue entry. */ 1171 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1172 dge_txintr(sc); 1173 if (sc->sc_txsfree == 0) { 1174 DPRINTF(DGE_DEBUG_TX, 1175 ("%s: TX: no free job descriptors\n", 1176 device_xname(&sc->sc_dev))); 1177 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1178 break; 1179 } 1180 } 1181 1182 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1183 dmamap = txs->txs_dmamap; 1184 1185 /* 1186 * Load the DMA map. If this fails, the packet either 1187 * didn't fit in the allotted number of segments, or we 1188 * were short on resources. For the too-many-segments 1189 * case, we simply report an error and drop the packet, 1190 * since we can't sanely copy a jumbo packet to a single 1191 * buffer. 1192 */ 1193 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1194 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1195 if (error) { 1196 if (error == EFBIG) { 1197 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1198 printf("%s: Tx packet consumes too many " 1199 "DMA segments, dropping...\n", 1200 device_xname(&sc->sc_dev)); 1201 IFQ_DEQUEUE(&ifp->if_snd, m0); 1202 m_freem(m0); 1203 continue; 1204 } 1205 /* 1206 * Short on resources, just stop for now. 1207 */ 1208 DPRINTF(DGE_DEBUG_TX, 1209 ("%s: TX: dmamap load failed: %d\n", 1210 device_xname(&sc->sc_dev), error)); 1211 break; 1212 } 1213 1214 /* 1215 * Ensure we have enough descriptors free to describe 1216 * the packet. Note, we always reserve one descriptor 1217 * at the end of the ring due to the semantics of the 1218 * TDT register, plus one more in the event we need 1219 * to re-load checksum offload context. 1220 */ 1221 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1222 /* 1223 * Not enough free descriptors to transmit this 1224 * packet. We haven't committed anything yet, 1225 * so just unload the DMA map, put the packet 1226 * pack on the queue, and punt. Notify the upper 1227 * layer that there are no more slots left. 1228 */ 1229 DPRINTF(DGE_DEBUG_TX, 1230 ("%s: TX: need %d descriptors, have %d\n", 1231 device_xname(&sc->sc_dev), dmamap->dm_nsegs, 1232 sc->sc_txfree - 1)); 1233 ifp->if_flags |= IFF_OACTIVE; 1234 bus_dmamap_unload(sc->sc_dmat, dmamap); 1235 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1236 break; 1237 } 1238 1239 IFQ_DEQUEUE(&ifp->if_snd, m0); 1240 1241 /* 1242 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1243 */ 1244 1245 /* Sync the DMA map. */ 1246 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1247 BUS_DMASYNC_PREWRITE); 1248 1249 DPRINTF(DGE_DEBUG_TX, 1250 ("%s: TX: packet has %d DMA segments\n", 1251 device_xname(&sc->sc_dev), dmamap->dm_nsegs)); 1252 1253 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1254 1255 /* 1256 * Store a pointer to the packet so that we can free it 1257 * later. 1258 * 1259 * Initially, we consider the number of descriptors the 1260 * packet uses the number of DMA segments. This may be 1261 * incremented by 1 if we do checksum offload (a descriptor 1262 * is used to set the checksum context). 1263 */ 1264 txs->txs_mbuf = m0; 1265 txs->txs_firstdesc = sc->sc_txnext; 1266 txs->txs_ndesc = dmamap->dm_nsegs; 1267 1268 /* 1269 * Set up checksum offload parameters for 1270 * this packet. 1271 */ 1272 if (m0->m_pkthdr.csum_flags & 1273 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1274 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1275 /* Error message already displayed. */ 1276 bus_dmamap_unload(sc->sc_dmat, dmamap); 1277 continue; 1278 } 1279 } else { 1280 cksumfields = 0; 1281 } 1282 1283 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1284 1285 /* 1286 * Initialize the transmit descriptor. 1287 */ 1288 for (nexttx = sc->sc_txnext, seg = 0; 1289 seg < dmamap->dm_nsegs; 1290 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1291 /* 1292 * Note: we currently only use 32-bit DMA 1293 * addresses. 1294 */ 1295 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1296 sc->sc_txdescs[nexttx].dt_baddrl = 1297 htole32(dmamap->dm_segs[seg].ds_addr); 1298 sc->sc_txdescs[nexttx].dt_ctl = 1299 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1300 sc->sc_txdescs[nexttx].dt_status = 0; 1301 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1302 sc->sc_txdescs[nexttx].dt_vlan = 0; 1303 lasttx = nexttx; 1304 1305 DPRINTF(DGE_DEBUG_TX, 1306 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1307 device_xname(&sc->sc_dev), nexttx, 1308 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_addr), 1309 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_len))); 1310 } 1311 1312 KASSERT(lasttx != -1); 1313 1314 /* 1315 * Set up the command byte on the last descriptor of 1316 * the packet. If we're in the interrupt delay window, 1317 * delay the interrupt. 1318 */ 1319 sc->sc_txdescs[lasttx].dt_ctl |= 1320 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1321 1322 txs->txs_lastdesc = lasttx; 1323 1324 DPRINTF(DGE_DEBUG_TX, 1325 ("%s: TX: desc %d: cmdlen 0x%08x\n", device_xname(&sc->sc_dev), 1326 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1327 1328 /* Sync the descriptors we're using. */ 1329 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1330 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1331 1332 /* Give the packet to the chip. */ 1333 CSR_WRITE(sc, DGE_TDT, nexttx); 1334 1335 DPRINTF(DGE_DEBUG_TX, 1336 ("%s: TX: TDT -> %d\n", device_xname(&sc->sc_dev), nexttx)); 1337 1338 DPRINTF(DGE_DEBUG_TX, 1339 ("%s: TX: finished transmitting packet, job %d\n", 1340 device_xname(&sc->sc_dev), sc->sc_txsnext)); 1341 1342 /* Advance the tx pointer. */ 1343 sc->sc_txfree -= txs->txs_ndesc; 1344 sc->sc_txnext = nexttx; 1345 1346 sc->sc_txsfree--; 1347 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1348 1349 /* Pass the packet to any BPF listeners. */ 1350 bpf_mtap(ifp, m0); 1351 } 1352 1353 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1354 /* No more slots; notify upper layer. */ 1355 ifp->if_flags |= IFF_OACTIVE; 1356 } 1357 1358 if (sc->sc_txfree != ofree) { 1359 /* Set a watchdog timer in case the chip flakes out. */ 1360 ifp->if_timer = 5; 1361 } 1362 } 1363 1364 /* 1365 * dge_watchdog: [ifnet interface function] 1366 * 1367 * Watchdog timer handler. 1368 */ 1369 static void 1370 dge_watchdog(struct ifnet *ifp) 1371 { 1372 struct dge_softc *sc = ifp->if_softc; 1373 1374 /* 1375 * Since we're using delayed interrupts, sweep up 1376 * before we report an error. 1377 */ 1378 dge_txintr(sc); 1379 1380 if (sc->sc_txfree != DGE_NTXDESC) { 1381 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1382 device_xname(&sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, 1383 sc->sc_txnext); 1384 ifp->if_oerrors++; 1385 1386 /* Reset the interface. */ 1387 (void) dge_init(ifp); 1388 } 1389 1390 /* Try to get more packets going. */ 1391 dge_start(ifp); 1392 } 1393 1394 /* 1395 * dge_ioctl: [ifnet interface function] 1396 * 1397 * Handle control requests from the operator. 1398 */ 1399 static int 1400 dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1401 { 1402 struct dge_softc *sc = ifp->if_softc; 1403 struct ifreq *ifr = (struct ifreq *) data; 1404 pcireg_t preg; 1405 int s, error, mmrbc; 1406 1407 s = splnet(); 1408 1409 switch (cmd) { 1410 case SIOCSIFMEDIA: 1411 case SIOCGIFMEDIA: 1412 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1413 break; 1414 1415 case SIOCSIFMTU: 1416 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) 1417 error = EINVAL; 1418 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1419 break; 1420 else if (ifp->if_flags & IFF_UP) 1421 error = (*ifp->if_init)(ifp); 1422 else 1423 error = 0; 1424 break; 1425 1426 case SIOCSIFFLAGS: 1427 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1428 break; 1429 /* extract link flags */ 1430 if ((ifp->if_flags & IFF_LINK0) == 0 && 1431 (ifp->if_flags & IFF_LINK1) == 0) 1432 mmrbc = PCIX_MMRBC_512; 1433 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1434 (ifp->if_flags & IFF_LINK1) != 0) 1435 mmrbc = PCIX_MMRBC_1024; 1436 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1437 (ifp->if_flags & IFF_LINK1) == 0) 1438 mmrbc = PCIX_MMRBC_2048; 1439 else 1440 mmrbc = PCIX_MMRBC_4096; 1441 if (mmrbc != sc->sc_mmrbc) { 1442 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1443 preg &= ~PCIX_MMRBC_MSK; 1444 preg |= mmrbc; 1445 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1446 sc->sc_mmrbc = mmrbc; 1447 } 1448 /* FALLTHROUGH */ 1449 default: 1450 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1451 break; 1452 1453 error = 0; 1454 1455 if (cmd == SIOCSIFCAP) 1456 error = (*ifp->if_init)(ifp); 1457 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1458 ; 1459 else if (ifp->if_flags & IFF_RUNNING) { 1460 /* 1461 * Multicast list has changed; set the hardware filter 1462 * accordingly. 1463 */ 1464 dge_set_filter(sc); 1465 } 1466 break; 1467 } 1468 1469 /* Try to get more packets going. */ 1470 dge_start(ifp); 1471 1472 splx(s); 1473 return (error); 1474 } 1475 1476 /* 1477 * dge_intr: 1478 * 1479 * Interrupt service routine. 1480 */ 1481 static int 1482 dge_intr(void *arg) 1483 { 1484 struct dge_softc *sc = arg; 1485 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1486 uint32_t icr; 1487 int wantinit, handled = 0; 1488 1489 for (wantinit = 0; wantinit == 0;) { 1490 icr = CSR_READ(sc, DGE_ICR); 1491 if ((icr & sc->sc_icr) == 0) 1492 break; 1493 1494 #if 0 /*NRND > 0*/ 1495 if (RND_ENABLED(&sc->rnd_source)) 1496 rnd_add_uint32(&sc->rnd_source, icr); 1497 #endif 1498 1499 handled = 1; 1500 1501 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1502 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1503 DPRINTF(DGE_DEBUG_RX, 1504 ("%s: RX: got Rx intr 0x%08x\n", 1505 device_xname(&sc->sc_dev), 1506 icr & (ICR_RXDMT0|ICR_RXT0))); 1507 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1508 } 1509 #endif 1510 dge_rxintr(sc); 1511 1512 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1513 if (icr & ICR_TXDW) { 1514 DPRINTF(DGE_DEBUG_TX, 1515 ("%s: TX: got TXDW interrupt\n", 1516 device_xname(&sc->sc_dev))); 1517 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1518 } 1519 if (icr & ICR_TXQE) 1520 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1521 #endif 1522 dge_txintr(sc); 1523 1524 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1525 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1526 dge_linkintr(sc, icr); 1527 } 1528 1529 if (icr & ICR_RXO) { 1530 printf("%s: Receive overrun\n", device_xname(&sc->sc_dev)); 1531 wantinit = 1; 1532 } 1533 } 1534 1535 if (handled) { 1536 if (wantinit) 1537 dge_init(ifp); 1538 1539 /* Try to get more packets going. */ 1540 dge_start(ifp); 1541 } 1542 1543 return (handled); 1544 } 1545 1546 /* 1547 * dge_txintr: 1548 * 1549 * Helper; handle transmit interrupts. 1550 */ 1551 static void 1552 dge_txintr(struct dge_softc *sc) 1553 { 1554 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1555 struct dge_txsoft *txs; 1556 uint8_t status; 1557 int i; 1558 1559 ifp->if_flags &= ~IFF_OACTIVE; 1560 1561 /* 1562 * Go through the Tx list and free mbufs for those 1563 * frames which have been transmitted. 1564 */ 1565 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1566 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1567 txs = &sc->sc_txsoft[i]; 1568 1569 DPRINTF(DGE_DEBUG_TX, 1570 ("%s: TX: checking job %d\n", device_xname(&sc->sc_dev), i)); 1571 1572 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1573 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1574 1575 status = 1576 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1577 if ((status & TDESC_STA_DD) == 0) { 1578 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1579 BUS_DMASYNC_PREREAD); 1580 break; 1581 } 1582 1583 DPRINTF(DGE_DEBUG_TX, 1584 ("%s: TX: job %d done: descs %d..%d\n", 1585 device_xname(&sc->sc_dev), i, txs->txs_firstdesc, 1586 txs->txs_lastdesc)); 1587 1588 ifp->if_opackets++; 1589 sc->sc_txfree += txs->txs_ndesc; 1590 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1591 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1592 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1593 m_freem(txs->txs_mbuf); 1594 txs->txs_mbuf = NULL; 1595 } 1596 1597 /* Update the dirty transmit buffer pointer. */ 1598 sc->sc_txsdirty = i; 1599 DPRINTF(DGE_DEBUG_TX, 1600 ("%s: TX: txsdirty -> %d\n", device_xname(&sc->sc_dev), i)); 1601 1602 /* 1603 * If there are no more pending transmissions, cancel the watchdog 1604 * timer. 1605 */ 1606 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1607 ifp->if_timer = 0; 1608 } 1609 1610 /* 1611 * dge_rxintr: 1612 * 1613 * Helper; handle receive interrupts. 1614 */ 1615 static void 1616 dge_rxintr(struct dge_softc *sc) 1617 { 1618 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1619 struct dge_rxsoft *rxs; 1620 struct mbuf *m; 1621 int i, len; 1622 uint8_t status, errors; 1623 1624 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1625 rxs = &sc->sc_rxsoft[i]; 1626 1627 DPRINTF(DGE_DEBUG_RX, 1628 ("%s: RX: checking descriptor %d\n", 1629 device_xname(&sc->sc_dev), i)); 1630 1631 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1632 1633 status = sc->sc_rxdescs[i].dr_status; 1634 errors = sc->sc_rxdescs[i].dr_errors; 1635 len = le16toh(sc->sc_rxdescs[i].dr_len); 1636 1637 if ((status & RDESC_STS_DD) == 0) { 1638 /* 1639 * We have processed all of the receive descriptors. 1640 */ 1641 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1642 break; 1643 } 1644 1645 if (__predict_false(sc->sc_rxdiscard)) { 1646 DPRINTF(DGE_DEBUG_RX, 1647 ("%s: RX: discarding contents of descriptor %d\n", 1648 device_xname(&sc->sc_dev), i)); 1649 DGE_INIT_RXDESC(sc, i); 1650 if (status & RDESC_STS_EOP) { 1651 /* Reset our state. */ 1652 DPRINTF(DGE_DEBUG_RX, 1653 ("%s: RX: resetting rxdiscard -> 0\n", 1654 device_xname(&sc->sc_dev))); 1655 sc->sc_rxdiscard = 0; 1656 } 1657 continue; 1658 } 1659 1660 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1661 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1662 1663 m = rxs->rxs_mbuf; 1664 1665 /* 1666 * Add a new receive buffer to the ring. 1667 */ 1668 if (dge_add_rxbuf(sc, i) != 0) { 1669 /* 1670 * Failed, throw away what we've done so 1671 * far, and discard the rest of the packet. 1672 */ 1673 ifp->if_ierrors++; 1674 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1675 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1676 DGE_INIT_RXDESC(sc, i); 1677 if ((status & RDESC_STS_EOP) == 0) 1678 sc->sc_rxdiscard = 1; 1679 if (sc->sc_rxhead != NULL) 1680 m_freem(sc->sc_rxhead); 1681 DGE_RXCHAIN_RESET(sc); 1682 DPRINTF(DGE_DEBUG_RX, 1683 ("%s: RX: Rx buffer allocation failed, " 1684 "dropping packet%s\n", device_xname(&sc->sc_dev), 1685 sc->sc_rxdiscard ? " (discard)" : "")); 1686 continue; 1687 } 1688 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1689 1690 DGE_RXCHAIN_LINK(sc, m); 1691 1692 m->m_len = len; 1693 1694 DPRINTF(DGE_DEBUG_RX, 1695 ("%s: RX: buffer at %p len %d\n", 1696 device_xname(&sc->sc_dev), m->m_data, len)); 1697 1698 /* 1699 * If this is not the end of the packet, keep 1700 * looking. 1701 */ 1702 if ((status & RDESC_STS_EOP) == 0) { 1703 sc->sc_rxlen += len; 1704 DPRINTF(DGE_DEBUG_RX, 1705 ("%s: RX: not yet EOP, rxlen -> %d\n", 1706 device_xname(&sc->sc_dev), sc->sc_rxlen)); 1707 continue; 1708 } 1709 1710 /* 1711 * Okay, we have the entire packet now... 1712 */ 1713 *sc->sc_rxtailp = NULL; 1714 m = sc->sc_rxhead; 1715 len += sc->sc_rxlen; 1716 1717 DGE_RXCHAIN_RESET(sc); 1718 1719 DPRINTF(DGE_DEBUG_RX, 1720 ("%s: RX: have entire packet, len -> %d\n", 1721 device_xname(&sc->sc_dev), len)); 1722 1723 /* 1724 * If an error occurred, update stats and drop the packet. 1725 */ 1726 if (errors & 1727 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1728 ifp->if_ierrors++; 1729 if (errors & RDESC_ERR_SE) 1730 printf("%s: symbol error\n", 1731 device_xname(&sc->sc_dev)); 1732 else if (errors & RDESC_ERR_P) 1733 printf("%s: parity error\n", 1734 device_xname(&sc->sc_dev)); 1735 else if (errors & RDESC_ERR_CE) 1736 printf("%s: CRC error\n", 1737 device_xname(&sc->sc_dev)); 1738 m_freem(m); 1739 continue; 1740 } 1741 1742 /* 1743 * No errors. Receive the packet. 1744 */ 1745 m->m_pkthdr.rcvif = ifp; 1746 m->m_pkthdr.len = len; 1747 1748 /* 1749 * Set up checksum info for this packet. 1750 */ 1751 if (status & RDESC_STS_IPCS) { 1752 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1753 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1754 if (errors & RDESC_ERR_IPE) 1755 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1756 } 1757 if (status & RDESC_STS_TCPCS) { 1758 /* 1759 * Note: we don't know if this was TCP or UDP, 1760 * so we just set both bits, and expect the 1761 * upper layers to deal. 1762 */ 1763 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1764 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1765 if (errors & RDESC_ERR_TCPE) 1766 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1767 } 1768 1769 ifp->if_ipackets++; 1770 1771 /* Pass this up to any BPF listeners. */ 1772 bpf_mtap(ifp, m); 1773 1774 /* Pass it on. */ 1775 (*ifp->if_input)(ifp, m); 1776 } 1777 1778 /* Update the receive pointer. */ 1779 sc->sc_rxptr = i; 1780 1781 DPRINTF(DGE_DEBUG_RX, 1782 ("%s: RX: rxptr -> %d\n", device_xname(&sc->sc_dev), i)); 1783 } 1784 1785 /* 1786 * dge_linkintr: 1787 * 1788 * Helper; handle link interrupts. 1789 */ 1790 static void 1791 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1792 { 1793 uint32_t status; 1794 1795 if (icr & ICR_LSC) { 1796 status = CSR_READ(sc, DGE_STATUS); 1797 if (status & STATUS_LINKUP) { 1798 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1799 device_xname(&sc->sc_dev))); 1800 } else { 1801 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1802 device_xname(&sc->sc_dev))); 1803 } 1804 } else if (icr & ICR_RXSEQ) { 1805 DPRINTF(DGE_DEBUG_LINK, 1806 ("%s: LINK: Receive sequence error\n", 1807 device_xname(&sc->sc_dev))); 1808 } 1809 /* XXX - fix errata */ 1810 } 1811 1812 /* 1813 * dge_reset: 1814 * 1815 * Reset the i82597 chip. 1816 */ 1817 static void 1818 dge_reset(struct dge_softc *sc) 1819 { 1820 int i; 1821 1822 /* 1823 * Do a chip reset. 1824 */ 1825 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1826 1827 delay(10000); 1828 1829 for (i = 0; i < 1000; i++) { 1830 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1831 break; 1832 delay(20); 1833 } 1834 1835 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1836 printf("%s: WARNING: reset failed to complete\n", 1837 device_xname(&sc->sc_dev)); 1838 /* 1839 * Reset the EEPROM logic. 1840 * This will cause the chip to reread its default values, 1841 * which doesn't happen otherwise (errata). 1842 */ 1843 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1844 delay(10000); 1845 } 1846 1847 /* 1848 * dge_init: [ifnet interface function] 1849 * 1850 * Initialize the interface. Must be called at splnet(). 1851 */ 1852 static int 1853 dge_init(struct ifnet *ifp) 1854 { 1855 struct dge_softc *sc = ifp->if_softc; 1856 struct dge_rxsoft *rxs; 1857 int i, error = 0; 1858 uint32_t reg; 1859 1860 /* 1861 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1862 * There is a small but measurable benefit to avoiding the adjusment 1863 * of the descriptor so that the headers are aligned, for normal mtu, 1864 * on such platforms. One possibility is that the DMA itself is 1865 * slightly more efficient if the front of the entire packet (instead 1866 * of the front of the headers) is aligned. 1867 * 1868 * Note we must always set align_tweak to 0 if we are using 1869 * jumbo frames. 1870 */ 1871 #ifdef __NO_STRICT_ALIGNMENT 1872 sc->sc_align_tweak = 0; 1873 #else 1874 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1875 sc->sc_align_tweak = 0; 1876 else 1877 sc->sc_align_tweak = 2; 1878 #endif /* __NO_STRICT_ALIGNMENT */ 1879 1880 /* Cancel any pending I/O. */ 1881 dge_stop(ifp, 0); 1882 1883 /* Reset the chip to a known state. */ 1884 dge_reset(sc); 1885 1886 /* Initialize the transmit descriptor ring. */ 1887 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1888 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1889 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1890 sc->sc_txfree = DGE_NTXDESC; 1891 sc->sc_txnext = 0; 1892 1893 sc->sc_txctx_ipcs = 0xffffffff; 1894 sc->sc_txctx_tucs = 0xffffffff; 1895 1896 CSR_WRITE(sc, DGE_TDBAH, 0); 1897 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1898 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1899 CSR_WRITE(sc, DGE_TDH, 0); 1900 CSR_WRITE(sc, DGE_TDT, 0); 1901 CSR_WRITE(sc, DGE_TIDV, TIDV); 1902 1903 #if 0 1904 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1905 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1906 #endif 1907 CSR_WRITE(sc, DGE_RXDCTL, 1908 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1909 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1910 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1911 1912 /* Initialize the transmit job descriptors. */ 1913 for (i = 0; i < DGE_TXQUEUELEN; i++) 1914 sc->sc_txsoft[i].txs_mbuf = NULL; 1915 sc->sc_txsfree = DGE_TXQUEUELEN; 1916 sc->sc_txsnext = 0; 1917 sc->sc_txsdirty = 0; 1918 1919 /* 1920 * Initialize the receive descriptor and receive job 1921 * descriptor rings. 1922 */ 1923 CSR_WRITE(sc, DGE_RDBAH, 0); 1924 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1925 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1926 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1927 CSR_WRITE(sc, DGE_RDT, 0); 1928 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1929 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1930 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1931 1932 for (i = 0; i < DGE_NRXDESC; i++) { 1933 rxs = &sc->sc_rxsoft[i]; 1934 if (rxs->rxs_mbuf == NULL) { 1935 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1936 printf("%s: unable to allocate or map rx " 1937 "buffer %d, error = %d\n", 1938 device_xname(&sc->sc_dev), i, error); 1939 /* 1940 * XXX Should attempt to run with fewer receive 1941 * XXX buffers instead of just failing. 1942 */ 1943 dge_rxdrain(sc); 1944 goto out; 1945 } 1946 } 1947 DGE_INIT_RXDESC(sc, i); 1948 } 1949 sc->sc_rxptr = DGE_RXSPACE; 1950 sc->sc_rxdiscard = 0; 1951 DGE_RXCHAIN_RESET(sc); 1952 1953 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1954 sc->sc_ctrl0 |= CTRL0_JFE; 1955 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1956 } 1957 1958 /* Write the control registers. */ 1959 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1960 1961 /* 1962 * Set up checksum offload parameters. 1963 */ 1964 reg = CSR_READ(sc, DGE_RXCSUM); 1965 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1966 reg |= RXCSUM_IPOFL; 1967 else 1968 reg &= ~RXCSUM_IPOFL; 1969 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1970 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1971 else { 1972 reg &= ~RXCSUM_TUOFL; 1973 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 1974 reg &= ~RXCSUM_IPOFL; 1975 } 1976 CSR_WRITE(sc, DGE_RXCSUM, reg); 1977 1978 /* 1979 * Set up the interrupt registers. 1980 */ 1981 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 1982 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 1983 ICR_RXO | ICR_RXT0; 1984 1985 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 1986 1987 /* 1988 * Set up the transmit control register. 1989 */ 1990 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 1991 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 1992 1993 /* 1994 * Set up the receive control register; we actually program 1995 * the register when we set the receive filter. Use multicast 1996 * address offset type 0. 1997 */ 1998 sc->sc_mchash_type = 0; 1999 2000 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2001 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2002 2003 #ifdef DGE_OFFBYONE_RXBUG 2004 sc->sc_rctl |= RCTL_BSIZE_16k; 2005 #else 2006 switch(MCLBYTES) { 2007 case 2048: 2008 sc->sc_rctl |= RCTL_BSIZE_2k; 2009 break; 2010 case 4096: 2011 sc->sc_rctl |= RCTL_BSIZE_4k; 2012 break; 2013 case 8192: 2014 sc->sc_rctl |= RCTL_BSIZE_8k; 2015 break; 2016 case 16384: 2017 sc->sc_rctl |= RCTL_BSIZE_16k; 2018 break; 2019 default: 2020 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2021 } 2022 #endif 2023 2024 /* Set the receive filter. */ 2025 /* Also sets RCTL */ 2026 dge_set_filter(sc); 2027 2028 /* ...all done! */ 2029 ifp->if_flags |= IFF_RUNNING; 2030 ifp->if_flags &= ~IFF_OACTIVE; 2031 2032 out: 2033 if (error) 2034 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 2035 return (error); 2036 } 2037 2038 /* 2039 * dge_rxdrain: 2040 * 2041 * Drain the receive queue. 2042 */ 2043 static void 2044 dge_rxdrain(struct dge_softc *sc) 2045 { 2046 struct dge_rxsoft *rxs; 2047 int i; 2048 2049 for (i = 0; i < DGE_NRXDESC; i++) { 2050 rxs = &sc->sc_rxsoft[i]; 2051 if (rxs->rxs_mbuf != NULL) { 2052 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2053 m_freem(rxs->rxs_mbuf); 2054 rxs->rxs_mbuf = NULL; 2055 } 2056 } 2057 } 2058 2059 /* 2060 * dge_stop: [ifnet interface function] 2061 * 2062 * Stop transmission on the interface. 2063 */ 2064 static void 2065 dge_stop(struct ifnet *ifp, int disable) 2066 { 2067 struct dge_softc *sc = ifp->if_softc; 2068 struct dge_txsoft *txs; 2069 int i; 2070 2071 /* Stop the transmit and receive processes. */ 2072 CSR_WRITE(sc, DGE_TCTL, 0); 2073 CSR_WRITE(sc, DGE_RCTL, 0); 2074 2075 /* Release any queued transmit buffers. */ 2076 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2077 txs = &sc->sc_txsoft[i]; 2078 if (txs->txs_mbuf != NULL) { 2079 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2080 m_freem(txs->txs_mbuf); 2081 txs->txs_mbuf = NULL; 2082 } 2083 } 2084 2085 /* Mark the interface as down and cancel the watchdog timer. */ 2086 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2087 ifp->if_timer = 0; 2088 2089 if (disable) 2090 dge_rxdrain(sc); 2091 } 2092 2093 /* 2094 * dge_add_rxbuf: 2095 * 2096 * Add a receive buffer to the indiciated descriptor. 2097 */ 2098 static int 2099 dge_add_rxbuf(struct dge_softc *sc, int idx) 2100 { 2101 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2102 struct mbuf *m; 2103 int error; 2104 #ifdef DGE_OFFBYONE_RXBUG 2105 void *buf; 2106 #endif 2107 2108 MGETHDR(m, M_DONTWAIT, MT_DATA); 2109 if (m == NULL) 2110 return (ENOBUFS); 2111 2112 #ifdef DGE_OFFBYONE_RXBUG 2113 if ((buf = dge_getbuf(sc)) == NULL) 2114 return ENOBUFS; 2115 2116 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2117 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2118 m->m_flags |= M_EXT_RW; 2119 2120 if (rxs->rxs_mbuf != NULL) 2121 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2122 rxs->rxs_mbuf = m; 2123 2124 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2125 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2126 #else 2127 MCLGET(m, M_DONTWAIT); 2128 if ((m->m_flags & M_EXT) == 0) { 2129 m_freem(m); 2130 return (ENOBUFS); 2131 } 2132 2133 if (rxs->rxs_mbuf != NULL) 2134 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2135 2136 rxs->rxs_mbuf = m; 2137 2138 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2139 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2140 BUS_DMA_READ|BUS_DMA_NOWAIT); 2141 #endif 2142 if (error) { 2143 printf("%s: unable to load rx DMA map %d, error = %d\n", 2144 device_xname(&sc->sc_dev), idx, error); 2145 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2146 } 2147 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2148 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2149 2150 return (0); 2151 } 2152 2153 /* 2154 * dge_set_ral: 2155 * 2156 * Set an entry in the receive address list. 2157 */ 2158 static void 2159 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2160 { 2161 uint32_t ral_lo, ral_hi; 2162 2163 if (enaddr != NULL) { 2164 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2165 (enaddr[3] << 24); 2166 ral_hi = enaddr[4] | (enaddr[5] << 8); 2167 ral_hi |= RAH_AV; 2168 } else { 2169 ral_lo = 0; 2170 ral_hi = 0; 2171 } 2172 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2173 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2174 } 2175 2176 /* 2177 * dge_mchash: 2178 * 2179 * Compute the hash of the multicast address for the 4096-bit 2180 * multicast filter. 2181 */ 2182 static uint32_t 2183 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2184 { 2185 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2186 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2187 uint32_t hash; 2188 2189 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2190 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2191 2192 return (hash & 0xfff); 2193 } 2194 2195 /* 2196 * dge_set_filter: 2197 * 2198 * Set up the receive filter. 2199 */ 2200 static void 2201 dge_set_filter(struct dge_softc *sc) 2202 { 2203 struct ethercom *ec = &sc->sc_ethercom; 2204 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2205 struct ether_multi *enm; 2206 struct ether_multistep step; 2207 uint32_t hash, reg, bit; 2208 int i; 2209 2210 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2211 2212 if (ifp->if_flags & IFF_BROADCAST) 2213 sc->sc_rctl |= RCTL_BAM; 2214 if (ifp->if_flags & IFF_PROMISC) { 2215 sc->sc_rctl |= RCTL_UPE; 2216 goto allmulti; 2217 } 2218 2219 /* 2220 * Set the station address in the first RAL slot, and 2221 * clear the remaining slots. 2222 */ 2223 dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 2224 for (i = 1; i < RA_TABSIZE; i++) 2225 dge_set_ral(sc, NULL, i); 2226 2227 /* Clear out the multicast table. */ 2228 for (i = 0; i < MC_TABSIZE; i++) 2229 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2230 2231 ETHER_FIRST_MULTI(step, ec, enm); 2232 while (enm != NULL) { 2233 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2234 /* 2235 * We must listen to a range of multicast addresses. 2236 * For now, just accept all multicasts, rather than 2237 * trying to set only those filter bits needed to match 2238 * the range. (At this time, the only use of address 2239 * ranges is for IP multicast routing, for which the 2240 * range is big enough to require all bits set.) 2241 */ 2242 goto allmulti; 2243 } 2244 2245 hash = dge_mchash(sc, enm->enm_addrlo); 2246 2247 reg = (hash >> 5) & 0x7f; 2248 bit = hash & 0x1f; 2249 2250 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2251 hash |= 1U << bit; 2252 2253 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2254 2255 ETHER_NEXT_MULTI(step, enm); 2256 } 2257 2258 ifp->if_flags &= ~IFF_ALLMULTI; 2259 goto setit; 2260 2261 allmulti: 2262 ifp->if_flags |= IFF_ALLMULTI; 2263 sc->sc_rctl |= RCTL_MPE; 2264 2265 setit: 2266 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2267 } 2268 2269 /* 2270 * Read in the EEPROM info and verify checksum. 2271 */ 2272 int 2273 dge_read_eeprom(struct dge_softc *sc) 2274 { 2275 uint16_t cksum; 2276 int i; 2277 2278 cksum = 0; 2279 for (i = 0; i < EEPROM_SIZE; i++) { 2280 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2281 cksum += sc->sc_eeprom[i]; 2282 } 2283 return cksum != EEPROM_CKSUM; 2284 } 2285 2286 2287 /* 2288 * Read a 16-bit word from address addr in the serial EEPROM. 2289 */ 2290 uint16_t 2291 dge_eeprom_word(struct dge_softc *sc, int addr) 2292 { 2293 uint32_t reg; 2294 uint16_t rval = 0; 2295 int i; 2296 2297 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2298 2299 /* Lower clock pulse (and data in to chip) */ 2300 CSR_WRITE(sc, DGE_EECD, reg); 2301 /* Select chip */ 2302 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2303 2304 /* Send read command */ 2305 dge_eeprom_clockout(sc, 1); 2306 dge_eeprom_clockout(sc, 1); 2307 dge_eeprom_clockout(sc, 0); 2308 2309 /* Send address */ 2310 for (i = 5; i >= 0; i--) 2311 dge_eeprom_clockout(sc, (addr >> i) & 1); 2312 2313 /* Read data */ 2314 for (i = 0; i < 16; i++) { 2315 rval <<= 1; 2316 rval |= dge_eeprom_clockin(sc); 2317 } 2318 2319 /* Deselect chip */ 2320 CSR_WRITE(sc, DGE_EECD, reg); 2321 2322 return rval; 2323 } 2324 2325 /* 2326 * Clock out a single bit to the EEPROM. 2327 */ 2328 void 2329 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2330 { 2331 int reg; 2332 2333 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2334 if (bit) 2335 reg |= EECD_DI; 2336 2337 CSR_WRITE(sc, DGE_EECD, reg); 2338 delay(2); 2339 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2340 delay(2); 2341 CSR_WRITE(sc, DGE_EECD, reg); 2342 delay(2); 2343 } 2344 2345 /* 2346 * Clock in a single bit from EEPROM. 2347 */ 2348 int 2349 dge_eeprom_clockin(struct dge_softc *sc) 2350 { 2351 int reg, rv; 2352 2353 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2354 2355 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2356 delay(2); 2357 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2358 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2359 delay(2); 2360 2361 return rv; 2362 } 2363 2364 static void 2365 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2366 { 2367 struct dge_softc *sc = ifp->if_softc; 2368 2369 ifmr->ifm_status = IFM_AVALID; 2370 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2371 2372 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2373 ifmr->ifm_status |= IFM_ACTIVE; 2374 } 2375 2376 static inline int 2377 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2378 { 2379 int i, mdic; 2380 2381 CSR_WRITE(sc, DGE_MDIO, 2382 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2383 for (i = 0; i < 10; i++) { 2384 delay(10); 2385 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2386 break; 2387 } 2388 return mdic; 2389 } 2390 2391 2392 static void 2393 dge_xgmii_writereg(device_t self, int phy, int reg, int val) 2394 { 2395 struct dge_softc *sc = device_private(self); 2396 int mdic; 2397 2398 CSR_WRITE(sc, DGE_MDIRW, val); 2399 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2400 printf("%s: address cycle timeout; phy %d reg %d\n", 2401 device_xname(&sc->sc_dev), phy, reg); 2402 return; 2403 } 2404 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2405 printf("%s: read cycle timeout; phy %d reg %d\n", 2406 device_xname(&sc->sc_dev), phy, reg); 2407 return; 2408 } 2409 } 2410 2411 static void 2412 dge_xgmii_reset(struct dge_softc *sc) 2413 { 2414 dge_xgmii_writereg((void *)sc, 0, 0, BMCR_RESET); 2415 } 2416 2417 static int 2418 dge_xgmii_mediachange(struct ifnet *ifp) 2419 { 2420 return 0; 2421 } 2422