1 /* $NetBSD: if_dge.c,v 1.12 2005/12/11 12:22:49 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.12 2005/12/11 12:22:49 christos Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <netinet/in.h> /* XXX for struct ip */ 116 #include <netinet/in_systm.h> /* XXX for struct ip */ 117 #include <netinet/ip.h> /* XXX for struct ip */ 118 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 #include <machine/endian.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/mii_bitbang.h> 127 128 #include <dev/pci/pcireg.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/pcidevs.h> 131 132 #include <dev/pci/if_dgereg.h> 133 134 /* 135 * The receive engine may sometimes become off-by-one when writing back 136 * chained descriptors. Avoid this by allocating a large chunk of 137 * memory and use if instead (to avoid chained descriptors). 138 * This only happens with chained descriptors under heavy load. 139 */ 140 #define DGE_OFFBYONE_RXBUG 141 142 #define DGE_EVENT_COUNTERS 143 #define DGE_DEBUG 144 145 #ifdef DGE_DEBUG 146 #define DGE_DEBUG_LINK 0x01 147 #define DGE_DEBUG_TX 0x02 148 #define DGE_DEBUG_RX 0x04 149 #define DGE_DEBUG_CKSUM 0x08 150 int dge_debug = 0; 151 152 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 153 #else 154 #define DPRINTF(x, y) /* nothing */ 155 #endif /* DGE_DEBUG */ 156 157 /* 158 * Transmit descriptor list size. We allow up to 100 DMA segments per 159 * packet (Intel reports of jumbo frame packets with as 160 * many as 80 DMA segments when using 16k buffers). 161 */ 162 #define DGE_NTXSEGS 100 163 #define DGE_IFQUEUELEN 20000 164 #define DGE_TXQUEUELEN 2048 165 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 166 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 167 #define DGE_NTXDESC 1024 168 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 169 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 170 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 171 172 /* 173 * Receive descriptor list size. 174 * Packet is of size MCLBYTES, and for jumbo packets buffers may 175 * be chained. Due to the nature of the card (high-speed), keep this 176 * ring large. With 2k buffers the ring can store 400 jumbo packets, 177 * which at full speed will be received in just under 3ms. 178 */ 179 #define DGE_NRXDESC 2048 180 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 181 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 182 /* 183 * # of descriptors between head and written descriptors. 184 * This is to work-around two erratas. 185 */ 186 #define DGE_RXSPACE 10 187 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 188 /* 189 * Receive descriptor fetch threshholds. These are values recommended 190 * by Intel, do not touch them unless you know what you are doing. 191 */ 192 #define RXDCTL_PTHRESH_VAL 128 193 #define RXDCTL_HTHRESH_VAL 16 194 #define RXDCTL_WTHRESH_VAL 16 195 196 197 /* 198 * Tweakable parameters; default values. 199 */ 200 #define FCRTH 0x30000 /* Send XOFF water mark */ 201 #define FCRTL 0x28000 /* Send XON water mark */ 202 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 203 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 204 205 /* 206 * Control structures are DMA'd to the i82597 chip. We allocate them in 207 * a single clump that maps to a single DMA segment to make serveral things 208 * easier. 209 */ 210 struct dge_control_data { 211 /* 212 * The transmit descriptors. 213 */ 214 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 215 216 /* 217 * The receive descriptors. 218 */ 219 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 220 }; 221 222 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 223 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 224 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 225 226 /* 227 * The DGE interface have a higher max MTU size than normal jumbo frames. 228 */ 229 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 230 231 /* 232 * Software state for transmit jobs. 233 */ 234 struct dge_txsoft { 235 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 236 bus_dmamap_t txs_dmamap; /* our DMA map */ 237 int txs_firstdesc; /* first descriptor in packet */ 238 int txs_lastdesc; /* last descriptor in packet */ 239 int txs_ndesc; /* # of descriptors used */ 240 }; 241 242 /* 243 * Software state for receive buffers. Each descriptor gets a 244 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 245 * more than one buffer, we chain them together. 246 */ 247 struct dge_rxsoft { 248 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 249 bus_dmamap_t rxs_dmamap; /* our DMA map */ 250 }; 251 252 /* 253 * Software state per device. 254 */ 255 struct dge_softc { 256 struct device sc_dev; /* generic device information */ 257 bus_space_tag_t sc_st; /* bus space tag */ 258 bus_space_handle_t sc_sh; /* bus space handle */ 259 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 260 struct ethercom sc_ethercom; /* ethernet common data */ 261 void *sc_sdhook; /* shutdown hook */ 262 263 int sc_flags; /* flags; see below */ 264 int sc_bus_speed; /* PCI/PCIX bus speed */ 265 int sc_pcix_offset; /* PCIX capability register offset */ 266 267 pci_chipset_tag_t sc_pc; 268 pcitag_t sc_pt; 269 int sc_mmrbc; /* Max PCIX memory read byte count */ 270 271 void *sc_ih; /* interrupt cookie */ 272 273 struct ifmedia sc_media; 274 275 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 276 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 277 278 int sc_align_tweak; 279 280 /* 281 * Software state for the transmit and receive descriptors. 282 */ 283 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 284 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 285 286 /* 287 * Control data structures. 288 */ 289 struct dge_control_data *sc_control_data; 290 #define sc_txdescs sc_control_data->wcd_txdescs 291 #define sc_rxdescs sc_control_data->wcd_rxdescs 292 293 #ifdef DGE_EVENT_COUNTERS 294 /* Event counters. */ 295 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 296 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 297 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 298 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 299 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 300 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 301 struct evcnt sc_ev_linkintr; /* Link interrupts */ 302 303 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 304 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 305 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 306 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 307 308 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 309 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 310 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 311 312 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 313 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 314 #endif /* DGE_EVENT_COUNTERS */ 315 316 int sc_txfree; /* number of free Tx descriptors */ 317 int sc_txnext; /* next ready Tx descriptor */ 318 319 int sc_txsfree; /* number of free Tx jobs */ 320 int sc_txsnext; /* next free Tx job */ 321 int sc_txsdirty; /* dirty Tx jobs */ 322 323 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 324 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 325 326 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 327 int sc_rxdiscard; 328 int sc_rxlen; 329 struct mbuf *sc_rxhead; 330 struct mbuf *sc_rxtail; 331 struct mbuf **sc_rxtailp; 332 333 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 334 uint32_t sc_icr; /* prototype interrupt bits */ 335 uint32_t sc_tctl; /* prototype TCTL register */ 336 uint32_t sc_rctl; /* prototype RCTL register */ 337 338 int sc_mchash_type; /* multicast filter offset */ 339 340 uint16_t sc_eeprom[EEPROM_SIZE]; 341 342 #if NRND > 0 343 rndsource_element_t rnd_source; /* random source */ 344 #endif 345 #ifdef DGE_OFFBYONE_RXBUG 346 caddr_t sc_bugbuf; 347 SLIST_HEAD(, rxbugentry) sc_buglist; 348 bus_dmamap_t sc_bugmap; 349 struct rxbugentry *sc_entry; 350 #endif 351 }; 352 353 #define DGE_RXCHAIN_RESET(sc) \ 354 do { \ 355 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 356 *(sc)->sc_rxtailp = NULL; \ 357 (sc)->sc_rxlen = 0; \ 358 } while (/*CONSTCOND*/0) 359 360 #define DGE_RXCHAIN_LINK(sc, m) \ 361 do { \ 362 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 363 (sc)->sc_rxtailp = &(m)->m_next; \ 364 } while (/*CONSTCOND*/0) 365 366 /* sc_flags */ 367 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 368 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 369 370 #ifdef DGE_EVENT_COUNTERS 371 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 372 #else 373 #define DGE_EVCNT_INCR(ev) /* nothing */ 374 #endif 375 376 #define CSR_READ(sc, reg) \ 377 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 #define CSR_WRITE(sc, reg, val) \ 379 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 381 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 382 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 383 384 #define DGE_CDTXSYNC(sc, x, n, ops) \ 385 do { \ 386 int __x, __n; \ 387 \ 388 __x = (x); \ 389 __n = (n); \ 390 \ 391 /* If it will wrap around, sync to the end of the ring. */ \ 392 if ((__x + __n) > DGE_NTXDESC) { \ 393 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 394 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 395 (DGE_NTXDESC - __x), (ops)); \ 396 __n -= (DGE_NTXDESC - __x); \ 397 __x = 0; \ 398 } \ 399 \ 400 /* Now sync whatever is left. */ \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 403 } while (/*CONSTCOND*/0) 404 405 #define DGE_CDRXSYNC(sc, x, ops) \ 406 do { \ 407 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 408 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 409 } while (/*CONSTCOND*/0) 410 411 #ifdef DGE_OFFBYONE_RXBUG 412 #define DGE_INIT_RXDESC(sc, x) \ 413 do { \ 414 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 415 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 416 struct mbuf *__m = __rxs->rxs_mbuf; \ 417 \ 418 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 419 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 420 __rxd->dr_baddrh = 0; \ 421 __rxd->dr_len = 0; \ 422 __rxd->dr_cksum = 0; \ 423 __rxd->dr_status = 0; \ 424 __rxd->dr_errors = 0; \ 425 __rxd->dr_special = 0; \ 426 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 427 \ 428 CSR_WRITE((sc), DGE_RDT, (x)); \ 429 } while (/*CONSTCOND*/0) 430 #else 431 #define DGE_INIT_RXDESC(sc, x) \ 432 do { \ 433 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 434 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 435 struct mbuf *__m = __rxs->rxs_mbuf; \ 436 \ 437 /* \ 438 * Note: We scoot the packet forward 2 bytes in the buffer \ 439 * so that the payload after the Ethernet header is aligned \ 440 * to a 4-byte boundary. \ 441 * \ 442 * XXX BRAINDAMAGE ALERT! \ 443 * The stupid chip uses the same size for every buffer, which \ 444 * is set in the Receive Control register. We are using the 2K \ 445 * size option, but what we REALLY want is (2K - 2)! For this \ 446 * reason, we can't "scoot" packets longer than the standard \ 447 * Ethernet MTU. On strict-alignment platforms, if the total \ 448 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 449 * the upper layer copy the headers. \ 450 */ \ 451 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 452 \ 453 __rxd->dr_baddrl = \ 454 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 455 (sc)->sc_align_tweak); \ 456 __rxd->dr_baddrh = 0; \ 457 __rxd->dr_len = 0; \ 458 __rxd->dr_cksum = 0; \ 459 __rxd->dr_status = 0; \ 460 __rxd->dr_errors = 0; \ 461 __rxd->dr_special = 0; \ 462 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 463 \ 464 CSR_WRITE((sc), DGE_RDT, (x)); \ 465 } while (/*CONSTCOND*/0) 466 #endif 467 468 #ifdef DGE_OFFBYONE_RXBUG 469 /* 470 * Allocation constants. Much memory may be used for this. 471 */ 472 #ifndef DGE_BUFFER_SIZE 473 #define DGE_BUFFER_SIZE DGE_MAX_MTU 474 #endif 475 #define DGE_NBUFFERS (4*DGE_NRXDESC) 476 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 477 478 struct rxbugentry { 479 SLIST_ENTRY(rxbugentry) rb_entry; 480 int rb_slot; 481 }; 482 483 static int 484 dge_alloc_rcvmem(struct dge_softc *sc) 485 { 486 caddr_t ptr, kva; 487 bus_dma_segment_t seg; 488 int i, rseg, state, error; 489 struct rxbugentry *entry; 490 491 state = error = 0; 492 493 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 494 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 495 printf("%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname); 496 return ENOBUFS; 497 } 498 499 state = 1; 500 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, &kva, 501 BUS_DMA_NOWAIT)) { 502 printf("%s: can't map DMA buffers (%d bytes)\n", 503 sc->sc_dev.dv_xname, (int)DGE_RXMEM); 504 error = ENOBUFS; 505 goto out; 506 } 507 508 state = 2; 509 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 510 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 511 printf("%s: can't create DMA map\n", sc->sc_dev.dv_xname); 512 error = ENOBUFS; 513 goto out; 514 } 515 516 state = 3; 517 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 518 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 519 printf("%s: can't load DMA map\n", sc->sc_dev.dv_xname); 520 error = ENOBUFS; 521 goto out; 522 } 523 524 state = 4; 525 sc->sc_bugbuf = (caddr_t)kva; 526 SLIST_INIT(&sc->sc_buglist); 527 528 /* 529 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 530 * in an array. 531 */ 532 ptr = sc->sc_bugbuf; 533 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 534 M_DEVBUF, M_NOWAIT)) == NULL) { 535 error = ENOBUFS; 536 goto out; 537 } 538 sc->sc_entry = entry; 539 for (i = 0; i < DGE_NBUFFERS; i++) { 540 entry[i].rb_slot = i; 541 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 542 } 543 out: 544 if (error != 0) { 545 switch (state) { 546 case 4: 547 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 548 case 3: 549 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 550 case 2: 551 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 552 case 1: 553 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 554 break; 555 default: 556 break; 557 } 558 } 559 560 return error; 561 } 562 563 /* 564 * Allocate a jumbo buffer. 565 */ 566 static void * 567 dge_getbuf(struct dge_softc *sc) 568 { 569 struct rxbugentry *entry; 570 571 entry = SLIST_FIRST(&sc->sc_buglist); 572 573 if (entry == NULL) { 574 printf("%s: no free RX buffers\n", sc->sc_dev.dv_xname); 575 return(NULL); 576 } 577 578 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 579 return sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 580 } 581 582 /* 583 * Release a jumbo buffer. 584 */ 585 static void 586 dge_freebuf(struct mbuf *m, caddr_t buf, size_t size, void *arg) 587 { 588 struct rxbugentry *entry; 589 struct dge_softc *sc; 590 int i, s; 591 592 /* Extract the softc struct pointer. */ 593 sc = (struct dge_softc *)arg; 594 595 if (sc == NULL) 596 panic("dge_freebuf: can't find softc pointer!"); 597 598 /* calculate the slot this buffer belongs to */ 599 600 i = (buf - sc->sc_bugbuf) / DGE_BUFFER_SIZE; 601 602 if ((i < 0) || (i >= DGE_NBUFFERS)) 603 panic("dge_freebuf: asked to free buffer %d!", i); 604 605 s = splvm(); 606 entry = sc->sc_entry + i; 607 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 608 609 if (__predict_true(m != NULL)) 610 pool_cache_put(&mbpool_cache, m); 611 splx(s); 612 } 613 #endif 614 615 static void dge_start(struct ifnet *); 616 static void dge_watchdog(struct ifnet *); 617 static int dge_ioctl(struct ifnet *, u_long, caddr_t); 618 static int dge_init(struct ifnet *); 619 static void dge_stop(struct ifnet *, int); 620 621 static void dge_shutdown(void *); 622 623 static void dge_reset(struct dge_softc *); 624 static void dge_rxdrain(struct dge_softc *); 625 static int dge_add_rxbuf(struct dge_softc *, int); 626 627 static void dge_set_filter(struct dge_softc *); 628 629 static int dge_intr(void *); 630 static void dge_txintr(struct dge_softc *); 631 static void dge_rxintr(struct dge_softc *); 632 static void dge_linkintr(struct dge_softc *, uint32_t); 633 634 static int dge_match(struct device *, struct cfdata *, void *); 635 static void dge_attach(struct device *, struct device *, void *); 636 637 static int dge_read_eeprom(struct dge_softc *sc); 638 static int dge_eeprom_clockin(struct dge_softc *sc); 639 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 640 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 641 static int dge_xgmii_mediachange(struct ifnet *); 642 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 643 static void dge_xgmii_reset(struct dge_softc *); 644 static void dge_xgmii_writereg(struct device *, int, int, int); 645 646 647 CFATTACH_DECL(dge, sizeof(struct dge_softc), 648 dge_match, dge_attach, NULL, NULL); 649 650 #ifdef DGE_EVENT_COUNTERS 651 #if DGE_NTXSEGS > 100 652 #error Update dge_txseg_evcnt_names 653 #endif 654 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 655 #endif /* DGE_EVENT_COUNTERS */ 656 657 static int 658 dge_match(struct device *parent, struct cfdata *cf, void *aux) 659 { 660 struct pci_attach_args *pa = aux; 661 662 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 663 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82597EX) 664 return (1); 665 666 return (0); 667 } 668 669 static void 670 dge_attach(struct device *parent, struct device *self, void *aux) 671 { 672 struct dge_softc *sc = (void *) self; 673 struct pci_attach_args *pa = aux; 674 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 675 pci_chipset_tag_t pc = pa->pa_pc; 676 pci_intr_handle_t ih; 677 const char *intrstr = NULL; 678 bus_dma_segment_t seg; 679 int i, rseg, error; 680 uint8_t enaddr[ETHER_ADDR_LEN]; 681 pcireg_t preg, memtype; 682 uint32_t reg; 683 684 sc->sc_dmat = pa->pa_dmat; 685 sc->sc_pc = pa->pa_pc; 686 sc->sc_pt = pa->pa_tag; 687 688 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 689 aprint_naive(": Ethernet controller\n"); 690 aprint_normal(": Intel i82597EX 10GbE-LR Ethernet, rev. %d\n", preg); 691 692 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 693 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 694 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 695 aprint_error("%s: unable to map device registers\n", 696 sc->sc_dev.dv_xname); 697 return; 698 } 699 700 /* Enable bus mastering */ 701 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 702 preg |= PCI_COMMAND_MASTER_ENABLE; 703 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 704 705 /* 706 * Map and establish our interrupt. 707 */ 708 if (pci_intr_map(pa, &ih)) { 709 aprint_error("%s: unable to map interrupt\n", 710 sc->sc_dev.dv_xname); 711 return; 712 } 713 intrstr = pci_intr_string(pc, ih); 714 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 715 if (sc->sc_ih == NULL) { 716 aprint_error("%s: unable to establish interrupt", 717 sc->sc_dev.dv_xname); 718 if (intrstr != NULL) 719 aprint_normal(" at %s", intrstr); 720 aprint_normal("\n"); 721 return; 722 } 723 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 724 725 /* 726 * Determine a few things about the bus we're connected to. 727 */ 728 reg = CSR_READ(sc, DGE_STATUS); 729 if (reg & STATUS_BUS64) 730 sc->sc_flags |= DGE_F_BUS64; 731 732 sc->sc_flags |= DGE_F_PCIX; 733 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 734 PCI_CAP_PCIX, 735 &sc->sc_pcix_offset, NULL) == 0) 736 aprint_error("%s: unable to find PCIX " 737 "capability\n", sc->sc_dev.dv_xname); 738 739 if (sc->sc_flags & DGE_F_PCIX) { 740 switch (reg & STATUS_PCIX_MSK) { 741 case STATUS_PCIX_66: 742 sc->sc_bus_speed = 66; 743 break; 744 case STATUS_PCIX_100: 745 sc->sc_bus_speed = 100; 746 break; 747 case STATUS_PCIX_133: 748 sc->sc_bus_speed = 133; 749 break; 750 default: 751 aprint_error( 752 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 753 sc->sc_dev.dv_xname, 754 reg & STATUS_PCIX_MSK); 755 sc->sc_bus_speed = 66; 756 } 757 } else 758 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 759 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 760 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 761 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 762 763 /* 764 * Allocate the control data structures, and create and load the 765 * DMA map for it. 766 */ 767 if ((error = bus_dmamem_alloc(sc->sc_dmat, 768 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 769 0)) != 0) { 770 aprint_error( 771 "%s: unable to allocate control data, error = %d\n", 772 sc->sc_dev.dv_xname, error); 773 goto fail_0; 774 } 775 776 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 777 sizeof(struct dge_control_data), (caddr_t *)&sc->sc_control_data, 778 0)) != 0) { 779 aprint_error("%s: unable to map control data, error = %d\n", 780 sc->sc_dev.dv_xname, error); 781 goto fail_1; 782 } 783 784 if ((error = bus_dmamap_create(sc->sc_dmat, 785 sizeof(struct dge_control_data), 1, 786 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 787 aprint_error("%s: unable to create control data DMA map, " 788 "error = %d\n", sc->sc_dev.dv_xname, error); 789 goto fail_2; 790 } 791 792 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 793 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 794 0)) != 0) { 795 aprint_error( 796 "%s: unable to load control data DMA map, error = %d\n", 797 sc->sc_dev.dv_xname, error); 798 goto fail_3; 799 } 800 801 #ifdef DGE_OFFBYONE_RXBUG 802 if (dge_alloc_rcvmem(sc) != 0) 803 return; /* Already complained */ 804 #endif 805 /* 806 * Create the transmit buffer DMA maps. 807 */ 808 for (i = 0; i < DGE_TXQUEUELEN; i++) { 809 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 810 DGE_NTXSEGS, MCLBYTES, 0, 0, 811 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 812 aprint_error("%s: unable to create Tx DMA map %d, " 813 "error = %d\n", sc->sc_dev.dv_xname, i, error); 814 goto fail_4; 815 } 816 } 817 818 /* 819 * Create the receive buffer DMA maps. 820 */ 821 for (i = 0; i < DGE_NRXDESC; i++) { 822 #ifdef DGE_OFFBYONE_RXBUG 823 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 824 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 825 #else 826 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 827 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 828 #endif 829 aprint_error("%s: unable to create Rx DMA map %d, " 830 "error = %d\n", sc->sc_dev.dv_xname, i, error); 831 goto fail_5; 832 } 833 sc->sc_rxsoft[i].rxs_mbuf = NULL; 834 } 835 836 /* 837 * Set bits in ctrl0 register. 838 * Should get the software defined pins out of EEPROM? 839 */ 840 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 841 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 842 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 843 844 /* 845 * Reset the chip to a known state. 846 */ 847 dge_reset(sc); 848 849 /* 850 * Reset the PHY. 851 */ 852 dge_xgmii_reset(sc); 853 854 /* 855 * Read in EEPROM data. 856 */ 857 if (dge_read_eeprom(sc)) { 858 aprint_error("%s: couldn't read EEPROM\n", sc->sc_dev.dv_xname); 859 return; 860 } 861 862 /* 863 * Get the ethernet address. 864 */ 865 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 866 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 867 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 868 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 869 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 870 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 871 872 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 873 ether_sprintf(enaddr)); 874 875 /* 876 * Setup media stuff. 877 */ 878 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 879 dge_xgmii_mediastatus); 880 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 881 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 882 883 ifp = &sc->sc_ethercom.ec_if; 884 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 885 ifp->if_softc = sc; 886 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 887 ifp->if_ioctl = dge_ioctl; 888 ifp->if_start = dge_start; 889 ifp->if_watchdog = dge_watchdog; 890 ifp->if_init = dge_init; 891 ifp->if_stop = dge_stop; 892 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 893 IFQ_SET_READY(&ifp->if_snd); 894 895 sc->sc_ethercom.ec_capabilities |= 896 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 897 898 /* 899 * We can perform TCPv4 and UDPv4 checkums in-bound. 900 */ 901 ifp->if_capabilities |= 902 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 903 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 904 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 905 906 /* 907 * Attach the interface. 908 */ 909 if_attach(ifp); 910 ether_ifattach(ifp, enaddr); 911 #if NRND > 0 912 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 913 RND_TYPE_NET, 0); 914 #endif 915 916 #ifdef DGE_EVENT_COUNTERS 917 /* Fix segment event naming */ 918 if (dge_txseg_evcnt_names == NULL) { 919 dge_txseg_evcnt_names = 920 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 921 for (i = 0; i < DGE_NTXSEGS; i++) 922 snprintf((*dge_txseg_evcnt_names)[i], 923 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 924 } 925 926 /* Attach event counters. */ 927 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 928 NULL, sc->sc_dev.dv_xname, "txsstall"); 929 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 930 NULL, sc->sc_dev.dv_xname, "txdstall"); 931 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 932 NULL, sc->sc_dev.dv_xname, "txforceintr"); 933 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 934 NULL, sc->sc_dev.dv_xname, "txdw"); 935 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 936 NULL, sc->sc_dev.dv_xname, "txqe"); 937 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 938 NULL, sc->sc_dev.dv_xname, "rxintr"); 939 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 940 NULL, sc->sc_dev.dv_xname, "linkintr"); 941 942 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 943 NULL, sc->sc_dev.dv_xname, "rxipsum"); 944 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 945 NULL, sc->sc_dev.dv_xname, "rxtusum"); 946 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 947 NULL, sc->sc_dev.dv_xname, "txipsum"); 948 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 949 NULL, sc->sc_dev.dv_xname, "txtusum"); 950 951 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 952 NULL, sc->sc_dev.dv_xname, "txctx init"); 953 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 954 NULL, sc->sc_dev.dv_xname, "txctx hit"); 955 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 956 NULL, sc->sc_dev.dv_xname, "txctx miss"); 957 958 for (i = 0; i < DGE_NTXSEGS; i++) 959 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 960 NULL, sc->sc_dev.dv_xname, (*dge_txseg_evcnt_names)[i]); 961 962 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 963 NULL, sc->sc_dev.dv_xname, "txdrop"); 964 965 #endif /* DGE_EVENT_COUNTERS */ 966 967 /* 968 * Make sure the interface is shutdown during reboot. 969 */ 970 sc->sc_sdhook = shutdownhook_establish(dge_shutdown, sc); 971 if (sc->sc_sdhook == NULL) 972 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 973 sc->sc_dev.dv_xname); 974 return; 975 976 /* 977 * Free any resources we've allocated during the failed attach 978 * attempt. Do this in reverse order and fall through. 979 */ 980 fail_5: 981 for (i = 0; i < DGE_NRXDESC; i++) { 982 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 983 bus_dmamap_destroy(sc->sc_dmat, 984 sc->sc_rxsoft[i].rxs_dmamap); 985 } 986 fail_4: 987 for (i = 0; i < DGE_TXQUEUELEN; i++) { 988 if (sc->sc_txsoft[i].txs_dmamap != NULL) 989 bus_dmamap_destroy(sc->sc_dmat, 990 sc->sc_txsoft[i].txs_dmamap); 991 } 992 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 993 fail_3: 994 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 995 fail_2: 996 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 997 sizeof(struct dge_control_data)); 998 fail_1: 999 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1000 fail_0: 1001 return; 1002 } 1003 1004 /* 1005 * dge_shutdown: 1006 * 1007 * Make sure the interface is stopped at reboot time. 1008 */ 1009 static void 1010 dge_shutdown(void *arg) 1011 { 1012 struct dge_softc *sc = arg; 1013 1014 dge_stop(&sc->sc_ethercom.ec_if, 1); 1015 } 1016 1017 /* 1018 * dge_tx_cksum: 1019 * 1020 * Set up TCP/IP checksumming parameters for the 1021 * specified packet. 1022 */ 1023 static int 1024 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1025 { 1026 struct mbuf *m0 = txs->txs_mbuf; 1027 struct dge_ctdes *t; 1028 uint32_t ipcs, tucs; 1029 struct ether_header *eh; 1030 int offset, iphl; 1031 uint8_t fields = 0; 1032 1033 /* 1034 * XXX It would be nice if the mbuf pkthdr had offset 1035 * fields for the protocol headers. 1036 */ 1037 1038 eh = mtod(m0, struct ether_header *); 1039 switch (htons(eh->ether_type)) { 1040 case ETHERTYPE_IP: 1041 offset = ETHER_HDR_LEN; 1042 break; 1043 1044 case ETHERTYPE_VLAN: 1045 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1046 break; 1047 1048 default: 1049 /* 1050 * Don't support this protocol or encapsulation. 1051 */ 1052 *fieldsp = 0; 1053 return (0); 1054 } 1055 1056 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1057 1058 /* 1059 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1060 * offload feature, if we load the context descriptor, we 1061 * MUST provide valid values for IPCSS and TUCSS fields. 1062 */ 1063 1064 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1065 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1066 fields |= TDESC_POPTS_IXSM; 1067 ipcs = DGE_TCPIP_IPCSS(offset) | 1068 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1069 DGE_TCPIP_IPCSE(offset + iphl - 1); 1070 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1071 /* Use the cached value. */ 1072 ipcs = sc->sc_txctx_ipcs; 1073 } else { 1074 /* Just initialize it to the likely value anyway. */ 1075 ipcs = DGE_TCPIP_IPCSS(offset) | 1076 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1077 DGE_TCPIP_IPCSE(offset + iphl - 1); 1078 } 1079 DPRINTF(DGE_DEBUG_CKSUM, 1080 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1081 sc->sc_dev.dv_xname, offset, ipcs)); 1082 1083 offset += iphl; 1084 1085 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1086 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1087 fields |= TDESC_POPTS_TXSM; 1088 tucs = DGE_TCPIP_TUCSS(offset) | 1089 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1090 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1091 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1092 /* Use the cached value. */ 1093 tucs = sc->sc_txctx_tucs; 1094 } else { 1095 /* Just initialize it to a valid TCP context. */ 1096 tucs = DGE_TCPIP_TUCSS(offset) | 1097 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1098 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1099 } 1100 1101 DPRINTF(DGE_DEBUG_CKSUM, 1102 ("%s: CKSUM: offset %d tucs 0x%x\n", 1103 sc->sc_dev.dv_xname, offset, tucs)); 1104 1105 if (sc->sc_txctx_ipcs == ipcs && 1106 sc->sc_txctx_tucs == tucs) { 1107 /* Cached context is fine. */ 1108 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1109 } else { 1110 /* Fill in the context descriptor. */ 1111 #ifdef DGE_EVENT_COUNTERS 1112 if (sc->sc_txctx_ipcs == 0xffffffff && 1113 sc->sc_txctx_tucs == 0xffffffff) 1114 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1115 else 1116 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1117 #endif 1118 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1119 t->dc_tcpip_ipcs = htole32(ipcs); 1120 t->dc_tcpip_tucs = htole32(tucs); 1121 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1122 t->dc_tcpip_seg = 0; 1123 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1124 1125 sc->sc_txctx_ipcs = ipcs; 1126 sc->sc_txctx_tucs = tucs; 1127 1128 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1129 txs->txs_ndesc++; 1130 } 1131 1132 *fieldsp = fields; 1133 1134 return (0); 1135 } 1136 1137 /* 1138 * dge_start: [ifnet interface function] 1139 * 1140 * Start packet transmission on the interface. 1141 */ 1142 static void 1143 dge_start(struct ifnet *ifp) 1144 { 1145 struct dge_softc *sc = ifp->if_softc; 1146 struct mbuf *m0; 1147 struct dge_txsoft *txs; 1148 bus_dmamap_t dmamap; 1149 int error, nexttx, lasttx = -1, ofree, seg; 1150 uint32_t cksumcmd; 1151 uint8_t cksumfields; 1152 1153 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1154 return; 1155 1156 /* 1157 * Remember the previous number of free descriptors. 1158 */ 1159 ofree = sc->sc_txfree; 1160 1161 /* 1162 * Loop through the send queue, setting up transmit descriptors 1163 * until we drain the queue, or use up all available transmit 1164 * descriptors. 1165 */ 1166 for (;;) { 1167 /* Grab a packet off the queue. */ 1168 IFQ_POLL(&ifp->if_snd, m0); 1169 if (m0 == NULL) 1170 break; 1171 1172 DPRINTF(DGE_DEBUG_TX, 1173 ("%s: TX: have packet to transmit: %p\n", 1174 sc->sc_dev.dv_xname, m0)); 1175 1176 /* Get a work queue entry. */ 1177 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1178 dge_txintr(sc); 1179 if (sc->sc_txsfree == 0) { 1180 DPRINTF(DGE_DEBUG_TX, 1181 ("%s: TX: no free job descriptors\n", 1182 sc->sc_dev.dv_xname)); 1183 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1184 break; 1185 } 1186 } 1187 1188 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1189 dmamap = txs->txs_dmamap; 1190 1191 /* 1192 * Load the DMA map. If this fails, the packet either 1193 * didn't fit in the allotted number of segments, or we 1194 * were short on resources. For the too-many-segments 1195 * case, we simply report an error and drop the packet, 1196 * since we can't sanely copy a jumbo packet to a single 1197 * buffer. 1198 */ 1199 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1200 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1201 if (error) { 1202 if (error == EFBIG) { 1203 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1204 printf("%s: Tx packet consumes too many " 1205 "DMA segments, dropping...\n", 1206 sc->sc_dev.dv_xname); 1207 IFQ_DEQUEUE(&ifp->if_snd, m0); 1208 m_freem(m0); 1209 continue; 1210 } 1211 /* 1212 * Short on resources, just stop for now. 1213 */ 1214 DPRINTF(DGE_DEBUG_TX, 1215 ("%s: TX: dmamap load failed: %d\n", 1216 sc->sc_dev.dv_xname, error)); 1217 break; 1218 } 1219 1220 /* 1221 * Ensure we have enough descriptors free to describe 1222 * the packet. Note, we always reserve one descriptor 1223 * at the end of the ring due to the semantics of the 1224 * TDT register, plus one more in the event we need 1225 * to re-load checksum offload context. 1226 */ 1227 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1228 /* 1229 * Not enough free descriptors to transmit this 1230 * packet. We haven't committed anything yet, 1231 * so just unload the DMA map, put the packet 1232 * pack on the queue, and punt. Notify the upper 1233 * layer that there are no more slots left. 1234 */ 1235 DPRINTF(DGE_DEBUG_TX, 1236 ("%s: TX: need %d descriptors, have %d\n", 1237 sc->sc_dev.dv_xname, dmamap->dm_nsegs, 1238 sc->sc_txfree - 1)); 1239 ifp->if_flags |= IFF_OACTIVE; 1240 bus_dmamap_unload(sc->sc_dmat, dmamap); 1241 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1242 break; 1243 } 1244 1245 IFQ_DEQUEUE(&ifp->if_snd, m0); 1246 1247 /* 1248 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1249 */ 1250 1251 /* Sync the DMA map. */ 1252 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1253 BUS_DMASYNC_PREWRITE); 1254 1255 DPRINTF(DGE_DEBUG_TX, 1256 ("%s: TX: packet has %d DMA segments\n", 1257 sc->sc_dev.dv_xname, dmamap->dm_nsegs)); 1258 1259 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1260 1261 /* 1262 * Store a pointer to the packet so that we can free it 1263 * later. 1264 * 1265 * Initially, we consider the number of descriptors the 1266 * packet uses the number of DMA segments. This may be 1267 * incremented by 1 if we do checksum offload (a descriptor 1268 * is used to set the checksum context). 1269 */ 1270 txs->txs_mbuf = m0; 1271 txs->txs_firstdesc = sc->sc_txnext; 1272 txs->txs_ndesc = dmamap->dm_nsegs; 1273 1274 /* 1275 * Set up checksum offload parameters for 1276 * this packet. 1277 */ 1278 if (m0->m_pkthdr.csum_flags & 1279 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1280 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1281 /* Error message already displayed. */ 1282 bus_dmamap_unload(sc->sc_dmat, dmamap); 1283 continue; 1284 } 1285 } else { 1286 cksumfields = 0; 1287 } 1288 1289 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1290 1291 /* 1292 * Initialize the transmit descriptor. 1293 */ 1294 for (nexttx = sc->sc_txnext, seg = 0; 1295 seg < dmamap->dm_nsegs; 1296 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1297 /* 1298 * Note: we currently only use 32-bit DMA 1299 * addresses. 1300 */ 1301 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1302 sc->sc_txdescs[nexttx].dt_baddrl = 1303 htole32(dmamap->dm_segs[seg].ds_addr); 1304 sc->sc_txdescs[nexttx].dt_ctl = 1305 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1306 sc->sc_txdescs[nexttx].dt_status = 0; 1307 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1308 sc->sc_txdescs[nexttx].dt_vlan = 0; 1309 lasttx = nexttx; 1310 1311 DPRINTF(DGE_DEBUG_TX, 1312 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1313 sc->sc_dev.dv_xname, nexttx, 1314 le32toh(dmamap->dm_segs[seg].ds_addr), 1315 le32toh(dmamap->dm_segs[seg].ds_len))); 1316 } 1317 1318 KASSERT(lasttx != -1); 1319 1320 /* 1321 * Set up the command byte on the last descriptor of 1322 * the packet. If we're in the interrupt delay window, 1323 * delay the interrupt. 1324 */ 1325 sc->sc_txdescs[lasttx].dt_ctl |= 1326 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1327 1328 txs->txs_lastdesc = lasttx; 1329 1330 DPRINTF(DGE_DEBUG_TX, 1331 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1332 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1333 1334 /* Sync the descriptors we're using. */ 1335 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1336 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1337 1338 /* Give the packet to the chip. */ 1339 CSR_WRITE(sc, DGE_TDT, nexttx); 1340 1341 DPRINTF(DGE_DEBUG_TX, 1342 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1343 1344 DPRINTF(DGE_DEBUG_TX, 1345 ("%s: TX: finished transmitting packet, job %d\n", 1346 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1347 1348 /* Advance the tx pointer. */ 1349 sc->sc_txfree -= txs->txs_ndesc; 1350 sc->sc_txnext = nexttx; 1351 1352 sc->sc_txsfree--; 1353 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1354 1355 #if NBPFILTER > 0 1356 /* Pass the packet to any BPF listeners. */ 1357 if (ifp->if_bpf) 1358 bpf_mtap(ifp->if_bpf, m0); 1359 #endif /* NBPFILTER > 0 */ 1360 } 1361 1362 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1363 /* No more slots; notify upper layer. */ 1364 ifp->if_flags |= IFF_OACTIVE; 1365 } 1366 1367 if (sc->sc_txfree != ofree) { 1368 /* Set a watchdog timer in case the chip flakes out. */ 1369 ifp->if_timer = 5; 1370 } 1371 } 1372 1373 /* 1374 * dge_watchdog: [ifnet interface function] 1375 * 1376 * Watchdog timer handler. 1377 */ 1378 static void 1379 dge_watchdog(struct ifnet *ifp) 1380 { 1381 struct dge_softc *sc = ifp->if_softc; 1382 1383 /* 1384 * Since we're using delayed interrupts, sweep up 1385 * before we report an error. 1386 */ 1387 dge_txintr(sc); 1388 1389 if (sc->sc_txfree != DGE_NTXDESC) { 1390 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1391 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1392 sc->sc_txnext); 1393 ifp->if_oerrors++; 1394 1395 /* Reset the interface. */ 1396 (void) dge_init(ifp); 1397 } 1398 1399 /* Try to get more packets going. */ 1400 dge_start(ifp); 1401 } 1402 1403 /* 1404 * dge_ioctl: [ifnet interface function] 1405 * 1406 * Handle control requests from the operator. 1407 */ 1408 static int 1409 dge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1410 { 1411 struct dge_softc *sc = ifp->if_softc; 1412 struct ifreq *ifr = (struct ifreq *) data; 1413 pcireg_t preg; 1414 int s, error, mmrbc; 1415 1416 s = splnet(); 1417 1418 switch (cmd) { 1419 case SIOCSIFMEDIA: 1420 case SIOCGIFMEDIA: 1421 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1422 break; 1423 1424 case SIOCSIFMTU: 1425 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) { 1426 error = EINVAL; 1427 } else { 1428 error = 0; 1429 ifp->if_mtu = ifr->ifr_mtu; 1430 if (ifp->if_flags & IFF_UP) 1431 error = (*ifp->if_init)(ifp); 1432 } 1433 break; 1434 1435 case SIOCSIFFLAGS: 1436 /* extract link flags */ 1437 if ((ifp->if_flags & IFF_LINK0) == 0 && 1438 (ifp->if_flags & IFF_LINK1) == 0) 1439 mmrbc = PCIX_MMRBC_512; 1440 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1441 (ifp->if_flags & IFF_LINK1) != 0) 1442 mmrbc = PCIX_MMRBC_1024; 1443 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1444 (ifp->if_flags & IFF_LINK1) == 0) 1445 mmrbc = PCIX_MMRBC_2048; 1446 else 1447 mmrbc = PCIX_MMRBC_4096; 1448 if (mmrbc != sc->sc_mmrbc) { 1449 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1450 preg &= ~PCIX_MMRBC_MSK; 1451 preg |= mmrbc; 1452 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1453 sc->sc_mmrbc = mmrbc; 1454 } 1455 /* FALLTHROUGH */ 1456 default: 1457 error = ether_ioctl(ifp, cmd, data); 1458 if (error == ENETRESET) { 1459 /* 1460 * Multicast list has changed; set the hardware filter 1461 * accordingly. 1462 */ 1463 if (ifp->if_flags & IFF_RUNNING) 1464 dge_set_filter(sc); 1465 error = 0; 1466 } 1467 break; 1468 } 1469 1470 /* Try to get more packets going. */ 1471 dge_start(ifp); 1472 1473 splx(s); 1474 return (error); 1475 } 1476 1477 /* 1478 * dge_intr: 1479 * 1480 * Interrupt service routine. 1481 */ 1482 static int 1483 dge_intr(void *arg) 1484 { 1485 struct dge_softc *sc = arg; 1486 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1487 uint32_t icr; 1488 int wantinit, handled = 0; 1489 1490 for (wantinit = 0; wantinit == 0;) { 1491 icr = CSR_READ(sc, DGE_ICR); 1492 if ((icr & sc->sc_icr) == 0) 1493 break; 1494 1495 #if 0 /*NRND > 0*/ 1496 if (RND_ENABLED(&sc->rnd_source)) 1497 rnd_add_uint32(&sc->rnd_source, icr); 1498 #endif 1499 1500 handled = 1; 1501 1502 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1503 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1504 DPRINTF(DGE_DEBUG_RX, 1505 ("%s: RX: got Rx intr 0x%08x\n", 1506 sc->sc_dev.dv_xname, 1507 icr & (ICR_RXDMT0|ICR_RXT0))); 1508 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1509 } 1510 #endif 1511 dge_rxintr(sc); 1512 1513 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1514 if (icr & ICR_TXDW) { 1515 DPRINTF(DGE_DEBUG_TX, 1516 ("%s: TX: got TXDW interrupt\n", 1517 sc->sc_dev.dv_xname)); 1518 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1519 } 1520 if (icr & ICR_TXQE) 1521 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1522 #endif 1523 dge_txintr(sc); 1524 1525 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1526 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1527 dge_linkintr(sc, icr); 1528 } 1529 1530 if (icr & ICR_RXO) { 1531 printf("%s: Receive overrun\n", sc->sc_dev.dv_xname); 1532 wantinit = 1; 1533 } 1534 } 1535 1536 if (handled) { 1537 if (wantinit) 1538 dge_init(ifp); 1539 1540 /* Try to get more packets going. */ 1541 dge_start(ifp); 1542 } 1543 1544 return (handled); 1545 } 1546 1547 /* 1548 * dge_txintr: 1549 * 1550 * Helper; handle transmit interrupts. 1551 */ 1552 static void 1553 dge_txintr(struct dge_softc *sc) 1554 { 1555 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1556 struct dge_txsoft *txs; 1557 uint8_t status; 1558 int i; 1559 1560 ifp->if_flags &= ~IFF_OACTIVE; 1561 1562 /* 1563 * Go through the Tx list and free mbufs for those 1564 * frames which have been transmitted. 1565 */ 1566 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1567 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1568 txs = &sc->sc_txsoft[i]; 1569 1570 DPRINTF(DGE_DEBUG_TX, 1571 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 1572 1573 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1574 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1575 1576 status = 1577 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1578 if ((status & TDESC_STA_DD) == 0) { 1579 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1580 BUS_DMASYNC_PREREAD); 1581 break; 1582 } 1583 1584 DPRINTF(DGE_DEBUG_TX, 1585 ("%s: TX: job %d done: descs %d..%d\n", 1586 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 1587 txs->txs_lastdesc)); 1588 1589 ifp->if_opackets++; 1590 sc->sc_txfree += txs->txs_ndesc; 1591 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1592 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1593 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1594 m_freem(txs->txs_mbuf); 1595 txs->txs_mbuf = NULL; 1596 } 1597 1598 /* Update the dirty transmit buffer pointer. */ 1599 sc->sc_txsdirty = i; 1600 DPRINTF(DGE_DEBUG_TX, 1601 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 1602 1603 /* 1604 * If there are no more pending transmissions, cancel the watchdog 1605 * timer. 1606 */ 1607 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1608 ifp->if_timer = 0; 1609 } 1610 1611 /* 1612 * dge_rxintr: 1613 * 1614 * Helper; handle receive interrupts. 1615 */ 1616 static void 1617 dge_rxintr(struct dge_softc *sc) 1618 { 1619 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1620 struct dge_rxsoft *rxs; 1621 struct mbuf *m; 1622 int i, len; 1623 uint8_t status, errors; 1624 1625 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1626 rxs = &sc->sc_rxsoft[i]; 1627 1628 DPRINTF(DGE_DEBUG_RX, 1629 ("%s: RX: checking descriptor %d\n", 1630 sc->sc_dev.dv_xname, i)); 1631 1632 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1633 1634 status = sc->sc_rxdescs[i].dr_status; 1635 errors = sc->sc_rxdescs[i].dr_errors; 1636 len = le16toh(sc->sc_rxdescs[i].dr_len); 1637 1638 if ((status & RDESC_STS_DD) == 0) { 1639 /* 1640 * We have processed all of the receive descriptors. 1641 */ 1642 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1643 break; 1644 } 1645 1646 if (__predict_false(sc->sc_rxdiscard)) { 1647 DPRINTF(DGE_DEBUG_RX, 1648 ("%s: RX: discarding contents of descriptor %d\n", 1649 sc->sc_dev.dv_xname, i)); 1650 DGE_INIT_RXDESC(sc, i); 1651 if (status & RDESC_STS_EOP) { 1652 /* Reset our state. */ 1653 DPRINTF(DGE_DEBUG_RX, 1654 ("%s: RX: resetting rxdiscard -> 0\n", 1655 sc->sc_dev.dv_xname)); 1656 sc->sc_rxdiscard = 0; 1657 } 1658 continue; 1659 } 1660 1661 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1662 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1663 1664 m = rxs->rxs_mbuf; 1665 1666 /* 1667 * Add a new receive buffer to the ring. 1668 */ 1669 if (dge_add_rxbuf(sc, i) != 0) { 1670 /* 1671 * Failed, throw away what we've done so 1672 * far, and discard the rest of the packet. 1673 */ 1674 ifp->if_ierrors++; 1675 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1676 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1677 DGE_INIT_RXDESC(sc, i); 1678 if ((status & RDESC_STS_EOP) == 0) 1679 sc->sc_rxdiscard = 1; 1680 if (sc->sc_rxhead != NULL) 1681 m_freem(sc->sc_rxhead); 1682 DGE_RXCHAIN_RESET(sc); 1683 DPRINTF(DGE_DEBUG_RX, 1684 ("%s: RX: Rx buffer allocation failed, " 1685 "dropping packet%s\n", sc->sc_dev.dv_xname, 1686 sc->sc_rxdiscard ? " (discard)" : "")); 1687 continue; 1688 } 1689 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1690 1691 DGE_RXCHAIN_LINK(sc, m); 1692 1693 m->m_len = len; 1694 1695 DPRINTF(DGE_DEBUG_RX, 1696 ("%s: RX: buffer at %p len %d\n", 1697 sc->sc_dev.dv_xname, m->m_data, len)); 1698 1699 /* 1700 * If this is not the end of the packet, keep 1701 * looking. 1702 */ 1703 if ((status & RDESC_STS_EOP) == 0) { 1704 sc->sc_rxlen += len; 1705 DPRINTF(DGE_DEBUG_RX, 1706 ("%s: RX: not yet EOP, rxlen -> %d\n", 1707 sc->sc_dev.dv_xname, sc->sc_rxlen)); 1708 continue; 1709 } 1710 1711 /* 1712 * Okay, we have the entire packet now... 1713 */ 1714 *sc->sc_rxtailp = NULL; 1715 m = sc->sc_rxhead; 1716 len += sc->sc_rxlen; 1717 1718 DGE_RXCHAIN_RESET(sc); 1719 1720 DPRINTF(DGE_DEBUG_RX, 1721 ("%s: RX: have entire packet, len -> %d\n", 1722 sc->sc_dev.dv_xname, len)); 1723 1724 /* 1725 * If an error occurred, update stats and drop the packet. 1726 */ 1727 if (errors & 1728 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1729 ifp->if_ierrors++; 1730 if (errors & RDESC_ERR_SE) 1731 printf("%s: symbol error\n", 1732 sc->sc_dev.dv_xname); 1733 else if (errors & RDESC_ERR_P) 1734 printf("%s: parity error\n", 1735 sc->sc_dev.dv_xname); 1736 else if (errors & RDESC_ERR_CE) 1737 printf("%s: CRC error\n", 1738 sc->sc_dev.dv_xname); 1739 m_freem(m); 1740 continue; 1741 } 1742 1743 /* 1744 * No errors. Receive the packet. 1745 */ 1746 m->m_pkthdr.rcvif = ifp; 1747 m->m_pkthdr.len = len; 1748 1749 /* 1750 * Set up checksum info for this packet. 1751 */ 1752 if (status & RDESC_STS_IPCS) { 1753 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1754 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1755 if (errors & RDESC_ERR_IPE) 1756 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1757 } 1758 if (status & RDESC_STS_TCPCS) { 1759 /* 1760 * Note: we don't know if this was TCP or UDP, 1761 * so we just set both bits, and expect the 1762 * upper layers to deal. 1763 */ 1764 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1765 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1766 if (errors & RDESC_ERR_TCPE) 1767 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1768 } 1769 1770 ifp->if_ipackets++; 1771 1772 #if NBPFILTER > 0 1773 /* Pass this up to any BPF listeners. */ 1774 if (ifp->if_bpf) 1775 bpf_mtap(ifp->if_bpf, m); 1776 #endif /* NBPFILTER > 0 */ 1777 1778 /* Pass it on. */ 1779 (*ifp->if_input)(ifp, m); 1780 } 1781 1782 /* Update the receive pointer. */ 1783 sc->sc_rxptr = i; 1784 1785 DPRINTF(DGE_DEBUG_RX, 1786 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 1787 } 1788 1789 /* 1790 * dge_linkintr: 1791 * 1792 * Helper; handle link interrupts. 1793 */ 1794 static void 1795 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1796 { 1797 uint32_t status; 1798 1799 if (icr & ICR_LSC) { 1800 status = CSR_READ(sc, DGE_STATUS); 1801 if (status & STATUS_LINKUP) { 1802 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1803 sc->sc_dev.dv_xname)); 1804 } else { 1805 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1806 sc->sc_dev.dv_xname)); 1807 } 1808 } else if (icr & ICR_RXSEQ) { 1809 DPRINTF(DGE_DEBUG_LINK, 1810 ("%s: LINK: Receive sequence error\n", 1811 sc->sc_dev.dv_xname)); 1812 } 1813 /* XXX - fix errata */ 1814 } 1815 1816 /* 1817 * dge_reset: 1818 * 1819 * Reset the i82597 chip. 1820 */ 1821 static void 1822 dge_reset(struct dge_softc *sc) 1823 { 1824 int i; 1825 1826 /* 1827 * Do a chip reset. 1828 */ 1829 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1830 1831 delay(10000); 1832 1833 for (i = 0; i < 1000; i++) { 1834 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1835 break; 1836 delay(20); 1837 } 1838 1839 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1840 printf("%s: WARNING: reset failed to complete\n", 1841 sc->sc_dev.dv_xname); 1842 /* 1843 * Reset the EEPROM logic. 1844 * This will cause the chip to reread its default values, 1845 * which doesn't happen otherwise (errata). 1846 */ 1847 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1848 delay(10000); 1849 } 1850 1851 /* 1852 * dge_init: [ifnet interface function] 1853 * 1854 * Initialize the interface. Must be called at splnet(). 1855 */ 1856 static int 1857 dge_init(struct ifnet *ifp) 1858 { 1859 struct dge_softc *sc = ifp->if_softc; 1860 struct dge_rxsoft *rxs; 1861 int i, error = 0; 1862 uint32_t reg; 1863 1864 /* 1865 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1866 * There is a small but measurable benefit to avoiding the adjusment 1867 * of the descriptor so that the headers are aligned, for normal mtu, 1868 * on such platforms. One possibility is that the DMA itself is 1869 * slightly more efficient if the front of the entire packet (instead 1870 * of the front of the headers) is aligned. 1871 * 1872 * Note we must always set align_tweak to 0 if we are using 1873 * jumbo frames. 1874 */ 1875 #ifdef __NO_STRICT_ALIGNMENT 1876 sc->sc_align_tweak = 0; 1877 #else 1878 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1879 sc->sc_align_tweak = 0; 1880 else 1881 sc->sc_align_tweak = 2; 1882 #endif /* __NO_STRICT_ALIGNMENT */ 1883 1884 /* Cancel any pending I/O. */ 1885 dge_stop(ifp, 0); 1886 1887 /* Reset the chip to a known state. */ 1888 dge_reset(sc); 1889 1890 /* Initialize the transmit descriptor ring. */ 1891 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1892 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1893 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1894 sc->sc_txfree = DGE_NTXDESC; 1895 sc->sc_txnext = 0; 1896 1897 sc->sc_txctx_ipcs = 0xffffffff; 1898 sc->sc_txctx_tucs = 0xffffffff; 1899 1900 CSR_WRITE(sc, DGE_TDBAH, 0); 1901 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1902 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1903 CSR_WRITE(sc, DGE_TDH, 0); 1904 CSR_WRITE(sc, DGE_TDT, 0); 1905 CSR_WRITE(sc, DGE_TIDV, TIDV); 1906 1907 #if 0 1908 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1909 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1910 #endif 1911 CSR_WRITE(sc, DGE_RXDCTL, 1912 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1913 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1914 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1915 1916 /* Initialize the transmit job descriptors. */ 1917 for (i = 0; i < DGE_TXQUEUELEN; i++) 1918 sc->sc_txsoft[i].txs_mbuf = NULL; 1919 sc->sc_txsfree = DGE_TXQUEUELEN; 1920 sc->sc_txsnext = 0; 1921 sc->sc_txsdirty = 0; 1922 1923 /* 1924 * Initialize the receive descriptor and receive job 1925 * descriptor rings. 1926 */ 1927 CSR_WRITE(sc, DGE_RDBAH, 0); 1928 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1929 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1930 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1931 CSR_WRITE(sc, DGE_RDT, 0); 1932 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1933 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1934 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1935 1936 for (i = 0; i < DGE_NRXDESC; i++) { 1937 rxs = &sc->sc_rxsoft[i]; 1938 if (rxs->rxs_mbuf == NULL) { 1939 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1940 printf("%s: unable to allocate or map rx " 1941 "buffer %d, error = %d\n", 1942 sc->sc_dev.dv_xname, i, error); 1943 /* 1944 * XXX Should attempt to run with fewer receive 1945 * XXX buffers instead of just failing. 1946 */ 1947 dge_rxdrain(sc); 1948 goto out; 1949 } 1950 } 1951 DGE_INIT_RXDESC(sc, i); 1952 } 1953 sc->sc_rxptr = DGE_RXSPACE; 1954 sc->sc_rxdiscard = 0; 1955 DGE_RXCHAIN_RESET(sc); 1956 1957 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1958 sc->sc_ctrl0 |= CTRL0_JFE; 1959 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1960 } 1961 1962 /* Write the control registers. */ 1963 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1964 1965 /* 1966 * Set up checksum offload parameters. 1967 */ 1968 reg = CSR_READ(sc, DGE_RXCSUM); 1969 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1970 reg |= RXCSUM_IPOFL; 1971 else 1972 reg &= ~RXCSUM_IPOFL; 1973 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1974 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1975 else { 1976 reg &= ~RXCSUM_TUOFL; 1977 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 1978 reg &= ~RXCSUM_IPOFL; 1979 } 1980 CSR_WRITE(sc, DGE_RXCSUM, reg); 1981 1982 /* 1983 * Set up the interrupt registers. 1984 */ 1985 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 1986 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 1987 ICR_RXO | ICR_RXT0; 1988 1989 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 1990 1991 /* 1992 * Set up the transmit control register. 1993 */ 1994 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 1995 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 1996 1997 /* 1998 * Set up the receive control register; we actually program 1999 * the register when we set the receive filter. Use multicast 2000 * address offset type 0. 2001 */ 2002 sc->sc_mchash_type = 0; 2003 2004 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2005 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2006 2007 #ifdef DGE_OFFBYONE_RXBUG 2008 sc->sc_rctl |= RCTL_BSIZE_16k; 2009 #else 2010 switch(MCLBYTES) { 2011 case 2048: 2012 sc->sc_rctl |= RCTL_BSIZE_2k; 2013 break; 2014 case 4096: 2015 sc->sc_rctl |= RCTL_BSIZE_4k; 2016 break; 2017 case 8192: 2018 sc->sc_rctl |= RCTL_BSIZE_8k; 2019 break; 2020 case 16384: 2021 sc->sc_rctl |= RCTL_BSIZE_16k; 2022 break; 2023 default: 2024 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2025 } 2026 #endif 2027 2028 /* Set the receive filter. */ 2029 /* Also sets RCTL */ 2030 dge_set_filter(sc); 2031 2032 /* ...all done! */ 2033 ifp->if_flags |= IFF_RUNNING; 2034 ifp->if_flags &= ~IFF_OACTIVE; 2035 2036 out: 2037 if (error) 2038 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2039 return (error); 2040 } 2041 2042 /* 2043 * dge_rxdrain: 2044 * 2045 * Drain the receive queue. 2046 */ 2047 static void 2048 dge_rxdrain(struct dge_softc *sc) 2049 { 2050 struct dge_rxsoft *rxs; 2051 int i; 2052 2053 for (i = 0; i < DGE_NRXDESC; i++) { 2054 rxs = &sc->sc_rxsoft[i]; 2055 if (rxs->rxs_mbuf != NULL) { 2056 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2057 m_freem(rxs->rxs_mbuf); 2058 rxs->rxs_mbuf = NULL; 2059 } 2060 } 2061 } 2062 2063 /* 2064 * dge_stop: [ifnet interface function] 2065 * 2066 * Stop transmission on the interface. 2067 */ 2068 static void 2069 dge_stop(struct ifnet *ifp, int disable) 2070 { 2071 struct dge_softc *sc = ifp->if_softc; 2072 struct dge_txsoft *txs; 2073 int i; 2074 2075 /* Stop the transmit and receive processes. */ 2076 CSR_WRITE(sc, DGE_TCTL, 0); 2077 CSR_WRITE(sc, DGE_RCTL, 0); 2078 2079 /* Release any queued transmit buffers. */ 2080 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2081 txs = &sc->sc_txsoft[i]; 2082 if (txs->txs_mbuf != NULL) { 2083 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2084 m_freem(txs->txs_mbuf); 2085 txs->txs_mbuf = NULL; 2086 } 2087 } 2088 2089 if (disable) 2090 dge_rxdrain(sc); 2091 2092 /* Mark the interface as down and cancel the watchdog timer. */ 2093 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2094 ifp->if_timer = 0; 2095 } 2096 2097 /* 2098 * dge_add_rxbuf: 2099 * 2100 * Add a receive buffer to the indiciated descriptor. 2101 */ 2102 static int 2103 dge_add_rxbuf(struct dge_softc *sc, int idx) 2104 { 2105 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2106 struct mbuf *m; 2107 int error; 2108 #ifdef DGE_OFFBYONE_RXBUG 2109 caddr_t buf; 2110 #endif 2111 2112 MGETHDR(m, M_DONTWAIT, MT_DATA); 2113 if (m == NULL) 2114 return (ENOBUFS); 2115 2116 #ifdef DGE_OFFBYONE_RXBUG 2117 if ((buf = dge_getbuf(sc)) == NULL) 2118 return ENOBUFS; 2119 2120 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2121 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2122 m->m_flags |= M_EXT_RW; 2123 2124 if (rxs->rxs_mbuf != NULL) 2125 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2126 rxs->rxs_mbuf = m; 2127 2128 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2129 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2130 #else 2131 MCLGET(m, M_DONTWAIT); 2132 if ((m->m_flags & M_EXT) == 0) { 2133 m_freem(m); 2134 return (ENOBUFS); 2135 } 2136 2137 if (rxs->rxs_mbuf != NULL) 2138 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2139 2140 rxs->rxs_mbuf = m; 2141 2142 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2143 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2144 BUS_DMA_READ|BUS_DMA_NOWAIT); 2145 #endif 2146 if (error) { 2147 printf("%s: unable to load rx DMA map %d, error = %d\n", 2148 sc->sc_dev.dv_xname, idx, error); 2149 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2150 } 2151 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2152 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2153 2154 return (0); 2155 } 2156 2157 /* 2158 * dge_set_ral: 2159 * 2160 * Set an entry in the receive address list. 2161 */ 2162 static void 2163 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2164 { 2165 uint32_t ral_lo, ral_hi; 2166 2167 if (enaddr != NULL) { 2168 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2169 (enaddr[3] << 24); 2170 ral_hi = enaddr[4] | (enaddr[5] << 8); 2171 ral_hi |= RAH_AV; 2172 } else { 2173 ral_lo = 0; 2174 ral_hi = 0; 2175 } 2176 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2177 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2178 } 2179 2180 /* 2181 * dge_mchash: 2182 * 2183 * Compute the hash of the multicast address for the 4096-bit 2184 * multicast filter. 2185 */ 2186 static uint32_t 2187 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2188 { 2189 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2190 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2191 uint32_t hash; 2192 2193 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2194 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2195 2196 return (hash & 0xfff); 2197 } 2198 2199 /* 2200 * dge_set_filter: 2201 * 2202 * Set up the receive filter. 2203 */ 2204 static void 2205 dge_set_filter(struct dge_softc *sc) 2206 { 2207 struct ethercom *ec = &sc->sc_ethercom; 2208 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2209 struct ether_multi *enm; 2210 struct ether_multistep step; 2211 uint32_t hash, reg, bit; 2212 int i; 2213 2214 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2215 2216 if (ifp->if_flags & IFF_BROADCAST) 2217 sc->sc_rctl |= RCTL_BAM; 2218 if (ifp->if_flags & IFF_PROMISC) { 2219 sc->sc_rctl |= RCTL_UPE; 2220 goto allmulti; 2221 } 2222 2223 /* 2224 * Set the station address in the first RAL slot, and 2225 * clear the remaining slots. 2226 */ 2227 dge_set_ral(sc, LLADDR(ifp->if_sadl), 0); 2228 for (i = 1; i < RA_TABSIZE; i++) 2229 dge_set_ral(sc, NULL, i); 2230 2231 /* Clear out the multicast table. */ 2232 for (i = 0; i < MC_TABSIZE; i++) 2233 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2234 2235 ETHER_FIRST_MULTI(step, ec, enm); 2236 while (enm != NULL) { 2237 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2238 /* 2239 * We must listen to a range of multicast addresses. 2240 * For now, just accept all multicasts, rather than 2241 * trying to set only those filter bits needed to match 2242 * the range. (At this time, the only use of address 2243 * ranges is for IP multicast routing, for which the 2244 * range is big enough to require all bits set.) 2245 */ 2246 goto allmulti; 2247 } 2248 2249 hash = dge_mchash(sc, enm->enm_addrlo); 2250 2251 reg = (hash >> 5) & 0x7f; 2252 bit = hash & 0x1f; 2253 2254 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2255 hash |= 1U << bit; 2256 2257 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2258 2259 ETHER_NEXT_MULTI(step, enm); 2260 } 2261 2262 ifp->if_flags &= ~IFF_ALLMULTI; 2263 goto setit; 2264 2265 allmulti: 2266 ifp->if_flags |= IFF_ALLMULTI; 2267 sc->sc_rctl |= RCTL_MPE; 2268 2269 setit: 2270 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2271 } 2272 2273 /* 2274 * Read in the EEPROM info and verify checksum. 2275 */ 2276 int 2277 dge_read_eeprom(struct dge_softc *sc) 2278 { 2279 uint16_t cksum; 2280 int i; 2281 2282 cksum = 0; 2283 for (i = 0; i < EEPROM_SIZE; i++) { 2284 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2285 cksum += sc->sc_eeprom[i]; 2286 } 2287 return cksum != EEPROM_CKSUM; 2288 } 2289 2290 2291 /* 2292 * Read a 16-bit word from address addr in the serial EEPROM. 2293 */ 2294 uint16_t 2295 dge_eeprom_word(struct dge_softc *sc, int addr) 2296 { 2297 uint32_t reg; 2298 uint16_t rval = 0; 2299 int i; 2300 2301 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2302 2303 /* Lower clock pulse (and data in to chip) */ 2304 CSR_WRITE(sc, DGE_EECD, reg); 2305 /* Select chip */ 2306 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2307 2308 /* Send read command */ 2309 dge_eeprom_clockout(sc, 1); 2310 dge_eeprom_clockout(sc, 1); 2311 dge_eeprom_clockout(sc, 0); 2312 2313 /* Send address */ 2314 for (i = 5; i >= 0; i--) 2315 dge_eeprom_clockout(sc, (addr >> i) & 1); 2316 2317 /* Read data */ 2318 for (i = 0; i < 16; i++) { 2319 rval <<= 1; 2320 rval |= dge_eeprom_clockin(sc); 2321 } 2322 2323 /* Deselect chip */ 2324 CSR_WRITE(sc, DGE_EECD, reg); 2325 2326 return rval; 2327 } 2328 2329 /* 2330 * Clock out a single bit to the EEPROM. 2331 */ 2332 void 2333 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2334 { 2335 int reg; 2336 2337 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2338 if (bit) 2339 reg |= EECD_DI; 2340 2341 CSR_WRITE(sc, DGE_EECD, reg); 2342 delay(2); 2343 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2344 delay(2); 2345 CSR_WRITE(sc, DGE_EECD, reg); 2346 delay(2); 2347 } 2348 2349 /* 2350 * Clock in a single bit from EEPROM. 2351 */ 2352 int 2353 dge_eeprom_clockin(struct dge_softc *sc) 2354 { 2355 int reg, rv; 2356 2357 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2358 2359 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2360 delay(2); 2361 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2362 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2363 delay(2); 2364 2365 return rv; 2366 } 2367 2368 static void 2369 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2370 { 2371 struct dge_softc *sc = ifp->if_softc; 2372 2373 ifmr->ifm_status = IFM_AVALID; 2374 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2375 2376 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2377 ifmr->ifm_status |= IFM_ACTIVE; 2378 } 2379 2380 static inline int 2381 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2382 { 2383 int i, mdic; 2384 2385 CSR_WRITE(sc, DGE_MDIO, 2386 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2387 for (i = 0; i < 10; i++) { 2388 delay(10); 2389 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2390 break; 2391 } 2392 return mdic; 2393 } 2394 2395 2396 static void 2397 dge_xgmii_writereg(struct device *self, int phy, int reg, int val) 2398 { 2399 struct dge_softc *sc = (void *) self; 2400 int mdic; 2401 2402 CSR_WRITE(sc, DGE_MDIRW, val); 2403 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2404 printf("%s: address cycle timeout; phy %d reg %d\n", 2405 sc->sc_dev.dv_xname, phy, reg); 2406 return; 2407 } 2408 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2409 printf("%s: read cycle timeout; phy %d reg %d\n", 2410 sc->sc_dev.dv_xname, phy, reg); 2411 return; 2412 } 2413 } 2414 2415 static void 2416 dge_xgmii_reset(struct dge_softc *sc) 2417 { 2418 dge_xgmii_writereg((void *)sc, 0, 0, BMCR_RESET); 2419 } 2420 2421 static int 2422 dge_xgmii_mediachange(struct ifnet *ifp) 2423 { 2424 return 0; 2425 } 2426