1 /* $NetBSD: if_dge.c,v 1.21 2008/04/10 19:13:36 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.21 2008/04/10 19:13:36 cegger Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <netinet/in.h> /* XXX for struct ip */ 116 #include <netinet/in_systm.h> /* XXX for struct ip */ 117 #include <netinet/ip.h> /* XXX for struct ip */ 118 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 119 120 #include <sys/bus.h> 121 #include <sys/intr.h> 122 #include <machine/endian.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/mii_bitbang.h> 127 128 #include <dev/pci/pcireg.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/pcidevs.h> 131 132 #include <dev/pci/if_dgereg.h> 133 134 /* 135 * The receive engine may sometimes become off-by-one when writing back 136 * chained descriptors. Avoid this by allocating a large chunk of 137 * memory and use if instead (to avoid chained descriptors). 138 * This only happens with chained descriptors under heavy load. 139 */ 140 #define DGE_OFFBYONE_RXBUG 141 142 #define DGE_EVENT_COUNTERS 143 #define DGE_DEBUG 144 145 #ifdef DGE_DEBUG 146 #define DGE_DEBUG_LINK 0x01 147 #define DGE_DEBUG_TX 0x02 148 #define DGE_DEBUG_RX 0x04 149 #define DGE_DEBUG_CKSUM 0x08 150 int dge_debug = 0; 151 152 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 153 #else 154 #define DPRINTF(x, y) /* nothing */ 155 #endif /* DGE_DEBUG */ 156 157 /* 158 * Transmit descriptor list size. We allow up to 100 DMA segments per 159 * packet (Intel reports of jumbo frame packets with as 160 * many as 80 DMA segments when using 16k buffers). 161 */ 162 #define DGE_NTXSEGS 100 163 #define DGE_IFQUEUELEN 20000 164 #define DGE_TXQUEUELEN 2048 165 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 166 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 167 #define DGE_NTXDESC 1024 168 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 169 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 170 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 171 172 /* 173 * Receive descriptor list size. 174 * Packet is of size MCLBYTES, and for jumbo packets buffers may 175 * be chained. Due to the nature of the card (high-speed), keep this 176 * ring large. With 2k buffers the ring can store 400 jumbo packets, 177 * which at full speed will be received in just under 3ms. 178 */ 179 #define DGE_NRXDESC 2048 180 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 181 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 182 /* 183 * # of descriptors between head and written descriptors. 184 * This is to work-around two erratas. 185 */ 186 #define DGE_RXSPACE 10 187 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 188 /* 189 * Receive descriptor fetch threshholds. These are values recommended 190 * by Intel, do not touch them unless you know what you are doing. 191 */ 192 #define RXDCTL_PTHRESH_VAL 128 193 #define RXDCTL_HTHRESH_VAL 16 194 #define RXDCTL_WTHRESH_VAL 16 195 196 197 /* 198 * Tweakable parameters; default values. 199 */ 200 #define FCRTH 0x30000 /* Send XOFF water mark */ 201 #define FCRTL 0x28000 /* Send XON water mark */ 202 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 203 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 204 205 /* 206 * Control structures are DMA'd to the i82597 chip. We allocate them in 207 * a single clump that maps to a single DMA segment to make serveral things 208 * easier. 209 */ 210 struct dge_control_data { 211 /* 212 * The transmit descriptors. 213 */ 214 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 215 216 /* 217 * The receive descriptors. 218 */ 219 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 220 }; 221 222 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 223 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 224 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 225 226 /* 227 * The DGE interface have a higher max MTU size than normal jumbo frames. 228 */ 229 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 230 231 /* 232 * Software state for transmit jobs. 233 */ 234 struct dge_txsoft { 235 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 236 bus_dmamap_t txs_dmamap; /* our DMA map */ 237 int txs_firstdesc; /* first descriptor in packet */ 238 int txs_lastdesc; /* last descriptor in packet */ 239 int txs_ndesc; /* # of descriptors used */ 240 }; 241 242 /* 243 * Software state for receive buffers. Each descriptor gets a 244 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 245 * more than one buffer, we chain them together. 246 */ 247 struct dge_rxsoft { 248 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 249 bus_dmamap_t rxs_dmamap; /* our DMA map */ 250 }; 251 252 /* 253 * Software state per device. 254 */ 255 struct dge_softc { 256 struct device sc_dev; /* generic device information */ 257 bus_space_tag_t sc_st; /* bus space tag */ 258 bus_space_handle_t sc_sh; /* bus space handle */ 259 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 260 struct ethercom sc_ethercom; /* ethernet common data */ 261 void *sc_sdhook; /* shutdown hook */ 262 263 int sc_flags; /* flags; see below */ 264 int sc_bus_speed; /* PCI/PCIX bus speed */ 265 int sc_pcix_offset; /* PCIX capability register offset */ 266 267 pci_chipset_tag_t sc_pc; 268 pcitag_t sc_pt; 269 int sc_mmrbc; /* Max PCIX memory read byte count */ 270 271 void *sc_ih; /* interrupt cookie */ 272 273 struct ifmedia sc_media; 274 275 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 276 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 277 278 int sc_align_tweak; 279 280 /* 281 * Software state for the transmit and receive descriptors. 282 */ 283 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 284 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 285 286 /* 287 * Control data structures. 288 */ 289 struct dge_control_data *sc_control_data; 290 #define sc_txdescs sc_control_data->wcd_txdescs 291 #define sc_rxdescs sc_control_data->wcd_rxdescs 292 293 #ifdef DGE_EVENT_COUNTERS 294 /* Event counters. */ 295 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 296 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 297 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 298 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 299 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 300 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 301 struct evcnt sc_ev_linkintr; /* Link interrupts */ 302 303 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 304 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 305 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 306 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 307 308 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 309 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 310 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 311 312 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 313 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 314 #endif /* DGE_EVENT_COUNTERS */ 315 316 int sc_txfree; /* number of free Tx descriptors */ 317 int sc_txnext; /* next ready Tx descriptor */ 318 319 int sc_txsfree; /* number of free Tx jobs */ 320 int sc_txsnext; /* next free Tx job */ 321 int sc_txsdirty; /* dirty Tx jobs */ 322 323 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 324 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 325 326 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 327 int sc_rxdiscard; 328 int sc_rxlen; 329 struct mbuf *sc_rxhead; 330 struct mbuf *sc_rxtail; 331 struct mbuf **sc_rxtailp; 332 333 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 334 uint32_t sc_icr; /* prototype interrupt bits */ 335 uint32_t sc_tctl; /* prototype TCTL register */ 336 uint32_t sc_rctl; /* prototype RCTL register */ 337 338 int sc_mchash_type; /* multicast filter offset */ 339 340 uint16_t sc_eeprom[EEPROM_SIZE]; 341 342 #if NRND > 0 343 rndsource_element_t rnd_source; /* random source */ 344 #endif 345 #ifdef DGE_OFFBYONE_RXBUG 346 void *sc_bugbuf; 347 SLIST_HEAD(, rxbugentry) sc_buglist; 348 bus_dmamap_t sc_bugmap; 349 struct rxbugentry *sc_entry; 350 #endif 351 }; 352 353 #define DGE_RXCHAIN_RESET(sc) \ 354 do { \ 355 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 356 *(sc)->sc_rxtailp = NULL; \ 357 (sc)->sc_rxlen = 0; \ 358 } while (/*CONSTCOND*/0) 359 360 #define DGE_RXCHAIN_LINK(sc, m) \ 361 do { \ 362 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 363 (sc)->sc_rxtailp = &(m)->m_next; \ 364 } while (/*CONSTCOND*/0) 365 366 /* sc_flags */ 367 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 368 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 369 370 #ifdef DGE_EVENT_COUNTERS 371 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 372 #else 373 #define DGE_EVCNT_INCR(ev) /* nothing */ 374 #endif 375 376 #define CSR_READ(sc, reg) \ 377 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 #define CSR_WRITE(sc, reg, val) \ 379 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 381 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 382 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 383 384 #define DGE_CDTXSYNC(sc, x, n, ops) \ 385 do { \ 386 int __x, __n; \ 387 \ 388 __x = (x); \ 389 __n = (n); \ 390 \ 391 /* If it will wrap around, sync to the end of the ring. */ \ 392 if ((__x + __n) > DGE_NTXDESC) { \ 393 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 394 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 395 (DGE_NTXDESC - __x), (ops)); \ 396 __n -= (DGE_NTXDESC - __x); \ 397 __x = 0; \ 398 } \ 399 \ 400 /* Now sync whatever is left. */ \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 403 } while (/*CONSTCOND*/0) 404 405 #define DGE_CDRXSYNC(sc, x, ops) \ 406 do { \ 407 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 408 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 409 } while (/*CONSTCOND*/0) 410 411 #ifdef DGE_OFFBYONE_RXBUG 412 #define DGE_INIT_RXDESC(sc, x) \ 413 do { \ 414 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 415 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 416 struct mbuf *__m = __rxs->rxs_mbuf; \ 417 \ 418 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 419 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 420 __rxd->dr_baddrh = 0; \ 421 __rxd->dr_len = 0; \ 422 __rxd->dr_cksum = 0; \ 423 __rxd->dr_status = 0; \ 424 __rxd->dr_errors = 0; \ 425 __rxd->dr_special = 0; \ 426 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 427 \ 428 CSR_WRITE((sc), DGE_RDT, (x)); \ 429 } while (/*CONSTCOND*/0) 430 #else 431 #define DGE_INIT_RXDESC(sc, x) \ 432 do { \ 433 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 434 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 435 struct mbuf *__m = __rxs->rxs_mbuf; \ 436 \ 437 /* \ 438 * Note: We scoot the packet forward 2 bytes in the buffer \ 439 * so that the payload after the Ethernet header is aligned \ 440 * to a 4-byte boundary. \ 441 * \ 442 * XXX BRAINDAMAGE ALERT! \ 443 * The stupid chip uses the same size for every buffer, which \ 444 * is set in the Receive Control register. We are using the 2K \ 445 * size option, but what we REALLY want is (2K - 2)! For this \ 446 * reason, we can't "scoot" packets longer than the standard \ 447 * Ethernet MTU. On strict-alignment platforms, if the total \ 448 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 449 * the upper layer copy the headers. \ 450 */ \ 451 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 452 \ 453 __rxd->dr_baddrl = \ 454 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 455 (sc)->sc_align_tweak); \ 456 __rxd->dr_baddrh = 0; \ 457 __rxd->dr_len = 0; \ 458 __rxd->dr_cksum = 0; \ 459 __rxd->dr_status = 0; \ 460 __rxd->dr_errors = 0; \ 461 __rxd->dr_special = 0; \ 462 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 463 \ 464 CSR_WRITE((sc), DGE_RDT, (x)); \ 465 } while (/*CONSTCOND*/0) 466 #endif 467 468 #ifdef DGE_OFFBYONE_RXBUG 469 /* 470 * Allocation constants. Much memory may be used for this. 471 */ 472 #ifndef DGE_BUFFER_SIZE 473 #define DGE_BUFFER_SIZE DGE_MAX_MTU 474 #endif 475 #define DGE_NBUFFERS (4*DGE_NRXDESC) 476 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 477 478 struct rxbugentry { 479 SLIST_ENTRY(rxbugentry) rb_entry; 480 int rb_slot; 481 }; 482 483 static int 484 dge_alloc_rcvmem(struct dge_softc *sc) 485 { 486 char *ptr, *kva; 487 bus_dma_segment_t seg; 488 int i, rseg, state, error; 489 struct rxbugentry *entry; 490 491 state = error = 0; 492 493 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 494 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 495 aprint_error_dev(&sc->sc_dev, "can't alloc rx buffers\n"); 496 return ENOBUFS; 497 } 498 499 state = 1; 500 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, 501 BUS_DMA_NOWAIT)) { 502 aprint_error_dev(&sc->sc_dev, "can't map DMA buffers (%d bytes)\n", 503 (int)DGE_RXMEM); 504 error = ENOBUFS; 505 goto out; 506 } 507 508 state = 2; 509 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 510 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 511 aprint_error_dev(&sc->sc_dev, "can't create DMA map\n"); 512 error = ENOBUFS; 513 goto out; 514 } 515 516 state = 3; 517 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 518 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 519 aprint_error_dev(&sc->sc_dev, "can't load DMA map\n"); 520 error = ENOBUFS; 521 goto out; 522 } 523 524 state = 4; 525 sc->sc_bugbuf = (void *)kva; 526 SLIST_INIT(&sc->sc_buglist); 527 528 /* 529 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 530 * in an array. 531 */ 532 ptr = sc->sc_bugbuf; 533 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 534 M_DEVBUF, M_NOWAIT)) == NULL) { 535 error = ENOBUFS; 536 goto out; 537 } 538 sc->sc_entry = entry; 539 for (i = 0; i < DGE_NBUFFERS; i++) { 540 entry[i].rb_slot = i; 541 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 542 } 543 out: 544 if (error != 0) { 545 switch (state) { 546 case 4: 547 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 548 case 3: 549 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 550 case 2: 551 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 552 case 1: 553 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 554 break; 555 default: 556 break; 557 } 558 } 559 560 return error; 561 } 562 563 /* 564 * Allocate a jumbo buffer. 565 */ 566 static void * 567 dge_getbuf(struct dge_softc *sc) 568 { 569 struct rxbugentry *entry; 570 571 entry = SLIST_FIRST(&sc->sc_buglist); 572 573 if (entry == NULL) { 574 printf("%s: no free RX buffers\n", device_xname(&sc->sc_dev)); 575 return(NULL); 576 } 577 578 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 579 return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 580 } 581 582 /* 583 * Release a jumbo buffer. 584 */ 585 static void 586 dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) 587 { 588 struct rxbugentry *entry; 589 struct dge_softc *sc; 590 int i, s; 591 592 /* Extract the softc struct pointer. */ 593 sc = (struct dge_softc *)arg; 594 595 if (sc == NULL) 596 panic("dge_freebuf: can't find softc pointer!"); 597 598 /* calculate the slot this buffer belongs to */ 599 600 i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; 601 602 if ((i < 0) || (i >= DGE_NBUFFERS)) 603 panic("dge_freebuf: asked to free buffer %d!", i); 604 605 s = splvm(); 606 entry = sc->sc_entry + i; 607 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 608 609 if (__predict_true(m != NULL)) 610 pool_cache_put(mb_cache, m); 611 splx(s); 612 } 613 #endif 614 615 static void dge_start(struct ifnet *); 616 static void dge_watchdog(struct ifnet *); 617 static int dge_ioctl(struct ifnet *, u_long, void *); 618 static int dge_init(struct ifnet *); 619 static void dge_stop(struct ifnet *, int); 620 621 static void dge_shutdown(void *); 622 623 static void dge_reset(struct dge_softc *); 624 static void dge_rxdrain(struct dge_softc *); 625 static int dge_add_rxbuf(struct dge_softc *, int); 626 627 static void dge_set_filter(struct dge_softc *); 628 629 static int dge_intr(void *); 630 static void dge_txintr(struct dge_softc *); 631 static void dge_rxintr(struct dge_softc *); 632 static void dge_linkintr(struct dge_softc *, uint32_t); 633 634 static int dge_match(struct device *, struct cfdata *, void *); 635 static void dge_attach(struct device *, struct device *, void *); 636 637 static int dge_read_eeprom(struct dge_softc *sc); 638 static int dge_eeprom_clockin(struct dge_softc *sc); 639 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 640 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 641 static int dge_xgmii_mediachange(struct ifnet *); 642 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 643 static void dge_xgmii_reset(struct dge_softc *); 644 static void dge_xgmii_writereg(struct device *, int, int, int); 645 646 647 CFATTACH_DECL(dge, sizeof(struct dge_softc), 648 dge_match, dge_attach, NULL, NULL); 649 650 #ifdef DGE_EVENT_COUNTERS 651 #if DGE_NTXSEGS > 100 652 #error Update dge_txseg_evcnt_names 653 #endif 654 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 655 #endif /* DGE_EVENT_COUNTERS */ 656 657 static int 658 dge_match(struct device *parent, struct cfdata *cf, void *aux) 659 { 660 struct pci_attach_args *pa = aux; 661 662 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 663 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82597EX) 664 return (1); 665 666 return (0); 667 } 668 669 static void 670 dge_attach(struct device *parent, struct device *self, void *aux) 671 { 672 struct dge_softc *sc = (void *) self; 673 struct pci_attach_args *pa = aux; 674 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 675 pci_chipset_tag_t pc = pa->pa_pc; 676 pci_intr_handle_t ih; 677 const char *intrstr = NULL; 678 bus_dma_segment_t seg; 679 int i, rseg, error; 680 uint8_t enaddr[ETHER_ADDR_LEN]; 681 pcireg_t preg, memtype; 682 uint32_t reg; 683 684 sc->sc_dmat = pa->pa_dmat; 685 sc->sc_pc = pa->pa_pc; 686 sc->sc_pt = pa->pa_tag; 687 688 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 689 aprint_naive(": Ethernet controller\n"); 690 aprint_normal(": Intel i82597EX 10GbE-LR Ethernet, rev. %d\n", preg); 691 692 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 693 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 694 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 695 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 696 return; 697 } 698 699 /* Enable bus mastering */ 700 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 701 preg |= PCI_COMMAND_MASTER_ENABLE; 702 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 703 704 /* 705 * Map and establish our interrupt. 706 */ 707 if (pci_intr_map(pa, &ih)) { 708 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 709 return; 710 } 711 intrstr = pci_intr_string(pc, ih); 712 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 713 if (sc->sc_ih == NULL) { 714 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 715 if (intrstr != NULL) 716 aprint_normal(" at %s", intrstr); 717 aprint_normal("\n"); 718 return; 719 } 720 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 721 722 /* 723 * Determine a few things about the bus we're connected to. 724 */ 725 reg = CSR_READ(sc, DGE_STATUS); 726 if (reg & STATUS_BUS64) 727 sc->sc_flags |= DGE_F_BUS64; 728 729 sc->sc_flags |= DGE_F_PCIX; 730 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 731 PCI_CAP_PCIX, 732 &sc->sc_pcix_offset, NULL) == 0) 733 aprint_error_dev(&sc->sc_dev, "unable to find PCIX " 734 "capability\n"); 735 736 if (sc->sc_flags & DGE_F_PCIX) { 737 switch (reg & STATUS_PCIX_MSK) { 738 case STATUS_PCIX_66: 739 sc->sc_bus_speed = 66; 740 break; 741 case STATUS_PCIX_100: 742 sc->sc_bus_speed = 100; 743 break; 744 case STATUS_PCIX_133: 745 sc->sc_bus_speed = 133; 746 break; 747 default: 748 aprint_error_dev(&sc->sc_dev, 749 "unknown PCIXSPD %d; assuming 66MHz\n", 750 reg & STATUS_PCIX_MSK); 751 sc->sc_bus_speed = 66; 752 } 753 } else 754 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 755 aprint_verbose_dev(&sc->sc_dev, "%d-bit %dMHz %s bus\n", 756 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 757 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 758 759 /* 760 * Allocate the control data structures, and create and load the 761 * DMA map for it. 762 */ 763 if ((error = bus_dmamem_alloc(sc->sc_dmat, 764 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 765 0)) != 0) { 766 aprint_error_dev(&sc->sc_dev, 767 "unable to allocate control data, error = %d\n", 768 error); 769 goto fail_0; 770 } 771 772 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 773 sizeof(struct dge_control_data), (void **)&sc->sc_control_data, 774 0)) != 0) { 775 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 776 error); 777 goto fail_1; 778 } 779 780 if ((error = bus_dmamap_create(sc->sc_dmat, 781 sizeof(struct dge_control_data), 1, 782 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 783 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 784 "error = %d\n", error); 785 goto fail_2; 786 } 787 788 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 789 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 790 0)) != 0) { 791 aprint_error_dev(&sc->sc_dev, 792 "unable to load control data DMA map, error = %d\n", 793 error); 794 goto fail_3; 795 } 796 797 #ifdef DGE_OFFBYONE_RXBUG 798 if (dge_alloc_rcvmem(sc) != 0) 799 return; /* Already complained */ 800 #endif 801 /* 802 * Create the transmit buffer DMA maps. 803 */ 804 for (i = 0; i < DGE_TXQUEUELEN; i++) { 805 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 806 DGE_NTXSEGS, MCLBYTES, 0, 0, 807 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 808 aprint_error_dev(&sc->sc_dev, "unable to create Tx DMA map %d, " 809 "error = %d\n", i, error); 810 goto fail_4; 811 } 812 } 813 814 /* 815 * Create the receive buffer DMA maps. 816 */ 817 for (i = 0; i < DGE_NRXDESC; i++) { 818 #ifdef DGE_OFFBYONE_RXBUG 819 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 820 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 821 #else 822 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 823 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 824 #endif 825 aprint_error_dev(&sc->sc_dev, "unable to create Rx DMA map %d, " 826 "error = %d\n", i, error); 827 goto fail_5; 828 } 829 sc->sc_rxsoft[i].rxs_mbuf = NULL; 830 } 831 832 /* 833 * Set bits in ctrl0 register. 834 * Should get the software defined pins out of EEPROM? 835 */ 836 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 837 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 838 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 839 840 /* 841 * Reset the chip to a known state. 842 */ 843 dge_reset(sc); 844 845 /* 846 * Reset the PHY. 847 */ 848 dge_xgmii_reset(sc); 849 850 /* 851 * Read in EEPROM data. 852 */ 853 if (dge_read_eeprom(sc)) { 854 aprint_error_dev(&sc->sc_dev, "couldn't read EEPROM\n"); 855 return; 856 } 857 858 /* 859 * Get the ethernet address. 860 */ 861 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 862 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 863 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 864 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 865 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 866 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 867 868 aprint_normal_dev(&sc->sc_dev, "Ethernet address %s\n", 869 ether_sprintf(enaddr)); 870 871 /* 872 * Setup media stuff. 873 */ 874 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 875 dge_xgmii_mediastatus); 876 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 877 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 878 879 ifp = &sc->sc_ethercom.ec_if; 880 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 881 ifp->if_softc = sc; 882 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 883 ifp->if_ioctl = dge_ioctl; 884 ifp->if_start = dge_start; 885 ifp->if_watchdog = dge_watchdog; 886 ifp->if_init = dge_init; 887 ifp->if_stop = dge_stop; 888 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 889 IFQ_SET_READY(&ifp->if_snd); 890 891 sc->sc_ethercom.ec_capabilities |= 892 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 893 894 /* 895 * We can perform TCPv4 and UDPv4 checkums in-bound. 896 */ 897 ifp->if_capabilities |= 898 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 899 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 900 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 901 902 /* 903 * Attach the interface. 904 */ 905 if_attach(ifp); 906 ether_ifattach(ifp, enaddr); 907 #if NRND > 0 908 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 909 RND_TYPE_NET, 0); 910 #endif 911 912 #ifdef DGE_EVENT_COUNTERS 913 /* Fix segment event naming */ 914 if (dge_txseg_evcnt_names == NULL) { 915 dge_txseg_evcnt_names = 916 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 917 for (i = 0; i < DGE_NTXSEGS; i++) 918 snprintf((*dge_txseg_evcnt_names)[i], 919 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 920 } 921 922 /* Attach event counters. */ 923 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 924 NULL, device_xname(&sc->sc_dev), "txsstall"); 925 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 926 NULL, device_xname(&sc->sc_dev), "txdstall"); 927 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 928 NULL, device_xname(&sc->sc_dev), "txforceintr"); 929 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 930 NULL, device_xname(&sc->sc_dev), "txdw"); 931 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 932 NULL, device_xname(&sc->sc_dev), "txqe"); 933 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 934 NULL, device_xname(&sc->sc_dev), "rxintr"); 935 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 936 NULL, device_xname(&sc->sc_dev), "linkintr"); 937 938 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 939 NULL, device_xname(&sc->sc_dev), "rxipsum"); 940 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 941 NULL, device_xname(&sc->sc_dev), "rxtusum"); 942 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 943 NULL, device_xname(&sc->sc_dev), "txipsum"); 944 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 945 NULL, device_xname(&sc->sc_dev), "txtusum"); 946 947 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 948 NULL, device_xname(&sc->sc_dev), "txctx init"); 949 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 950 NULL, device_xname(&sc->sc_dev), "txctx hit"); 951 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 952 NULL, device_xname(&sc->sc_dev), "txctx miss"); 953 954 for (i = 0; i < DGE_NTXSEGS; i++) 955 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 956 NULL, device_xname(&sc->sc_dev), (*dge_txseg_evcnt_names)[i]); 957 958 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 959 NULL, device_xname(&sc->sc_dev), "txdrop"); 960 961 #endif /* DGE_EVENT_COUNTERS */ 962 963 /* 964 * Make sure the interface is shutdown during reboot. 965 */ 966 sc->sc_sdhook = shutdownhook_establish(dge_shutdown, sc); 967 if (sc->sc_sdhook == NULL) 968 aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish shutdown hook\n"); 969 return; 970 971 /* 972 * Free any resources we've allocated during the failed attach 973 * attempt. Do this in reverse order and fall through. 974 */ 975 fail_5: 976 for (i = 0; i < DGE_NRXDESC; i++) { 977 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 978 bus_dmamap_destroy(sc->sc_dmat, 979 sc->sc_rxsoft[i].rxs_dmamap); 980 } 981 fail_4: 982 for (i = 0; i < DGE_TXQUEUELEN; i++) { 983 if (sc->sc_txsoft[i].txs_dmamap != NULL) 984 bus_dmamap_destroy(sc->sc_dmat, 985 sc->sc_txsoft[i].txs_dmamap); 986 } 987 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 988 fail_3: 989 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 990 fail_2: 991 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 992 sizeof(struct dge_control_data)); 993 fail_1: 994 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 995 fail_0: 996 return; 997 } 998 999 /* 1000 * dge_shutdown: 1001 * 1002 * Make sure the interface is stopped at reboot time. 1003 */ 1004 static void 1005 dge_shutdown(void *arg) 1006 { 1007 struct dge_softc *sc = arg; 1008 1009 dge_stop(&sc->sc_ethercom.ec_if, 1); 1010 } 1011 1012 /* 1013 * dge_tx_cksum: 1014 * 1015 * Set up TCP/IP checksumming parameters for the 1016 * specified packet. 1017 */ 1018 static int 1019 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1020 { 1021 struct mbuf *m0 = txs->txs_mbuf; 1022 struct dge_ctdes *t; 1023 uint32_t ipcs, tucs; 1024 struct ether_header *eh; 1025 int offset, iphl; 1026 uint8_t fields = 0; 1027 1028 /* 1029 * XXX It would be nice if the mbuf pkthdr had offset 1030 * fields for the protocol headers. 1031 */ 1032 1033 eh = mtod(m0, struct ether_header *); 1034 switch (htons(eh->ether_type)) { 1035 case ETHERTYPE_IP: 1036 offset = ETHER_HDR_LEN; 1037 break; 1038 1039 case ETHERTYPE_VLAN: 1040 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1041 break; 1042 1043 default: 1044 /* 1045 * Don't support this protocol or encapsulation. 1046 */ 1047 *fieldsp = 0; 1048 return (0); 1049 } 1050 1051 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1052 1053 /* 1054 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1055 * offload feature, if we load the context descriptor, we 1056 * MUST provide valid values for IPCSS and TUCSS fields. 1057 */ 1058 1059 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1060 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1061 fields |= TDESC_POPTS_IXSM; 1062 ipcs = DGE_TCPIP_IPCSS(offset) | 1063 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1064 DGE_TCPIP_IPCSE(offset + iphl - 1); 1065 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1066 /* Use the cached value. */ 1067 ipcs = sc->sc_txctx_ipcs; 1068 } else { 1069 /* Just initialize it to the likely value anyway. */ 1070 ipcs = DGE_TCPIP_IPCSS(offset) | 1071 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1072 DGE_TCPIP_IPCSE(offset + iphl - 1); 1073 } 1074 DPRINTF(DGE_DEBUG_CKSUM, 1075 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1076 device_xname(&sc->sc_dev), offset, ipcs)); 1077 1078 offset += iphl; 1079 1080 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1081 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1082 fields |= TDESC_POPTS_TXSM; 1083 tucs = DGE_TCPIP_TUCSS(offset) | 1084 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1085 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1086 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1087 /* Use the cached value. */ 1088 tucs = sc->sc_txctx_tucs; 1089 } else { 1090 /* Just initialize it to a valid TCP context. */ 1091 tucs = DGE_TCPIP_TUCSS(offset) | 1092 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1093 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1094 } 1095 1096 DPRINTF(DGE_DEBUG_CKSUM, 1097 ("%s: CKSUM: offset %d tucs 0x%x\n", 1098 device_xname(&sc->sc_dev), offset, tucs)); 1099 1100 if (sc->sc_txctx_ipcs == ipcs && 1101 sc->sc_txctx_tucs == tucs) { 1102 /* Cached context is fine. */ 1103 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1104 } else { 1105 /* Fill in the context descriptor. */ 1106 #ifdef DGE_EVENT_COUNTERS 1107 if (sc->sc_txctx_ipcs == 0xffffffff && 1108 sc->sc_txctx_tucs == 0xffffffff) 1109 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1110 else 1111 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1112 #endif 1113 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1114 t->dc_tcpip_ipcs = htole32(ipcs); 1115 t->dc_tcpip_tucs = htole32(tucs); 1116 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1117 t->dc_tcpip_seg = 0; 1118 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1119 1120 sc->sc_txctx_ipcs = ipcs; 1121 sc->sc_txctx_tucs = tucs; 1122 1123 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1124 txs->txs_ndesc++; 1125 } 1126 1127 *fieldsp = fields; 1128 1129 return (0); 1130 } 1131 1132 /* 1133 * dge_start: [ifnet interface function] 1134 * 1135 * Start packet transmission on the interface. 1136 */ 1137 static void 1138 dge_start(struct ifnet *ifp) 1139 { 1140 struct dge_softc *sc = ifp->if_softc; 1141 struct mbuf *m0; 1142 struct dge_txsoft *txs; 1143 bus_dmamap_t dmamap; 1144 int error, nexttx, lasttx = -1, ofree, seg; 1145 uint32_t cksumcmd; 1146 uint8_t cksumfields; 1147 1148 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1149 return; 1150 1151 /* 1152 * Remember the previous number of free descriptors. 1153 */ 1154 ofree = sc->sc_txfree; 1155 1156 /* 1157 * Loop through the send queue, setting up transmit descriptors 1158 * until we drain the queue, or use up all available transmit 1159 * descriptors. 1160 */ 1161 for (;;) { 1162 /* Grab a packet off the queue. */ 1163 IFQ_POLL(&ifp->if_snd, m0); 1164 if (m0 == NULL) 1165 break; 1166 1167 DPRINTF(DGE_DEBUG_TX, 1168 ("%s: TX: have packet to transmit: %p\n", 1169 device_xname(&sc->sc_dev), m0)); 1170 1171 /* Get a work queue entry. */ 1172 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1173 dge_txintr(sc); 1174 if (sc->sc_txsfree == 0) { 1175 DPRINTF(DGE_DEBUG_TX, 1176 ("%s: TX: no free job descriptors\n", 1177 device_xname(&sc->sc_dev))); 1178 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1179 break; 1180 } 1181 } 1182 1183 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1184 dmamap = txs->txs_dmamap; 1185 1186 /* 1187 * Load the DMA map. If this fails, the packet either 1188 * didn't fit in the allotted number of segments, or we 1189 * were short on resources. For the too-many-segments 1190 * case, we simply report an error and drop the packet, 1191 * since we can't sanely copy a jumbo packet to a single 1192 * buffer. 1193 */ 1194 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1195 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1196 if (error) { 1197 if (error == EFBIG) { 1198 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1199 printf("%s: Tx packet consumes too many " 1200 "DMA segments, dropping...\n", 1201 device_xname(&sc->sc_dev)); 1202 IFQ_DEQUEUE(&ifp->if_snd, m0); 1203 m_freem(m0); 1204 continue; 1205 } 1206 /* 1207 * Short on resources, just stop for now. 1208 */ 1209 DPRINTF(DGE_DEBUG_TX, 1210 ("%s: TX: dmamap load failed: %d\n", 1211 device_xname(&sc->sc_dev), error)); 1212 break; 1213 } 1214 1215 /* 1216 * Ensure we have enough descriptors free to describe 1217 * the packet. Note, we always reserve one descriptor 1218 * at the end of the ring due to the semantics of the 1219 * TDT register, plus one more in the event we need 1220 * to re-load checksum offload context. 1221 */ 1222 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1223 /* 1224 * Not enough free descriptors to transmit this 1225 * packet. We haven't committed anything yet, 1226 * so just unload the DMA map, put the packet 1227 * pack on the queue, and punt. Notify the upper 1228 * layer that there are no more slots left. 1229 */ 1230 DPRINTF(DGE_DEBUG_TX, 1231 ("%s: TX: need %d descriptors, have %d\n", 1232 device_xname(&sc->sc_dev), dmamap->dm_nsegs, 1233 sc->sc_txfree - 1)); 1234 ifp->if_flags |= IFF_OACTIVE; 1235 bus_dmamap_unload(sc->sc_dmat, dmamap); 1236 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1237 break; 1238 } 1239 1240 IFQ_DEQUEUE(&ifp->if_snd, m0); 1241 1242 /* 1243 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1244 */ 1245 1246 /* Sync the DMA map. */ 1247 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1248 BUS_DMASYNC_PREWRITE); 1249 1250 DPRINTF(DGE_DEBUG_TX, 1251 ("%s: TX: packet has %d DMA segments\n", 1252 device_xname(&sc->sc_dev), dmamap->dm_nsegs)); 1253 1254 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1255 1256 /* 1257 * Store a pointer to the packet so that we can free it 1258 * later. 1259 * 1260 * Initially, we consider the number of descriptors the 1261 * packet uses the number of DMA segments. This may be 1262 * incremented by 1 if we do checksum offload (a descriptor 1263 * is used to set the checksum context). 1264 */ 1265 txs->txs_mbuf = m0; 1266 txs->txs_firstdesc = sc->sc_txnext; 1267 txs->txs_ndesc = dmamap->dm_nsegs; 1268 1269 /* 1270 * Set up checksum offload parameters for 1271 * this packet. 1272 */ 1273 if (m0->m_pkthdr.csum_flags & 1274 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1275 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1276 /* Error message already displayed. */ 1277 bus_dmamap_unload(sc->sc_dmat, dmamap); 1278 continue; 1279 } 1280 } else { 1281 cksumfields = 0; 1282 } 1283 1284 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1285 1286 /* 1287 * Initialize the transmit descriptor. 1288 */ 1289 for (nexttx = sc->sc_txnext, seg = 0; 1290 seg < dmamap->dm_nsegs; 1291 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1292 /* 1293 * Note: we currently only use 32-bit DMA 1294 * addresses. 1295 */ 1296 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1297 sc->sc_txdescs[nexttx].dt_baddrl = 1298 htole32(dmamap->dm_segs[seg].ds_addr); 1299 sc->sc_txdescs[nexttx].dt_ctl = 1300 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1301 sc->sc_txdescs[nexttx].dt_status = 0; 1302 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1303 sc->sc_txdescs[nexttx].dt_vlan = 0; 1304 lasttx = nexttx; 1305 1306 DPRINTF(DGE_DEBUG_TX, 1307 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1308 device_xname(&sc->sc_dev), nexttx, 1309 le32toh(dmamap->dm_segs[seg].ds_addr), 1310 le32toh(dmamap->dm_segs[seg].ds_len))); 1311 } 1312 1313 KASSERT(lasttx != -1); 1314 1315 /* 1316 * Set up the command byte on the last descriptor of 1317 * the packet. If we're in the interrupt delay window, 1318 * delay the interrupt. 1319 */ 1320 sc->sc_txdescs[lasttx].dt_ctl |= 1321 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1322 1323 txs->txs_lastdesc = lasttx; 1324 1325 DPRINTF(DGE_DEBUG_TX, 1326 ("%s: TX: desc %d: cmdlen 0x%08x\n", device_xname(&sc->sc_dev), 1327 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1328 1329 /* Sync the descriptors we're using. */ 1330 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1331 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1332 1333 /* Give the packet to the chip. */ 1334 CSR_WRITE(sc, DGE_TDT, nexttx); 1335 1336 DPRINTF(DGE_DEBUG_TX, 1337 ("%s: TX: TDT -> %d\n", device_xname(&sc->sc_dev), nexttx)); 1338 1339 DPRINTF(DGE_DEBUG_TX, 1340 ("%s: TX: finished transmitting packet, job %d\n", 1341 device_xname(&sc->sc_dev), sc->sc_txsnext)); 1342 1343 /* Advance the tx pointer. */ 1344 sc->sc_txfree -= txs->txs_ndesc; 1345 sc->sc_txnext = nexttx; 1346 1347 sc->sc_txsfree--; 1348 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1349 1350 #if NBPFILTER > 0 1351 /* Pass the packet to any BPF listeners. */ 1352 if (ifp->if_bpf) 1353 bpf_mtap(ifp->if_bpf, m0); 1354 #endif /* NBPFILTER > 0 */ 1355 } 1356 1357 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1358 /* No more slots; notify upper layer. */ 1359 ifp->if_flags |= IFF_OACTIVE; 1360 } 1361 1362 if (sc->sc_txfree != ofree) { 1363 /* Set a watchdog timer in case the chip flakes out. */ 1364 ifp->if_timer = 5; 1365 } 1366 } 1367 1368 /* 1369 * dge_watchdog: [ifnet interface function] 1370 * 1371 * Watchdog timer handler. 1372 */ 1373 static void 1374 dge_watchdog(struct ifnet *ifp) 1375 { 1376 struct dge_softc *sc = ifp->if_softc; 1377 1378 /* 1379 * Since we're using delayed interrupts, sweep up 1380 * before we report an error. 1381 */ 1382 dge_txintr(sc); 1383 1384 if (sc->sc_txfree != DGE_NTXDESC) { 1385 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1386 device_xname(&sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, 1387 sc->sc_txnext); 1388 ifp->if_oerrors++; 1389 1390 /* Reset the interface. */ 1391 (void) dge_init(ifp); 1392 } 1393 1394 /* Try to get more packets going. */ 1395 dge_start(ifp); 1396 } 1397 1398 /* 1399 * dge_ioctl: [ifnet interface function] 1400 * 1401 * Handle control requests from the operator. 1402 */ 1403 static int 1404 dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1405 { 1406 struct dge_softc *sc = ifp->if_softc; 1407 struct ifreq *ifr = (struct ifreq *) data; 1408 pcireg_t preg; 1409 int s, error, mmrbc; 1410 1411 s = splnet(); 1412 1413 switch (cmd) { 1414 case SIOCSIFMEDIA: 1415 case SIOCGIFMEDIA: 1416 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1417 break; 1418 1419 case SIOCSIFMTU: 1420 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) 1421 error = EINVAL; 1422 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1423 break; 1424 else if (ifp->if_flags & IFF_UP) 1425 error = (*ifp->if_init)(ifp); 1426 else 1427 error = 0; 1428 break; 1429 1430 case SIOCSIFFLAGS: 1431 /* extract link flags */ 1432 if ((ifp->if_flags & IFF_LINK0) == 0 && 1433 (ifp->if_flags & IFF_LINK1) == 0) 1434 mmrbc = PCIX_MMRBC_512; 1435 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1436 (ifp->if_flags & IFF_LINK1) != 0) 1437 mmrbc = PCIX_MMRBC_1024; 1438 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1439 (ifp->if_flags & IFF_LINK1) == 0) 1440 mmrbc = PCIX_MMRBC_2048; 1441 else 1442 mmrbc = PCIX_MMRBC_4096; 1443 if (mmrbc != sc->sc_mmrbc) { 1444 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1445 preg &= ~PCIX_MMRBC_MSK; 1446 preg |= mmrbc; 1447 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1448 sc->sc_mmrbc = mmrbc; 1449 } 1450 /* FALLTHROUGH */ 1451 default: 1452 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1453 break; 1454 1455 error = 0; 1456 1457 if (cmd == SIOCSIFCAP) 1458 error = (*ifp->if_init)(ifp); 1459 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1460 ; 1461 else if (ifp->if_flags & IFF_RUNNING) { 1462 /* 1463 * Multicast list has changed; set the hardware filter 1464 * accordingly. 1465 */ 1466 dge_set_filter(sc); 1467 } 1468 break; 1469 } 1470 1471 /* Try to get more packets going. */ 1472 dge_start(ifp); 1473 1474 splx(s); 1475 return (error); 1476 } 1477 1478 /* 1479 * dge_intr: 1480 * 1481 * Interrupt service routine. 1482 */ 1483 static int 1484 dge_intr(void *arg) 1485 { 1486 struct dge_softc *sc = arg; 1487 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1488 uint32_t icr; 1489 int wantinit, handled = 0; 1490 1491 for (wantinit = 0; wantinit == 0;) { 1492 icr = CSR_READ(sc, DGE_ICR); 1493 if ((icr & sc->sc_icr) == 0) 1494 break; 1495 1496 #if 0 /*NRND > 0*/ 1497 if (RND_ENABLED(&sc->rnd_source)) 1498 rnd_add_uint32(&sc->rnd_source, icr); 1499 #endif 1500 1501 handled = 1; 1502 1503 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1504 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1505 DPRINTF(DGE_DEBUG_RX, 1506 ("%s: RX: got Rx intr 0x%08x\n", 1507 device_xname(&sc->sc_dev), 1508 icr & (ICR_RXDMT0|ICR_RXT0))); 1509 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1510 } 1511 #endif 1512 dge_rxintr(sc); 1513 1514 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1515 if (icr & ICR_TXDW) { 1516 DPRINTF(DGE_DEBUG_TX, 1517 ("%s: TX: got TXDW interrupt\n", 1518 device_xname(&sc->sc_dev))); 1519 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1520 } 1521 if (icr & ICR_TXQE) 1522 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1523 #endif 1524 dge_txintr(sc); 1525 1526 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1527 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1528 dge_linkintr(sc, icr); 1529 } 1530 1531 if (icr & ICR_RXO) { 1532 printf("%s: Receive overrun\n", device_xname(&sc->sc_dev)); 1533 wantinit = 1; 1534 } 1535 } 1536 1537 if (handled) { 1538 if (wantinit) 1539 dge_init(ifp); 1540 1541 /* Try to get more packets going. */ 1542 dge_start(ifp); 1543 } 1544 1545 return (handled); 1546 } 1547 1548 /* 1549 * dge_txintr: 1550 * 1551 * Helper; handle transmit interrupts. 1552 */ 1553 static void 1554 dge_txintr(struct dge_softc *sc) 1555 { 1556 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1557 struct dge_txsoft *txs; 1558 uint8_t status; 1559 int i; 1560 1561 ifp->if_flags &= ~IFF_OACTIVE; 1562 1563 /* 1564 * Go through the Tx list and free mbufs for those 1565 * frames which have been transmitted. 1566 */ 1567 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1568 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1569 txs = &sc->sc_txsoft[i]; 1570 1571 DPRINTF(DGE_DEBUG_TX, 1572 ("%s: TX: checking job %d\n", device_xname(&sc->sc_dev), i)); 1573 1574 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1575 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1576 1577 status = 1578 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1579 if ((status & TDESC_STA_DD) == 0) { 1580 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1581 BUS_DMASYNC_PREREAD); 1582 break; 1583 } 1584 1585 DPRINTF(DGE_DEBUG_TX, 1586 ("%s: TX: job %d done: descs %d..%d\n", 1587 device_xname(&sc->sc_dev), i, txs->txs_firstdesc, 1588 txs->txs_lastdesc)); 1589 1590 ifp->if_opackets++; 1591 sc->sc_txfree += txs->txs_ndesc; 1592 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1593 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1594 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1595 m_freem(txs->txs_mbuf); 1596 txs->txs_mbuf = NULL; 1597 } 1598 1599 /* Update the dirty transmit buffer pointer. */ 1600 sc->sc_txsdirty = i; 1601 DPRINTF(DGE_DEBUG_TX, 1602 ("%s: TX: txsdirty -> %d\n", device_xname(&sc->sc_dev), i)); 1603 1604 /* 1605 * If there are no more pending transmissions, cancel the watchdog 1606 * timer. 1607 */ 1608 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1609 ifp->if_timer = 0; 1610 } 1611 1612 /* 1613 * dge_rxintr: 1614 * 1615 * Helper; handle receive interrupts. 1616 */ 1617 static void 1618 dge_rxintr(struct dge_softc *sc) 1619 { 1620 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1621 struct dge_rxsoft *rxs; 1622 struct mbuf *m; 1623 int i, len; 1624 uint8_t status, errors; 1625 1626 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1627 rxs = &sc->sc_rxsoft[i]; 1628 1629 DPRINTF(DGE_DEBUG_RX, 1630 ("%s: RX: checking descriptor %d\n", 1631 device_xname(&sc->sc_dev), i)); 1632 1633 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1634 1635 status = sc->sc_rxdescs[i].dr_status; 1636 errors = sc->sc_rxdescs[i].dr_errors; 1637 len = le16toh(sc->sc_rxdescs[i].dr_len); 1638 1639 if ((status & RDESC_STS_DD) == 0) { 1640 /* 1641 * We have processed all of the receive descriptors. 1642 */ 1643 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1644 break; 1645 } 1646 1647 if (__predict_false(sc->sc_rxdiscard)) { 1648 DPRINTF(DGE_DEBUG_RX, 1649 ("%s: RX: discarding contents of descriptor %d\n", 1650 device_xname(&sc->sc_dev), i)); 1651 DGE_INIT_RXDESC(sc, i); 1652 if (status & RDESC_STS_EOP) { 1653 /* Reset our state. */ 1654 DPRINTF(DGE_DEBUG_RX, 1655 ("%s: RX: resetting rxdiscard -> 0\n", 1656 device_xname(&sc->sc_dev))); 1657 sc->sc_rxdiscard = 0; 1658 } 1659 continue; 1660 } 1661 1662 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1663 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1664 1665 m = rxs->rxs_mbuf; 1666 1667 /* 1668 * Add a new receive buffer to the ring. 1669 */ 1670 if (dge_add_rxbuf(sc, i) != 0) { 1671 /* 1672 * Failed, throw away what we've done so 1673 * far, and discard the rest of the packet. 1674 */ 1675 ifp->if_ierrors++; 1676 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1677 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1678 DGE_INIT_RXDESC(sc, i); 1679 if ((status & RDESC_STS_EOP) == 0) 1680 sc->sc_rxdiscard = 1; 1681 if (sc->sc_rxhead != NULL) 1682 m_freem(sc->sc_rxhead); 1683 DGE_RXCHAIN_RESET(sc); 1684 DPRINTF(DGE_DEBUG_RX, 1685 ("%s: RX: Rx buffer allocation failed, " 1686 "dropping packet%s\n", device_xname(&sc->sc_dev), 1687 sc->sc_rxdiscard ? " (discard)" : "")); 1688 continue; 1689 } 1690 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1691 1692 DGE_RXCHAIN_LINK(sc, m); 1693 1694 m->m_len = len; 1695 1696 DPRINTF(DGE_DEBUG_RX, 1697 ("%s: RX: buffer at %p len %d\n", 1698 device_xname(&sc->sc_dev), m->m_data, len)); 1699 1700 /* 1701 * If this is not the end of the packet, keep 1702 * looking. 1703 */ 1704 if ((status & RDESC_STS_EOP) == 0) { 1705 sc->sc_rxlen += len; 1706 DPRINTF(DGE_DEBUG_RX, 1707 ("%s: RX: not yet EOP, rxlen -> %d\n", 1708 device_xname(&sc->sc_dev), sc->sc_rxlen)); 1709 continue; 1710 } 1711 1712 /* 1713 * Okay, we have the entire packet now... 1714 */ 1715 *sc->sc_rxtailp = NULL; 1716 m = sc->sc_rxhead; 1717 len += sc->sc_rxlen; 1718 1719 DGE_RXCHAIN_RESET(sc); 1720 1721 DPRINTF(DGE_DEBUG_RX, 1722 ("%s: RX: have entire packet, len -> %d\n", 1723 device_xname(&sc->sc_dev), len)); 1724 1725 /* 1726 * If an error occurred, update stats and drop the packet. 1727 */ 1728 if (errors & 1729 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1730 ifp->if_ierrors++; 1731 if (errors & RDESC_ERR_SE) 1732 printf("%s: symbol error\n", 1733 device_xname(&sc->sc_dev)); 1734 else if (errors & RDESC_ERR_P) 1735 printf("%s: parity error\n", 1736 device_xname(&sc->sc_dev)); 1737 else if (errors & RDESC_ERR_CE) 1738 printf("%s: CRC error\n", 1739 device_xname(&sc->sc_dev)); 1740 m_freem(m); 1741 continue; 1742 } 1743 1744 /* 1745 * No errors. Receive the packet. 1746 */ 1747 m->m_pkthdr.rcvif = ifp; 1748 m->m_pkthdr.len = len; 1749 1750 /* 1751 * Set up checksum info for this packet. 1752 */ 1753 if (status & RDESC_STS_IPCS) { 1754 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1755 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1756 if (errors & RDESC_ERR_IPE) 1757 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1758 } 1759 if (status & RDESC_STS_TCPCS) { 1760 /* 1761 * Note: we don't know if this was TCP or UDP, 1762 * so we just set both bits, and expect the 1763 * upper layers to deal. 1764 */ 1765 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1766 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1767 if (errors & RDESC_ERR_TCPE) 1768 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1769 } 1770 1771 ifp->if_ipackets++; 1772 1773 #if NBPFILTER > 0 1774 /* Pass this up to any BPF listeners. */ 1775 if (ifp->if_bpf) 1776 bpf_mtap(ifp->if_bpf, m); 1777 #endif /* NBPFILTER > 0 */ 1778 1779 /* Pass it on. */ 1780 (*ifp->if_input)(ifp, m); 1781 } 1782 1783 /* Update the receive pointer. */ 1784 sc->sc_rxptr = i; 1785 1786 DPRINTF(DGE_DEBUG_RX, 1787 ("%s: RX: rxptr -> %d\n", device_xname(&sc->sc_dev), i)); 1788 } 1789 1790 /* 1791 * dge_linkintr: 1792 * 1793 * Helper; handle link interrupts. 1794 */ 1795 static void 1796 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1797 { 1798 uint32_t status; 1799 1800 if (icr & ICR_LSC) { 1801 status = CSR_READ(sc, DGE_STATUS); 1802 if (status & STATUS_LINKUP) { 1803 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1804 device_xname(&sc->sc_dev))); 1805 } else { 1806 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1807 device_xname(&sc->sc_dev))); 1808 } 1809 } else if (icr & ICR_RXSEQ) { 1810 DPRINTF(DGE_DEBUG_LINK, 1811 ("%s: LINK: Receive sequence error\n", 1812 device_xname(&sc->sc_dev))); 1813 } 1814 /* XXX - fix errata */ 1815 } 1816 1817 /* 1818 * dge_reset: 1819 * 1820 * Reset the i82597 chip. 1821 */ 1822 static void 1823 dge_reset(struct dge_softc *sc) 1824 { 1825 int i; 1826 1827 /* 1828 * Do a chip reset. 1829 */ 1830 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1831 1832 delay(10000); 1833 1834 for (i = 0; i < 1000; i++) { 1835 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1836 break; 1837 delay(20); 1838 } 1839 1840 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1841 printf("%s: WARNING: reset failed to complete\n", 1842 device_xname(&sc->sc_dev)); 1843 /* 1844 * Reset the EEPROM logic. 1845 * This will cause the chip to reread its default values, 1846 * which doesn't happen otherwise (errata). 1847 */ 1848 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1849 delay(10000); 1850 } 1851 1852 /* 1853 * dge_init: [ifnet interface function] 1854 * 1855 * Initialize the interface. Must be called at splnet(). 1856 */ 1857 static int 1858 dge_init(struct ifnet *ifp) 1859 { 1860 struct dge_softc *sc = ifp->if_softc; 1861 struct dge_rxsoft *rxs; 1862 int i, error = 0; 1863 uint32_t reg; 1864 1865 /* 1866 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1867 * There is a small but measurable benefit to avoiding the adjusment 1868 * of the descriptor so that the headers are aligned, for normal mtu, 1869 * on such platforms. One possibility is that the DMA itself is 1870 * slightly more efficient if the front of the entire packet (instead 1871 * of the front of the headers) is aligned. 1872 * 1873 * Note we must always set align_tweak to 0 if we are using 1874 * jumbo frames. 1875 */ 1876 #ifdef __NO_STRICT_ALIGNMENT 1877 sc->sc_align_tweak = 0; 1878 #else 1879 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1880 sc->sc_align_tweak = 0; 1881 else 1882 sc->sc_align_tweak = 2; 1883 #endif /* __NO_STRICT_ALIGNMENT */ 1884 1885 /* Cancel any pending I/O. */ 1886 dge_stop(ifp, 0); 1887 1888 /* Reset the chip to a known state. */ 1889 dge_reset(sc); 1890 1891 /* Initialize the transmit descriptor ring. */ 1892 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1893 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1894 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1895 sc->sc_txfree = DGE_NTXDESC; 1896 sc->sc_txnext = 0; 1897 1898 sc->sc_txctx_ipcs = 0xffffffff; 1899 sc->sc_txctx_tucs = 0xffffffff; 1900 1901 CSR_WRITE(sc, DGE_TDBAH, 0); 1902 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1903 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1904 CSR_WRITE(sc, DGE_TDH, 0); 1905 CSR_WRITE(sc, DGE_TDT, 0); 1906 CSR_WRITE(sc, DGE_TIDV, TIDV); 1907 1908 #if 0 1909 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1910 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1911 #endif 1912 CSR_WRITE(sc, DGE_RXDCTL, 1913 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1914 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1915 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1916 1917 /* Initialize the transmit job descriptors. */ 1918 for (i = 0; i < DGE_TXQUEUELEN; i++) 1919 sc->sc_txsoft[i].txs_mbuf = NULL; 1920 sc->sc_txsfree = DGE_TXQUEUELEN; 1921 sc->sc_txsnext = 0; 1922 sc->sc_txsdirty = 0; 1923 1924 /* 1925 * Initialize the receive descriptor and receive job 1926 * descriptor rings. 1927 */ 1928 CSR_WRITE(sc, DGE_RDBAH, 0); 1929 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1930 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1931 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1932 CSR_WRITE(sc, DGE_RDT, 0); 1933 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1934 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1935 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1936 1937 for (i = 0; i < DGE_NRXDESC; i++) { 1938 rxs = &sc->sc_rxsoft[i]; 1939 if (rxs->rxs_mbuf == NULL) { 1940 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1941 printf("%s: unable to allocate or map rx " 1942 "buffer %d, error = %d\n", 1943 device_xname(&sc->sc_dev), i, error); 1944 /* 1945 * XXX Should attempt to run with fewer receive 1946 * XXX buffers instead of just failing. 1947 */ 1948 dge_rxdrain(sc); 1949 goto out; 1950 } 1951 } 1952 DGE_INIT_RXDESC(sc, i); 1953 } 1954 sc->sc_rxptr = DGE_RXSPACE; 1955 sc->sc_rxdiscard = 0; 1956 DGE_RXCHAIN_RESET(sc); 1957 1958 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1959 sc->sc_ctrl0 |= CTRL0_JFE; 1960 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1961 } 1962 1963 /* Write the control registers. */ 1964 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1965 1966 /* 1967 * Set up checksum offload parameters. 1968 */ 1969 reg = CSR_READ(sc, DGE_RXCSUM); 1970 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1971 reg |= RXCSUM_IPOFL; 1972 else 1973 reg &= ~RXCSUM_IPOFL; 1974 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1975 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1976 else { 1977 reg &= ~RXCSUM_TUOFL; 1978 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 1979 reg &= ~RXCSUM_IPOFL; 1980 } 1981 CSR_WRITE(sc, DGE_RXCSUM, reg); 1982 1983 /* 1984 * Set up the interrupt registers. 1985 */ 1986 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 1987 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 1988 ICR_RXO | ICR_RXT0; 1989 1990 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 1991 1992 /* 1993 * Set up the transmit control register. 1994 */ 1995 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 1996 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 1997 1998 /* 1999 * Set up the receive control register; we actually program 2000 * the register when we set the receive filter. Use multicast 2001 * address offset type 0. 2002 */ 2003 sc->sc_mchash_type = 0; 2004 2005 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2006 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2007 2008 #ifdef DGE_OFFBYONE_RXBUG 2009 sc->sc_rctl |= RCTL_BSIZE_16k; 2010 #else 2011 switch(MCLBYTES) { 2012 case 2048: 2013 sc->sc_rctl |= RCTL_BSIZE_2k; 2014 break; 2015 case 4096: 2016 sc->sc_rctl |= RCTL_BSIZE_4k; 2017 break; 2018 case 8192: 2019 sc->sc_rctl |= RCTL_BSIZE_8k; 2020 break; 2021 case 16384: 2022 sc->sc_rctl |= RCTL_BSIZE_16k; 2023 break; 2024 default: 2025 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2026 } 2027 #endif 2028 2029 /* Set the receive filter. */ 2030 /* Also sets RCTL */ 2031 dge_set_filter(sc); 2032 2033 /* ...all done! */ 2034 ifp->if_flags |= IFF_RUNNING; 2035 ifp->if_flags &= ~IFF_OACTIVE; 2036 2037 out: 2038 if (error) 2039 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 2040 return (error); 2041 } 2042 2043 /* 2044 * dge_rxdrain: 2045 * 2046 * Drain the receive queue. 2047 */ 2048 static void 2049 dge_rxdrain(struct dge_softc *sc) 2050 { 2051 struct dge_rxsoft *rxs; 2052 int i; 2053 2054 for (i = 0; i < DGE_NRXDESC; i++) { 2055 rxs = &sc->sc_rxsoft[i]; 2056 if (rxs->rxs_mbuf != NULL) { 2057 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2058 m_freem(rxs->rxs_mbuf); 2059 rxs->rxs_mbuf = NULL; 2060 } 2061 } 2062 } 2063 2064 /* 2065 * dge_stop: [ifnet interface function] 2066 * 2067 * Stop transmission on the interface. 2068 */ 2069 static void 2070 dge_stop(struct ifnet *ifp, int disable) 2071 { 2072 struct dge_softc *sc = ifp->if_softc; 2073 struct dge_txsoft *txs; 2074 int i; 2075 2076 /* Stop the transmit and receive processes. */ 2077 CSR_WRITE(sc, DGE_TCTL, 0); 2078 CSR_WRITE(sc, DGE_RCTL, 0); 2079 2080 /* Release any queued transmit buffers. */ 2081 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2082 txs = &sc->sc_txsoft[i]; 2083 if (txs->txs_mbuf != NULL) { 2084 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2085 m_freem(txs->txs_mbuf); 2086 txs->txs_mbuf = NULL; 2087 } 2088 } 2089 2090 /* Mark the interface as down and cancel the watchdog timer. */ 2091 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2092 ifp->if_timer = 0; 2093 2094 if (disable) 2095 dge_rxdrain(sc); 2096 } 2097 2098 /* 2099 * dge_add_rxbuf: 2100 * 2101 * Add a receive buffer to the indiciated descriptor. 2102 */ 2103 static int 2104 dge_add_rxbuf(struct dge_softc *sc, int idx) 2105 { 2106 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2107 struct mbuf *m; 2108 int error; 2109 #ifdef DGE_OFFBYONE_RXBUG 2110 void *buf; 2111 #endif 2112 2113 MGETHDR(m, M_DONTWAIT, MT_DATA); 2114 if (m == NULL) 2115 return (ENOBUFS); 2116 2117 #ifdef DGE_OFFBYONE_RXBUG 2118 if ((buf = dge_getbuf(sc)) == NULL) 2119 return ENOBUFS; 2120 2121 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2122 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2123 m->m_flags |= M_EXT_RW; 2124 2125 if (rxs->rxs_mbuf != NULL) 2126 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2127 rxs->rxs_mbuf = m; 2128 2129 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2130 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2131 #else 2132 MCLGET(m, M_DONTWAIT); 2133 if ((m->m_flags & M_EXT) == 0) { 2134 m_freem(m); 2135 return (ENOBUFS); 2136 } 2137 2138 if (rxs->rxs_mbuf != NULL) 2139 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2140 2141 rxs->rxs_mbuf = m; 2142 2143 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2144 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2145 BUS_DMA_READ|BUS_DMA_NOWAIT); 2146 #endif 2147 if (error) { 2148 printf("%s: unable to load rx DMA map %d, error = %d\n", 2149 device_xname(&sc->sc_dev), idx, error); 2150 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2151 } 2152 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2153 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2154 2155 return (0); 2156 } 2157 2158 /* 2159 * dge_set_ral: 2160 * 2161 * Set an entry in the receive address list. 2162 */ 2163 static void 2164 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2165 { 2166 uint32_t ral_lo, ral_hi; 2167 2168 if (enaddr != NULL) { 2169 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2170 (enaddr[3] << 24); 2171 ral_hi = enaddr[4] | (enaddr[5] << 8); 2172 ral_hi |= RAH_AV; 2173 } else { 2174 ral_lo = 0; 2175 ral_hi = 0; 2176 } 2177 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2178 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2179 } 2180 2181 /* 2182 * dge_mchash: 2183 * 2184 * Compute the hash of the multicast address for the 4096-bit 2185 * multicast filter. 2186 */ 2187 static uint32_t 2188 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2189 { 2190 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2191 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2192 uint32_t hash; 2193 2194 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2195 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2196 2197 return (hash & 0xfff); 2198 } 2199 2200 /* 2201 * dge_set_filter: 2202 * 2203 * Set up the receive filter. 2204 */ 2205 static void 2206 dge_set_filter(struct dge_softc *sc) 2207 { 2208 struct ethercom *ec = &sc->sc_ethercom; 2209 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2210 struct ether_multi *enm; 2211 struct ether_multistep step; 2212 uint32_t hash, reg, bit; 2213 int i; 2214 2215 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2216 2217 if (ifp->if_flags & IFF_BROADCAST) 2218 sc->sc_rctl |= RCTL_BAM; 2219 if (ifp->if_flags & IFF_PROMISC) { 2220 sc->sc_rctl |= RCTL_UPE; 2221 goto allmulti; 2222 } 2223 2224 /* 2225 * Set the station address in the first RAL slot, and 2226 * clear the remaining slots. 2227 */ 2228 dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 2229 for (i = 1; i < RA_TABSIZE; i++) 2230 dge_set_ral(sc, NULL, i); 2231 2232 /* Clear out the multicast table. */ 2233 for (i = 0; i < MC_TABSIZE; i++) 2234 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2235 2236 ETHER_FIRST_MULTI(step, ec, enm); 2237 while (enm != NULL) { 2238 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2239 /* 2240 * We must listen to a range of multicast addresses. 2241 * For now, just accept all multicasts, rather than 2242 * trying to set only those filter bits needed to match 2243 * the range. (At this time, the only use of address 2244 * ranges is for IP multicast routing, for which the 2245 * range is big enough to require all bits set.) 2246 */ 2247 goto allmulti; 2248 } 2249 2250 hash = dge_mchash(sc, enm->enm_addrlo); 2251 2252 reg = (hash >> 5) & 0x7f; 2253 bit = hash & 0x1f; 2254 2255 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2256 hash |= 1U << bit; 2257 2258 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2259 2260 ETHER_NEXT_MULTI(step, enm); 2261 } 2262 2263 ifp->if_flags &= ~IFF_ALLMULTI; 2264 goto setit; 2265 2266 allmulti: 2267 ifp->if_flags |= IFF_ALLMULTI; 2268 sc->sc_rctl |= RCTL_MPE; 2269 2270 setit: 2271 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2272 } 2273 2274 /* 2275 * Read in the EEPROM info and verify checksum. 2276 */ 2277 int 2278 dge_read_eeprom(struct dge_softc *sc) 2279 { 2280 uint16_t cksum; 2281 int i; 2282 2283 cksum = 0; 2284 for (i = 0; i < EEPROM_SIZE; i++) { 2285 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2286 cksum += sc->sc_eeprom[i]; 2287 } 2288 return cksum != EEPROM_CKSUM; 2289 } 2290 2291 2292 /* 2293 * Read a 16-bit word from address addr in the serial EEPROM. 2294 */ 2295 uint16_t 2296 dge_eeprom_word(struct dge_softc *sc, int addr) 2297 { 2298 uint32_t reg; 2299 uint16_t rval = 0; 2300 int i; 2301 2302 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2303 2304 /* Lower clock pulse (and data in to chip) */ 2305 CSR_WRITE(sc, DGE_EECD, reg); 2306 /* Select chip */ 2307 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2308 2309 /* Send read command */ 2310 dge_eeprom_clockout(sc, 1); 2311 dge_eeprom_clockout(sc, 1); 2312 dge_eeprom_clockout(sc, 0); 2313 2314 /* Send address */ 2315 for (i = 5; i >= 0; i--) 2316 dge_eeprom_clockout(sc, (addr >> i) & 1); 2317 2318 /* Read data */ 2319 for (i = 0; i < 16; i++) { 2320 rval <<= 1; 2321 rval |= dge_eeprom_clockin(sc); 2322 } 2323 2324 /* Deselect chip */ 2325 CSR_WRITE(sc, DGE_EECD, reg); 2326 2327 return rval; 2328 } 2329 2330 /* 2331 * Clock out a single bit to the EEPROM. 2332 */ 2333 void 2334 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2335 { 2336 int reg; 2337 2338 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2339 if (bit) 2340 reg |= EECD_DI; 2341 2342 CSR_WRITE(sc, DGE_EECD, reg); 2343 delay(2); 2344 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2345 delay(2); 2346 CSR_WRITE(sc, DGE_EECD, reg); 2347 delay(2); 2348 } 2349 2350 /* 2351 * Clock in a single bit from EEPROM. 2352 */ 2353 int 2354 dge_eeprom_clockin(struct dge_softc *sc) 2355 { 2356 int reg, rv; 2357 2358 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2359 2360 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2361 delay(2); 2362 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2363 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2364 delay(2); 2365 2366 return rv; 2367 } 2368 2369 static void 2370 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2371 { 2372 struct dge_softc *sc = ifp->if_softc; 2373 2374 ifmr->ifm_status = IFM_AVALID; 2375 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2376 2377 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2378 ifmr->ifm_status |= IFM_ACTIVE; 2379 } 2380 2381 static inline int 2382 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2383 { 2384 int i, mdic; 2385 2386 CSR_WRITE(sc, DGE_MDIO, 2387 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2388 for (i = 0; i < 10; i++) { 2389 delay(10); 2390 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2391 break; 2392 } 2393 return mdic; 2394 } 2395 2396 2397 static void 2398 dge_xgmii_writereg(struct device *self, int phy, int reg, int val) 2399 { 2400 struct dge_softc *sc = (void *) self; 2401 int mdic; 2402 2403 CSR_WRITE(sc, DGE_MDIRW, val); 2404 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2405 printf("%s: address cycle timeout; phy %d reg %d\n", 2406 device_xname(&sc->sc_dev), phy, reg); 2407 return; 2408 } 2409 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2410 printf("%s: read cycle timeout; phy %d reg %d\n", 2411 device_xname(&sc->sc_dev), phy, reg); 2412 return; 2413 } 2414 } 2415 2416 static void 2417 dge_xgmii_reset(struct dge_softc *sc) 2418 { 2419 dge_xgmii_writereg((void *)sc, 0, 0, BMCR_RESET); 2420 } 2421 2422 static int 2423 dge_xgmii_mediachange(struct ifnet *ifp) 2424 { 2425 return 0; 2426 } 2427