1 /* $NetBSD: if_dge.c,v 1.48 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.48 2018/06/26 06:48:01 msaitoh Exp $"); 84 85 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 99 #include <sys/rndsource.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #include <net/bpf.h> 107 108 #include <netinet/in.h> /* XXX for struct ip */ 109 #include <netinet/in_systm.h> /* XXX for struct ip */ 110 #include <netinet/ip.h> /* XXX for struct ip */ 111 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 112 113 #include <sys/bus.h> 114 #include <sys/intr.h> 115 #include <machine/endian.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/mii_bitbang.h> 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/pci/if_dgereg.h> 126 127 /* 128 * The receive engine may sometimes become off-by-one when writing back 129 * chained descriptors. Avoid this by allocating a large chunk of 130 * memory and use if instead (to avoid chained descriptors). 131 * This only happens with chained descriptors under heavy load. 132 */ 133 #define DGE_OFFBYONE_RXBUG 134 135 #define DGE_EVENT_COUNTERS 136 #define DGE_DEBUG 137 138 #ifdef DGE_DEBUG 139 #define DGE_DEBUG_LINK 0x01 140 #define DGE_DEBUG_TX 0x02 141 #define DGE_DEBUG_RX 0x04 142 #define DGE_DEBUG_CKSUM 0x08 143 int dge_debug = 0; 144 145 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 146 #else 147 #define DPRINTF(x, y) /* nothing */ 148 #endif /* DGE_DEBUG */ 149 150 /* 151 * Transmit descriptor list size. We allow up to 100 DMA segments per 152 * packet (Intel reports of jumbo frame packets with as 153 * many as 80 DMA segments when using 16k buffers). 154 */ 155 #define DGE_NTXSEGS 100 156 #define DGE_IFQUEUELEN 20000 157 #define DGE_TXQUEUELEN 2048 158 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 159 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 160 #define DGE_NTXDESC 1024 161 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 162 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 163 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 164 165 /* 166 * Receive descriptor list size. 167 * Packet is of size MCLBYTES, and for jumbo packets buffers may 168 * be chained. Due to the nature of the card (high-speed), keep this 169 * ring large. With 2k buffers the ring can store 400 jumbo packets, 170 * which at full speed will be received in just under 3ms. 171 */ 172 #define DGE_NRXDESC 2048 173 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 174 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 175 /* 176 * # of descriptors between head and written descriptors. 177 * This is to work-around two erratas. 178 */ 179 #define DGE_RXSPACE 10 180 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 181 /* 182 * Receive descriptor fetch threshholds. These are values recommended 183 * by Intel, do not touch them unless you know what you are doing. 184 */ 185 #define RXDCTL_PTHRESH_VAL 128 186 #define RXDCTL_HTHRESH_VAL 16 187 #define RXDCTL_WTHRESH_VAL 16 188 189 190 /* 191 * Tweakable parameters; default values. 192 */ 193 #define FCRTH 0x30000 /* Send XOFF water mark */ 194 #define FCRTL 0x28000 /* Send XON water mark */ 195 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 196 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 197 198 /* 199 * Control structures are DMA'd to the i82597 chip. We allocate them in 200 * a single clump that maps to a single DMA segment to make serveral things 201 * easier. 202 */ 203 struct dge_control_data { 204 /* 205 * The transmit descriptors. 206 */ 207 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 208 209 /* 210 * The receive descriptors. 211 */ 212 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 213 }; 214 215 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 216 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 217 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 218 219 /* 220 * The DGE interface have a higher max MTU size than normal jumbo frames. 221 */ 222 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 223 224 /* 225 * Software state for transmit jobs. 226 */ 227 struct dge_txsoft { 228 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 229 bus_dmamap_t txs_dmamap; /* our DMA map */ 230 int txs_firstdesc; /* first descriptor in packet */ 231 int txs_lastdesc; /* last descriptor in packet */ 232 int txs_ndesc; /* # of descriptors used */ 233 }; 234 235 /* 236 * Software state for receive buffers. Each descriptor gets a 237 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 238 * more than one buffer, we chain them together. 239 */ 240 struct dge_rxsoft { 241 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 242 bus_dmamap_t rxs_dmamap; /* our DMA map */ 243 }; 244 245 /* 246 * Software state per device. 247 */ 248 struct dge_softc { 249 device_t sc_dev; /* generic device information */ 250 bus_space_tag_t sc_st; /* bus space tag */ 251 bus_space_handle_t sc_sh; /* bus space handle */ 252 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 253 struct ethercom sc_ethercom; /* ethernet common data */ 254 255 int sc_flags; /* flags; see below */ 256 int sc_bus_speed; /* PCI/PCIX bus speed */ 257 int sc_pcix_offset; /* PCIX capability register offset */ 258 259 const struct dge_product *sc_dgep; /* Pointer to the dge_product entry */ 260 pci_chipset_tag_t sc_pc; 261 pcitag_t sc_pt; 262 int sc_mmrbc; /* Max PCIX memory read byte count */ 263 264 void *sc_ih; /* interrupt cookie */ 265 266 struct ifmedia sc_media; 267 268 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 269 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 270 271 int sc_align_tweak; 272 273 /* 274 * Software state for the transmit and receive descriptors. 275 */ 276 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 277 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 278 279 /* 280 * Control data structures. 281 */ 282 struct dge_control_data *sc_control_data; 283 #define sc_txdescs sc_control_data->wcd_txdescs 284 #define sc_rxdescs sc_control_data->wcd_rxdescs 285 286 #ifdef DGE_EVENT_COUNTERS 287 /* Event counters. */ 288 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 289 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 290 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 291 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 292 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 293 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 294 struct evcnt sc_ev_linkintr; /* Link interrupts */ 295 296 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 297 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 298 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 299 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 300 301 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 302 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 303 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 304 305 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 306 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 307 #endif /* DGE_EVENT_COUNTERS */ 308 309 int sc_txfree; /* number of free Tx descriptors */ 310 int sc_txnext; /* next ready Tx descriptor */ 311 312 int sc_txsfree; /* number of free Tx jobs */ 313 int sc_txsnext; /* next free Tx job */ 314 int sc_txsdirty; /* dirty Tx jobs */ 315 316 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 317 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 318 319 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 320 int sc_rxdiscard; 321 int sc_rxlen; 322 struct mbuf *sc_rxhead; 323 struct mbuf *sc_rxtail; 324 struct mbuf **sc_rxtailp; 325 326 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 327 uint32_t sc_icr; /* prototype interrupt bits */ 328 uint32_t sc_tctl; /* prototype TCTL register */ 329 uint32_t sc_rctl; /* prototype RCTL register */ 330 331 int sc_mchash_type; /* multicast filter offset */ 332 333 uint16_t sc_eeprom[EEPROM_SIZE]; 334 335 krndsource_t rnd_source; /* random source */ 336 #ifdef DGE_OFFBYONE_RXBUG 337 void *sc_bugbuf; 338 SLIST_HEAD(, rxbugentry) sc_buglist; 339 bus_dmamap_t sc_bugmap; 340 struct rxbugentry *sc_entry; 341 #endif 342 }; 343 344 #define DGE_RXCHAIN_RESET(sc) \ 345 do { \ 346 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 347 *(sc)->sc_rxtailp = NULL; \ 348 (sc)->sc_rxlen = 0; \ 349 } while (/*CONSTCOND*/0) 350 351 #define DGE_RXCHAIN_LINK(sc, m) \ 352 do { \ 353 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 354 (sc)->sc_rxtailp = &(m)->m_next; \ 355 } while (/*CONSTCOND*/0) 356 357 /* sc_flags */ 358 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 359 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 360 361 #ifdef DGE_EVENT_COUNTERS 362 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 363 #else 364 #define DGE_EVCNT_INCR(ev) /* nothing */ 365 #endif 366 367 #define CSR_READ(sc, reg) \ 368 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 369 #define CSR_WRITE(sc, reg, val) \ 370 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 371 372 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 373 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 374 375 #define DGE_CDTXSYNC(sc, x, n, ops) \ 376 do { \ 377 int __x, __n; \ 378 \ 379 __x = (x); \ 380 __n = (n); \ 381 \ 382 /* If it will wrap around, sync to the end of the ring. */ \ 383 if ((__x + __n) > DGE_NTXDESC) { \ 384 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 385 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 386 (DGE_NTXDESC - __x), (ops)); \ 387 __n -= (DGE_NTXDESC - __x); \ 388 __x = 0; \ 389 } \ 390 \ 391 /* Now sync whatever is left. */ \ 392 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 393 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 394 } while (/*CONSTCOND*/0) 395 396 #define DGE_CDRXSYNC(sc, x, ops) \ 397 do { \ 398 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 399 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 400 } while (/*CONSTCOND*/0) 401 402 #ifdef DGE_OFFBYONE_RXBUG 403 #define DGE_INIT_RXDESC(sc, x) \ 404 do { \ 405 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 406 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 407 struct mbuf *__m = __rxs->rxs_mbuf; \ 408 \ 409 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 410 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 411 __rxd->dr_baddrh = 0; \ 412 __rxd->dr_len = 0; \ 413 __rxd->dr_cksum = 0; \ 414 __rxd->dr_status = 0; \ 415 __rxd->dr_errors = 0; \ 416 __rxd->dr_special = 0; \ 417 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 418 \ 419 CSR_WRITE((sc), DGE_RDT, (x)); \ 420 } while (/*CONSTCOND*/0) 421 #else 422 #define DGE_INIT_RXDESC(sc, x) \ 423 do { \ 424 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 425 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 426 struct mbuf *__m = __rxs->rxs_mbuf; \ 427 \ 428 /* \ 429 * Note: We scoot the packet forward 2 bytes in the buffer \ 430 * so that the payload after the Ethernet header is aligned \ 431 * to a 4-byte boundary. \ 432 * \ 433 * XXX BRAINDAMAGE ALERT! \ 434 * The stupid chip uses the same size for every buffer, which \ 435 * is set in the Receive Control register. We are using the 2K \ 436 * size option, but what we REALLY want is (2K - 2)! For this \ 437 * reason, we can't "scoot" packets longer than the standard \ 438 * Ethernet MTU. On strict-alignment platforms, if the total \ 439 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 440 * the upper layer copy the headers. \ 441 */ \ 442 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 443 \ 444 __rxd->dr_baddrl = \ 445 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 446 (sc)->sc_align_tweak); \ 447 __rxd->dr_baddrh = 0; \ 448 __rxd->dr_len = 0; \ 449 __rxd->dr_cksum = 0; \ 450 __rxd->dr_status = 0; \ 451 __rxd->dr_errors = 0; \ 452 __rxd->dr_special = 0; \ 453 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 454 \ 455 CSR_WRITE((sc), DGE_RDT, (x)); \ 456 } while (/*CONSTCOND*/0) 457 #endif 458 459 #ifdef DGE_OFFBYONE_RXBUG 460 /* 461 * Allocation constants. Much memory may be used for this. 462 */ 463 #ifndef DGE_BUFFER_SIZE 464 #define DGE_BUFFER_SIZE DGE_MAX_MTU 465 #endif 466 #define DGE_NBUFFERS (4*DGE_NRXDESC) 467 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 468 469 struct rxbugentry { 470 SLIST_ENTRY(rxbugentry) rb_entry; 471 int rb_slot; 472 }; 473 474 static int 475 dge_alloc_rcvmem(struct dge_softc *sc) 476 { 477 char *kva; 478 bus_dma_segment_t seg; 479 int i, rseg, state, error; 480 struct rxbugentry *entry; 481 482 state = error = 0; 483 484 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 485 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 486 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 487 return ENOBUFS; 488 } 489 490 state = 1; 491 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, 492 BUS_DMA_NOWAIT)) { 493 aprint_error_dev(sc->sc_dev, "can't map DMA buffers (%d bytes)\n", 494 (int)DGE_RXMEM); 495 error = ENOBUFS; 496 goto out; 497 } 498 499 state = 2; 500 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 501 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 502 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 503 error = ENOBUFS; 504 goto out; 505 } 506 507 state = 3; 508 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 509 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 510 aprint_error_dev(sc->sc_dev, "can't load DMA map\n"); 511 error = ENOBUFS; 512 goto out; 513 } 514 515 state = 4; 516 sc->sc_bugbuf = (void *)kva; 517 SLIST_INIT(&sc->sc_buglist); 518 519 /* 520 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 521 * in an array. 522 */ 523 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 524 M_DEVBUF, M_NOWAIT)) == NULL) { 525 error = ENOBUFS; 526 goto out; 527 } 528 sc->sc_entry = entry; 529 for (i = 0; i < DGE_NBUFFERS; i++) { 530 entry[i].rb_slot = i; 531 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 532 } 533 out: 534 if (error != 0) { 535 switch (state) { 536 case 4: 537 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 538 case 3: 539 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 540 case 2: 541 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 542 case 1: 543 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 544 break; 545 default: 546 break; 547 } 548 } 549 550 return error; 551 } 552 553 /* 554 * Allocate a jumbo buffer. 555 */ 556 static void * 557 dge_getbuf(struct dge_softc *sc) 558 { 559 struct rxbugentry *entry; 560 561 entry = SLIST_FIRST(&sc->sc_buglist); 562 563 if (entry == NULL) { 564 printf("%s: no free RX buffers\n", device_xname(sc->sc_dev)); 565 return(NULL); 566 } 567 568 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 569 return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 570 } 571 572 /* 573 * Release a jumbo buffer. 574 */ 575 static void 576 dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) 577 { 578 struct rxbugentry *entry; 579 struct dge_softc *sc; 580 int i, s; 581 582 /* Extract the softc struct pointer. */ 583 sc = (struct dge_softc *)arg; 584 585 if (sc == NULL) 586 panic("dge_freebuf: can't find softc pointer!"); 587 588 /* calculate the slot this buffer belongs to */ 589 590 i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; 591 592 if ((i < 0) || (i >= DGE_NBUFFERS)) 593 panic("dge_freebuf: asked to free buffer %d!", i); 594 595 s = splvm(); 596 entry = sc->sc_entry + i; 597 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 598 599 if (__predict_true(m != NULL)) 600 pool_cache_put(mb_cache, m); 601 splx(s); 602 } 603 #endif 604 605 static void dge_start(struct ifnet *); 606 static void dge_watchdog(struct ifnet *); 607 static int dge_ioctl(struct ifnet *, u_long, void *); 608 static int dge_init(struct ifnet *); 609 static void dge_stop(struct ifnet *, int); 610 611 static bool dge_shutdown(device_t, int); 612 613 static void dge_reset(struct dge_softc *); 614 static void dge_rxdrain(struct dge_softc *); 615 static int dge_add_rxbuf(struct dge_softc *, int); 616 617 static void dge_set_filter(struct dge_softc *); 618 619 static int dge_intr(void *); 620 static void dge_txintr(struct dge_softc *); 621 static void dge_rxintr(struct dge_softc *); 622 static void dge_linkintr(struct dge_softc *, uint32_t); 623 624 static int dge_match(device_t, cfdata_t, void *); 625 static void dge_attach(device_t, device_t, void *); 626 627 static int dge_read_eeprom(struct dge_softc *sc); 628 static int dge_eeprom_clockin(struct dge_softc *sc); 629 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 630 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 631 static int dge_xgmii_mediachange(struct ifnet *); 632 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 633 static void dge_xgmii_reset(struct dge_softc *); 634 static void dge_xgmii_writereg(struct dge_softc *, int, int, int); 635 636 637 CFATTACH_DECL_NEW(dge, sizeof(struct dge_softc), 638 dge_match, dge_attach, NULL, NULL); 639 640 #ifdef DGE_EVENT_COUNTERS 641 #if DGE_NTXSEGS > 100 642 #error Update dge_txseg_evcnt_names 643 #endif 644 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 645 #endif /* DGE_EVENT_COUNTERS */ 646 647 /* 648 * Devices supported by this driver. 649 */ 650 static const struct dge_product { 651 pci_vendor_id_t dgep_vendor; 652 pci_product_id_t dgep_product; 653 const char *dgep_name; 654 int dgep_flags; 655 #define DGEP_F_10G_LR 0x01 656 #define DGEP_F_10G_SR 0x02 657 } dge_products[] = { 658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX, 659 "Intel i82597EX 10GbE-LR Ethernet", 660 DGEP_F_10G_LR }, 661 662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_SR, 663 "Intel i82597EX 10GbE-SR Ethernet", 664 DGEP_F_10G_SR }, 665 666 { 0, 0, 667 NULL, 668 0 }, 669 }; 670 671 static const struct dge_product * 672 dge_lookup(const struct pci_attach_args *pa) 673 { 674 const struct dge_product *dgep; 675 676 for (dgep = dge_products; dgep->dgep_name != NULL; dgep++) { 677 if (PCI_VENDOR(pa->pa_id) == dgep->dgep_vendor && 678 PCI_PRODUCT(pa->pa_id) == dgep->dgep_product) 679 return dgep; 680 } 681 return NULL; 682 } 683 684 static int 685 dge_match(device_t parent, cfdata_t cf, void *aux) 686 { 687 struct pci_attach_args *pa = aux; 688 689 if (dge_lookup(pa) != NULL) 690 return (1); 691 692 return (0); 693 } 694 695 static void 696 dge_attach(device_t parent, device_t self, void *aux) 697 { 698 struct dge_softc *sc = device_private(self); 699 struct pci_attach_args *pa = aux; 700 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 701 pci_chipset_tag_t pc = pa->pa_pc; 702 pci_intr_handle_t ih; 703 const char *intrstr = NULL; 704 bus_dma_segment_t seg; 705 int i, rseg, error; 706 uint8_t enaddr[ETHER_ADDR_LEN]; 707 pcireg_t preg, memtype; 708 uint32_t reg; 709 char intrbuf[PCI_INTRSTR_LEN]; 710 const struct dge_product *dgep; 711 712 sc->sc_dgep = dgep = dge_lookup(pa); 713 if (dgep == NULL) { 714 printf("\n"); 715 panic("dge_attach: impossible"); 716 } 717 718 sc->sc_dev = self; 719 sc->sc_dmat = pa->pa_dmat; 720 sc->sc_pc = pa->pa_pc; 721 sc->sc_pt = pa->pa_tag; 722 723 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 724 dgep->dgep_name, 1); 725 726 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 727 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 728 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 729 aprint_error_dev(sc->sc_dev, 730 "unable to map device registers\n"); 731 return; 732 } 733 734 /* Enable bus mastering */ 735 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 736 preg |= PCI_COMMAND_MASTER_ENABLE; 737 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 738 739 /* 740 * Map and establish our interrupt. 741 */ 742 if (pci_intr_map(pa, &ih)) { 743 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 744 return; 745 } 746 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 747 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 748 if (sc->sc_ih == NULL) { 749 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 750 if (intrstr != NULL) 751 aprint_error(" at %s", intrstr); 752 aprint_error("\n"); 753 return; 754 } 755 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 756 757 /* 758 * Determine a few things about the bus we're connected to. 759 */ 760 reg = CSR_READ(sc, DGE_STATUS); 761 if (reg & STATUS_BUS64) 762 sc->sc_flags |= DGE_F_BUS64; 763 764 sc->sc_flags |= DGE_F_PCIX; 765 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 766 PCI_CAP_PCIX, 767 &sc->sc_pcix_offset, NULL) == 0) 768 aprint_error_dev(sc->sc_dev, "unable to find PCIX " 769 "capability\n"); 770 771 if (sc->sc_flags & DGE_F_PCIX) { 772 switch (reg & STATUS_PCIX_MSK) { 773 case STATUS_PCIX_66: 774 sc->sc_bus_speed = 66; 775 break; 776 case STATUS_PCIX_100: 777 sc->sc_bus_speed = 100; 778 break; 779 case STATUS_PCIX_133: 780 sc->sc_bus_speed = 133; 781 break; 782 default: 783 aprint_error_dev(sc->sc_dev, 784 "unknown PCIXSPD %d; assuming 66MHz\n", 785 reg & STATUS_PCIX_MSK); 786 sc->sc_bus_speed = 66; 787 } 788 } else 789 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 790 aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", 791 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 792 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 793 794 /* 795 * Allocate the control data structures, and create and load the 796 * DMA map for it. 797 */ 798 if ((error = bus_dmamem_alloc(sc->sc_dmat, 799 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 800 0)) != 0) { 801 aprint_error_dev(sc->sc_dev, 802 "unable to allocate control data, error = %d\n", 803 error); 804 goto fail_0; 805 } 806 807 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 808 sizeof(struct dge_control_data), (void **)&sc->sc_control_data, 809 0)) != 0) { 810 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 811 error); 812 goto fail_1; 813 } 814 815 if ((error = bus_dmamap_create(sc->sc_dmat, 816 sizeof(struct dge_control_data), 1, 817 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 818 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 819 "error = %d\n", error); 820 goto fail_2; 821 } 822 823 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 824 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 825 0)) != 0) { 826 aprint_error_dev(sc->sc_dev, 827 "unable to load control data DMA map, error = %d\n", 828 error); 829 goto fail_3; 830 } 831 832 #ifdef DGE_OFFBYONE_RXBUG 833 if (dge_alloc_rcvmem(sc) != 0) 834 return; /* Already complained */ 835 #endif 836 /* 837 * Create the transmit buffer DMA maps. 838 */ 839 for (i = 0; i < DGE_TXQUEUELEN; i++) { 840 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 841 DGE_NTXSEGS, MCLBYTES, 0, 0, 842 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 843 aprint_error_dev(sc->sc_dev, "unable to create Tx DMA map %d, " 844 "error = %d\n", i, error); 845 goto fail_4; 846 } 847 } 848 849 /* 850 * Create the receive buffer DMA maps. 851 */ 852 for (i = 0; i < DGE_NRXDESC; i++) { 853 #ifdef DGE_OFFBYONE_RXBUG 854 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 855 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 856 #else 857 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 858 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 859 #endif 860 aprint_error_dev(sc->sc_dev, "unable to create Rx DMA map %d, " 861 "error = %d\n", i, error); 862 goto fail_5; 863 } 864 sc->sc_rxsoft[i].rxs_mbuf = NULL; 865 } 866 867 /* 868 * Set bits in ctrl0 register. 869 * Should get the software defined pins out of EEPROM? 870 */ 871 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 872 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 873 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 874 875 /* 876 * Reset the chip to a known state. 877 */ 878 dge_reset(sc); 879 880 /* 881 * Reset the PHY. 882 */ 883 dge_xgmii_reset(sc); 884 885 /* 886 * Read in EEPROM data. 887 */ 888 if (dge_read_eeprom(sc)) { 889 aprint_error_dev(sc->sc_dev, "couldn't read EEPROM\n"); 890 return; 891 } 892 893 /* 894 * Get the ethernet address. 895 */ 896 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 897 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 898 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 899 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 900 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 901 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 902 903 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 904 ether_sprintf(enaddr)); 905 906 /* 907 * Setup media stuff. 908 */ 909 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 910 dge_xgmii_mediastatus); 911 if (dgep->dgep_flags & DGEP_F_10G_SR) { 912 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_SR, 0, NULL); 913 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_SR); 914 } else { /* XXX default is LR */ 915 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 916 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 917 } 918 919 ifp = &sc->sc_ethercom.ec_if; 920 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 921 ifp->if_softc = sc; 922 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 923 ifp->if_ioctl = dge_ioctl; 924 ifp->if_start = dge_start; 925 ifp->if_watchdog = dge_watchdog; 926 ifp->if_init = dge_init; 927 ifp->if_stop = dge_stop; 928 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 929 IFQ_SET_READY(&ifp->if_snd); 930 931 sc->sc_ethercom.ec_capabilities |= 932 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 933 934 /* 935 * We can perform TCPv4 and UDPv4 checkums in-bound. 936 */ 937 ifp->if_capabilities |= 938 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 939 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 940 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 941 942 /* 943 * Attach the interface. 944 */ 945 if_attach(ifp); 946 if_deferred_start_init(ifp, NULL); 947 ether_ifattach(ifp, enaddr); 948 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 949 RND_TYPE_NET, RND_FLAG_DEFAULT); 950 951 #ifdef DGE_EVENT_COUNTERS 952 /* Fix segment event naming */ 953 if (dge_txseg_evcnt_names == NULL) { 954 dge_txseg_evcnt_names = 955 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 956 for (i = 0; i < DGE_NTXSEGS; i++) 957 snprintf((*dge_txseg_evcnt_names)[i], 958 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 959 } 960 961 /* Attach event counters. */ 962 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 963 NULL, device_xname(sc->sc_dev), "txsstall"); 964 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 965 NULL, device_xname(sc->sc_dev), "txdstall"); 966 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 967 NULL, device_xname(sc->sc_dev), "txforceintr"); 968 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 969 NULL, device_xname(sc->sc_dev), "txdw"); 970 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 971 NULL, device_xname(sc->sc_dev), "txqe"); 972 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 973 NULL, device_xname(sc->sc_dev), "rxintr"); 974 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 975 NULL, device_xname(sc->sc_dev), "linkintr"); 976 977 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 978 NULL, device_xname(sc->sc_dev), "rxipsum"); 979 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 980 NULL, device_xname(sc->sc_dev), "rxtusum"); 981 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 982 NULL, device_xname(sc->sc_dev), "txipsum"); 983 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 984 NULL, device_xname(sc->sc_dev), "txtusum"); 985 986 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 987 NULL, device_xname(sc->sc_dev), "txctx init"); 988 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 989 NULL, device_xname(sc->sc_dev), "txctx hit"); 990 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 991 NULL, device_xname(sc->sc_dev), "txctx miss"); 992 993 for (i = 0; i < DGE_NTXSEGS; i++) 994 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 995 NULL, device_xname(sc->sc_dev), (*dge_txseg_evcnt_names)[i]); 996 997 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 998 NULL, device_xname(sc->sc_dev), "txdrop"); 999 1000 #endif /* DGE_EVENT_COUNTERS */ 1001 1002 /* 1003 * Make sure the interface is shutdown during reboot. 1004 */ 1005 if (pmf_device_register1(self, NULL, NULL, dge_shutdown)) 1006 pmf_class_network_register(self, ifp); 1007 else 1008 aprint_error_dev(self, "couldn't establish power handler\n"); 1009 1010 return; 1011 1012 /* 1013 * Free any resources we've allocated during the failed attach 1014 * attempt. Do this in reverse order and fall through. 1015 */ 1016 fail_5: 1017 for (i = 0; i < DGE_NRXDESC; i++) { 1018 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1019 bus_dmamap_destroy(sc->sc_dmat, 1020 sc->sc_rxsoft[i].rxs_dmamap); 1021 } 1022 fail_4: 1023 for (i = 0; i < DGE_TXQUEUELEN; i++) { 1024 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1025 bus_dmamap_destroy(sc->sc_dmat, 1026 sc->sc_txsoft[i].txs_dmamap); 1027 } 1028 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1029 fail_3: 1030 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1031 fail_2: 1032 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1033 sizeof(struct dge_control_data)); 1034 fail_1: 1035 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1036 fail_0: 1037 return; 1038 } 1039 1040 /* 1041 * dge_shutdown: 1042 * 1043 * Make sure the interface is stopped at reboot time. 1044 */ 1045 static bool 1046 dge_shutdown(device_t self, int howto) 1047 { 1048 struct dge_softc *sc; 1049 1050 sc = device_private(self); 1051 dge_stop(&sc->sc_ethercom.ec_if, 1); 1052 1053 return true; 1054 } 1055 1056 /* 1057 * dge_tx_cksum: 1058 * 1059 * Set up TCP/IP checksumming parameters for the 1060 * specified packet. 1061 */ 1062 static int 1063 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1064 { 1065 struct mbuf *m0 = txs->txs_mbuf; 1066 struct dge_ctdes *t; 1067 uint32_t ipcs, tucs; 1068 struct ether_header *eh; 1069 int offset, iphl; 1070 uint8_t fields = 0; 1071 1072 /* 1073 * XXX It would be nice if the mbuf pkthdr had offset 1074 * fields for the protocol headers. 1075 */ 1076 1077 eh = mtod(m0, struct ether_header *); 1078 switch (htons(eh->ether_type)) { 1079 case ETHERTYPE_IP: 1080 offset = ETHER_HDR_LEN; 1081 break; 1082 1083 case ETHERTYPE_VLAN: 1084 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1085 break; 1086 1087 default: 1088 /* 1089 * Don't support this protocol or encapsulation. 1090 */ 1091 *fieldsp = 0; 1092 return (0); 1093 } 1094 1095 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1096 1097 /* 1098 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1099 * offload feature, if we load the context descriptor, we 1100 * MUST provide valid values for IPCSS and TUCSS fields. 1101 */ 1102 1103 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1104 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1105 fields |= TDESC_POPTS_IXSM; 1106 ipcs = DGE_TCPIP_IPCSS(offset) | 1107 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1108 DGE_TCPIP_IPCSE(offset + iphl - 1); 1109 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1110 /* Use the cached value. */ 1111 ipcs = sc->sc_txctx_ipcs; 1112 } else { 1113 /* Just initialize it to the likely value anyway. */ 1114 ipcs = DGE_TCPIP_IPCSS(offset) | 1115 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1116 DGE_TCPIP_IPCSE(offset + iphl - 1); 1117 } 1118 DPRINTF(DGE_DEBUG_CKSUM, 1119 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1120 device_xname(sc->sc_dev), offset, ipcs)); 1121 1122 offset += iphl; 1123 1124 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1125 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1126 fields |= TDESC_POPTS_TXSM; 1127 tucs = DGE_TCPIP_TUCSS(offset) | 1128 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1129 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1130 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1131 /* Use the cached value. */ 1132 tucs = sc->sc_txctx_tucs; 1133 } else { 1134 /* Just initialize it to a valid TCP context. */ 1135 tucs = DGE_TCPIP_TUCSS(offset) | 1136 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1137 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1138 } 1139 1140 DPRINTF(DGE_DEBUG_CKSUM, 1141 ("%s: CKSUM: offset %d tucs 0x%x\n", 1142 device_xname(sc->sc_dev), offset, tucs)); 1143 1144 if (sc->sc_txctx_ipcs == ipcs && 1145 sc->sc_txctx_tucs == tucs) { 1146 /* Cached context is fine. */ 1147 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1148 } else { 1149 /* Fill in the context descriptor. */ 1150 #ifdef DGE_EVENT_COUNTERS 1151 if (sc->sc_txctx_ipcs == 0xffffffff && 1152 sc->sc_txctx_tucs == 0xffffffff) 1153 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1154 else 1155 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1156 #endif 1157 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1158 t->dc_tcpip_ipcs = htole32(ipcs); 1159 t->dc_tcpip_tucs = htole32(tucs); 1160 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1161 t->dc_tcpip_seg = 0; 1162 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1163 1164 sc->sc_txctx_ipcs = ipcs; 1165 sc->sc_txctx_tucs = tucs; 1166 1167 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1168 txs->txs_ndesc++; 1169 } 1170 1171 *fieldsp = fields; 1172 1173 return (0); 1174 } 1175 1176 /* 1177 * dge_start: [ifnet interface function] 1178 * 1179 * Start packet transmission on the interface. 1180 */ 1181 static void 1182 dge_start(struct ifnet *ifp) 1183 { 1184 struct dge_softc *sc = ifp->if_softc; 1185 struct mbuf *m0; 1186 struct dge_txsoft *txs; 1187 bus_dmamap_t dmamap; 1188 int error, nexttx, lasttx = -1, ofree, seg; 1189 uint32_t cksumcmd; 1190 uint8_t cksumfields; 1191 1192 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1193 return; 1194 1195 /* 1196 * Remember the previous number of free descriptors. 1197 */ 1198 ofree = sc->sc_txfree; 1199 1200 /* 1201 * Loop through the send queue, setting up transmit descriptors 1202 * until we drain the queue, or use up all available transmit 1203 * descriptors. 1204 */ 1205 for (;;) { 1206 /* Grab a packet off the queue. */ 1207 IFQ_POLL(&ifp->if_snd, m0); 1208 if (m0 == NULL) 1209 break; 1210 1211 DPRINTF(DGE_DEBUG_TX, 1212 ("%s: TX: have packet to transmit: %p\n", 1213 device_xname(sc->sc_dev), m0)); 1214 1215 /* Get a work queue entry. */ 1216 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1217 dge_txintr(sc); 1218 if (sc->sc_txsfree == 0) { 1219 DPRINTF(DGE_DEBUG_TX, 1220 ("%s: TX: no free job descriptors\n", 1221 device_xname(sc->sc_dev))); 1222 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1223 break; 1224 } 1225 } 1226 1227 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1228 dmamap = txs->txs_dmamap; 1229 1230 /* 1231 * Load the DMA map. If this fails, the packet either 1232 * didn't fit in the allotted number of segments, or we 1233 * were short on resources. For the too-many-segments 1234 * case, we simply report an error and drop the packet, 1235 * since we can't sanely copy a jumbo packet to a single 1236 * buffer. 1237 */ 1238 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1239 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1240 if (error) { 1241 if (error == EFBIG) { 1242 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1243 printf("%s: Tx packet consumes too many " 1244 "DMA segments, dropping...\n", 1245 device_xname(sc->sc_dev)); 1246 IFQ_DEQUEUE(&ifp->if_snd, m0); 1247 m_freem(m0); 1248 continue; 1249 } 1250 /* 1251 * Short on resources, just stop for now. 1252 */ 1253 DPRINTF(DGE_DEBUG_TX, 1254 ("%s: TX: dmamap load failed: %d\n", 1255 device_xname(sc->sc_dev), error)); 1256 break; 1257 } 1258 1259 /* 1260 * Ensure we have enough descriptors free to describe 1261 * the packet. Note, we always reserve one descriptor 1262 * at the end of the ring due to the semantics of the 1263 * TDT register, plus one more in the event we need 1264 * to re-load checksum offload context. 1265 */ 1266 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1267 /* 1268 * Not enough free descriptors to transmit this 1269 * packet. We haven't committed anything yet, 1270 * so just unload the DMA map, put the packet 1271 * pack on the queue, and punt. Notify the upper 1272 * layer that there are no more slots left. 1273 */ 1274 DPRINTF(DGE_DEBUG_TX, 1275 ("%s: TX: need %d descriptors, have %d\n", 1276 device_xname(sc->sc_dev), dmamap->dm_nsegs, 1277 sc->sc_txfree - 1)); 1278 ifp->if_flags |= IFF_OACTIVE; 1279 bus_dmamap_unload(sc->sc_dmat, dmamap); 1280 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1281 break; 1282 } 1283 1284 IFQ_DEQUEUE(&ifp->if_snd, m0); 1285 1286 /* 1287 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1288 */ 1289 1290 /* Sync the DMA map. */ 1291 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1292 BUS_DMASYNC_PREWRITE); 1293 1294 DPRINTF(DGE_DEBUG_TX, 1295 ("%s: TX: packet has %d DMA segments\n", 1296 device_xname(sc->sc_dev), dmamap->dm_nsegs)); 1297 1298 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1299 1300 /* 1301 * Store a pointer to the packet so that we can free it 1302 * later. 1303 * 1304 * Initially, we consider the number of descriptors the 1305 * packet uses the number of DMA segments. This may be 1306 * incremented by 1 if we do checksum offload (a descriptor 1307 * is used to set the checksum context). 1308 */ 1309 txs->txs_mbuf = m0; 1310 txs->txs_firstdesc = sc->sc_txnext; 1311 txs->txs_ndesc = dmamap->dm_nsegs; 1312 1313 /* 1314 * Set up checksum offload parameters for 1315 * this packet. 1316 */ 1317 if (m0->m_pkthdr.csum_flags & 1318 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1319 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1320 /* Error message already displayed. */ 1321 bus_dmamap_unload(sc->sc_dmat, dmamap); 1322 continue; 1323 } 1324 } else { 1325 cksumfields = 0; 1326 } 1327 1328 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1329 1330 /* 1331 * Initialize the transmit descriptor. 1332 */ 1333 for (nexttx = sc->sc_txnext, seg = 0; 1334 seg < dmamap->dm_nsegs; 1335 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1336 /* 1337 * Note: we currently only use 32-bit DMA 1338 * addresses. 1339 */ 1340 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1341 sc->sc_txdescs[nexttx].dt_baddrl = 1342 htole32(dmamap->dm_segs[seg].ds_addr); 1343 sc->sc_txdescs[nexttx].dt_ctl = 1344 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1345 sc->sc_txdescs[nexttx].dt_status = 0; 1346 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1347 sc->sc_txdescs[nexttx].dt_vlan = 0; 1348 lasttx = nexttx; 1349 1350 DPRINTF(DGE_DEBUG_TX, 1351 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1352 device_xname(sc->sc_dev), nexttx, 1353 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_addr), 1354 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_len))); 1355 } 1356 1357 KASSERT(lasttx != -1); 1358 1359 /* 1360 * Set up the command byte on the last descriptor of 1361 * the packet. If we're in the interrupt delay window, 1362 * delay the interrupt. 1363 */ 1364 sc->sc_txdescs[lasttx].dt_ctl |= 1365 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1366 1367 txs->txs_lastdesc = lasttx; 1368 1369 DPRINTF(DGE_DEBUG_TX, 1370 ("%s: TX: desc %d: cmdlen 0x%08x\n", device_xname(sc->sc_dev), 1371 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1372 1373 /* Sync the descriptors we're using. */ 1374 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1375 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1376 1377 /* Give the packet to the chip. */ 1378 CSR_WRITE(sc, DGE_TDT, nexttx); 1379 1380 DPRINTF(DGE_DEBUG_TX, 1381 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 1382 1383 DPRINTF(DGE_DEBUG_TX, 1384 ("%s: TX: finished transmitting packet, job %d\n", 1385 device_xname(sc->sc_dev), sc->sc_txsnext)); 1386 1387 /* Advance the tx pointer. */ 1388 sc->sc_txfree -= txs->txs_ndesc; 1389 sc->sc_txnext = nexttx; 1390 1391 sc->sc_txsfree--; 1392 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1393 1394 /* Pass the packet to any BPF listeners. */ 1395 bpf_mtap(ifp, m0, BPF_D_OUT); 1396 } 1397 1398 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1399 /* No more slots; notify upper layer. */ 1400 ifp->if_flags |= IFF_OACTIVE; 1401 } 1402 1403 if (sc->sc_txfree != ofree) { 1404 /* Set a watchdog timer in case the chip flakes out. */ 1405 ifp->if_timer = 5; 1406 } 1407 } 1408 1409 /* 1410 * dge_watchdog: [ifnet interface function] 1411 * 1412 * Watchdog timer handler. 1413 */ 1414 static void 1415 dge_watchdog(struct ifnet *ifp) 1416 { 1417 struct dge_softc *sc = ifp->if_softc; 1418 1419 /* 1420 * Since we're using delayed interrupts, sweep up 1421 * before we report an error. 1422 */ 1423 dge_txintr(sc); 1424 1425 if (sc->sc_txfree != DGE_NTXDESC) { 1426 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1427 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, 1428 sc->sc_txnext); 1429 ifp->if_oerrors++; 1430 1431 /* Reset the interface. */ 1432 (void) dge_init(ifp); 1433 } 1434 1435 /* Try to get more packets going. */ 1436 dge_start(ifp); 1437 } 1438 1439 /* 1440 * dge_ioctl: [ifnet interface function] 1441 * 1442 * Handle control requests from the operator. 1443 */ 1444 static int 1445 dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1446 { 1447 struct dge_softc *sc = ifp->if_softc; 1448 struct ifreq *ifr = (struct ifreq *) data; 1449 pcireg_t preg; 1450 int s, error, mmrbc; 1451 1452 s = splnet(); 1453 1454 switch (cmd) { 1455 case SIOCSIFMEDIA: 1456 case SIOCGIFMEDIA: 1457 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1458 break; 1459 1460 case SIOCSIFMTU: 1461 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) 1462 error = EINVAL; 1463 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1464 break; 1465 else if (ifp->if_flags & IFF_UP) 1466 error = (*ifp->if_init)(ifp); 1467 else 1468 error = 0; 1469 break; 1470 1471 case SIOCSIFFLAGS: 1472 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1473 break; 1474 /* extract link flags */ 1475 if ((ifp->if_flags & IFF_LINK0) == 0 && 1476 (ifp->if_flags & IFF_LINK1) == 0) 1477 mmrbc = PCIX_MMRBC_512; 1478 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1479 (ifp->if_flags & IFF_LINK1) != 0) 1480 mmrbc = PCIX_MMRBC_1024; 1481 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1482 (ifp->if_flags & IFF_LINK1) == 0) 1483 mmrbc = PCIX_MMRBC_2048; 1484 else 1485 mmrbc = PCIX_MMRBC_4096; 1486 if (mmrbc != sc->sc_mmrbc) { 1487 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1488 preg &= ~PCIX_MMRBC_MSK; 1489 preg |= mmrbc; 1490 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1491 sc->sc_mmrbc = mmrbc; 1492 } 1493 /* FALLTHROUGH */ 1494 default: 1495 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1496 break; 1497 1498 error = 0; 1499 1500 if (cmd == SIOCSIFCAP) 1501 error = (*ifp->if_init)(ifp); 1502 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1503 ; 1504 else if (ifp->if_flags & IFF_RUNNING) { 1505 /* 1506 * Multicast list has changed; set the hardware filter 1507 * accordingly. 1508 */ 1509 dge_set_filter(sc); 1510 } 1511 break; 1512 } 1513 1514 /* Try to get more packets going. */ 1515 dge_start(ifp); 1516 1517 splx(s); 1518 return (error); 1519 } 1520 1521 /* 1522 * dge_intr: 1523 * 1524 * Interrupt service routine. 1525 */ 1526 static int 1527 dge_intr(void *arg) 1528 { 1529 struct dge_softc *sc = arg; 1530 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1531 uint32_t icr; 1532 int wantinit, handled = 0; 1533 1534 for (wantinit = 0; wantinit == 0;) { 1535 icr = CSR_READ(sc, DGE_ICR); 1536 if ((icr & sc->sc_icr) == 0) 1537 break; 1538 1539 rnd_add_uint32(&sc->rnd_source, icr); 1540 1541 handled = 1; 1542 1543 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1544 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1545 DPRINTF(DGE_DEBUG_RX, 1546 ("%s: RX: got Rx intr 0x%08x\n", 1547 device_xname(sc->sc_dev), 1548 icr & (ICR_RXDMT0|ICR_RXT0))); 1549 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1550 } 1551 #endif 1552 dge_rxintr(sc); 1553 1554 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1555 if (icr & ICR_TXDW) { 1556 DPRINTF(DGE_DEBUG_TX, 1557 ("%s: TX: got TXDW interrupt\n", 1558 device_xname(sc->sc_dev))); 1559 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1560 } 1561 if (icr & ICR_TXQE) 1562 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1563 #endif 1564 dge_txintr(sc); 1565 1566 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1567 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1568 dge_linkintr(sc, icr); 1569 } 1570 1571 if (icr & ICR_RXO) { 1572 printf("%s: Receive overrun\n", device_xname(sc->sc_dev)); 1573 wantinit = 1; 1574 } 1575 } 1576 1577 if (handled) { 1578 if (wantinit) 1579 dge_init(ifp); 1580 1581 /* Try to get more packets going. */ 1582 if_schedule_deferred_start(ifp); 1583 } 1584 1585 return (handled); 1586 } 1587 1588 /* 1589 * dge_txintr: 1590 * 1591 * Helper; handle transmit interrupts. 1592 */ 1593 static void 1594 dge_txintr(struct dge_softc *sc) 1595 { 1596 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1597 struct dge_txsoft *txs; 1598 uint8_t status; 1599 int i; 1600 1601 ifp->if_flags &= ~IFF_OACTIVE; 1602 1603 /* 1604 * Go through the Tx list and free mbufs for those 1605 * frames which have been transmitted. 1606 */ 1607 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1608 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1609 txs = &sc->sc_txsoft[i]; 1610 1611 DPRINTF(DGE_DEBUG_TX, 1612 ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i)); 1613 1614 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1615 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1616 1617 status = 1618 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1619 if ((status & TDESC_STA_DD) == 0) { 1620 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1621 BUS_DMASYNC_PREREAD); 1622 break; 1623 } 1624 1625 DPRINTF(DGE_DEBUG_TX, 1626 ("%s: TX: job %d done: descs %d..%d\n", 1627 device_xname(sc->sc_dev), i, txs->txs_firstdesc, 1628 txs->txs_lastdesc)); 1629 1630 ifp->if_opackets++; 1631 sc->sc_txfree += txs->txs_ndesc; 1632 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1633 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1634 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1635 m_freem(txs->txs_mbuf); 1636 txs->txs_mbuf = NULL; 1637 } 1638 1639 /* Update the dirty transmit buffer pointer. */ 1640 sc->sc_txsdirty = i; 1641 DPRINTF(DGE_DEBUG_TX, 1642 ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i)); 1643 1644 /* 1645 * If there are no more pending transmissions, cancel the watchdog 1646 * timer. 1647 */ 1648 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1649 ifp->if_timer = 0; 1650 } 1651 1652 /* 1653 * dge_rxintr: 1654 * 1655 * Helper; handle receive interrupts. 1656 */ 1657 static void 1658 dge_rxintr(struct dge_softc *sc) 1659 { 1660 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1661 struct dge_rxsoft *rxs; 1662 struct mbuf *m; 1663 int i, len; 1664 uint8_t status, errors; 1665 1666 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1667 rxs = &sc->sc_rxsoft[i]; 1668 1669 DPRINTF(DGE_DEBUG_RX, 1670 ("%s: RX: checking descriptor %d\n", 1671 device_xname(sc->sc_dev), i)); 1672 1673 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1674 1675 status = sc->sc_rxdescs[i].dr_status; 1676 errors = sc->sc_rxdescs[i].dr_errors; 1677 len = le16toh(sc->sc_rxdescs[i].dr_len); 1678 1679 if ((status & RDESC_STS_DD) == 0) { 1680 /* 1681 * We have processed all of the receive descriptors. 1682 */ 1683 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1684 break; 1685 } 1686 1687 if (__predict_false(sc->sc_rxdiscard)) { 1688 DPRINTF(DGE_DEBUG_RX, 1689 ("%s: RX: discarding contents of descriptor %d\n", 1690 device_xname(sc->sc_dev), i)); 1691 DGE_INIT_RXDESC(sc, i); 1692 if (status & RDESC_STS_EOP) { 1693 /* Reset our state. */ 1694 DPRINTF(DGE_DEBUG_RX, 1695 ("%s: RX: resetting rxdiscard -> 0\n", 1696 device_xname(sc->sc_dev))); 1697 sc->sc_rxdiscard = 0; 1698 } 1699 continue; 1700 } 1701 1702 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1703 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1704 1705 m = rxs->rxs_mbuf; 1706 1707 /* 1708 * Add a new receive buffer to the ring. 1709 */ 1710 if (dge_add_rxbuf(sc, i) != 0) { 1711 /* 1712 * Failed, throw away what we've done so 1713 * far, and discard the rest of the packet. 1714 */ 1715 ifp->if_ierrors++; 1716 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1717 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1718 DGE_INIT_RXDESC(sc, i); 1719 if ((status & RDESC_STS_EOP) == 0) 1720 sc->sc_rxdiscard = 1; 1721 if (sc->sc_rxhead != NULL) 1722 m_freem(sc->sc_rxhead); 1723 DGE_RXCHAIN_RESET(sc); 1724 DPRINTF(DGE_DEBUG_RX, 1725 ("%s: RX: Rx buffer allocation failed, " 1726 "dropping packet%s\n", device_xname(sc->sc_dev), 1727 sc->sc_rxdiscard ? " (discard)" : "")); 1728 continue; 1729 } 1730 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1731 1732 DGE_RXCHAIN_LINK(sc, m); 1733 1734 m->m_len = len; 1735 1736 DPRINTF(DGE_DEBUG_RX, 1737 ("%s: RX: buffer at %p len %d\n", 1738 device_xname(sc->sc_dev), m->m_data, len)); 1739 1740 /* 1741 * If this is not the end of the packet, keep 1742 * looking. 1743 */ 1744 if ((status & RDESC_STS_EOP) == 0) { 1745 sc->sc_rxlen += len; 1746 DPRINTF(DGE_DEBUG_RX, 1747 ("%s: RX: not yet EOP, rxlen -> %d\n", 1748 device_xname(sc->sc_dev), sc->sc_rxlen)); 1749 continue; 1750 } 1751 1752 /* 1753 * Okay, we have the entire packet now... 1754 */ 1755 *sc->sc_rxtailp = NULL; 1756 m = sc->sc_rxhead; 1757 len += sc->sc_rxlen; 1758 1759 DGE_RXCHAIN_RESET(sc); 1760 1761 DPRINTF(DGE_DEBUG_RX, 1762 ("%s: RX: have entire packet, len -> %d\n", 1763 device_xname(sc->sc_dev), len)); 1764 1765 /* 1766 * If an error occurred, update stats and drop the packet. 1767 */ 1768 if (errors & 1769 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1770 ifp->if_ierrors++; 1771 if (errors & RDESC_ERR_SE) 1772 printf("%s: symbol error\n", 1773 device_xname(sc->sc_dev)); 1774 else if (errors & RDESC_ERR_P) 1775 printf("%s: parity error\n", 1776 device_xname(sc->sc_dev)); 1777 else if (errors & RDESC_ERR_CE) 1778 printf("%s: CRC error\n", 1779 device_xname(sc->sc_dev)); 1780 m_freem(m); 1781 continue; 1782 } 1783 1784 /* 1785 * No errors. Receive the packet. 1786 */ 1787 m_set_rcvif(m, ifp); 1788 m->m_pkthdr.len = len; 1789 1790 /* 1791 * Set up checksum info for this packet. 1792 */ 1793 if (status & RDESC_STS_IPCS) { 1794 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1795 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1796 if (errors & RDESC_ERR_IPE) 1797 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1798 } 1799 if (status & RDESC_STS_TCPCS) { 1800 /* 1801 * Note: we don't know if this was TCP or UDP, 1802 * so we just set both bits, and expect the 1803 * upper layers to deal. 1804 */ 1805 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1806 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1807 if (errors & RDESC_ERR_TCPE) 1808 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1809 } 1810 1811 /* Pass it on. */ 1812 if_percpuq_enqueue(ifp->if_percpuq, m); 1813 } 1814 1815 /* Update the receive pointer. */ 1816 sc->sc_rxptr = i; 1817 1818 DPRINTF(DGE_DEBUG_RX, 1819 ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i)); 1820 } 1821 1822 /* 1823 * dge_linkintr: 1824 * 1825 * Helper; handle link interrupts. 1826 */ 1827 static void 1828 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1829 { 1830 uint32_t status; 1831 1832 if (icr & ICR_LSC) { 1833 status = CSR_READ(sc, DGE_STATUS); 1834 if (status & STATUS_LINKUP) { 1835 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1836 device_xname(sc->sc_dev))); 1837 } else { 1838 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1839 device_xname(sc->sc_dev))); 1840 } 1841 } else if (icr & ICR_RXSEQ) { 1842 DPRINTF(DGE_DEBUG_LINK, 1843 ("%s: LINK: Receive sequence error\n", 1844 device_xname(sc->sc_dev))); 1845 } 1846 /* XXX - fix errata */ 1847 } 1848 1849 /* 1850 * dge_reset: 1851 * 1852 * Reset the i82597 chip. 1853 */ 1854 static void 1855 dge_reset(struct dge_softc *sc) 1856 { 1857 int i; 1858 1859 /* 1860 * Do a chip reset. 1861 */ 1862 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1863 1864 delay(10000); 1865 1866 for (i = 0; i < 1000; i++) { 1867 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1868 break; 1869 delay(20); 1870 } 1871 1872 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1873 printf("%s: WARNING: reset failed to complete\n", 1874 device_xname(sc->sc_dev)); 1875 /* 1876 * Reset the EEPROM logic. 1877 * This will cause the chip to reread its default values, 1878 * which doesn't happen otherwise (errata). 1879 */ 1880 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1881 delay(10000); 1882 } 1883 1884 /* 1885 * dge_init: [ifnet interface function] 1886 * 1887 * Initialize the interface. Must be called at splnet(). 1888 */ 1889 static int 1890 dge_init(struct ifnet *ifp) 1891 { 1892 struct dge_softc *sc = ifp->if_softc; 1893 struct dge_rxsoft *rxs; 1894 int i, error = 0; 1895 uint32_t reg; 1896 1897 /* 1898 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1899 * There is a small but measurable benefit to avoiding the adjusment 1900 * of the descriptor so that the headers are aligned, for normal mtu, 1901 * on such platforms. One possibility is that the DMA itself is 1902 * slightly more efficient if the front of the entire packet (instead 1903 * of the front of the headers) is aligned. 1904 * 1905 * Note we must always set align_tweak to 0 if we are using 1906 * jumbo frames. 1907 */ 1908 #ifdef __NO_STRICT_ALIGNMENT 1909 sc->sc_align_tweak = 0; 1910 #else 1911 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1912 sc->sc_align_tweak = 0; 1913 else 1914 sc->sc_align_tweak = 2; 1915 #endif /* __NO_STRICT_ALIGNMENT */ 1916 1917 /* Cancel any pending I/O. */ 1918 dge_stop(ifp, 0); 1919 1920 /* Reset the chip to a known state. */ 1921 dge_reset(sc); 1922 1923 /* Initialize the transmit descriptor ring. */ 1924 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1925 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1926 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1927 sc->sc_txfree = DGE_NTXDESC; 1928 sc->sc_txnext = 0; 1929 1930 sc->sc_txctx_ipcs = 0xffffffff; 1931 sc->sc_txctx_tucs = 0xffffffff; 1932 1933 CSR_WRITE(sc, DGE_TDBAH, 0); 1934 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1935 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1936 CSR_WRITE(sc, DGE_TDH, 0); 1937 CSR_WRITE(sc, DGE_TDT, 0); 1938 CSR_WRITE(sc, DGE_TIDV, TIDV); 1939 1940 #if 0 1941 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1942 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1943 #endif 1944 CSR_WRITE(sc, DGE_RXDCTL, 1945 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1946 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1947 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1948 1949 /* Initialize the transmit job descriptors. */ 1950 for (i = 0; i < DGE_TXQUEUELEN; i++) 1951 sc->sc_txsoft[i].txs_mbuf = NULL; 1952 sc->sc_txsfree = DGE_TXQUEUELEN; 1953 sc->sc_txsnext = 0; 1954 sc->sc_txsdirty = 0; 1955 1956 /* 1957 * Initialize the receive descriptor and receive job 1958 * descriptor rings. 1959 */ 1960 CSR_WRITE(sc, DGE_RDBAH, 0); 1961 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1962 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1963 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1964 CSR_WRITE(sc, DGE_RDT, 0); 1965 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1966 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1967 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1968 1969 for (i = 0; i < DGE_NRXDESC; i++) { 1970 rxs = &sc->sc_rxsoft[i]; 1971 if (rxs->rxs_mbuf == NULL) { 1972 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1973 printf("%s: unable to allocate or map rx " 1974 "buffer %d, error = %d\n", 1975 device_xname(sc->sc_dev), i, error); 1976 /* 1977 * XXX Should attempt to run with fewer receive 1978 * XXX buffers instead of just failing. 1979 */ 1980 dge_rxdrain(sc); 1981 goto out; 1982 } 1983 } 1984 DGE_INIT_RXDESC(sc, i); 1985 } 1986 sc->sc_rxptr = DGE_RXSPACE; 1987 sc->sc_rxdiscard = 0; 1988 DGE_RXCHAIN_RESET(sc); 1989 1990 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1991 sc->sc_ctrl0 |= CTRL0_JFE; 1992 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1993 } 1994 1995 /* Write the control registers. */ 1996 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1997 1998 /* 1999 * Set up checksum offload parameters. 2000 */ 2001 reg = CSR_READ(sc, DGE_RXCSUM); 2002 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2003 reg |= RXCSUM_IPOFL; 2004 else 2005 reg &= ~RXCSUM_IPOFL; 2006 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2007 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2008 else { 2009 reg &= ~RXCSUM_TUOFL; 2010 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2011 reg &= ~RXCSUM_IPOFL; 2012 } 2013 CSR_WRITE(sc, DGE_RXCSUM, reg); 2014 2015 /* 2016 * Set up the interrupt registers. 2017 */ 2018 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 2019 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2020 ICR_RXO | ICR_RXT0; 2021 2022 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 2023 2024 /* 2025 * Set up the transmit control register. 2026 */ 2027 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 2028 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 2029 2030 /* 2031 * Set up the receive control register; we actually program 2032 * the register when we set the receive filter. Use multicast 2033 * address offset type 0. 2034 */ 2035 sc->sc_mchash_type = 0; 2036 2037 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2038 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2039 2040 #ifdef DGE_OFFBYONE_RXBUG 2041 sc->sc_rctl |= RCTL_BSIZE_16k; 2042 #else 2043 switch(MCLBYTES) { 2044 case 2048: 2045 sc->sc_rctl |= RCTL_BSIZE_2k; 2046 break; 2047 case 4096: 2048 sc->sc_rctl |= RCTL_BSIZE_4k; 2049 break; 2050 case 8192: 2051 sc->sc_rctl |= RCTL_BSIZE_8k; 2052 break; 2053 case 16384: 2054 sc->sc_rctl |= RCTL_BSIZE_16k; 2055 break; 2056 default: 2057 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2058 } 2059 #endif 2060 2061 /* Set the receive filter. */ 2062 /* Also sets RCTL */ 2063 dge_set_filter(sc); 2064 2065 /* ...all done! */ 2066 ifp->if_flags |= IFF_RUNNING; 2067 ifp->if_flags &= ~IFF_OACTIVE; 2068 2069 out: 2070 if (error) 2071 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2072 return (error); 2073 } 2074 2075 /* 2076 * dge_rxdrain: 2077 * 2078 * Drain the receive queue. 2079 */ 2080 static void 2081 dge_rxdrain(struct dge_softc *sc) 2082 { 2083 struct dge_rxsoft *rxs; 2084 int i; 2085 2086 for (i = 0; i < DGE_NRXDESC; i++) { 2087 rxs = &sc->sc_rxsoft[i]; 2088 if (rxs->rxs_mbuf != NULL) { 2089 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2090 m_freem(rxs->rxs_mbuf); 2091 rxs->rxs_mbuf = NULL; 2092 } 2093 } 2094 } 2095 2096 /* 2097 * dge_stop: [ifnet interface function] 2098 * 2099 * Stop transmission on the interface. 2100 */ 2101 static void 2102 dge_stop(struct ifnet *ifp, int disable) 2103 { 2104 struct dge_softc *sc = ifp->if_softc; 2105 struct dge_txsoft *txs; 2106 int i; 2107 2108 /* Stop the transmit and receive processes. */ 2109 CSR_WRITE(sc, DGE_TCTL, 0); 2110 CSR_WRITE(sc, DGE_RCTL, 0); 2111 2112 /* Release any queued transmit buffers. */ 2113 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2114 txs = &sc->sc_txsoft[i]; 2115 if (txs->txs_mbuf != NULL) { 2116 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2117 m_freem(txs->txs_mbuf); 2118 txs->txs_mbuf = NULL; 2119 } 2120 } 2121 2122 /* Mark the interface as down and cancel the watchdog timer. */ 2123 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2124 ifp->if_timer = 0; 2125 2126 if (disable) 2127 dge_rxdrain(sc); 2128 } 2129 2130 /* 2131 * dge_add_rxbuf: 2132 * 2133 * Add a receive buffer to the indiciated descriptor. 2134 */ 2135 static int 2136 dge_add_rxbuf(struct dge_softc *sc, int idx) 2137 { 2138 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2139 struct mbuf *m; 2140 int error; 2141 #ifdef DGE_OFFBYONE_RXBUG 2142 void *buf; 2143 #endif 2144 2145 MGETHDR(m, M_DONTWAIT, MT_DATA); 2146 if (m == NULL) 2147 return (ENOBUFS); 2148 2149 #ifdef DGE_OFFBYONE_RXBUG 2150 if ((buf = dge_getbuf(sc)) == NULL) 2151 return ENOBUFS; 2152 2153 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2154 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2155 m->m_flags |= M_EXT_RW; 2156 2157 if (rxs->rxs_mbuf != NULL) 2158 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2159 rxs->rxs_mbuf = m; 2160 2161 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2162 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2163 #else 2164 MCLGET(m, M_DONTWAIT); 2165 if ((m->m_flags & M_EXT) == 0) { 2166 m_freem(m); 2167 return (ENOBUFS); 2168 } 2169 2170 if (rxs->rxs_mbuf != NULL) 2171 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2172 2173 rxs->rxs_mbuf = m; 2174 2175 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2176 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2177 BUS_DMA_READ|BUS_DMA_NOWAIT); 2178 #endif 2179 if (error) { 2180 printf("%s: unable to load rx DMA map %d, error = %d\n", 2181 device_xname(sc->sc_dev), idx, error); 2182 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2183 } 2184 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2185 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2186 2187 return (0); 2188 } 2189 2190 /* 2191 * dge_set_ral: 2192 * 2193 * Set an entry in the receive address list. 2194 */ 2195 static void 2196 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2197 { 2198 uint32_t ral_lo, ral_hi; 2199 2200 if (enaddr != NULL) { 2201 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2202 (enaddr[3] << 24); 2203 ral_hi = enaddr[4] | (enaddr[5] << 8); 2204 ral_hi |= RAH_AV; 2205 } else { 2206 ral_lo = 0; 2207 ral_hi = 0; 2208 } 2209 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2210 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2211 } 2212 2213 /* 2214 * dge_mchash: 2215 * 2216 * Compute the hash of the multicast address for the 4096-bit 2217 * multicast filter. 2218 */ 2219 static uint32_t 2220 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2221 { 2222 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2223 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2224 uint32_t hash; 2225 2226 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2227 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2228 2229 return (hash & 0xfff); 2230 } 2231 2232 /* 2233 * dge_set_filter: 2234 * 2235 * Set up the receive filter. 2236 */ 2237 static void 2238 dge_set_filter(struct dge_softc *sc) 2239 { 2240 struct ethercom *ec = &sc->sc_ethercom; 2241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2242 struct ether_multi *enm; 2243 struct ether_multistep step; 2244 uint32_t hash, reg, bit; 2245 int i; 2246 2247 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2248 2249 if (ifp->if_flags & IFF_BROADCAST) 2250 sc->sc_rctl |= RCTL_BAM; 2251 if (ifp->if_flags & IFF_PROMISC) { 2252 sc->sc_rctl |= RCTL_UPE; 2253 goto allmulti; 2254 } 2255 2256 /* 2257 * Set the station address in the first RAL slot, and 2258 * clear the remaining slots. 2259 */ 2260 dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 2261 for (i = 1; i < RA_TABSIZE; i++) 2262 dge_set_ral(sc, NULL, i); 2263 2264 /* Clear out the multicast table. */ 2265 for (i = 0; i < MC_TABSIZE; i++) 2266 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2267 2268 ETHER_FIRST_MULTI(step, ec, enm); 2269 while (enm != NULL) { 2270 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2271 /* 2272 * We must listen to a range of multicast addresses. 2273 * For now, just accept all multicasts, rather than 2274 * trying to set only those filter bits needed to match 2275 * the range. (At this time, the only use of address 2276 * ranges is for IP multicast routing, for which the 2277 * range is big enough to require all bits set.) 2278 */ 2279 goto allmulti; 2280 } 2281 2282 hash = dge_mchash(sc, enm->enm_addrlo); 2283 2284 reg = (hash >> 5) & 0x7f; 2285 bit = hash & 0x1f; 2286 2287 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2288 hash |= 1U << bit; 2289 2290 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2291 2292 ETHER_NEXT_MULTI(step, enm); 2293 } 2294 2295 ifp->if_flags &= ~IFF_ALLMULTI; 2296 goto setit; 2297 2298 allmulti: 2299 ifp->if_flags |= IFF_ALLMULTI; 2300 sc->sc_rctl |= RCTL_MPE; 2301 2302 setit: 2303 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2304 } 2305 2306 /* 2307 * Read in the EEPROM info and verify checksum. 2308 */ 2309 int 2310 dge_read_eeprom(struct dge_softc *sc) 2311 { 2312 uint16_t cksum; 2313 int i; 2314 2315 cksum = 0; 2316 for (i = 0; i < EEPROM_SIZE; i++) { 2317 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2318 cksum += sc->sc_eeprom[i]; 2319 } 2320 return cksum != EEPROM_CKSUM; 2321 } 2322 2323 2324 /* 2325 * Read a 16-bit word from address addr in the serial EEPROM. 2326 */ 2327 uint16_t 2328 dge_eeprom_word(struct dge_softc *sc, int addr) 2329 { 2330 uint32_t reg; 2331 uint16_t rval = 0; 2332 int i; 2333 2334 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2335 2336 /* Lower clock pulse (and data in to chip) */ 2337 CSR_WRITE(sc, DGE_EECD, reg); 2338 /* Select chip */ 2339 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2340 2341 /* Send read command */ 2342 dge_eeprom_clockout(sc, 1); 2343 dge_eeprom_clockout(sc, 1); 2344 dge_eeprom_clockout(sc, 0); 2345 2346 /* Send address */ 2347 for (i = 5; i >= 0; i--) 2348 dge_eeprom_clockout(sc, (addr >> i) & 1); 2349 2350 /* Read data */ 2351 for (i = 0; i < 16; i++) { 2352 rval <<= 1; 2353 rval |= dge_eeprom_clockin(sc); 2354 } 2355 2356 /* Deselect chip */ 2357 CSR_WRITE(sc, DGE_EECD, reg); 2358 2359 return rval; 2360 } 2361 2362 /* 2363 * Clock out a single bit to the EEPROM. 2364 */ 2365 void 2366 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2367 { 2368 int reg; 2369 2370 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2371 if (bit) 2372 reg |= EECD_DI; 2373 2374 CSR_WRITE(sc, DGE_EECD, reg); 2375 delay(2); 2376 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2377 delay(2); 2378 CSR_WRITE(sc, DGE_EECD, reg); 2379 delay(2); 2380 } 2381 2382 /* 2383 * Clock in a single bit from EEPROM. 2384 */ 2385 int 2386 dge_eeprom_clockin(struct dge_softc *sc) 2387 { 2388 int reg, rv; 2389 2390 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2391 2392 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2393 delay(2); 2394 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2395 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2396 delay(2); 2397 2398 return rv; 2399 } 2400 2401 static void 2402 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2403 { 2404 struct dge_softc *sc = ifp->if_softc; 2405 2406 ifmr->ifm_status = IFM_AVALID; 2407 if (sc->sc_dgep->dgep_flags & DGEP_F_10G_SR ) { 2408 ifmr->ifm_active = IFM_ETHER|IFM_10G_SR; 2409 } else { 2410 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2411 } 2412 2413 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2414 ifmr->ifm_status |= IFM_ACTIVE; 2415 } 2416 2417 static inline int 2418 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2419 { 2420 int i, mdic; 2421 2422 CSR_WRITE(sc, DGE_MDIO, 2423 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2424 for (i = 0; i < 10; i++) { 2425 delay(10); 2426 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2427 break; 2428 } 2429 return mdic; 2430 } 2431 2432 static void 2433 dge_xgmii_writereg(struct dge_softc *sc, int phy, int reg, int val) 2434 { 2435 int mdic; 2436 2437 CSR_WRITE(sc, DGE_MDIRW, val); 2438 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2439 printf("%s: address cycle timeout; phy %d reg %d\n", 2440 device_xname(sc->sc_dev), phy, reg); 2441 return; 2442 } 2443 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2444 printf("%s: write cycle timeout; phy %d reg %d\n", 2445 device_xname(sc->sc_dev), phy, reg); 2446 return; 2447 } 2448 } 2449 2450 static void 2451 dge_xgmii_reset(struct dge_softc *sc) 2452 { 2453 dge_xgmii_writereg(sc, 0, 0, BMCR_RESET); 2454 } 2455 2456 static int 2457 dge_xgmii_mediachange(struct ifnet *ifp) 2458 { 2459 return 0; 2460 } 2461