1 /* $NetBSD: if_dge.c,v 1.10 2005/02/27 00:27:32 perry Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.10 2005/02/27 00:27:32 perry Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <netinet/in.h> /* XXX for struct ip */ 116 #include <netinet/in_systm.h> /* XXX for struct ip */ 117 #include <netinet/ip.h> /* XXX for struct ip */ 118 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 119 120 #include <machine/bus.h> 121 #include <machine/intr.h> 122 #include <machine/endian.h> 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/mii_bitbang.h> 127 128 #include <dev/pci/pcireg.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/pcidevs.h> 131 132 #include <dev/pci/if_dgereg.h> 133 134 /* 135 * The receive engine may sometimes become off-by-one when writing back 136 * chained descriptors. Avoid this by allocating a large chunk of 137 * memory and use if instead (to avoid chained descriptors). 138 * This only happens with chained descriptors under heavy load. 139 */ 140 #define DGE_OFFBYONE_RXBUG 141 142 #define DGE_EVENT_COUNTERS 143 #define DGE_DEBUG 144 145 #ifdef DGE_DEBUG 146 #define DGE_DEBUG_LINK 0x01 147 #define DGE_DEBUG_TX 0x02 148 #define DGE_DEBUG_RX 0x04 149 #define DGE_DEBUG_CKSUM 0x08 150 int dge_debug = 0; 151 152 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 153 #else 154 #define DPRINTF(x, y) /* nothing */ 155 #endif /* DGE_DEBUG */ 156 157 /* 158 * Transmit descriptor list size. We allow up to 100 DMA segments per 159 * packet (Intel reports of jumbo frame packets with as 160 * many as 80 DMA segments when using 16k buffers). 161 */ 162 #define DGE_NTXSEGS 100 163 #define DGE_IFQUEUELEN 20000 164 #define DGE_TXQUEUELEN 2048 165 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 166 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 167 #define DGE_NTXDESC 1024 168 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 169 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 170 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 171 172 /* 173 * Receive descriptor list size. 174 * Packet is of size MCLBYTES, and for jumbo packets buffers may 175 * be chained. Due to the nature of the card (high-speed), keep this 176 * ring large. With 2k buffers the ring can store 400 jumbo packets, 177 * which at full speed will be received in just under 3ms. 178 */ 179 #define DGE_NRXDESC 2048 180 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 181 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 182 /* 183 * # of descriptors between head and written descriptors. 184 * This is to work-around two erratas. 185 */ 186 #define DGE_RXSPACE 10 187 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 188 /* 189 * Receive descriptor fetch threshholds. These are values recommended 190 * by Intel, do not touch them unless you know what you are doing. 191 */ 192 #define RXDCTL_PTHRESH_VAL 128 193 #define RXDCTL_HTHRESH_VAL 16 194 #define RXDCTL_WTHRESH_VAL 16 195 196 197 /* 198 * Tweakable parameters; default values. 199 */ 200 #define FCRTH 0x30000 /* Send XOFF water mark */ 201 #define FCRTL 0x28000 /* Send XON water mark */ 202 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 203 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 204 205 /* 206 * Control structures are DMA'd to the i82597 chip. We allocate them in 207 * a single clump that maps to a single DMA segment to make serveral things 208 * easier. 209 */ 210 struct dge_control_data { 211 /* 212 * The transmit descriptors. 213 */ 214 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 215 216 /* 217 * The receive descriptors. 218 */ 219 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 220 }; 221 222 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 223 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 224 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 225 226 /* 227 * The DGE interface have a higher max MTU size than normal jumbo frames. 228 */ 229 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 230 231 /* 232 * Software state for transmit jobs. 233 */ 234 struct dge_txsoft { 235 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 236 bus_dmamap_t txs_dmamap; /* our DMA map */ 237 int txs_firstdesc; /* first descriptor in packet */ 238 int txs_lastdesc; /* last descriptor in packet */ 239 int txs_ndesc; /* # of descriptors used */ 240 }; 241 242 /* 243 * Software state for receive buffers. Each descriptor gets a 244 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 245 * more than one buffer, we chain them together. 246 */ 247 struct dge_rxsoft { 248 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 249 bus_dmamap_t rxs_dmamap; /* our DMA map */ 250 }; 251 252 /* 253 * Software state per device. 254 */ 255 struct dge_softc { 256 struct device sc_dev; /* generic device information */ 257 bus_space_tag_t sc_st; /* bus space tag */ 258 bus_space_handle_t sc_sh; /* bus space handle */ 259 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 260 struct ethercom sc_ethercom; /* ethernet common data */ 261 void *sc_sdhook; /* shutdown hook */ 262 263 int sc_flags; /* flags; see below */ 264 int sc_bus_speed; /* PCI/PCIX bus speed */ 265 int sc_pcix_offset; /* PCIX capability register offset */ 266 267 pci_chipset_tag_t sc_pc; 268 pcitag_t sc_pt; 269 int sc_mmrbc; /* Max PCIX memory read byte count */ 270 271 void *sc_ih; /* interrupt cookie */ 272 273 struct ifmedia sc_media; 274 275 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 276 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 277 278 int sc_align_tweak; 279 280 /* 281 * Software state for the transmit and receive descriptors. 282 */ 283 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 284 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 285 286 /* 287 * Control data structures. 288 */ 289 struct dge_control_data *sc_control_data; 290 #define sc_txdescs sc_control_data->wcd_txdescs 291 #define sc_rxdescs sc_control_data->wcd_rxdescs 292 293 #ifdef DGE_EVENT_COUNTERS 294 /* Event counters. */ 295 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 296 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 297 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 298 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 299 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 300 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 301 struct evcnt sc_ev_linkintr; /* Link interrupts */ 302 303 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 304 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 305 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 306 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 307 308 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 309 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 310 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 311 312 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 313 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 314 #endif /* DGE_EVENT_COUNTERS */ 315 316 int sc_txfree; /* number of free Tx descriptors */ 317 int sc_txnext; /* next ready Tx descriptor */ 318 319 int sc_txsfree; /* number of free Tx jobs */ 320 int sc_txsnext; /* next free Tx job */ 321 int sc_txsdirty; /* dirty Tx jobs */ 322 323 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 324 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 325 326 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 327 int sc_rxdiscard; 328 int sc_rxlen; 329 struct mbuf *sc_rxhead; 330 struct mbuf *sc_rxtail; 331 struct mbuf **sc_rxtailp; 332 333 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 334 uint32_t sc_icr; /* prototype interrupt bits */ 335 uint32_t sc_tctl; /* prototype TCTL register */ 336 uint32_t sc_rctl; /* prototype RCTL register */ 337 338 int sc_mchash_type; /* multicast filter offset */ 339 340 uint16_t sc_eeprom[EEPROM_SIZE]; 341 342 #if NRND > 0 343 rndsource_element_t rnd_source; /* random source */ 344 #endif 345 #ifdef DGE_OFFBYONE_RXBUG 346 caddr_t sc_bugbuf; 347 SLIST_HEAD(, rxbugentry) sc_buglist; 348 bus_dmamap_t sc_bugmap; 349 struct rxbugentry *sc_entry; 350 #endif 351 }; 352 353 #define DGE_RXCHAIN_RESET(sc) \ 354 do { \ 355 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 356 *(sc)->sc_rxtailp = NULL; \ 357 (sc)->sc_rxlen = 0; \ 358 } while (/*CONSTCOND*/0) 359 360 #define DGE_RXCHAIN_LINK(sc, m) \ 361 do { \ 362 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 363 (sc)->sc_rxtailp = &(m)->m_next; \ 364 } while (/*CONSTCOND*/0) 365 366 /* sc_flags */ 367 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 368 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 369 370 #ifdef DGE_EVENT_COUNTERS 371 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 372 #else 373 #define DGE_EVCNT_INCR(ev) /* nothing */ 374 #endif 375 376 #define CSR_READ(sc, reg) \ 377 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 378 #define CSR_WRITE(sc, reg, val) \ 379 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 380 381 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 382 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 383 384 #define DGE_CDTXSYNC(sc, x, n, ops) \ 385 do { \ 386 int __x, __n; \ 387 \ 388 __x = (x); \ 389 __n = (n); \ 390 \ 391 /* If it will wrap around, sync to the end of the ring. */ \ 392 if ((__x + __n) > DGE_NTXDESC) { \ 393 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 394 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 395 (DGE_NTXDESC - __x), (ops)); \ 396 __n -= (DGE_NTXDESC - __x); \ 397 __x = 0; \ 398 } \ 399 \ 400 /* Now sync whatever is left. */ \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 403 } while (/*CONSTCOND*/0) 404 405 #define DGE_CDRXSYNC(sc, x, ops) \ 406 do { \ 407 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 408 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 409 } while (/*CONSTCOND*/0) 410 411 #ifdef DGE_OFFBYONE_RXBUG 412 #define DGE_INIT_RXDESC(sc, x) \ 413 do { \ 414 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 415 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 416 struct mbuf *__m = __rxs->rxs_mbuf; \ 417 \ 418 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 419 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 420 __rxd->dr_baddrh = 0; \ 421 __rxd->dr_len = 0; \ 422 __rxd->dr_cksum = 0; \ 423 __rxd->dr_status = 0; \ 424 __rxd->dr_errors = 0; \ 425 __rxd->dr_special = 0; \ 426 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 427 \ 428 CSR_WRITE((sc), DGE_RDT, (x)); \ 429 } while (/*CONSTCOND*/0) 430 #else 431 #define DGE_INIT_RXDESC(sc, x) \ 432 do { \ 433 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 434 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 435 struct mbuf *__m = __rxs->rxs_mbuf; \ 436 \ 437 /* \ 438 * Note: We scoot the packet forward 2 bytes in the buffer \ 439 * so that the payload after the Ethernet header is aligned \ 440 * to a 4-byte boundary. \ 441 * \ 442 * XXX BRAINDAMAGE ALERT! \ 443 * The stupid chip uses the same size for every buffer, which \ 444 * is set in the Receive Control register. We are using the 2K \ 445 * size option, but what we REALLY want is (2K - 2)! For this \ 446 * reason, we can't "scoot" packets longer than the standard \ 447 * Ethernet MTU. On strict-alignment platforms, if the total \ 448 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 449 * the upper layer copy the headers. \ 450 */ \ 451 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 452 \ 453 __rxd->dr_baddrl = \ 454 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 455 (sc)->sc_align_tweak); \ 456 __rxd->dr_baddrh = 0; \ 457 __rxd->dr_len = 0; \ 458 __rxd->dr_cksum = 0; \ 459 __rxd->dr_status = 0; \ 460 __rxd->dr_errors = 0; \ 461 __rxd->dr_special = 0; \ 462 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 463 \ 464 CSR_WRITE((sc), DGE_RDT, (x)); \ 465 } while (/*CONSTCOND*/0) 466 #endif 467 468 #ifdef DGE_OFFBYONE_RXBUG 469 /* 470 * Allocation constants. Much memory may be used for this. 471 */ 472 #ifndef DGE_BUFFER_SIZE 473 #define DGE_BUFFER_SIZE DGE_MAX_MTU 474 #endif 475 #define DGE_NBUFFERS (4*DGE_NRXDESC) 476 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 477 478 struct rxbugentry { 479 SLIST_ENTRY(rxbugentry) rb_entry; 480 int rb_slot; 481 }; 482 483 static int 484 dge_alloc_rcvmem(struct dge_softc *sc) 485 { 486 caddr_t ptr, kva; 487 bus_dma_segment_t seg; 488 int i, rseg, state, error; 489 struct rxbugentry *entry; 490 491 state = error = 0; 492 493 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 494 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 495 printf("%s: can't alloc rx buffers\n", sc->sc_dev.dv_xname); 496 return ENOBUFS; 497 } 498 499 state = 1; 500 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, &kva, 501 BUS_DMA_NOWAIT)) { 502 printf("%s: can't map DMA buffers (%d bytes)\n", 503 sc->sc_dev.dv_xname, (int)DGE_RXMEM); 504 error = ENOBUFS; 505 goto out; 506 } 507 508 state = 2; 509 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 510 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 511 printf("%s: can't create DMA map\n", sc->sc_dev.dv_xname); 512 error = ENOBUFS; 513 goto out; 514 } 515 516 state = 3; 517 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 518 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 519 printf("%s: can't load DMA map\n", sc->sc_dev.dv_xname); 520 error = ENOBUFS; 521 goto out; 522 } 523 524 state = 4; 525 sc->sc_bugbuf = (caddr_t)kva; 526 SLIST_INIT(&sc->sc_buglist); 527 528 /* 529 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 530 * in an array. 531 */ 532 ptr = sc->sc_bugbuf; 533 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 534 M_DEVBUF, M_NOWAIT)) == NULL) { 535 error = ENOBUFS; 536 goto out; 537 } 538 sc->sc_entry = entry; 539 for (i = 0; i < DGE_NBUFFERS; i++) { 540 entry[i].rb_slot = i; 541 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 542 } 543 out: 544 if (error != 0) { 545 switch (state) { 546 case 4: 547 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 548 case 3: 549 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 550 case 2: 551 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 552 case 1: 553 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 554 break; 555 default: 556 break; 557 } 558 } 559 560 return error; 561 } 562 563 /* 564 * Allocate a jumbo buffer. 565 */ 566 static void * 567 dge_getbuf(struct dge_softc *sc) 568 { 569 struct rxbugentry *entry; 570 571 entry = SLIST_FIRST(&sc->sc_buglist); 572 573 if (entry == NULL) { 574 printf("%s: no free RX buffers\n", sc->sc_dev.dv_xname); 575 return(NULL); 576 } 577 578 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 579 return sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 580 } 581 582 /* 583 * Release a jumbo buffer. 584 */ 585 static void 586 dge_freebuf(struct mbuf *m, caddr_t buf, size_t size, void *arg) 587 { 588 struct rxbugentry *entry; 589 struct dge_softc *sc; 590 int i, s; 591 592 /* Extract the softc struct pointer. */ 593 sc = (struct dge_softc *)arg; 594 595 if (sc == NULL) 596 panic("dge_freebuf: can't find softc pointer!"); 597 598 /* calculate the slot this buffer belongs to */ 599 600 i = (buf - sc->sc_bugbuf) / DGE_BUFFER_SIZE; 601 602 if ((i < 0) || (i >= DGE_NBUFFERS)) 603 panic("dge_freebuf: asked to free buffer %d!", i); 604 605 s = splvm(); 606 entry = sc->sc_entry + i; 607 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 608 609 if (__predict_true(m != NULL)) 610 pool_cache_put(&mbpool_cache, m); 611 splx(s); 612 } 613 #endif 614 615 static void dge_start(struct ifnet *); 616 static void dge_watchdog(struct ifnet *); 617 static int dge_ioctl(struct ifnet *, u_long, caddr_t); 618 static int dge_init(struct ifnet *); 619 static void dge_stop(struct ifnet *, int); 620 621 static void dge_shutdown(void *); 622 623 static void dge_reset(struct dge_softc *); 624 static void dge_rxdrain(struct dge_softc *); 625 static int dge_add_rxbuf(struct dge_softc *, int); 626 627 static void dge_set_filter(struct dge_softc *); 628 629 static int dge_intr(void *); 630 static void dge_txintr(struct dge_softc *); 631 static void dge_rxintr(struct dge_softc *); 632 static void dge_linkintr(struct dge_softc *, uint32_t); 633 634 static int dge_match(struct device *, struct cfdata *, void *); 635 static void dge_attach(struct device *, struct device *, void *); 636 637 static int dge_read_eeprom(struct dge_softc *sc); 638 static int dge_eeprom_clockin(struct dge_softc *sc); 639 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 640 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 641 static int dge_xgmii_mediachange(struct ifnet *); 642 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 643 static void dge_xgmii_reset(struct dge_softc *); 644 static void dge_xgmii_writereg(struct device *, int, int, int); 645 646 647 CFATTACH_DECL(dge, sizeof(struct dge_softc), 648 dge_match, dge_attach, NULL, NULL); 649 650 #ifdef DGE_EVENT_COUNTERS 651 #if DGE_NTXSEGS > 100 652 #error Update dge_txseg_evcnt_names 653 #endif 654 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 655 #endif /* DGE_EVENT_COUNTERS */ 656 657 static int 658 dge_match(struct device *parent, struct cfdata *cf, void *aux) 659 { 660 struct pci_attach_args *pa = aux; 661 662 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 663 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82597EX) 664 return (1); 665 666 return (0); 667 } 668 669 static void 670 dge_attach(struct device *parent, struct device *self, void *aux) 671 { 672 struct dge_softc *sc = (void *) self; 673 struct pci_attach_args *pa = aux; 674 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 675 pci_chipset_tag_t pc = pa->pa_pc; 676 pci_intr_handle_t ih; 677 const char *intrstr = NULL; 678 bus_dma_segment_t seg; 679 int i, rseg, error; 680 uint8_t enaddr[ETHER_ADDR_LEN]; 681 pcireg_t preg, memtype; 682 uint32_t reg; 683 684 sc->sc_dmat = pa->pa_dmat; 685 sc->sc_pc = pa->pa_pc; 686 sc->sc_pt = pa->pa_tag; 687 688 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 689 aprint_naive(": Ethernet controller\n"); 690 aprint_normal(": Intel i82597EX 10GbE-LR Ethernet, rev. %d\n", preg); 691 692 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 693 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 694 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 695 aprint_error("%s: unable to map device registers\n", 696 sc->sc_dev.dv_xname); 697 return; 698 } 699 700 /* Enable bus mastering */ 701 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 702 preg |= PCI_COMMAND_MASTER_ENABLE; 703 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 704 705 /* 706 * Map and establish our interrupt. 707 */ 708 if (pci_intr_map(pa, &ih)) { 709 aprint_error("%s: unable to map interrupt\n", 710 sc->sc_dev.dv_xname); 711 return; 712 } 713 intrstr = pci_intr_string(pc, ih); 714 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 715 if (sc->sc_ih == NULL) { 716 aprint_error("%s: unable to establish interrupt", 717 sc->sc_dev.dv_xname); 718 if (intrstr != NULL) 719 aprint_normal(" at %s", intrstr); 720 aprint_normal("\n"); 721 return; 722 } 723 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 724 725 /* 726 * Determine a few things about the bus we're connected to. 727 */ 728 reg = CSR_READ(sc, DGE_STATUS); 729 if (reg & STATUS_BUS64) 730 sc->sc_flags |= DGE_F_BUS64; 731 732 sc->sc_flags |= DGE_F_PCIX; 733 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 734 PCI_CAP_PCIX, 735 &sc->sc_pcix_offset, NULL) == 0) 736 aprint_error("%s: unable to find PCIX " 737 "capability\n", sc->sc_dev.dv_xname); 738 739 if (sc->sc_flags & DGE_F_PCIX) { 740 switch (reg & STATUS_PCIX_MSK) { 741 case STATUS_PCIX_66: 742 sc->sc_bus_speed = 66; 743 break; 744 case STATUS_PCIX_100: 745 sc->sc_bus_speed = 100; 746 break; 747 case STATUS_PCIX_133: 748 sc->sc_bus_speed = 133; 749 break; 750 default: 751 aprint_error( 752 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 753 sc->sc_dev.dv_xname, 754 reg & STATUS_PCIX_MSK); 755 sc->sc_bus_speed = 66; 756 } 757 } else 758 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 759 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 760 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 761 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 762 763 /* 764 * Allocate the control data structures, and create and load the 765 * DMA map for it. 766 */ 767 if ((error = bus_dmamem_alloc(sc->sc_dmat, 768 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 769 0)) != 0) { 770 aprint_error( 771 "%s: unable to allocate control data, error = %d\n", 772 sc->sc_dev.dv_xname, error); 773 goto fail_0; 774 } 775 776 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 777 sizeof(struct dge_control_data), (caddr_t *)&sc->sc_control_data, 778 0)) != 0) { 779 aprint_error("%s: unable to map control data, error = %d\n", 780 sc->sc_dev.dv_xname, error); 781 goto fail_1; 782 } 783 784 if ((error = bus_dmamap_create(sc->sc_dmat, 785 sizeof(struct dge_control_data), 1, 786 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 787 aprint_error("%s: unable to create control data DMA map, " 788 "error = %d\n", sc->sc_dev.dv_xname, error); 789 goto fail_2; 790 } 791 792 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 793 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 794 0)) != 0) { 795 aprint_error( 796 "%s: unable to load control data DMA map, error = %d\n", 797 sc->sc_dev.dv_xname, error); 798 goto fail_3; 799 } 800 801 #ifdef DGE_OFFBYONE_RXBUG 802 if (dge_alloc_rcvmem(sc) != 0) 803 return; /* Already complained */ 804 #endif 805 /* 806 * Create the transmit buffer DMA maps. 807 */ 808 for (i = 0; i < DGE_TXQUEUELEN; i++) { 809 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 810 DGE_NTXSEGS, MCLBYTES, 0, 0, 811 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 812 aprint_error("%s: unable to create Tx DMA map %d, " 813 "error = %d\n", sc->sc_dev.dv_xname, i, error); 814 goto fail_4; 815 } 816 } 817 818 /* 819 * Create the receive buffer DMA maps. 820 */ 821 for (i = 0; i < DGE_NRXDESC; i++) { 822 #ifdef DGE_OFFBYONE_RXBUG 823 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 824 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 825 #else 826 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 827 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 828 #endif 829 aprint_error("%s: unable to create Rx DMA map %d, " 830 "error = %d\n", sc->sc_dev.dv_xname, i, error); 831 goto fail_5; 832 } 833 sc->sc_rxsoft[i].rxs_mbuf = NULL; 834 } 835 836 /* 837 * Set bits in ctrl0 register. 838 * Should get the software defined pins out of EEPROM? 839 */ 840 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 841 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 842 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 843 844 /* 845 * Reset the chip to a known state. 846 */ 847 dge_reset(sc); 848 849 /* 850 * Reset the PHY. 851 */ 852 dge_xgmii_reset(sc); 853 854 /* 855 * Read in EEPROM data. 856 */ 857 if (dge_read_eeprom(sc)) { 858 aprint_error("%s: couldn't read EEPROM\n", sc->sc_dev.dv_xname); 859 return; 860 } 861 862 /* 863 * Get the ethernet address. 864 */ 865 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 866 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 867 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 868 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 869 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 870 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 871 872 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 873 ether_sprintf(enaddr)); 874 875 /* 876 * Setup media stuff. 877 */ 878 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 879 dge_xgmii_mediastatus); 880 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 881 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 882 883 ifp = &sc->sc_ethercom.ec_if; 884 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 885 ifp->if_softc = sc; 886 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 887 ifp->if_ioctl = dge_ioctl; 888 ifp->if_start = dge_start; 889 ifp->if_watchdog = dge_watchdog; 890 ifp->if_init = dge_init; 891 ifp->if_stop = dge_stop; 892 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 893 IFQ_SET_READY(&ifp->if_snd); 894 895 sc->sc_ethercom.ec_capabilities |= 896 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 897 898 /* 899 * We can perform TCPv4 and UDPv4 checkums in-bound. 900 */ 901 ifp->if_capabilities |= 902 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 903 904 /* 905 * Attach the interface. 906 */ 907 if_attach(ifp); 908 ether_ifattach(ifp, enaddr); 909 #if NRND > 0 910 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 911 RND_TYPE_NET, 0); 912 #endif 913 914 #ifdef DGE_EVENT_COUNTERS 915 /* Fix segment event naming */ 916 if (dge_txseg_evcnt_names == NULL) { 917 dge_txseg_evcnt_names = 918 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 919 for (i = 0; i < DGE_NTXSEGS; i++) 920 snprintf((*dge_txseg_evcnt_names)[i], 921 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 922 } 923 924 /* Attach event counters. */ 925 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 926 NULL, sc->sc_dev.dv_xname, "txsstall"); 927 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 928 NULL, sc->sc_dev.dv_xname, "txdstall"); 929 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 930 NULL, sc->sc_dev.dv_xname, "txforceintr"); 931 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 932 NULL, sc->sc_dev.dv_xname, "txdw"); 933 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 934 NULL, sc->sc_dev.dv_xname, "txqe"); 935 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 936 NULL, sc->sc_dev.dv_xname, "rxintr"); 937 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 938 NULL, sc->sc_dev.dv_xname, "linkintr"); 939 940 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 941 NULL, sc->sc_dev.dv_xname, "rxipsum"); 942 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 943 NULL, sc->sc_dev.dv_xname, "rxtusum"); 944 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 945 NULL, sc->sc_dev.dv_xname, "txipsum"); 946 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 947 NULL, sc->sc_dev.dv_xname, "txtusum"); 948 949 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 950 NULL, sc->sc_dev.dv_xname, "txctx init"); 951 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 952 NULL, sc->sc_dev.dv_xname, "txctx hit"); 953 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 954 NULL, sc->sc_dev.dv_xname, "txctx miss"); 955 956 for (i = 0; i < DGE_NTXSEGS; i++) 957 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 958 NULL, sc->sc_dev.dv_xname, (*dge_txseg_evcnt_names)[i]); 959 960 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 961 NULL, sc->sc_dev.dv_xname, "txdrop"); 962 963 #endif /* DGE_EVENT_COUNTERS */ 964 965 /* 966 * Make sure the interface is shutdown during reboot. 967 */ 968 sc->sc_sdhook = shutdownhook_establish(dge_shutdown, sc); 969 if (sc->sc_sdhook == NULL) 970 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 971 sc->sc_dev.dv_xname); 972 return; 973 974 /* 975 * Free any resources we've allocated during the failed attach 976 * attempt. Do this in reverse order and fall through. 977 */ 978 fail_5: 979 for (i = 0; i < DGE_NRXDESC; i++) { 980 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 981 bus_dmamap_destroy(sc->sc_dmat, 982 sc->sc_rxsoft[i].rxs_dmamap); 983 } 984 fail_4: 985 for (i = 0; i < DGE_TXQUEUELEN; i++) { 986 if (sc->sc_txsoft[i].txs_dmamap != NULL) 987 bus_dmamap_destroy(sc->sc_dmat, 988 sc->sc_txsoft[i].txs_dmamap); 989 } 990 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 991 fail_3: 992 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 993 fail_2: 994 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 995 sizeof(struct dge_control_data)); 996 fail_1: 997 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 998 fail_0: 999 return; 1000 } 1001 1002 /* 1003 * dge_shutdown: 1004 * 1005 * Make sure the interface is stopped at reboot time. 1006 */ 1007 static void 1008 dge_shutdown(void *arg) 1009 { 1010 struct dge_softc *sc = arg; 1011 1012 dge_stop(&sc->sc_ethercom.ec_if, 1); 1013 } 1014 1015 /* 1016 * dge_tx_cksum: 1017 * 1018 * Set up TCP/IP checksumming parameters for the 1019 * specified packet. 1020 */ 1021 static int 1022 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1023 { 1024 struct mbuf *m0 = txs->txs_mbuf; 1025 struct dge_ctdes *t; 1026 uint32_t ipcs, tucs; 1027 struct ether_header *eh; 1028 int offset, iphl; 1029 uint8_t fields = 0; 1030 1031 /* 1032 * XXX It would be nice if the mbuf pkthdr had offset 1033 * fields for the protocol headers. 1034 */ 1035 1036 eh = mtod(m0, struct ether_header *); 1037 switch (htons(eh->ether_type)) { 1038 case ETHERTYPE_IP: 1039 offset = ETHER_HDR_LEN; 1040 break; 1041 1042 case ETHERTYPE_VLAN: 1043 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1044 break; 1045 1046 default: 1047 /* 1048 * Don't support this protocol or encapsulation. 1049 */ 1050 *fieldsp = 0; 1051 return (0); 1052 } 1053 1054 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1055 1056 /* 1057 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1058 * offload feature, if we load the context descriptor, we 1059 * MUST provide valid values for IPCSS and TUCSS fields. 1060 */ 1061 1062 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1063 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1064 fields |= TDESC_POPTS_IXSM; 1065 ipcs = DGE_TCPIP_IPCSS(offset) | 1066 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1067 DGE_TCPIP_IPCSE(offset + iphl - 1); 1068 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1069 /* Use the cached value. */ 1070 ipcs = sc->sc_txctx_ipcs; 1071 } else { 1072 /* Just initialize it to the likely value anyway. */ 1073 ipcs = DGE_TCPIP_IPCSS(offset) | 1074 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1075 DGE_TCPIP_IPCSE(offset + iphl - 1); 1076 } 1077 DPRINTF(DGE_DEBUG_CKSUM, 1078 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1079 sc->sc_dev.dv_xname, offset, ipcs)); 1080 1081 offset += iphl; 1082 1083 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1084 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1085 fields |= TDESC_POPTS_TXSM; 1086 tucs = DGE_TCPIP_TUCSS(offset) | 1087 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1088 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1089 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1090 /* Use the cached value. */ 1091 tucs = sc->sc_txctx_tucs; 1092 } else { 1093 /* Just initialize it to a valid TCP context. */ 1094 tucs = DGE_TCPIP_TUCSS(offset) | 1095 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1096 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1097 } 1098 1099 DPRINTF(DGE_DEBUG_CKSUM, 1100 ("%s: CKSUM: offset %d tucs 0x%x\n", 1101 sc->sc_dev.dv_xname, offset, tucs)); 1102 1103 if (sc->sc_txctx_ipcs == ipcs && 1104 sc->sc_txctx_tucs == tucs) { 1105 /* Cached context is fine. */ 1106 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1107 } else { 1108 /* Fill in the context descriptor. */ 1109 #ifdef DGE_EVENT_COUNTERS 1110 if (sc->sc_txctx_ipcs == 0xffffffff && 1111 sc->sc_txctx_tucs == 0xffffffff) 1112 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1113 else 1114 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1115 #endif 1116 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1117 t->dc_tcpip_ipcs = htole32(ipcs); 1118 t->dc_tcpip_tucs = htole32(tucs); 1119 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1120 t->dc_tcpip_seg = 0; 1121 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1122 1123 sc->sc_txctx_ipcs = ipcs; 1124 sc->sc_txctx_tucs = tucs; 1125 1126 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1127 txs->txs_ndesc++; 1128 } 1129 1130 *fieldsp = fields; 1131 1132 return (0); 1133 } 1134 1135 /* 1136 * dge_start: [ifnet interface function] 1137 * 1138 * Start packet transmission on the interface. 1139 */ 1140 static void 1141 dge_start(struct ifnet *ifp) 1142 { 1143 struct dge_softc *sc = ifp->if_softc; 1144 struct mbuf *m0; 1145 struct dge_txsoft *txs; 1146 bus_dmamap_t dmamap; 1147 int error, nexttx, lasttx = -1, ofree, seg; 1148 uint32_t cksumcmd; 1149 uint8_t cksumfields; 1150 1151 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1152 return; 1153 1154 /* 1155 * Remember the previous number of free descriptors. 1156 */ 1157 ofree = sc->sc_txfree; 1158 1159 /* 1160 * Loop through the send queue, setting up transmit descriptors 1161 * until we drain the queue, or use up all available transmit 1162 * descriptors. 1163 */ 1164 for (;;) { 1165 /* Grab a packet off the queue. */ 1166 IFQ_POLL(&ifp->if_snd, m0); 1167 if (m0 == NULL) 1168 break; 1169 1170 DPRINTF(DGE_DEBUG_TX, 1171 ("%s: TX: have packet to transmit: %p\n", 1172 sc->sc_dev.dv_xname, m0)); 1173 1174 /* Get a work queue entry. */ 1175 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1176 dge_txintr(sc); 1177 if (sc->sc_txsfree == 0) { 1178 DPRINTF(DGE_DEBUG_TX, 1179 ("%s: TX: no free job descriptors\n", 1180 sc->sc_dev.dv_xname)); 1181 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1182 break; 1183 } 1184 } 1185 1186 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1187 dmamap = txs->txs_dmamap; 1188 1189 /* 1190 * Load the DMA map. If this fails, the packet either 1191 * didn't fit in the allotted number of segments, or we 1192 * were short on resources. For the too-many-segments 1193 * case, we simply report an error and drop the packet, 1194 * since we can't sanely copy a jumbo packet to a single 1195 * buffer. 1196 */ 1197 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1198 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1199 if (error) { 1200 if (error == EFBIG) { 1201 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1202 printf("%s: Tx packet consumes too many " 1203 "DMA segments, dropping...\n", 1204 sc->sc_dev.dv_xname); 1205 IFQ_DEQUEUE(&ifp->if_snd, m0); 1206 m_freem(m0); 1207 continue; 1208 } 1209 /* 1210 * Short on resources, just stop for now. 1211 */ 1212 DPRINTF(DGE_DEBUG_TX, 1213 ("%s: TX: dmamap load failed: %d\n", 1214 sc->sc_dev.dv_xname, error)); 1215 break; 1216 } 1217 1218 /* 1219 * Ensure we have enough descriptors free to describe 1220 * the packet. Note, we always reserve one descriptor 1221 * at the end of the ring due to the semantics of the 1222 * TDT register, plus one more in the event we need 1223 * to re-load checksum offload context. 1224 */ 1225 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1226 /* 1227 * Not enough free descriptors to transmit this 1228 * packet. We haven't committed anything yet, 1229 * so just unload the DMA map, put the packet 1230 * pack on the queue, and punt. Notify the upper 1231 * layer that there are no more slots left. 1232 */ 1233 DPRINTF(DGE_DEBUG_TX, 1234 ("%s: TX: need %d descriptors, have %d\n", 1235 sc->sc_dev.dv_xname, dmamap->dm_nsegs, 1236 sc->sc_txfree - 1)); 1237 ifp->if_flags |= IFF_OACTIVE; 1238 bus_dmamap_unload(sc->sc_dmat, dmamap); 1239 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1240 break; 1241 } 1242 1243 IFQ_DEQUEUE(&ifp->if_snd, m0); 1244 1245 /* 1246 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1247 */ 1248 1249 /* Sync the DMA map. */ 1250 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1251 BUS_DMASYNC_PREWRITE); 1252 1253 DPRINTF(DGE_DEBUG_TX, 1254 ("%s: TX: packet has %d DMA segments\n", 1255 sc->sc_dev.dv_xname, dmamap->dm_nsegs)); 1256 1257 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1258 1259 /* 1260 * Store a pointer to the packet so that we can free it 1261 * later. 1262 * 1263 * Initially, we consider the number of descriptors the 1264 * packet uses the number of DMA segments. This may be 1265 * incremented by 1 if we do checksum offload (a descriptor 1266 * is used to set the checksum context). 1267 */ 1268 txs->txs_mbuf = m0; 1269 txs->txs_firstdesc = sc->sc_txnext; 1270 txs->txs_ndesc = dmamap->dm_nsegs; 1271 1272 /* 1273 * Set up checksum offload parameters for 1274 * this packet. 1275 */ 1276 if (m0->m_pkthdr.csum_flags & 1277 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1278 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1279 /* Error message already displayed. */ 1280 bus_dmamap_unload(sc->sc_dmat, dmamap); 1281 continue; 1282 } 1283 } else { 1284 cksumfields = 0; 1285 } 1286 1287 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1288 1289 /* 1290 * Initialize the transmit descriptor. 1291 */ 1292 for (nexttx = sc->sc_txnext, seg = 0; 1293 seg < dmamap->dm_nsegs; 1294 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1295 /* 1296 * Note: we currently only use 32-bit DMA 1297 * addresses. 1298 */ 1299 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1300 sc->sc_txdescs[nexttx].dt_baddrl = 1301 htole32(dmamap->dm_segs[seg].ds_addr); 1302 sc->sc_txdescs[nexttx].dt_ctl = 1303 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1304 sc->sc_txdescs[nexttx].dt_status = 0; 1305 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1306 sc->sc_txdescs[nexttx].dt_vlan = 0; 1307 lasttx = nexttx; 1308 1309 DPRINTF(DGE_DEBUG_TX, 1310 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1311 sc->sc_dev.dv_xname, nexttx, 1312 le32toh(dmamap->dm_segs[seg].ds_addr), 1313 le32toh(dmamap->dm_segs[seg].ds_len))); 1314 } 1315 1316 KASSERT(lasttx != -1); 1317 1318 /* 1319 * Set up the command byte on the last descriptor of 1320 * the packet. If we're in the interrupt delay window, 1321 * delay the interrupt. 1322 */ 1323 sc->sc_txdescs[lasttx].dt_ctl |= 1324 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1325 1326 txs->txs_lastdesc = lasttx; 1327 1328 DPRINTF(DGE_DEBUG_TX, 1329 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1330 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1331 1332 /* Sync the descriptors we're using. */ 1333 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1334 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1335 1336 /* Give the packet to the chip. */ 1337 CSR_WRITE(sc, DGE_TDT, nexttx); 1338 1339 DPRINTF(DGE_DEBUG_TX, 1340 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1341 1342 DPRINTF(DGE_DEBUG_TX, 1343 ("%s: TX: finished transmitting packet, job %d\n", 1344 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1345 1346 /* Advance the tx pointer. */ 1347 sc->sc_txfree -= txs->txs_ndesc; 1348 sc->sc_txnext = nexttx; 1349 1350 sc->sc_txsfree--; 1351 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1352 1353 #if NBPFILTER > 0 1354 /* Pass the packet to any BPF listeners. */ 1355 if (ifp->if_bpf) 1356 bpf_mtap(ifp->if_bpf, m0); 1357 #endif /* NBPFILTER > 0 */ 1358 } 1359 1360 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1361 /* No more slots; notify upper layer. */ 1362 ifp->if_flags |= IFF_OACTIVE; 1363 } 1364 1365 if (sc->sc_txfree != ofree) { 1366 /* Set a watchdog timer in case the chip flakes out. */ 1367 ifp->if_timer = 5; 1368 } 1369 } 1370 1371 /* 1372 * dge_watchdog: [ifnet interface function] 1373 * 1374 * Watchdog timer handler. 1375 */ 1376 static void 1377 dge_watchdog(struct ifnet *ifp) 1378 { 1379 struct dge_softc *sc = ifp->if_softc; 1380 1381 /* 1382 * Since we're using delayed interrupts, sweep up 1383 * before we report an error. 1384 */ 1385 dge_txintr(sc); 1386 1387 if (sc->sc_txfree != DGE_NTXDESC) { 1388 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1389 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1390 sc->sc_txnext); 1391 ifp->if_oerrors++; 1392 1393 /* Reset the interface. */ 1394 (void) dge_init(ifp); 1395 } 1396 1397 /* Try to get more packets going. */ 1398 dge_start(ifp); 1399 } 1400 1401 /* 1402 * dge_ioctl: [ifnet interface function] 1403 * 1404 * Handle control requests from the operator. 1405 */ 1406 static int 1407 dge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1408 { 1409 struct dge_softc *sc = ifp->if_softc; 1410 struct ifreq *ifr = (struct ifreq *) data; 1411 pcireg_t preg; 1412 int s, error, mmrbc; 1413 1414 s = splnet(); 1415 1416 switch (cmd) { 1417 case SIOCSIFMEDIA: 1418 case SIOCGIFMEDIA: 1419 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1420 break; 1421 1422 case SIOCSIFMTU: 1423 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) { 1424 error = EINVAL; 1425 } else { 1426 error = 0; 1427 ifp->if_mtu = ifr->ifr_mtu; 1428 if (ifp->if_flags & IFF_UP) 1429 error = (*ifp->if_init)(ifp); 1430 } 1431 break; 1432 1433 case SIOCSIFFLAGS: 1434 /* extract link flags */ 1435 if ((ifp->if_flags & IFF_LINK0) == 0 && 1436 (ifp->if_flags & IFF_LINK1) == 0) 1437 mmrbc = PCIX_MMRBC_512; 1438 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1439 (ifp->if_flags & IFF_LINK1) != 0) 1440 mmrbc = PCIX_MMRBC_1024; 1441 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1442 (ifp->if_flags & IFF_LINK1) == 0) 1443 mmrbc = PCIX_MMRBC_2048; 1444 else 1445 mmrbc = PCIX_MMRBC_4096; 1446 if (mmrbc != sc->sc_mmrbc) { 1447 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1448 preg &= ~PCIX_MMRBC_MSK; 1449 preg |= mmrbc; 1450 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1451 sc->sc_mmrbc = mmrbc; 1452 } 1453 /* FALLTHROUGH */ 1454 default: 1455 error = ether_ioctl(ifp, cmd, data); 1456 if (error == ENETRESET) { 1457 /* 1458 * Multicast list has changed; set the hardware filter 1459 * accordingly. 1460 */ 1461 if (ifp->if_flags & IFF_RUNNING) 1462 dge_set_filter(sc); 1463 error = 0; 1464 } 1465 break; 1466 } 1467 1468 /* Try to get more packets going. */ 1469 dge_start(ifp); 1470 1471 splx(s); 1472 return (error); 1473 } 1474 1475 /* 1476 * dge_intr: 1477 * 1478 * Interrupt service routine. 1479 */ 1480 static int 1481 dge_intr(void *arg) 1482 { 1483 struct dge_softc *sc = arg; 1484 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1485 uint32_t icr; 1486 int wantinit, handled = 0; 1487 1488 for (wantinit = 0; wantinit == 0;) { 1489 icr = CSR_READ(sc, DGE_ICR); 1490 if ((icr & sc->sc_icr) == 0) 1491 break; 1492 1493 #if 0 /*NRND > 0*/ 1494 if (RND_ENABLED(&sc->rnd_source)) 1495 rnd_add_uint32(&sc->rnd_source, icr); 1496 #endif 1497 1498 handled = 1; 1499 1500 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1501 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1502 DPRINTF(DGE_DEBUG_RX, 1503 ("%s: RX: got Rx intr 0x%08x\n", 1504 sc->sc_dev.dv_xname, 1505 icr & (ICR_RXDMT0|ICR_RXT0))); 1506 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1507 } 1508 #endif 1509 dge_rxintr(sc); 1510 1511 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1512 if (icr & ICR_TXDW) { 1513 DPRINTF(DGE_DEBUG_TX, 1514 ("%s: TX: got TXDW interrupt\n", 1515 sc->sc_dev.dv_xname)); 1516 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1517 } 1518 if (icr & ICR_TXQE) 1519 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1520 #endif 1521 dge_txintr(sc); 1522 1523 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1524 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1525 dge_linkintr(sc, icr); 1526 } 1527 1528 if (icr & ICR_RXO) { 1529 printf("%s: Receive overrun\n", sc->sc_dev.dv_xname); 1530 wantinit = 1; 1531 } 1532 } 1533 1534 if (handled) { 1535 if (wantinit) 1536 dge_init(ifp); 1537 1538 /* Try to get more packets going. */ 1539 dge_start(ifp); 1540 } 1541 1542 return (handled); 1543 } 1544 1545 /* 1546 * dge_txintr: 1547 * 1548 * Helper; handle transmit interrupts. 1549 */ 1550 static void 1551 dge_txintr(struct dge_softc *sc) 1552 { 1553 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1554 struct dge_txsoft *txs; 1555 uint8_t status; 1556 int i; 1557 1558 ifp->if_flags &= ~IFF_OACTIVE; 1559 1560 /* 1561 * Go through the Tx list and free mbufs for those 1562 * frames which have been transmitted. 1563 */ 1564 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1565 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1566 txs = &sc->sc_txsoft[i]; 1567 1568 DPRINTF(DGE_DEBUG_TX, 1569 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 1570 1571 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1572 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1573 1574 status = 1575 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1576 if ((status & TDESC_STA_DD) == 0) { 1577 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1578 BUS_DMASYNC_PREREAD); 1579 break; 1580 } 1581 1582 DPRINTF(DGE_DEBUG_TX, 1583 ("%s: TX: job %d done: descs %d..%d\n", 1584 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 1585 txs->txs_lastdesc)); 1586 1587 ifp->if_opackets++; 1588 sc->sc_txfree += txs->txs_ndesc; 1589 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1590 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1591 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1592 m_freem(txs->txs_mbuf); 1593 txs->txs_mbuf = NULL; 1594 } 1595 1596 /* Update the dirty transmit buffer pointer. */ 1597 sc->sc_txsdirty = i; 1598 DPRINTF(DGE_DEBUG_TX, 1599 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 1600 1601 /* 1602 * If there are no more pending transmissions, cancel the watchdog 1603 * timer. 1604 */ 1605 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1606 ifp->if_timer = 0; 1607 } 1608 1609 /* 1610 * dge_rxintr: 1611 * 1612 * Helper; handle receive interrupts. 1613 */ 1614 static void 1615 dge_rxintr(struct dge_softc *sc) 1616 { 1617 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1618 struct dge_rxsoft *rxs; 1619 struct mbuf *m; 1620 int i, len; 1621 uint8_t status, errors; 1622 1623 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1624 rxs = &sc->sc_rxsoft[i]; 1625 1626 DPRINTF(DGE_DEBUG_RX, 1627 ("%s: RX: checking descriptor %d\n", 1628 sc->sc_dev.dv_xname, i)); 1629 1630 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1631 1632 status = sc->sc_rxdescs[i].dr_status; 1633 errors = sc->sc_rxdescs[i].dr_errors; 1634 len = le16toh(sc->sc_rxdescs[i].dr_len); 1635 1636 if ((status & RDESC_STS_DD) == 0) { 1637 /* 1638 * We have processed all of the receive descriptors. 1639 */ 1640 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1641 break; 1642 } 1643 1644 if (__predict_false(sc->sc_rxdiscard)) { 1645 DPRINTF(DGE_DEBUG_RX, 1646 ("%s: RX: discarding contents of descriptor %d\n", 1647 sc->sc_dev.dv_xname, i)); 1648 DGE_INIT_RXDESC(sc, i); 1649 if (status & RDESC_STS_EOP) { 1650 /* Reset our state. */ 1651 DPRINTF(DGE_DEBUG_RX, 1652 ("%s: RX: resetting rxdiscard -> 0\n", 1653 sc->sc_dev.dv_xname)); 1654 sc->sc_rxdiscard = 0; 1655 } 1656 continue; 1657 } 1658 1659 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1660 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1661 1662 m = rxs->rxs_mbuf; 1663 1664 /* 1665 * Add a new receive buffer to the ring. 1666 */ 1667 if (dge_add_rxbuf(sc, i) != 0) { 1668 /* 1669 * Failed, throw away what we've done so 1670 * far, and discard the rest of the packet. 1671 */ 1672 ifp->if_ierrors++; 1673 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1674 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1675 DGE_INIT_RXDESC(sc, i); 1676 if ((status & RDESC_STS_EOP) == 0) 1677 sc->sc_rxdiscard = 1; 1678 if (sc->sc_rxhead != NULL) 1679 m_freem(sc->sc_rxhead); 1680 DGE_RXCHAIN_RESET(sc); 1681 DPRINTF(DGE_DEBUG_RX, 1682 ("%s: RX: Rx buffer allocation failed, " 1683 "dropping packet%s\n", sc->sc_dev.dv_xname, 1684 sc->sc_rxdiscard ? " (discard)" : "")); 1685 continue; 1686 } 1687 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1688 1689 DGE_RXCHAIN_LINK(sc, m); 1690 1691 m->m_len = len; 1692 1693 DPRINTF(DGE_DEBUG_RX, 1694 ("%s: RX: buffer at %p len %d\n", 1695 sc->sc_dev.dv_xname, m->m_data, len)); 1696 1697 /* 1698 * If this is not the end of the packet, keep 1699 * looking. 1700 */ 1701 if ((status & RDESC_STS_EOP) == 0) { 1702 sc->sc_rxlen += len; 1703 DPRINTF(DGE_DEBUG_RX, 1704 ("%s: RX: not yet EOP, rxlen -> %d\n", 1705 sc->sc_dev.dv_xname, sc->sc_rxlen)); 1706 continue; 1707 } 1708 1709 /* 1710 * Okay, we have the entire packet now... 1711 */ 1712 *sc->sc_rxtailp = NULL; 1713 m = sc->sc_rxhead; 1714 len += sc->sc_rxlen; 1715 1716 DGE_RXCHAIN_RESET(sc); 1717 1718 DPRINTF(DGE_DEBUG_RX, 1719 ("%s: RX: have entire packet, len -> %d\n", 1720 sc->sc_dev.dv_xname, len)); 1721 1722 /* 1723 * If an error occurred, update stats and drop the packet. 1724 */ 1725 if (errors & 1726 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1727 ifp->if_ierrors++; 1728 if (errors & RDESC_ERR_SE) 1729 printf("%s: symbol error\n", 1730 sc->sc_dev.dv_xname); 1731 else if (errors & RDESC_ERR_P) 1732 printf("%s: parity error\n", 1733 sc->sc_dev.dv_xname); 1734 else if (errors & RDESC_ERR_CE) 1735 printf("%s: CRC error\n", 1736 sc->sc_dev.dv_xname); 1737 m_freem(m); 1738 continue; 1739 } 1740 1741 /* 1742 * No errors. Receive the packet. 1743 */ 1744 m->m_pkthdr.rcvif = ifp; 1745 m->m_pkthdr.len = len; 1746 1747 /* 1748 * Set up checksum info for this packet. 1749 */ 1750 if (status & RDESC_STS_IPCS) { 1751 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1752 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1753 if (errors & RDESC_ERR_IPE) 1754 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1755 } 1756 if (status & RDESC_STS_TCPCS) { 1757 /* 1758 * Note: we don't know if this was TCP or UDP, 1759 * so we just set both bits, and expect the 1760 * upper layers to deal. 1761 */ 1762 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1763 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1764 if (errors & RDESC_ERR_TCPE) 1765 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1766 } 1767 1768 ifp->if_ipackets++; 1769 1770 #if NBPFILTER > 0 1771 /* Pass this up to any BPF listeners. */ 1772 if (ifp->if_bpf) 1773 bpf_mtap(ifp->if_bpf, m); 1774 #endif /* NBPFILTER > 0 */ 1775 1776 /* Pass it on. */ 1777 (*ifp->if_input)(ifp, m); 1778 } 1779 1780 /* Update the receive pointer. */ 1781 sc->sc_rxptr = i; 1782 1783 DPRINTF(DGE_DEBUG_RX, 1784 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 1785 } 1786 1787 /* 1788 * dge_linkintr: 1789 * 1790 * Helper; handle link interrupts. 1791 */ 1792 static void 1793 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1794 { 1795 uint32_t status; 1796 1797 if (icr & ICR_LSC) { 1798 status = CSR_READ(sc, DGE_STATUS); 1799 if (status & STATUS_LINKUP) { 1800 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1801 sc->sc_dev.dv_xname)); 1802 } else { 1803 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1804 sc->sc_dev.dv_xname)); 1805 } 1806 } else if (icr & ICR_RXSEQ) { 1807 DPRINTF(DGE_DEBUG_LINK, 1808 ("%s: LINK: Receive sequence error\n", 1809 sc->sc_dev.dv_xname)); 1810 } 1811 /* XXX - fix errata */ 1812 } 1813 1814 /* 1815 * dge_reset: 1816 * 1817 * Reset the i82597 chip. 1818 */ 1819 static void 1820 dge_reset(struct dge_softc *sc) 1821 { 1822 int i; 1823 1824 /* 1825 * Do a chip reset. 1826 */ 1827 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1828 1829 delay(10000); 1830 1831 for (i = 0; i < 1000; i++) { 1832 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1833 break; 1834 delay(20); 1835 } 1836 1837 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1838 printf("%s: WARNING: reset failed to complete\n", 1839 sc->sc_dev.dv_xname); 1840 /* 1841 * Reset the EEPROM logic. 1842 * This will cause the chip to reread its default values, 1843 * which doesn't happen otherwise (errata). 1844 */ 1845 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1846 delay(10000); 1847 } 1848 1849 /* 1850 * dge_init: [ifnet interface function] 1851 * 1852 * Initialize the interface. Must be called at splnet(). 1853 */ 1854 static int 1855 dge_init(struct ifnet *ifp) 1856 { 1857 struct dge_softc *sc = ifp->if_softc; 1858 struct dge_rxsoft *rxs; 1859 int i, error = 0; 1860 uint32_t reg; 1861 1862 /* 1863 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1864 * There is a small but measurable benefit to avoiding the adjusment 1865 * of the descriptor so that the headers are aligned, for normal mtu, 1866 * on such platforms. One possibility is that the DMA itself is 1867 * slightly more efficient if the front of the entire packet (instead 1868 * of the front of the headers) is aligned. 1869 * 1870 * Note we must always set align_tweak to 0 if we are using 1871 * jumbo frames. 1872 */ 1873 #ifdef __NO_STRICT_ALIGNMENT 1874 sc->sc_align_tweak = 0; 1875 #else 1876 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1877 sc->sc_align_tweak = 0; 1878 else 1879 sc->sc_align_tweak = 2; 1880 #endif /* __NO_STRICT_ALIGNMENT */ 1881 1882 /* Cancel any pending I/O. */ 1883 dge_stop(ifp, 0); 1884 1885 /* Reset the chip to a known state. */ 1886 dge_reset(sc); 1887 1888 /* Initialize the transmit descriptor ring. */ 1889 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1890 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1891 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1892 sc->sc_txfree = DGE_NTXDESC; 1893 sc->sc_txnext = 0; 1894 1895 sc->sc_txctx_ipcs = 0xffffffff; 1896 sc->sc_txctx_tucs = 0xffffffff; 1897 1898 CSR_WRITE(sc, DGE_TDBAH, 0); 1899 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1900 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1901 CSR_WRITE(sc, DGE_TDH, 0); 1902 CSR_WRITE(sc, DGE_TDT, 0); 1903 CSR_WRITE(sc, DGE_TIDV, TIDV); 1904 1905 #if 0 1906 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1907 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1908 #endif 1909 CSR_WRITE(sc, DGE_RXDCTL, 1910 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1911 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1912 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1913 1914 /* Initialize the transmit job descriptors. */ 1915 for (i = 0; i < DGE_TXQUEUELEN; i++) 1916 sc->sc_txsoft[i].txs_mbuf = NULL; 1917 sc->sc_txsfree = DGE_TXQUEUELEN; 1918 sc->sc_txsnext = 0; 1919 sc->sc_txsdirty = 0; 1920 1921 /* 1922 * Initialize the receive descriptor and receive job 1923 * descriptor rings. 1924 */ 1925 CSR_WRITE(sc, DGE_RDBAH, 0); 1926 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1927 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1928 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1929 CSR_WRITE(sc, DGE_RDT, 0); 1930 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1931 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1932 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1933 1934 for (i = 0; i < DGE_NRXDESC; i++) { 1935 rxs = &sc->sc_rxsoft[i]; 1936 if (rxs->rxs_mbuf == NULL) { 1937 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1938 printf("%s: unable to allocate or map rx " 1939 "buffer %d, error = %d\n", 1940 sc->sc_dev.dv_xname, i, error); 1941 /* 1942 * XXX Should attempt to run with fewer receive 1943 * XXX buffers instead of just failing. 1944 */ 1945 dge_rxdrain(sc); 1946 goto out; 1947 } 1948 } 1949 DGE_INIT_RXDESC(sc, i); 1950 } 1951 sc->sc_rxptr = DGE_RXSPACE; 1952 sc->sc_rxdiscard = 0; 1953 DGE_RXCHAIN_RESET(sc); 1954 1955 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1956 sc->sc_ctrl0 |= CTRL0_JFE; 1957 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1958 } 1959 1960 /* Write the control registers. */ 1961 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1962 1963 /* 1964 * Set up checksum offload parameters. 1965 */ 1966 reg = CSR_READ(sc, DGE_RXCSUM); 1967 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1968 reg |= RXCSUM_IPOFL; 1969 else 1970 reg &= ~RXCSUM_IPOFL; 1971 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 1972 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1973 else { 1974 reg &= ~RXCSUM_TUOFL; 1975 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 1976 reg &= ~RXCSUM_IPOFL; 1977 } 1978 CSR_WRITE(sc, DGE_RXCSUM, reg); 1979 1980 /* 1981 * Set up the interrupt registers. 1982 */ 1983 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 1984 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 1985 ICR_RXO | ICR_RXT0; 1986 1987 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 1988 1989 /* 1990 * Set up the transmit control register. 1991 */ 1992 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 1993 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 1994 1995 /* 1996 * Set up the receive control register; we actually program 1997 * the register when we set the receive filter. Use multicast 1998 * address offset type 0. 1999 */ 2000 sc->sc_mchash_type = 0; 2001 2002 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2003 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2004 2005 #ifdef DGE_OFFBYONE_RXBUG 2006 sc->sc_rctl |= RCTL_BSIZE_16k; 2007 #else 2008 switch(MCLBYTES) { 2009 case 2048: 2010 sc->sc_rctl |= RCTL_BSIZE_2k; 2011 break; 2012 case 4096: 2013 sc->sc_rctl |= RCTL_BSIZE_4k; 2014 break; 2015 case 8192: 2016 sc->sc_rctl |= RCTL_BSIZE_8k; 2017 break; 2018 case 16384: 2019 sc->sc_rctl |= RCTL_BSIZE_16k; 2020 break; 2021 default: 2022 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2023 } 2024 #endif 2025 2026 /* Set the receive filter. */ 2027 /* Also sets RCTL */ 2028 dge_set_filter(sc); 2029 2030 /* ...all done! */ 2031 ifp->if_flags |= IFF_RUNNING; 2032 ifp->if_flags &= ~IFF_OACTIVE; 2033 2034 out: 2035 if (error) 2036 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2037 return (error); 2038 } 2039 2040 /* 2041 * dge_rxdrain: 2042 * 2043 * Drain the receive queue. 2044 */ 2045 static void 2046 dge_rxdrain(struct dge_softc *sc) 2047 { 2048 struct dge_rxsoft *rxs; 2049 int i; 2050 2051 for (i = 0; i < DGE_NRXDESC; i++) { 2052 rxs = &sc->sc_rxsoft[i]; 2053 if (rxs->rxs_mbuf != NULL) { 2054 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2055 m_freem(rxs->rxs_mbuf); 2056 rxs->rxs_mbuf = NULL; 2057 } 2058 } 2059 } 2060 2061 /* 2062 * dge_stop: [ifnet interface function] 2063 * 2064 * Stop transmission on the interface. 2065 */ 2066 static void 2067 dge_stop(struct ifnet *ifp, int disable) 2068 { 2069 struct dge_softc *sc = ifp->if_softc; 2070 struct dge_txsoft *txs; 2071 int i; 2072 2073 /* Stop the transmit and receive processes. */ 2074 CSR_WRITE(sc, DGE_TCTL, 0); 2075 CSR_WRITE(sc, DGE_RCTL, 0); 2076 2077 /* Release any queued transmit buffers. */ 2078 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2079 txs = &sc->sc_txsoft[i]; 2080 if (txs->txs_mbuf != NULL) { 2081 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2082 m_freem(txs->txs_mbuf); 2083 txs->txs_mbuf = NULL; 2084 } 2085 } 2086 2087 if (disable) 2088 dge_rxdrain(sc); 2089 2090 /* Mark the interface as down and cancel the watchdog timer. */ 2091 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2092 ifp->if_timer = 0; 2093 } 2094 2095 /* 2096 * dge_add_rxbuf: 2097 * 2098 * Add a receive buffer to the indiciated descriptor. 2099 */ 2100 static int 2101 dge_add_rxbuf(struct dge_softc *sc, int idx) 2102 { 2103 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2104 struct mbuf *m; 2105 int error; 2106 #ifdef DGE_OFFBYONE_RXBUG 2107 caddr_t buf; 2108 #endif 2109 2110 MGETHDR(m, M_DONTWAIT, MT_DATA); 2111 if (m == NULL) 2112 return (ENOBUFS); 2113 2114 #ifdef DGE_OFFBYONE_RXBUG 2115 if ((buf = dge_getbuf(sc)) == NULL) 2116 return ENOBUFS; 2117 2118 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2119 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2120 m->m_flags |= M_EXT_RW; 2121 2122 if (rxs->rxs_mbuf != NULL) 2123 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2124 rxs->rxs_mbuf = m; 2125 2126 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2127 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2128 #else 2129 MCLGET(m, M_DONTWAIT); 2130 if ((m->m_flags & M_EXT) == 0) { 2131 m_freem(m); 2132 return (ENOBUFS); 2133 } 2134 2135 if (rxs->rxs_mbuf != NULL) 2136 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2137 2138 rxs->rxs_mbuf = m; 2139 2140 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2141 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2142 BUS_DMA_READ|BUS_DMA_NOWAIT); 2143 #endif 2144 if (error) { 2145 printf("%s: unable to load rx DMA map %d, error = %d\n", 2146 sc->sc_dev.dv_xname, idx, error); 2147 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2148 } 2149 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2150 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2151 2152 return (0); 2153 } 2154 2155 /* 2156 * dge_set_ral: 2157 * 2158 * Set an entry in the receive address list. 2159 */ 2160 static void 2161 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2162 { 2163 uint32_t ral_lo, ral_hi; 2164 2165 if (enaddr != NULL) { 2166 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2167 (enaddr[3] << 24); 2168 ral_hi = enaddr[4] | (enaddr[5] << 8); 2169 ral_hi |= RAH_AV; 2170 } else { 2171 ral_lo = 0; 2172 ral_hi = 0; 2173 } 2174 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2175 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2176 } 2177 2178 /* 2179 * dge_mchash: 2180 * 2181 * Compute the hash of the multicast address for the 4096-bit 2182 * multicast filter. 2183 */ 2184 static uint32_t 2185 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2186 { 2187 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2188 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2189 uint32_t hash; 2190 2191 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2192 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2193 2194 return (hash & 0xfff); 2195 } 2196 2197 /* 2198 * dge_set_filter: 2199 * 2200 * Set up the receive filter. 2201 */ 2202 static void 2203 dge_set_filter(struct dge_softc *sc) 2204 { 2205 struct ethercom *ec = &sc->sc_ethercom; 2206 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2207 struct ether_multi *enm; 2208 struct ether_multistep step; 2209 uint32_t hash, reg, bit; 2210 int i; 2211 2212 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2213 2214 if (ifp->if_flags & IFF_BROADCAST) 2215 sc->sc_rctl |= RCTL_BAM; 2216 if (ifp->if_flags & IFF_PROMISC) { 2217 sc->sc_rctl |= RCTL_UPE; 2218 goto allmulti; 2219 } 2220 2221 /* 2222 * Set the station address in the first RAL slot, and 2223 * clear the remaining slots. 2224 */ 2225 dge_set_ral(sc, LLADDR(ifp->if_sadl), 0); 2226 for (i = 1; i < RA_TABSIZE; i++) 2227 dge_set_ral(sc, NULL, i); 2228 2229 /* Clear out the multicast table. */ 2230 for (i = 0; i < MC_TABSIZE; i++) 2231 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2232 2233 ETHER_FIRST_MULTI(step, ec, enm); 2234 while (enm != NULL) { 2235 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2236 /* 2237 * We must listen to a range of multicast addresses. 2238 * For now, just accept all multicasts, rather than 2239 * trying to set only those filter bits needed to match 2240 * the range. (At this time, the only use of address 2241 * ranges is for IP multicast routing, for which the 2242 * range is big enough to require all bits set.) 2243 */ 2244 goto allmulti; 2245 } 2246 2247 hash = dge_mchash(sc, enm->enm_addrlo); 2248 2249 reg = (hash >> 5) & 0x7f; 2250 bit = hash & 0x1f; 2251 2252 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2253 hash |= 1U << bit; 2254 2255 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2256 2257 ETHER_NEXT_MULTI(step, enm); 2258 } 2259 2260 ifp->if_flags &= ~IFF_ALLMULTI; 2261 goto setit; 2262 2263 allmulti: 2264 ifp->if_flags |= IFF_ALLMULTI; 2265 sc->sc_rctl |= RCTL_MPE; 2266 2267 setit: 2268 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2269 } 2270 2271 /* 2272 * Read in the EEPROM info and verify checksum. 2273 */ 2274 int 2275 dge_read_eeprom(struct dge_softc *sc) 2276 { 2277 uint16_t cksum; 2278 int i; 2279 2280 cksum = 0; 2281 for (i = 0; i < EEPROM_SIZE; i++) { 2282 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2283 cksum += sc->sc_eeprom[i]; 2284 } 2285 return cksum != EEPROM_CKSUM; 2286 } 2287 2288 2289 /* 2290 * Read a 16-bit word from address addr in the serial EEPROM. 2291 */ 2292 uint16_t 2293 dge_eeprom_word(struct dge_softc *sc, int addr) 2294 { 2295 uint32_t reg; 2296 uint16_t rval = 0; 2297 int i; 2298 2299 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2300 2301 /* Lower clock pulse (and data in to chip) */ 2302 CSR_WRITE(sc, DGE_EECD, reg); 2303 /* Select chip */ 2304 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2305 2306 /* Send read command */ 2307 dge_eeprom_clockout(sc, 1); 2308 dge_eeprom_clockout(sc, 1); 2309 dge_eeprom_clockout(sc, 0); 2310 2311 /* Send address */ 2312 for (i = 5; i >= 0; i--) 2313 dge_eeprom_clockout(sc, (addr >> i) & 1); 2314 2315 /* Read data */ 2316 for (i = 0; i < 16; i++) { 2317 rval <<= 1; 2318 rval |= dge_eeprom_clockin(sc); 2319 } 2320 2321 /* Deselect chip */ 2322 CSR_WRITE(sc, DGE_EECD, reg); 2323 2324 return rval; 2325 } 2326 2327 /* 2328 * Clock out a single bit to the EEPROM. 2329 */ 2330 void 2331 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2332 { 2333 int reg; 2334 2335 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2336 if (bit) 2337 reg |= EECD_DI; 2338 2339 CSR_WRITE(sc, DGE_EECD, reg); 2340 delay(2); 2341 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2342 delay(2); 2343 CSR_WRITE(sc, DGE_EECD, reg); 2344 delay(2); 2345 } 2346 2347 /* 2348 * Clock in a single bit from EEPROM. 2349 */ 2350 int 2351 dge_eeprom_clockin(struct dge_softc *sc) 2352 { 2353 int reg, rv; 2354 2355 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2356 2357 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2358 delay(2); 2359 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2360 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2361 delay(2); 2362 2363 return rv; 2364 } 2365 2366 static void 2367 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2368 { 2369 struct dge_softc *sc = ifp->if_softc; 2370 2371 ifmr->ifm_status = IFM_AVALID; 2372 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2373 2374 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2375 ifmr->ifm_status |= IFM_ACTIVE; 2376 } 2377 2378 static inline int 2379 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2380 { 2381 int i, mdic; 2382 2383 CSR_WRITE(sc, DGE_MDIO, 2384 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2385 for (i = 0; i < 10; i++) { 2386 delay(10); 2387 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2388 break; 2389 } 2390 return mdic; 2391 } 2392 2393 2394 static void 2395 dge_xgmii_writereg(struct device *self, int phy, int reg, int val) 2396 { 2397 struct dge_softc *sc = (void *) self; 2398 int mdic; 2399 2400 CSR_WRITE(sc, DGE_MDIRW, val); 2401 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2402 printf("%s: address cycle timeout; phy %d reg %d\n", 2403 sc->sc_dev.dv_xname, phy, reg); 2404 return; 2405 } 2406 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2407 printf("%s: read cycle timeout; phy %d reg %d\n", 2408 sc->sc_dev.dv_xname, phy, reg); 2409 return; 2410 } 2411 } 2412 2413 static void 2414 dge_xgmii_reset(struct dge_softc *sc) 2415 { 2416 dge_xgmii_writereg((void *)sc, 0, 0, BMCR_RESET); 2417 } 2418 2419 static int 2420 dge_xgmii_mediachange(struct ifnet *ifp) 2421 { 2422 return 0; 2423 } 2424