1 /* $NetBSD: if_dge.c,v 1.43 2016/06/01 12:45:46 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.43 2016/06/01 12:45:46 pgoyette Exp $"); 84 85 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 99 #include <sys/rndsource.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #include <net/bpf.h> 107 108 #include <netinet/in.h> /* XXX for struct ip */ 109 #include <netinet/in_systm.h> /* XXX for struct ip */ 110 #include <netinet/ip.h> /* XXX for struct ip */ 111 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 112 113 #include <sys/bus.h> 114 #include <sys/intr.h> 115 #include <machine/endian.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/mii_bitbang.h> 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/pci/if_dgereg.h> 126 127 /* 128 * The receive engine may sometimes become off-by-one when writing back 129 * chained descriptors. Avoid this by allocating a large chunk of 130 * memory and use if instead (to avoid chained descriptors). 131 * This only happens with chained descriptors under heavy load. 132 */ 133 #define DGE_OFFBYONE_RXBUG 134 135 #define DGE_EVENT_COUNTERS 136 #define DGE_DEBUG 137 138 #ifdef DGE_DEBUG 139 #define DGE_DEBUG_LINK 0x01 140 #define DGE_DEBUG_TX 0x02 141 #define DGE_DEBUG_RX 0x04 142 #define DGE_DEBUG_CKSUM 0x08 143 int dge_debug = 0; 144 145 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 146 #else 147 #define DPRINTF(x, y) /* nothing */ 148 #endif /* DGE_DEBUG */ 149 150 /* 151 * Transmit descriptor list size. We allow up to 100 DMA segments per 152 * packet (Intel reports of jumbo frame packets with as 153 * many as 80 DMA segments when using 16k buffers). 154 */ 155 #define DGE_NTXSEGS 100 156 #define DGE_IFQUEUELEN 20000 157 #define DGE_TXQUEUELEN 2048 158 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 159 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 160 #define DGE_NTXDESC 1024 161 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 162 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 163 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 164 165 /* 166 * Receive descriptor list size. 167 * Packet is of size MCLBYTES, and for jumbo packets buffers may 168 * be chained. Due to the nature of the card (high-speed), keep this 169 * ring large. With 2k buffers the ring can store 400 jumbo packets, 170 * which at full speed will be received in just under 3ms. 171 */ 172 #define DGE_NRXDESC 2048 173 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 174 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 175 /* 176 * # of descriptors between head and written descriptors. 177 * This is to work-around two erratas. 178 */ 179 #define DGE_RXSPACE 10 180 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 181 /* 182 * Receive descriptor fetch threshholds. These are values recommended 183 * by Intel, do not touch them unless you know what you are doing. 184 */ 185 #define RXDCTL_PTHRESH_VAL 128 186 #define RXDCTL_HTHRESH_VAL 16 187 #define RXDCTL_WTHRESH_VAL 16 188 189 190 /* 191 * Tweakable parameters; default values. 192 */ 193 #define FCRTH 0x30000 /* Send XOFF water mark */ 194 #define FCRTL 0x28000 /* Send XON water mark */ 195 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 196 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 197 198 /* 199 * Control structures are DMA'd to the i82597 chip. We allocate them in 200 * a single clump that maps to a single DMA segment to make serveral things 201 * easier. 202 */ 203 struct dge_control_data { 204 /* 205 * The transmit descriptors. 206 */ 207 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 208 209 /* 210 * The receive descriptors. 211 */ 212 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 213 }; 214 215 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 216 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 217 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 218 219 /* 220 * The DGE interface have a higher max MTU size than normal jumbo frames. 221 */ 222 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 223 224 /* 225 * Software state for transmit jobs. 226 */ 227 struct dge_txsoft { 228 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 229 bus_dmamap_t txs_dmamap; /* our DMA map */ 230 int txs_firstdesc; /* first descriptor in packet */ 231 int txs_lastdesc; /* last descriptor in packet */ 232 int txs_ndesc; /* # of descriptors used */ 233 }; 234 235 /* 236 * Software state for receive buffers. Each descriptor gets a 237 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 238 * more than one buffer, we chain them together. 239 */ 240 struct dge_rxsoft { 241 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 242 bus_dmamap_t rxs_dmamap; /* our DMA map */ 243 }; 244 245 /* 246 * Software state per device. 247 */ 248 struct dge_softc { 249 device_t sc_dev; /* generic device information */ 250 bus_space_tag_t sc_st; /* bus space tag */ 251 bus_space_handle_t sc_sh; /* bus space handle */ 252 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 253 struct ethercom sc_ethercom; /* ethernet common data */ 254 255 int sc_flags; /* flags; see below */ 256 int sc_bus_speed; /* PCI/PCIX bus speed */ 257 int sc_pcix_offset; /* PCIX capability register offset */ 258 259 const struct dge_product *sc_dgep; /* Pointer to the dge_product entry */ 260 pci_chipset_tag_t sc_pc; 261 pcitag_t sc_pt; 262 int sc_mmrbc; /* Max PCIX memory read byte count */ 263 264 void *sc_ih; /* interrupt cookie */ 265 266 struct ifmedia sc_media; 267 268 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 269 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 270 271 int sc_align_tweak; 272 273 /* 274 * Software state for the transmit and receive descriptors. 275 */ 276 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 277 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 278 279 /* 280 * Control data structures. 281 */ 282 struct dge_control_data *sc_control_data; 283 #define sc_txdescs sc_control_data->wcd_txdescs 284 #define sc_rxdescs sc_control_data->wcd_rxdescs 285 286 #ifdef DGE_EVENT_COUNTERS 287 /* Event counters. */ 288 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 289 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 290 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 291 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 292 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 293 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 294 struct evcnt sc_ev_linkintr; /* Link interrupts */ 295 296 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 297 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 298 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 299 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 300 301 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 302 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 303 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 304 305 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 306 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 307 #endif /* DGE_EVENT_COUNTERS */ 308 309 int sc_txfree; /* number of free Tx descriptors */ 310 int sc_txnext; /* next ready Tx descriptor */ 311 312 int sc_txsfree; /* number of free Tx jobs */ 313 int sc_txsnext; /* next free Tx job */ 314 int sc_txsdirty; /* dirty Tx jobs */ 315 316 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 317 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 318 319 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 320 int sc_rxdiscard; 321 int sc_rxlen; 322 struct mbuf *sc_rxhead; 323 struct mbuf *sc_rxtail; 324 struct mbuf **sc_rxtailp; 325 326 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 327 uint32_t sc_icr; /* prototype interrupt bits */ 328 uint32_t sc_tctl; /* prototype TCTL register */ 329 uint32_t sc_rctl; /* prototype RCTL register */ 330 331 int sc_mchash_type; /* multicast filter offset */ 332 333 uint16_t sc_eeprom[EEPROM_SIZE]; 334 335 krndsource_t rnd_source; /* random source */ 336 #ifdef DGE_OFFBYONE_RXBUG 337 void *sc_bugbuf; 338 SLIST_HEAD(, rxbugentry) sc_buglist; 339 bus_dmamap_t sc_bugmap; 340 struct rxbugentry *sc_entry; 341 #endif 342 }; 343 344 #define DGE_RXCHAIN_RESET(sc) \ 345 do { \ 346 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 347 *(sc)->sc_rxtailp = NULL; \ 348 (sc)->sc_rxlen = 0; \ 349 } while (/*CONSTCOND*/0) 350 351 #define DGE_RXCHAIN_LINK(sc, m) \ 352 do { \ 353 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 354 (sc)->sc_rxtailp = &(m)->m_next; \ 355 } while (/*CONSTCOND*/0) 356 357 /* sc_flags */ 358 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 359 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 360 361 #ifdef DGE_EVENT_COUNTERS 362 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 363 #else 364 #define DGE_EVCNT_INCR(ev) /* nothing */ 365 #endif 366 367 #define CSR_READ(sc, reg) \ 368 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 369 #define CSR_WRITE(sc, reg, val) \ 370 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 371 372 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 373 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 374 375 #define DGE_CDTXSYNC(sc, x, n, ops) \ 376 do { \ 377 int __x, __n; \ 378 \ 379 __x = (x); \ 380 __n = (n); \ 381 \ 382 /* If it will wrap around, sync to the end of the ring. */ \ 383 if ((__x + __n) > DGE_NTXDESC) { \ 384 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 385 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 386 (DGE_NTXDESC - __x), (ops)); \ 387 __n -= (DGE_NTXDESC - __x); \ 388 __x = 0; \ 389 } \ 390 \ 391 /* Now sync whatever is left. */ \ 392 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 393 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 394 } while (/*CONSTCOND*/0) 395 396 #define DGE_CDRXSYNC(sc, x, ops) \ 397 do { \ 398 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 399 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 400 } while (/*CONSTCOND*/0) 401 402 #ifdef DGE_OFFBYONE_RXBUG 403 #define DGE_INIT_RXDESC(sc, x) \ 404 do { \ 405 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 406 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 407 struct mbuf *__m = __rxs->rxs_mbuf; \ 408 \ 409 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 410 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 411 __rxd->dr_baddrh = 0; \ 412 __rxd->dr_len = 0; \ 413 __rxd->dr_cksum = 0; \ 414 __rxd->dr_status = 0; \ 415 __rxd->dr_errors = 0; \ 416 __rxd->dr_special = 0; \ 417 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 418 \ 419 CSR_WRITE((sc), DGE_RDT, (x)); \ 420 } while (/*CONSTCOND*/0) 421 #else 422 #define DGE_INIT_RXDESC(sc, x) \ 423 do { \ 424 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 425 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 426 struct mbuf *__m = __rxs->rxs_mbuf; \ 427 \ 428 /* \ 429 * Note: We scoot the packet forward 2 bytes in the buffer \ 430 * so that the payload after the Ethernet header is aligned \ 431 * to a 4-byte boundary. \ 432 * \ 433 * XXX BRAINDAMAGE ALERT! \ 434 * The stupid chip uses the same size for every buffer, which \ 435 * is set in the Receive Control register. We are using the 2K \ 436 * size option, but what we REALLY want is (2K - 2)! For this \ 437 * reason, we can't "scoot" packets longer than the standard \ 438 * Ethernet MTU. On strict-alignment platforms, if the total \ 439 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 440 * the upper layer copy the headers. \ 441 */ \ 442 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 443 \ 444 __rxd->dr_baddrl = \ 445 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 446 (sc)->sc_align_tweak); \ 447 __rxd->dr_baddrh = 0; \ 448 __rxd->dr_len = 0; \ 449 __rxd->dr_cksum = 0; \ 450 __rxd->dr_status = 0; \ 451 __rxd->dr_errors = 0; \ 452 __rxd->dr_special = 0; \ 453 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 454 \ 455 CSR_WRITE((sc), DGE_RDT, (x)); \ 456 } while (/*CONSTCOND*/0) 457 #endif 458 459 #ifdef DGE_OFFBYONE_RXBUG 460 /* 461 * Allocation constants. Much memory may be used for this. 462 */ 463 #ifndef DGE_BUFFER_SIZE 464 #define DGE_BUFFER_SIZE DGE_MAX_MTU 465 #endif 466 #define DGE_NBUFFERS (4*DGE_NRXDESC) 467 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 468 469 struct rxbugentry { 470 SLIST_ENTRY(rxbugentry) rb_entry; 471 int rb_slot; 472 }; 473 474 static int 475 dge_alloc_rcvmem(struct dge_softc *sc) 476 { 477 char *kva; 478 bus_dma_segment_t seg; 479 int i, rseg, state, error; 480 struct rxbugentry *entry; 481 482 state = error = 0; 483 484 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 485 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 486 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 487 return ENOBUFS; 488 } 489 490 state = 1; 491 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, 492 BUS_DMA_NOWAIT)) { 493 aprint_error_dev(sc->sc_dev, "can't map DMA buffers (%d bytes)\n", 494 (int)DGE_RXMEM); 495 error = ENOBUFS; 496 goto out; 497 } 498 499 state = 2; 500 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 501 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 502 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 503 error = ENOBUFS; 504 goto out; 505 } 506 507 state = 3; 508 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 509 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 510 aprint_error_dev(sc->sc_dev, "can't load DMA map\n"); 511 error = ENOBUFS; 512 goto out; 513 } 514 515 state = 4; 516 sc->sc_bugbuf = (void *)kva; 517 SLIST_INIT(&sc->sc_buglist); 518 519 /* 520 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 521 * in an array. 522 */ 523 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 524 M_DEVBUF, M_NOWAIT)) == NULL) { 525 error = ENOBUFS; 526 goto out; 527 } 528 sc->sc_entry = entry; 529 for (i = 0; i < DGE_NBUFFERS; i++) { 530 entry[i].rb_slot = i; 531 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 532 } 533 out: 534 if (error != 0) { 535 switch (state) { 536 case 4: 537 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 538 case 3: 539 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 540 case 2: 541 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 542 case 1: 543 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 544 break; 545 default: 546 break; 547 } 548 } 549 550 return error; 551 } 552 553 /* 554 * Allocate a jumbo buffer. 555 */ 556 static void * 557 dge_getbuf(struct dge_softc *sc) 558 { 559 struct rxbugentry *entry; 560 561 entry = SLIST_FIRST(&sc->sc_buglist); 562 563 if (entry == NULL) { 564 printf("%s: no free RX buffers\n", device_xname(sc->sc_dev)); 565 return(NULL); 566 } 567 568 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 569 return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 570 } 571 572 /* 573 * Release a jumbo buffer. 574 */ 575 static void 576 dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) 577 { 578 struct rxbugentry *entry; 579 struct dge_softc *sc; 580 int i, s; 581 582 /* Extract the softc struct pointer. */ 583 sc = (struct dge_softc *)arg; 584 585 if (sc == NULL) 586 panic("dge_freebuf: can't find softc pointer!"); 587 588 /* calculate the slot this buffer belongs to */ 589 590 i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; 591 592 if ((i < 0) || (i >= DGE_NBUFFERS)) 593 panic("dge_freebuf: asked to free buffer %d!", i); 594 595 s = splvm(); 596 entry = sc->sc_entry + i; 597 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 598 599 if (__predict_true(m != NULL)) 600 pool_cache_put(mb_cache, m); 601 splx(s); 602 } 603 #endif 604 605 static void dge_start(struct ifnet *); 606 static void dge_watchdog(struct ifnet *); 607 static int dge_ioctl(struct ifnet *, u_long, void *); 608 static int dge_init(struct ifnet *); 609 static void dge_stop(struct ifnet *, int); 610 611 static bool dge_shutdown(device_t, int); 612 613 static void dge_reset(struct dge_softc *); 614 static void dge_rxdrain(struct dge_softc *); 615 static int dge_add_rxbuf(struct dge_softc *, int); 616 617 static void dge_set_filter(struct dge_softc *); 618 619 static int dge_intr(void *); 620 static void dge_txintr(struct dge_softc *); 621 static void dge_rxintr(struct dge_softc *); 622 static void dge_linkintr(struct dge_softc *, uint32_t); 623 624 static int dge_match(device_t, cfdata_t, void *); 625 static void dge_attach(device_t, device_t, void *); 626 627 static int dge_read_eeprom(struct dge_softc *sc); 628 static int dge_eeprom_clockin(struct dge_softc *sc); 629 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 630 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 631 static int dge_xgmii_mediachange(struct ifnet *); 632 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 633 static void dge_xgmii_reset(struct dge_softc *); 634 static void dge_xgmii_writereg(struct dge_softc *, int, int, int); 635 636 637 CFATTACH_DECL_NEW(dge, sizeof(struct dge_softc), 638 dge_match, dge_attach, NULL, NULL); 639 640 #ifdef DGE_EVENT_COUNTERS 641 #if DGE_NTXSEGS > 100 642 #error Update dge_txseg_evcnt_names 643 #endif 644 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 645 #endif /* DGE_EVENT_COUNTERS */ 646 647 /* 648 * Devices supported by this driver. 649 */ 650 static const struct dge_product { 651 pci_vendor_id_t dgep_vendor; 652 pci_product_id_t dgep_product; 653 const char *dgep_name; 654 int dgep_flags; 655 #define DGEP_F_10G_LR 0x01 656 #define DGEP_F_10G_SR 0x02 657 } dge_products[] = { 658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX, 659 "Intel i82597EX 10GbE-LR Ethernet", 660 DGEP_F_10G_LR }, 661 662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_SR, 663 "Intel i82597EX 10GbE-SR Ethernet", 664 DGEP_F_10G_SR }, 665 666 { 0, 0, 667 NULL, 668 0 }, 669 }; 670 671 static const struct dge_product * 672 dge_lookup(const struct pci_attach_args *pa) 673 { 674 const struct dge_product *dgep; 675 676 for (dgep = dge_products; dgep->dgep_name != NULL; dgep++) { 677 if (PCI_VENDOR(pa->pa_id) == dgep->dgep_vendor && 678 PCI_PRODUCT(pa->pa_id) == dgep->dgep_product) 679 return dgep; 680 } 681 return NULL; 682 } 683 684 static int 685 dge_match(device_t parent, cfdata_t cf, void *aux) 686 { 687 struct pci_attach_args *pa = aux; 688 689 if (dge_lookup(pa) != NULL) 690 return (1); 691 692 return (0); 693 } 694 695 static void 696 dge_attach(device_t parent, device_t self, void *aux) 697 { 698 struct dge_softc *sc = device_private(self); 699 struct pci_attach_args *pa = aux; 700 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 701 pci_chipset_tag_t pc = pa->pa_pc; 702 pci_intr_handle_t ih; 703 const char *intrstr = NULL; 704 bus_dma_segment_t seg; 705 int i, rseg, error; 706 uint8_t enaddr[ETHER_ADDR_LEN]; 707 pcireg_t preg, memtype; 708 uint32_t reg; 709 char intrbuf[PCI_INTRSTR_LEN]; 710 const struct dge_product *dgep; 711 712 sc->sc_dgep = dgep = dge_lookup(pa); 713 if (dgep == NULL) { 714 printf("\n"); 715 panic("dge_attach: impossible"); 716 } 717 718 sc->sc_dev = self; 719 sc->sc_dmat = pa->pa_dmat; 720 sc->sc_pc = pa->pa_pc; 721 sc->sc_pt = pa->pa_tag; 722 723 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 724 dgep->dgep_name, 1); 725 726 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 727 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 728 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 729 aprint_error_dev(sc->sc_dev, "unable to map device registers\n"); 730 return; 731 } 732 733 /* Enable bus mastering */ 734 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 735 preg |= PCI_COMMAND_MASTER_ENABLE; 736 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 737 738 /* 739 * Map and establish our interrupt. 740 */ 741 if (pci_intr_map(pa, &ih)) { 742 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 743 return; 744 } 745 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 746 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 747 if (sc->sc_ih == NULL) { 748 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 749 if (intrstr != NULL) 750 aprint_error(" at %s", intrstr); 751 aprint_error("\n"); 752 return; 753 } 754 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 755 756 /* 757 * Determine a few things about the bus we're connected to. 758 */ 759 reg = CSR_READ(sc, DGE_STATUS); 760 if (reg & STATUS_BUS64) 761 sc->sc_flags |= DGE_F_BUS64; 762 763 sc->sc_flags |= DGE_F_PCIX; 764 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 765 PCI_CAP_PCIX, 766 &sc->sc_pcix_offset, NULL) == 0) 767 aprint_error_dev(sc->sc_dev, "unable to find PCIX " 768 "capability\n"); 769 770 if (sc->sc_flags & DGE_F_PCIX) { 771 switch (reg & STATUS_PCIX_MSK) { 772 case STATUS_PCIX_66: 773 sc->sc_bus_speed = 66; 774 break; 775 case STATUS_PCIX_100: 776 sc->sc_bus_speed = 100; 777 break; 778 case STATUS_PCIX_133: 779 sc->sc_bus_speed = 133; 780 break; 781 default: 782 aprint_error_dev(sc->sc_dev, 783 "unknown PCIXSPD %d; assuming 66MHz\n", 784 reg & STATUS_PCIX_MSK); 785 sc->sc_bus_speed = 66; 786 } 787 } else 788 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 789 aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", 790 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 791 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 792 793 /* 794 * Allocate the control data structures, and create and load the 795 * DMA map for it. 796 */ 797 if ((error = bus_dmamem_alloc(sc->sc_dmat, 798 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 799 0)) != 0) { 800 aprint_error_dev(sc->sc_dev, 801 "unable to allocate control data, error = %d\n", 802 error); 803 goto fail_0; 804 } 805 806 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 807 sizeof(struct dge_control_data), (void **)&sc->sc_control_data, 808 0)) != 0) { 809 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 810 error); 811 goto fail_1; 812 } 813 814 if ((error = bus_dmamap_create(sc->sc_dmat, 815 sizeof(struct dge_control_data), 1, 816 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 817 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 818 "error = %d\n", error); 819 goto fail_2; 820 } 821 822 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 823 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 824 0)) != 0) { 825 aprint_error_dev(sc->sc_dev, 826 "unable to load control data DMA map, error = %d\n", 827 error); 828 goto fail_3; 829 } 830 831 #ifdef DGE_OFFBYONE_RXBUG 832 if (dge_alloc_rcvmem(sc) != 0) 833 return; /* Already complained */ 834 #endif 835 /* 836 * Create the transmit buffer DMA maps. 837 */ 838 for (i = 0; i < DGE_TXQUEUELEN; i++) { 839 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 840 DGE_NTXSEGS, MCLBYTES, 0, 0, 841 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 842 aprint_error_dev(sc->sc_dev, "unable to create Tx DMA map %d, " 843 "error = %d\n", i, error); 844 goto fail_4; 845 } 846 } 847 848 /* 849 * Create the receive buffer DMA maps. 850 */ 851 for (i = 0; i < DGE_NRXDESC; i++) { 852 #ifdef DGE_OFFBYONE_RXBUG 853 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 854 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 855 #else 856 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 857 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 858 #endif 859 aprint_error_dev(sc->sc_dev, "unable to create Rx DMA map %d, " 860 "error = %d\n", i, error); 861 goto fail_5; 862 } 863 sc->sc_rxsoft[i].rxs_mbuf = NULL; 864 } 865 866 /* 867 * Set bits in ctrl0 register. 868 * Should get the software defined pins out of EEPROM? 869 */ 870 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 871 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 872 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 873 874 /* 875 * Reset the chip to a known state. 876 */ 877 dge_reset(sc); 878 879 /* 880 * Reset the PHY. 881 */ 882 dge_xgmii_reset(sc); 883 884 /* 885 * Read in EEPROM data. 886 */ 887 if (dge_read_eeprom(sc)) { 888 aprint_error_dev(sc->sc_dev, "couldn't read EEPROM\n"); 889 return; 890 } 891 892 /* 893 * Get the ethernet address. 894 */ 895 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 896 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 897 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 898 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 899 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 900 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 901 902 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 903 ether_sprintf(enaddr)); 904 905 /* 906 * Setup media stuff. 907 */ 908 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 909 dge_xgmii_mediastatus); 910 if (dgep->dgep_flags & DGEP_F_10G_SR) { 911 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_SR, 0, NULL); 912 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_SR); 913 } else { /* XXX default is LR */ 914 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 915 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 916 } 917 918 ifp = &sc->sc_ethercom.ec_if; 919 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 920 ifp->if_softc = sc; 921 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 922 ifp->if_ioctl = dge_ioctl; 923 ifp->if_start = dge_start; 924 ifp->if_watchdog = dge_watchdog; 925 ifp->if_init = dge_init; 926 ifp->if_stop = dge_stop; 927 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 928 IFQ_SET_READY(&ifp->if_snd); 929 930 sc->sc_ethercom.ec_capabilities |= 931 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 932 933 /* 934 * We can perform TCPv4 and UDPv4 checkums in-bound. 935 */ 936 ifp->if_capabilities |= 937 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 938 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 939 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 940 941 /* 942 * Attach the interface. 943 */ 944 if_attach(ifp); 945 ether_ifattach(ifp, enaddr); 946 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 947 RND_TYPE_NET, RND_FLAG_DEFAULT); 948 949 #ifdef DGE_EVENT_COUNTERS 950 /* Fix segment event naming */ 951 if (dge_txseg_evcnt_names == NULL) { 952 dge_txseg_evcnt_names = 953 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 954 for (i = 0; i < DGE_NTXSEGS; i++) 955 snprintf((*dge_txseg_evcnt_names)[i], 956 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 957 } 958 959 /* Attach event counters. */ 960 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 961 NULL, device_xname(sc->sc_dev), "txsstall"); 962 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 963 NULL, device_xname(sc->sc_dev), "txdstall"); 964 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 965 NULL, device_xname(sc->sc_dev), "txforceintr"); 966 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 967 NULL, device_xname(sc->sc_dev), "txdw"); 968 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 969 NULL, device_xname(sc->sc_dev), "txqe"); 970 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 971 NULL, device_xname(sc->sc_dev), "rxintr"); 972 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 973 NULL, device_xname(sc->sc_dev), "linkintr"); 974 975 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 976 NULL, device_xname(sc->sc_dev), "rxipsum"); 977 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 978 NULL, device_xname(sc->sc_dev), "rxtusum"); 979 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 980 NULL, device_xname(sc->sc_dev), "txipsum"); 981 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 982 NULL, device_xname(sc->sc_dev), "txtusum"); 983 984 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 985 NULL, device_xname(sc->sc_dev), "txctx init"); 986 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 987 NULL, device_xname(sc->sc_dev), "txctx hit"); 988 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 989 NULL, device_xname(sc->sc_dev), "txctx miss"); 990 991 for (i = 0; i < DGE_NTXSEGS; i++) 992 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 993 NULL, device_xname(sc->sc_dev), (*dge_txseg_evcnt_names)[i]); 994 995 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 996 NULL, device_xname(sc->sc_dev), "txdrop"); 997 998 #endif /* DGE_EVENT_COUNTERS */ 999 1000 /* 1001 * Make sure the interface is shutdown during reboot. 1002 */ 1003 if (pmf_device_register1(self, NULL, NULL, dge_shutdown)) 1004 pmf_class_network_register(self, ifp); 1005 else 1006 aprint_error_dev(self, "couldn't establish power handler\n"); 1007 1008 return; 1009 1010 /* 1011 * Free any resources we've allocated during the failed attach 1012 * attempt. Do this in reverse order and fall through. 1013 */ 1014 fail_5: 1015 for (i = 0; i < DGE_NRXDESC; i++) { 1016 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1017 bus_dmamap_destroy(sc->sc_dmat, 1018 sc->sc_rxsoft[i].rxs_dmamap); 1019 } 1020 fail_4: 1021 for (i = 0; i < DGE_TXQUEUELEN; i++) { 1022 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1023 bus_dmamap_destroy(sc->sc_dmat, 1024 sc->sc_txsoft[i].txs_dmamap); 1025 } 1026 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1027 fail_3: 1028 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1029 fail_2: 1030 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1031 sizeof(struct dge_control_data)); 1032 fail_1: 1033 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1034 fail_0: 1035 return; 1036 } 1037 1038 /* 1039 * dge_shutdown: 1040 * 1041 * Make sure the interface is stopped at reboot time. 1042 */ 1043 static bool 1044 dge_shutdown(device_t self, int howto) 1045 { 1046 struct dge_softc *sc; 1047 1048 sc = device_private(self); 1049 dge_stop(&sc->sc_ethercom.ec_if, 1); 1050 1051 return true; 1052 } 1053 1054 /* 1055 * dge_tx_cksum: 1056 * 1057 * Set up TCP/IP checksumming parameters for the 1058 * specified packet. 1059 */ 1060 static int 1061 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1062 { 1063 struct mbuf *m0 = txs->txs_mbuf; 1064 struct dge_ctdes *t; 1065 uint32_t ipcs, tucs; 1066 struct ether_header *eh; 1067 int offset, iphl; 1068 uint8_t fields = 0; 1069 1070 /* 1071 * XXX It would be nice if the mbuf pkthdr had offset 1072 * fields for the protocol headers. 1073 */ 1074 1075 eh = mtod(m0, struct ether_header *); 1076 switch (htons(eh->ether_type)) { 1077 case ETHERTYPE_IP: 1078 offset = ETHER_HDR_LEN; 1079 break; 1080 1081 case ETHERTYPE_VLAN: 1082 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1083 break; 1084 1085 default: 1086 /* 1087 * Don't support this protocol or encapsulation. 1088 */ 1089 *fieldsp = 0; 1090 return (0); 1091 } 1092 1093 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1094 1095 /* 1096 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1097 * offload feature, if we load the context descriptor, we 1098 * MUST provide valid values for IPCSS and TUCSS fields. 1099 */ 1100 1101 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1102 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1103 fields |= TDESC_POPTS_IXSM; 1104 ipcs = DGE_TCPIP_IPCSS(offset) | 1105 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1106 DGE_TCPIP_IPCSE(offset + iphl - 1); 1107 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1108 /* Use the cached value. */ 1109 ipcs = sc->sc_txctx_ipcs; 1110 } else { 1111 /* Just initialize it to the likely value anyway. */ 1112 ipcs = DGE_TCPIP_IPCSS(offset) | 1113 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1114 DGE_TCPIP_IPCSE(offset + iphl - 1); 1115 } 1116 DPRINTF(DGE_DEBUG_CKSUM, 1117 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1118 device_xname(sc->sc_dev), offset, ipcs)); 1119 1120 offset += iphl; 1121 1122 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1123 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1124 fields |= TDESC_POPTS_TXSM; 1125 tucs = DGE_TCPIP_TUCSS(offset) | 1126 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1127 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1128 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1129 /* Use the cached value. */ 1130 tucs = sc->sc_txctx_tucs; 1131 } else { 1132 /* Just initialize it to a valid TCP context. */ 1133 tucs = DGE_TCPIP_TUCSS(offset) | 1134 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1135 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1136 } 1137 1138 DPRINTF(DGE_DEBUG_CKSUM, 1139 ("%s: CKSUM: offset %d tucs 0x%x\n", 1140 device_xname(sc->sc_dev), offset, tucs)); 1141 1142 if (sc->sc_txctx_ipcs == ipcs && 1143 sc->sc_txctx_tucs == tucs) { 1144 /* Cached context is fine. */ 1145 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1146 } else { 1147 /* Fill in the context descriptor. */ 1148 #ifdef DGE_EVENT_COUNTERS 1149 if (sc->sc_txctx_ipcs == 0xffffffff && 1150 sc->sc_txctx_tucs == 0xffffffff) 1151 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1152 else 1153 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1154 #endif 1155 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1156 t->dc_tcpip_ipcs = htole32(ipcs); 1157 t->dc_tcpip_tucs = htole32(tucs); 1158 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1159 t->dc_tcpip_seg = 0; 1160 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1161 1162 sc->sc_txctx_ipcs = ipcs; 1163 sc->sc_txctx_tucs = tucs; 1164 1165 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1166 txs->txs_ndesc++; 1167 } 1168 1169 *fieldsp = fields; 1170 1171 return (0); 1172 } 1173 1174 /* 1175 * dge_start: [ifnet interface function] 1176 * 1177 * Start packet transmission on the interface. 1178 */ 1179 static void 1180 dge_start(struct ifnet *ifp) 1181 { 1182 struct dge_softc *sc = ifp->if_softc; 1183 struct mbuf *m0; 1184 struct dge_txsoft *txs; 1185 bus_dmamap_t dmamap; 1186 int error, nexttx, lasttx = -1, ofree, seg; 1187 uint32_t cksumcmd; 1188 uint8_t cksumfields; 1189 1190 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1191 return; 1192 1193 /* 1194 * Remember the previous number of free descriptors. 1195 */ 1196 ofree = sc->sc_txfree; 1197 1198 /* 1199 * Loop through the send queue, setting up transmit descriptors 1200 * until we drain the queue, or use up all available transmit 1201 * descriptors. 1202 */ 1203 for (;;) { 1204 /* Grab a packet off the queue. */ 1205 IFQ_POLL(&ifp->if_snd, m0); 1206 if (m0 == NULL) 1207 break; 1208 1209 DPRINTF(DGE_DEBUG_TX, 1210 ("%s: TX: have packet to transmit: %p\n", 1211 device_xname(sc->sc_dev), m0)); 1212 1213 /* Get a work queue entry. */ 1214 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1215 dge_txintr(sc); 1216 if (sc->sc_txsfree == 0) { 1217 DPRINTF(DGE_DEBUG_TX, 1218 ("%s: TX: no free job descriptors\n", 1219 device_xname(sc->sc_dev))); 1220 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1221 break; 1222 } 1223 } 1224 1225 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1226 dmamap = txs->txs_dmamap; 1227 1228 /* 1229 * Load the DMA map. If this fails, the packet either 1230 * didn't fit in the allotted number of segments, or we 1231 * were short on resources. For the too-many-segments 1232 * case, we simply report an error and drop the packet, 1233 * since we can't sanely copy a jumbo packet to a single 1234 * buffer. 1235 */ 1236 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1237 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1238 if (error) { 1239 if (error == EFBIG) { 1240 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1241 printf("%s: Tx packet consumes too many " 1242 "DMA segments, dropping...\n", 1243 device_xname(sc->sc_dev)); 1244 IFQ_DEQUEUE(&ifp->if_snd, m0); 1245 m_freem(m0); 1246 continue; 1247 } 1248 /* 1249 * Short on resources, just stop for now. 1250 */ 1251 DPRINTF(DGE_DEBUG_TX, 1252 ("%s: TX: dmamap load failed: %d\n", 1253 device_xname(sc->sc_dev), error)); 1254 break; 1255 } 1256 1257 /* 1258 * Ensure we have enough descriptors free to describe 1259 * the packet. Note, we always reserve one descriptor 1260 * at the end of the ring due to the semantics of the 1261 * TDT register, plus one more in the event we need 1262 * to re-load checksum offload context. 1263 */ 1264 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1265 /* 1266 * Not enough free descriptors to transmit this 1267 * packet. We haven't committed anything yet, 1268 * so just unload the DMA map, put the packet 1269 * pack on the queue, and punt. Notify the upper 1270 * layer that there are no more slots left. 1271 */ 1272 DPRINTF(DGE_DEBUG_TX, 1273 ("%s: TX: need %d descriptors, have %d\n", 1274 device_xname(sc->sc_dev), dmamap->dm_nsegs, 1275 sc->sc_txfree - 1)); 1276 ifp->if_flags |= IFF_OACTIVE; 1277 bus_dmamap_unload(sc->sc_dmat, dmamap); 1278 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1279 break; 1280 } 1281 1282 IFQ_DEQUEUE(&ifp->if_snd, m0); 1283 1284 /* 1285 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1286 */ 1287 1288 /* Sync the DMA map. */ 1289 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1290 BUS_DMASYNC_PREWRITE); 1291 1292 DPRINTF(DGE_DEBUG_TX, 1293 ("%s: TX: packet has %d DMA segments\n", 1294 device_xname(sc->sc_dev), dmamap->dm_nsegs)); 1295 1296 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1297 1298 /* 1299 * Store a pointer to the packet so that we can free it 1300 * later. 1301 * 1302 * Initially, we consider the number of descriptors the 1303 * packet uses the number of DMA segments. This may be 1304 * incremented by 1 if we do checksum offload (a descriptor 1305 * is used to set the checksum context). 1306 */ 1307 txs->txs_mbuf = m0; 1308 txs->txs_firstdesc = sc->sc_txnext; 1309 txs->txs_ndesc = dmamap->dm_nsegs; 1310 1311 /* 1312 * Set up checksum offload parameters for 1313 * this packet. 1314 */ 1315 if (m0->m_pkthdr.csum_flags & 1316 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1317 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1318 /* Error message already displayed. */ 1319 bus_dmamap_unload(sc->sc_dmat, dmamap); 1320 continue; 1321 } 1322 } else { 1323 cksumfields = 0; 1324 } 1325 1326 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1327 1328 /* 1329 * Initialize the transmit descriptor. 1330 */ 1331 for (nexttx = sc->sc_txnext, seg = 0; 1332 seg < dmamap->dm_nsegs; 1333 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1334 /* 1335 * Note: we currently only use 32-bit DMA 1336 * addresses. 1337 */ 1338 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1339 sc->sc_txdescs[nexttx].dt_baddrl = 1340 htole32(dmamap->dm_segs[seg].ds_addr); 1341 sc->sc_txdescs[nexttx].dt_ctl = 1342 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1343 sc->sc_txdescs[nexttx].dt_status = 0; 1344 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1345 sc->sc_txdescs[nexttx].dt_vlan = 0; 1346 lasttx = nexttx; 1347 1348 DPRINTF(DGE_DEBUG_TX, 1349 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1350 device_xname(sc->sc_dev), nexttx, 1351 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_addr), 1352 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_len))); 1353 } 1354 1355 KASSERT(lasttx != -1); 1356 1357 /* 1358 * Set up the command byte on the last descriptor of 1359 * the packet. If we're in the interrupt delay window, 1360 * delay the interrupt. 1361 */ 1362 sc->sc_txdescs[lasttx].dt_ctl |= 1363 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1364 1365 txs->txs_lastdesc = lasttx; 1366 1367 DPRINTF(DGE_DEBUG_TX, 1368 ("%s: TX: desc %d: cmdlen 0x%08x\n", device_xname(sc->sc_dev), 1369 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1370 1371 /* Sync the descriptors we're using. */ 1372 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1373 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1374 1375 /* Give the packet to the chip. */ 1376 CSR_WRITE(sc, DGE_TDT, nexttx); 1377 1378 DPRINTF(DGE_DEBUG_TX, 1379 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 1380 1381 DPRINTF(DGE_DEBUG_TX, 1382 ("%s: TX: finished transmitting packet, job %d\n", 1383 device_xname(sc->sc_dev), sc->sc_txsnext)); 1384 1385 /* Advance the tx pointer. */ 1386 sc->sc_txfree -= txs->txs_ndesc; 1387 sc->sc_txnext = nexttx; 1388 1389 sc->sc_txsfree--; 1390 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1391 1392 /* Pass the packet to any BPF listeners. */ 1393 bpf_mtap(ifp, m0); 1394 } 1395 1396 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1397 /* No more slots; notify upper layer. */ 1398 ifp->if_flags |= IFF_OACTIVE; 1399 } 1400 1401 if (sc->sc_txfree != ofree) { 1402 /* Set a watchdog timer in case the chip flakes out. */ 1403 ifp->if_timer = 5; 1404 } 1405 } 1406 1407 /* 1408 * dge_watchdog: [ifnet interface function] 1409 * 1410 * Watchdog timer handler. 1411 */ 1412 static void 1413 dge_watchdog(struct ifnet *ifp) 1414 { 1415 struct dge_softc *sc = ifp->if_softc; 1416 1417 /* 1418 * Since we're using delayed interrupts, sweep up 1419 * before we report an error. 1420 */ 1421 dge_txintr(sc); 1422 1423 if (sc->sc_txfree != DGE_NTXDESC) { 1424 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1425 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, 1426 sc->sc_txnext); 1427 ifp->if_oerrors++; 1428 1429 /* Reset the interface. */ 1430 (void) dge_init(ifp); 1431 } 1432 1433 /* Try to get more packets going. */ 1434 dge_start(ifp); 1435 } 1436 1437 /* 1438 * dge_ioctl: [ifnet interface function] 1439 * 1440 * Handle control requests from the operator. 1441 */ 1442 static int 1443 dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1444 { 1445 struct dge_softc *sc = ifp->if_softc; 1446 struct ifreq *ifr = (struct ifreq *) data; 1447 pcireg_t preg; 1448 int s, error, mmrbc; 1449 1450 s = splnet(); 1451 1452 switch (cmd) { 1453 case SIOCSIFMEDIA: 1454 case SIOCGIFMEDIA: 1455 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1456 break; 1457 1458 case SIOCSIFMTU: 1459 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) 1460 error = EINVAL; 1461 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1462 break; 1463 else if (ifp->if_flags & IFF_UP) 1464 error = (*ifp->if_init)(ifp); 1465 else 1466 error = 0; 1467 break; 1468 1469 case SIOCSIFFLAGS: 1470 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1471 break; 1472 /* extract link flags */ 1473 if ((ifp->if_flags & IFF_LINK0) == 0 && 1474 (ifp->if_flags & IFF_LINK1) == 0) 1475 mmrbc = PCIX_MMRBC_512; 1476 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1477 (ifp->if_flags & IFF_LINK1) != 0) 1478 mmrbc = PCIX_MMRBC_1024; 1479 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1480 (ifp->if_flags & IFF_LINK1) == 0) 1481 mmrbc = PCIX_MMRBC_2048; 1482 else 1483 mmrbc = PCIX_MMRBC_4096; 1484 if (mmrbc != sc->sc_mmrbc) { 1485 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1486 preg &= ~PCIX_MMRBC_MSK; 1487 preg |= mmrbc; 1488 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1489 sc->sc_mmrbc = mmrbc; 1490 } 1491 /* FALLTHROUGH */ 1492 default: 1493 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1494 break; 1495 1496 error = 0; 1497 1498 if (cmd == SIOCSIFCAP) 1499 error = (*ifp->if_init)(ifp); 1500 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1501 ; 1502 else if (ifp->if_flags & IFF_RUNNING) { 1503 /* 1504 * Multicast list has changed; set the hardware filter 1505 * accordingly. 1506 */ 1507 dge_set_filter(sc); 1508 } 1509 break; 1510 } 1511 1512 /* Try to get more packets going. */ 1513 dge_start(ifp); 1514 1515 splx(s); 1516 return (error); 1517 } 1518 1519 /* 1520 * dge_intr: 1521 * 1522 * Interrupt service routine. 1523 */ 1524 static int 1525 dge_intr(void *arg) 1526 { 1527 struct dge_softc *sc = arg; 1528 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1529 uint32_t icr; 1530 int wantinit, handled = 0; 1531 1532 for (wantinit = 0; wantinit == 0;) { 1533 icr = CSR_READ(sc, DGE_ICR); 1534 if ((icr & sc->sc_icr) == 0) 1535 break; 1536 1537 rnd_add_uint32(&sc->rnd_source, icr); 1538 1539 handled = 1; 1540 1541 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1542 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1543 DPRINTF(DGE_DEBUG_RX, 1544 ("%s: RX: got Rx intr 0x%08x\n", 1545 device_xname(sc->sc_dev), 1546 icr & (ICR_RXDMT0|ICR_RXT0))); 1547 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1548 } 1549 #endif 1550 dge_rxintr(sc); 1551 1552 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1553 if (icr & ICR_TXDW) { 1554 DPRINTF(DGE_DEBUG_TX, 1555 ("%s: TX: got TXDW interrupt\n", 1556 device_xname(sc->sc_dev))); 1557 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1558 } 1559 if (icr & ICR_TXQE) 1560 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1561 #endif 1562 dge_txintr(sc); 1563 1564 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1565 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1566 dge_linkintr(sc, icr); 1567 } 1568 1569 if (icr & ICR_RXO) { 1570 printf("%s: Receive overrun\n", device_xname(sc->sc_dev)); 1571 wantinit = 1; 1572 } 1573 } 1574 1575 if (handled) { 1576 if (wantinit) 1577 dge_init(ifp); 1578 1579 /* Try to get more packets going. */ 1580 dge_start(ifp); 1581 } 1582 1583 return (handled); 1584 } 1585 1586 /* 1587 * dge_txintr: 1588 * 1589 * Helper; handle transmit interrupts. 1590 */ 1591 static void 1592 dge_txintr(struct dge_softc *sc) 1593 { 1594 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1595 struct dge_txsoft *txs; 1596 uint8_t status; 1597 int i; 1598 1599 ifp->if_flags &= ~IFF_OACTIVE; 1600 1601 /* 1602 * Go through the Tx list and free mbufs for those 1603 * frames which have been transmitted. 1604 */ 1605 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1606 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1607 txs = &sc->sc_txsoft[i]; 1608 1609 DPRINTF(DGE_DEBUG_TX, 1610 ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i)); 1611 1612 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1613 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1614 1615 status = 1616 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1617 if ((status & TDESC_STA_DD) == 0) { 1618 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1619 BUS_DMASYNC_PREREAD); 1620 break; 1621 } 1622 1623 DPRINTF(DGE_DEBUG_TX, 1624 ("%s: TX: job %d done: descs %d..%d\n", 1625 device_xname(sc->sc_dev), i, txs->txs_firstdesc, 1626 txs->txs_lastdesc)); 1627 1628 ifp->if_opackets++; 1629 sc->sc_txfree += txs->txs_ndesc; 1630 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1631 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1632 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1633 m_freem(txs->txs_mbuf); 1634 txs->txs_mbuf = NULL; 1635 } 1636 1637 /* Update the dirty transmit buffer pointer. */ 1638 sc->sc_txsdirty = i; 1639 DPRINTF(DGE_DEBUG_TX, 1640 ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i)); 1641 1642 /* 1643 * If there are no more pending transmissions, cancel the watchdog 1644 * timer. 1645 */ 1646 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1647 ifp->if_timer = 0; 1648 } 1649 1650 /* 1651 * dge_rxintr: 1652 * 1653 * Helper; handle receive interrupts. 1654 */ 1655 static void 1656 dge_rxintr(struct dge_softc *sc) 1657 { 1658 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1659 struct dge_rxsoft *rxs; 1660 struct mbuf *m; 1661 int i, len; 1662 uint8_t status, errors; 1663 1664 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1665 rxs = &sc->sc_rxsoft[i]; 1666 1667 DPRINTF(DGE_DEBUG_RX, 1668 ("%s: RX: checking descriptor %d\n", 1669 device_xname(sc->sc_dev), i)); 1670 1671 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1672 1673 status = sc->sc_rxdescs[i].dr_status; 1674 errors = sc->sc_rxdescs[i].dr_errors; 1675 len = le16toh(sc->sc_rxdescs[i].dr_len); 1676 1677 if ((status & RDESC_STS_DD) == 0) { 1678 /* 1679 * We have processed all of the receive descriptors. 1680 */ 1681 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1682 break; 1683 } 1684 1685 if (__predict_false(sc->sc_rxdiscard)) { 1686 DPRINTF(DGE_DEBUG_RX, 1687 ("%s: RX: discarding contents of descriptor %d\n", 1688 device_xname(sc->sc_dev), i)); 1689 DGE_INIT_RXDESC(sc, i); 1690 if (status & RDESC_STS_EOP) { 1691 /* Reset our state. */ 1692 DPRINTF(DGE_DEBUG_RX, 1693 ("%s: RX: resetting rxdiscard -> 0\n", 1694 device_xname(sc->sc_dev))); 1695 sc->sc_rxdiscard = 0; 1696 } 1697 continue; 1698 } 1699 1700 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1701 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1702 1703 m = rxs->rxs_mbuf; 1704 1705 /* 1706 * Add a new receive buffer to the ring. 1707 */ 1708 if (dge_add_rxbuf(sc, i) != 0) { 1709 /* 1710 * Failed, throw away what we've done so 1711 * far, and discard the rest of the packet. 1712 */ 1713 ifp->if_ierrors++; 1714 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1715 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1716 DGE_INIT_RXDESC(sc, i); 1717 if ((status & RDESC_STS_EOP) == 0) 1718 sc->sc_rxdiscard = 1; 1719 if (sc->sc_rxhead != NULL) 1720 m_freem(sc->sc_rxhead); 1721 DGE_RXCHAIN_RESET(sc); 1722 DPRINTF(DGE_DEBUG_RX, 1723 ("%s: RX: Rx buffer allocation failed, " 1724 "dropping packet%s\n", device_xname(sc->sc_dev), 1725 sc->sc_rxdiscard ? " (discard)" : "")); 1726 continue; 1727 } 1728 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1729 1730 DGE_RXCHAIN_LINK(sc, m); 1731 1732 m->m_len = len; 1733 1734 DPRINTF(DGE_DEBUG_RX, 1735 ("%s: RX: buffer at %p len %d\n", 1736 device_xname(sc->sc_dev), m->m_data, len)); 1737 1738 /* 1739 * If this is not the end of the packet, keep 1740 * looking. 1741 */ 1742 if ((status & RDESC_STS_EOP) == 0) { 1743 sc->sc_rxlen += len; 1744 DPRINTF(DGE_DEBUG_RX, 1745 ("%s: RX: not yet EOP, rxlen -> %d\n", 1746 device_xname(sc->sc_dev), sc->sc_rxlen)); 1747 continue; 1748 } 1749 1750 /* 1751 * Okay, we have the entire packet now... 1752 */ 1753 *sc->sc_rxtailp = NULL; 1754 m = sc->sc_rxhead; 1755 len += sc->sc_rxlen; 1756 1757 DGE_RXCHAIN_RESET(sc); 1758 1759 DPRINTF(DGE_DEBUG_RX, 1760 ("%s: RX: have entire packet, len -> %d\n", 1761 device_xname(sc->sc_dev), len)); 1762 1763 /* 1764 * If an error occurred, update stats and drop the packet. 1765 */ 1766 if (errors & 1767 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1768 ifp->if_ierrors++; 1769 if (errors & RDESC_ERR_SE) 1770 printf("%s: symbol error\n", 1771 device_xname(sc->sc_dev)); 1772 else if (errors & RDESC_ERR_P) 1773 printf("%s: parity error\n", 1774 device_xname(sc->sc_dev)); 1775 else if (errors & RDESC_ERR_CE) 1776 printf("%s: CRC error\n", 1777 device_xname(sc->sc_dev)); 1778 m_freem(m); 1779 continue; 1780 } 1781 1782 /* 1783 * No errors. Receive the packet. 1784 */ 1785 m->m_pkthdr.rcvif = ifp; 1786 m->m_pkthdr.len = len; 1787 1788 /* 1789 * Set up checksum info for this packet. 1790 */ 1791 if (status & RDESC_STS_IPCS) { 1792 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1793 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1794 if (errors & RDESC_ERR_IPE) 1795 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1796 } 1797 if (status & RDESC_STS_TCPCS) { 1798 /* 1799 * Note: we don't know if this was TCP or UDP, 1800 * so we just set both bits, and expect the 1801 * upper layers to deal. 1802 */ 1803 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1804 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1805 if (errors & RDESC_ERR_TCPE) 1806 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1807 } 1808 1809 ifp->if_ipackets++; 1810 1811 /* Pass this up to any BPF listeners. */ 1812 bpf_mtap(ifp, m); 1813 1814 /* Pass it on. */ 1815 if_percpuq_enqueue(ifp->if_percpuq, m); 1816 } 1817 1818 /* Update the receive pointer. */ 1819 sc->sc_rxptr = i; 1820 1821 DPRINTF(DGE_DEBUG_RX, 1822 ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i)); 1823 } 1824 1825 /* 1826 * dge_linkintr: 1827 * 1828 * Helper; handle link interrupts. 1829 */ 1830 static void 1831 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1832 { 1833 uint32_t status; 1834 1835 if (icr & ICR_LSC) { 1836 status = CSR_READ(sc, DGE_STATUS); 1837 if (status & STATUS_LINKUP) { 1838 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1839 device_xname(sc->sc_dev))); 1840 } else { 1841 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1842 device_xname(sc->sc_dev))); 1843 } 1844 } else if (icr & ICR_RXSEQ) { 1845 DPRINTF(DGE_DEBUG_LINK, 1846 ("%s: LINK: Receive sequence error\n", 1847 device_xname(sc->sc_dev))); 1848 } 1849 /* XXX - fix errata */ 1850 } 1851 1852 /* 1853 * dge_reset: 1854 * 1855 * Reset the i82597 chip. 1856 */ 1857 static void 1858 dge_reset(struct dge_softc *sc) 1859 { 1860 int i; 1861 1862 /* 1863 * Do a chip reset. 1864 */ 1865 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1866 1867 delay(10000); 1868 1869 for (i = 0; i < 1000; i++) { 1870 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1871 break; 1872 delay(20); 1873 } 1874 1875 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1876 printf("%s: WARNING: reset failed to complete\n", 1877 device_xname(sc->sc_dev)); 1878 /* 1879 * Reset the EEPROM logic. 1880 * This will cause the chip to reread its default values, 1881 * which doesn't happen otherwise (errata). 1882 */ 1883 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1884 delay(10000); 1885 } 1886 1887 /* 1888 * dge_init: [ifnet interface function] 1889 * 1890 * Initialize the interface. Must be called at splnet(). 1891 */ 1892 static int 1893 dge_init(struct ifnet *ifp) 1894 { 1895 struct dge_softc *sc = ifp->if_softc; 1896 struct dge_rxsoft *rxs; 1897 int i, error = 0; 1898 uint32_t reg; 1899 1900 /* 1901 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1902 * There is a small but measurable benefit to avoiding the adjusment 1903 * of the descriptor so that the headers are aligned, for normal mtu, 1904 * on such platforms. One possibility is that the DMA itself is 1905 * slightly more efficient if the front of the entire packet (instead 1906 * of the front of the headers) is aligned. 1907 * 1908 * Note we must always set align_tweak to 0 if we are using 1909 * jumbo frames. 1910 */ 1911 #ifdef __NO_STRICT_ALIGNMENT 1912 sc->sc_align_tweak = 0; 1913 #else 1914 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1915 sc->sc_align_tweak = 0; 1916 else 1917 sc->sc_align_tweak = 2; 1918 #endif /* __NO_STRICT_ALIGNMENT */ 1919 1920 /* Cancel any pending I/O. */ 1921 dge_stop(ifp, 0); 1922 1923 /* Reset the chip to a known state. */ 1924 dge_reset(sc); 1925 1926 /* Initialize the transmit descriptor ring. */ 1927 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1928 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1929 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1930 sc->sc_txfree = DGE_NTXDESC; 1931 sc->sc_txnext = 0; 1932 1933 sc->sc_txctx_ipcs = 0xffffffff; 1934 sc->sc_txctx_tucs = 0xffffffff; 1935 1936 CSR_WRITE(sc, DGE_TDBAH, 0); 1937 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1938 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1939 CSR_WRITE(sc, DGE_TDH, 0); 1940 CSR_WRITE(sc, DGE_TDT, 0); 1941 CSR_WRITE(sc, DGE_TIDV, TIDV); 1942 1943 #if 0 1944 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1945 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1946 #endif 1947 CSR_WRITE(sc, DGE_RXDCTL, 1948 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1949 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1950 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1951 1952 /* Initialize the transmit job descriptors. */ 1953 for (i = 0; i < DGE_TXQUEUELEN; i++) 1954 sc->sc_txsoft[i].txs_mbuf = NULL; 1955 sc->sc_txsfree = DGE_TXQUEUELEN; 1956 sc->sc_txsnext = 0; 1957 sc->sc_txsdirty = 0; 1958 1959 /* 1960 * Initialize the receive descriptor and receive job 1961 * descriptor rings. 1962 */ 1963 CSR_WRITE(sc, DGE_RDBAH, 0); 1964 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1965 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1966 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1967 CSR_WRITE(sc, DGE_RDT, 0); 1968 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1969 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1970 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1971 1972 for (i = 0; i < DGE_NRXDESC; i++) { 1973 rxs = &sc->sc_rxsoft[i]; 1974 if (rxs->rxs_mbuf == NULL) { 1975 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1976 printf("%s: unable to allocate or map rx " 1977 "buffer %d, error = %d\n", 1978 device_xname(sc->sc_dev), i, error); 1979 /* 1980 * XXX Should attempt to run with fewer receive 1981 * XXX buffers instead of just failing. 1982 */ 1983 dge_rxdrain(sc); 1984 goto out; 1985 } 1986 } 1987 DGE_INIT_RXDESC(sc, i); 1988 } 1989 sc->sc_rxptr = DGE_RXSPACE; 1990 sc->sc_rxdiscard = 0; 1991 DGE_RXCHAIN_RESET(sc); 1992 1993 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1994 sc->sc_ctrl0 |= CTRL0_JFE; 1995 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1996 } 1997 1998 /* Write the control registers. */ 1999 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 2000 2001 /* 2002 * Set up checksum offload parameters. 2003 */ 2004 reg = CSR_READ(sc, DGE_RXCSUM); 2005 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2006 reg |= RXCSUM_IPOFL; 2007 else 2008 reg &= ~RXCSUM_IPOFL; 2009 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2010 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2011 else { 2012 reg &= ~RXCSUM_TUOFL; 2013 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2014 reg &= ~RXCSUM_IPOFL; 2015 } 2016 CSR_WRITE(sc, DGE_RXCSUM, reg); 2017 2018 /* 2019 * Set up the interrupt registers. 2020 */ 2021 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 2022 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2023 ICR_RXO | ICR_RXT0; 2024 2025 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 2026 2027 /* 2028 * Set up the transmit control register. 2029 */ 2030 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 2031 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 2032 2033 /* 2034 * Set up the receive control register; we actually program 2035 * the register when we set the receive filter. Use multicast 2036 * address offset type 0. 2037 */ 2038 sc->sc_mchash_type = 0; 2039 2040 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2041 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2042 2043 #ifdef DGE_OFFBYONE_RXBUG 2044 sc->sc_rctl |= RCTL_BSIZE_16k; 2045 #else 2046 switch(MCLBYTES) { 2047 case 2048: 2048 sc->sc_rctl |= RCTL_BSIZE_2k; 2049 break; 2050 case 4096: 2051 sc->sc_rctl |= RCTL_BSIZE_4k; 2052 break; 2053 case 8192: 2054 sc->sc_rctl |= RCTL_BSIZE_8k; 2055 break; 2056 case 16384: 2057 sc->sc_rctl |= RCTL_BSIZE_16k; 2058 break; 2059 default: 2060 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2061 } 2062 #endif 2063 2064 /* Set the receive filter. */ 2065 /* Also sets RCTL */ 2066 dge_set_filter(sc); 2067 2068 /* ...all done! */ 2069 ifp->if_flags |= IFF_RUNNING; 2070 ifp->if_flags &= ~IFF_OACTIVE; 2071 2072 out: 2073 if (error) 2074 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2075 return (error); 2076 } 2077 2078 /* 2079 * dge_rxdrain: 2080 * 2081 * Drain the receive queue. 2082 */ 2083 static void 2084 dge_rxdrain(struct dge_softc *sc) 2085 { 2086 struct dge_rxsoft *rxs; 2087 int i; 2088 2089 for (i = 0; i < DGE_NRXDESC; i++) { 2090 rxs = &sc->sc_rxsoft[i]; 2091 if (rxs->rxs_mbuf != NULL) { 2092 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2093 m_freem(rxs->rxs_mbuf); 2094 rxs->rxs_mbuf = NULL; 2095 } 2096 } 2097 } 2098 2099 /* 2100 * dge_stop: [ifnet interface function] 2101 * 2102 * Stop transmission on the interface. 2103 */ 2104 static void 2105 dge_stop(struct ifnet *ifp, int disable) 2106 { 2107 struct dge_softc *sc = ifp->if_softc; 2108 struct dge_txsoft *txs; 2109 int i; 2110 2111 /* Stop the transmit and receive processes. */ 2112 CSR_WRITE(sc, DGE_TCTL, 0); 2113 CSR_WRITE(sc, DGE_RCTL, 0); 2114 2115 /* Release any queued transmit buffers. */ 2116 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2117 txs = &sc->sc_txsoft[i]; 2118 if (txs->txs_mbuf != NULL) { 2119 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2120 m_freem(txs->txs_mbuf); 2121 txs->txs_mbuf = NULL; 2122 } 2123 } 2124 2125 /* Mark the interface as down and cancel the watchdog timer. */ 2126 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2127 ifp->if_timer = 0; 2128 2129 if (disable) 2130 dge_rxdrain(sc); 2131 } 2132 2133 /* 2134 * dge_add_rxbuf: 2135 * 2136 * Add a receive buffer to the indiciated descriptor. 2137 */ 2138 static int 2139 dge_add_rxbuf(struct dge_softc *sc, int idx) 2140 { 2141 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2142 struct mbuf *m; 2143 int error; 2144 #ifdef DGE_OFFBYONE_RXBUG 2145 void *buf; 2146 #endif 2147 2148 MGETHDR(m, M_DONTWAIT, MT_DATA); 2149 if (m == NULL) 2150 return (ENOBUFS); 2151 2152 #ifdef DGE_OFFBYONE_RXBUG 2153 if ((buf = dge_getbuf(sc)) == NULL) 2154 return ENOBUFS; 2155 2156 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2157 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2158 m->m_flags |= M_EXT_RW; 2159 2160 if (rxs->rxs_mbuf != NULL) 2161 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2162 rxs->rxs_mbuf = m; 2163 2164 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2165 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2166 #else 2167 MCLGET(m, M_DONTWAIT); 2168 if ((m->m_flags & M_EXT) == 0) { 2169 m_freem(m); 2170 return (ENOBUFS); 2171 } 2172 2173 if (rxs->rxs_mbuf != NULL) 2174 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2175 2176 rxs->rxs_mbuf = m; 2177 2178 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2179 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2180 BUS_DMA_READ|BUS_DMA_NOWAIT); 2181 #endif 2182 if (error) { 2183 printf("%s: unable to load rx DMA map %d, error = %d\n", 2184 device_xname(sc->sc_dev), idx, error); 2185 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2186 } 2187 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2188 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2189 2190 return (0); 2191 } 2192 2193 /* 2194 * dge_set_ral: 2195 * 2196 * Set an entry in the receive address list. 2197 */ 2198 static void 2199 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2200 { 2201 uint32_t ral_lo, ral_hi; 2202 2203 if (enaddr != NULL) { 2204 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2205 (enaddr[3] << 24); 2206 ral_hi = enaddr[4] | (enaddr[5] << 8); 2207 ral_hi |= RAH_AV; 2208 } else { 2209 ral_lo = 0; 2210 ral_hi = 0; 2211 } 2212 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2213 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2214 } 2215 2216 /* 2217 * dge_mchash: 2218 * 2219 * Compute the hash of the multicast address for the 4096-bit 2220 * multicast filter. 2221 */ 2222 static uint32_t 2223 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2224 { 2225 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2226 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2227 uint32_t hash; 2228 2229 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2230 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2231 2232 return (hash & 0xfff); 2233 } 2234 2235 /* 2236 * dge_set_filter: 2237 * 2238 * Set up the receive filter. 2239 */ 2240 static void 2241 dge_set_filter(struct dge_softc *sc) 2242 { 2243 struct ethercom *ec = &sc->sc_ethercom; 2244 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2245 struct ether_multi *enm; 2246 struct ether_multistep step; 2247 uint32_t hash, reg, bit; 2248 int i; 2249 2250 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2251 2252 if (ifp->if_flags & IFF_BROADCAST) 2253 sc->sc_rctl |= RCTL_BAM; 2254 if (ifp->if_flags & IFF_PROMISC) { 2255 sc->sc_rctl |= RCTL_UPE; 2256 goto allmulti; 2257 } 2258 2259 /* 2260 * Set the station address in the first RAL slot, and 2261 * clear the remaining slots. 2262 */ 2263 dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 2264 for (i = 1; i < RA_TABSIZE; i++) 2265 dge_set_ral(sc, NULL, i); 2266 2267 /* Clear out the multicast table. */ 2268 for (i = 0; i < MC_TABSIZE; i++) 2269 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2270 2271 ETHER_FIRST_MULTI(step, ec, enm); 2272 while (enm != NULL) { 2273 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2274 /* 2275 * We must listen to a range of multicast addresses. 2276 * For now, just accept all multicasts, rather than 2277 * trying to set only those filter bits needed to match 2278 * the range. (At this time, the only use of address 2279 * ranges is for IP multicast routing, for which the 2280 * range is big enough to require all bits set.) 2281 */ 2282 goto allmulti; 2283 } 2284 2285 hash = dge_mchash(sc, enm->enm_addrlo); 2286 2287 reg = (hash >> 5) & 0x7f; 2288 bit = hash & 0x1f; 2289 2290 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2291 hash |= 1U << bit; 2292 2293 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2294 2295 ETHER_NEXT_MULTI(step, enm); 2296 } 2297 2298 ifp->if_flags &= ~IFF_ALLMULTI; 2299 goto setit; 2300 2301 allmulti: 2302 ifp->if_flags |= IFF_ALLMULTI; 2303 sc->sc_rctl |= RCTL_MPE; 2304 2305 setit: 2306 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2307 } 2308 2309 /* 2310 * Read in the EEPROM info and verify checksum. 2311 */ 2312 int 2313 dge_read_eeprom(struct dge_softc *sc) 2314 { 2315 uint16_t cksum; 2316 int i; 2317 2318 cksum = 0; 2319 for (i = 0; i < EEPROM_SIZE; i++) { 2320 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2321 cksum += sc->sc_eeprom[i]; 2322 } 2323 return cksum != EEPROM_CKSUM; 2324 } 2325 2326 2327 /* 2328 * Read a 16-bit word from address addr in the serial EEPROM. 2329 */ 2330 uint16_t 2331 dge_eeprom_word(struct dge_softc *sc, int addr) 2332 { 2333 uint32_t reg; 2334 uint16_t rval = 0; 2335 int i; 2336 2337 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2338 2339 /* Lower clock pulse (and data in to chip) */ 2340 CSR_WRITE(sc, DGE_EECD, reg); 2341 /* Select chip */ 2342 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2343 2344 /* Send read command */ 2345 dge_eeprom_clockout(sc, 1); 2346 dge_eeprom_clockout(sc, 1); 2347 dge_eeprom_clockout(sc, 0); 2348 2349 /* Send address */ 2350 for (i = 5; i >= 0; i--) 2351 dge_eeprom_clockout(sc, (addr >> i) & 1); 2352 2353 /* Read data */ 2354 for (i = 0; i < 16; i++) { 2355 rval <<= 1; 2356 rval |= dge_eeprom_clockin(sc); 2357 } 2358 2359 /* Deselect chip */ 2360 CSR_WRITE(sc, DGE_EECD, reg); 2361 2362 return rval; 2363 } 2364 2365 /* 2366 * Clock out a single bit to the EEPROM. 2367 */ 2368 void 2369 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2370 { 2371 int reg; 2372 2373 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2374 if (bit) 2375 reg |= EECD_DI; 2376 2377 CSR_WRITE(sc, DGE_EECD, reg); 2378 delay(2); 2379 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2380 delay(2); 2381 CSR_WRITE(sc, DGE_EECD, reg); 2382 delay(2); 2383 } 2384 2385 /* 2386 * Clock in a single bit from EEPROM. 2387 */ 2388 int 2389 dge_eeprom_clockin(struct dge_softc *sc) 2390 { 2391 int reg, rv; 2392 2393 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2394 2395 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2396 delay(2); 2397 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2398 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2399 delay(2); 2400 2401 return rv; 2402 } 2403 2404 static void 2405 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2406 { 2407 struct dge_softc *sc = ifp->if_softc; 2408 2409 ifmr->ifm_status = IFM_AVALID; 2410 if (sc->sc_dgep->dgep_flags & DGEP_F_10G_SR ) { 2411 ifmr->ifm_active = IFM_ETHER|IFM_10G_SR; 2412 } else { 2413 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2414 } 2415 2416 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2417 ifmr->ifm_status |= IFM_ACTIVE; 2418 } 2419 2420 static inline int 2421 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2422 { 2423 int i, mdic; 2424 2425 CSR_WRITE(sc, DGE_MDIO, 2426 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2427 for (i = 0; i < 10; i++) { 2428 delay(10); 2429 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2430 break; 2431 } 2432 return mdic; 2433 } 2434 2435 static void 2436 dge_xgmii_writereg(struct dge_softc *sc, int phy, int reg, int val) 2437 { 2438 int mdic; 2439 2440 CSR_WRITE(sc, DGE_MDIRW, val); 2441 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2442 printf("%s: address cycle timeout; phy %d reg %d\n", 2443 device_xname(sc->sc_dev), phy, reg); 2444 return; 2445 } 2446 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2447 printf("%s: write cycle timeout; phy %d reg %d\n", 2448 device_xname(sc->sc_dev), phy, reg); 2449 return; 2450 } 2451 } 2452 2453 static void 2454 dge_xgmii_reset(struct dge_softc *sc) 2455 { 2456 dge_xgmii_writereg(sc, 0, 0, BMCR_RESET); 2457 } 2458 2459 static int 2460 dge_xgmii_mediachange(struct ifnet *ifp) 2461 { 2462 return 0; 2463 } 2464