1 /* $NetBSD: if_dge.c,v 1.55 2019/05/29 10:07:29 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.55 2019/05/29 10:07:29 msaitoh Exp $"); 84 85 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 #include <sys/rndsource.h> 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 #include <net/bpf.h> 105 106 #include <netinet/in.h> /* XXX for struct ip */ 107 #include <netinet/in_systm.h> /* XXX for struct ip */ 108 #include <netinet/ip.h> /* XXX for struct ip */ 109 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 110 111 #include <sys/bus.h> 112 #include <sys/intr.h> 113 #include <machine/endian.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/miivar.h> 117 #include <dev/mii/mii_bitbang.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pcidevs.h> 122 123 #include <dev/pci/if_dgereg.h> 124 125 /* 126 * The receive engine may sometimes become off-by-one when writing back 127 * chained descriptors. Avoid this by allocating a large chunk of 128 * memory and use if instead (to avoid chained descriptors). 129 * This only happens with chained descriptors under heavy load. 130 */ 131 #define DGE_OFFBYONE_RXBUG 132 133 #define DGE_EVENT_COUNTERS 134 #define DGE_DEBUG 135 136 #ifdef DGE_DEBUG 137 #define DGE_DEBUG_LINK 0x01 138 #define DGE_DEBUG_TX 0x02 139 #define DGE_DEBUG_RX 0x04 140 #define DGE_DEBUG_CKSUM 0x08 141 int dge_debug = 0; 142 143 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 144 #else 145 #define DPRINTF(x, y) /* nothing */ 146 #endif /* DGE_DEBUG */ 147 148 /* 149 * Transmit descriptor list size. We allow up to 100 DMA segments per 150 * packet (Intel reports of jumbo frame packets with as 151 * many as 80 DMA segments when using 16k buffers). 152 */ 153 #define DGE_NTXSEGS 100 154 #define DGE_IFQUEUELEN 20000 155 #define DGE_TXQUEUELEN 2048 156 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 157 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 158 #define DGE_NTXDESC 1024 159 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 160 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 161 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 162 163 /* 164 * Receive descriptor list size. 165 * Packet is of size MCLBYTES, and for jumbo packets buffers may 166 * be chained. Due to the nature of the card (high-speed), keep this 167 * ring large. With 2k buffers the ring can store 400 jumbo packets, 168 * which at full speed will be received in just under 3ms. 169 */ 170 #define DGE_NRXDESC 2048 171 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 172 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 173 /* 174 * # of descriptors between head and written descriptors. 175 * This is to work-around two erratas. 176 */ 177 #define DGE_RXSPACE 10 178 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 179 /* 180 * Receive descriptor fetch threshholds. These are values recommended 181 * by Intel, do not touch them unless you know what you are doing. 182 */ 183 #define RXDCTL_PTHRESH_VAL 128 184 #define RXDCTL_HTHRESH_VAL 16 185 #define RXDCTL_WTHRESH_VAL 16 186 187 188 /* 189 * Tweakable parameters; default values. 190 */ 191 #define FCRTH 0x30000 /* Send XOFF water mark */ 192 #define FCRTL 0x28000 /* Send XON water mark */ 193 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 194 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 195 196 /* 197 * Control structures are DMA'd to the i82597 chip. We allocate them in 198 * a single clump that maps to a single DMA segment to make serveral things 199 * easier. 200 */ 201 struct dge_control_data { 202 /* 203 * The transmit descriptors. 204 */ 205 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 206 207 /* 208 * The receive descriptors. 209 */ 210 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 211 }; 212 213 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 214 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 215 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 216 217 /* 218 * The DGE interface have a higher max MTU size than normal jumbo frames. 219 */ 220 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 221 222 /* 223 * Software state for transmit jobs. 224 */ 225 struct dge_txsoft { 226 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 227 bus_dmamap_t txs_dmamap; /* our DMA map */ 228 int txs_firstdesc; /* first descriptor in packet */ 229 int txs_lastdesc; /* last descriptor in packet */ 230 int txs_ndesc; /* # of descriptors used */ 231 }; 232 233 /* 234 * Software state for receive buffers. Each descriptor gets a 235 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 236 * more than one buffer, we chain them together. 237 */ 238 struct dge_rxsoft { 239 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 240 bus_dmamap_t rxs_dmamap; /* our DMA map */ 241 }; 242 243 /* 244 * Software state per device. 245 */ 246 struct dge_softc { 247 device_t sc_dev; /* generic device information */ 248 bus_space_tag_t sc_st; /* bus space tag */ 249 bus_space_handle_t sc_sh; /* bus space handle */ 250 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 251 struct ethercom sc_ethercom; /* ethernet common data */ 252 253 int sc_flags; /* flags; see below */ 254 int sc_bus_speed; /* PCI/PCIX bus speed */ 255 int sc_pcix_offset; /* PCIX capability register offset */ 256 257 const struct dge_product *sc_dgep; /* Pointer to the dge_product entry */ 258 pci_chipset_tag_t sc_pc; 259 pcitag_t sc_pt; 260 int sc_mmrbc; /* Max PCIX memory read byte count */ 261 262 void *sc_ih; /* interrupt cookie */ 263 264 struct ifmedia sc_media; 265 266 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 267 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 268 269 int sc_align_tweak; 270 271 /* 272 * Software state for the transmit and receive descriptors. 273 */ 274 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 275 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 276 277 /* 278 * Control data structures. 279 */ 280 struct dge_control_data *sc_control_data; 281 #define sc_txdescs sc_control_data->wcd_txdescs 282 #define sc_rxdescs sc_control_data->wcd_rxdescs 283 284 #ifdef DGE_EVENT_COUNTERS 285 /* Event counters. */ 286 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 287 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 288 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 289 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 290 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 291 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 292 struct evcnt sc_ev_linkintr; /* Link interrupts */ 293 294 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 295 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 296 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 297 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 298 299 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 300 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 301 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 302 303 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 304 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 305 #endif /* DGE_EVENT_COUNTERS */ 306 307 int sc_txfree; /* number of free Tx descriptors */ 308 int sc_txnext; /* next ready Tx descriptor */ 309 310 int sc_txsfree; /* number of free Tx jobs */ 311 int sc_txsnext; /* next free Tx job */ 312 int sc_txsdirty; /* dirty Tx jobs */ 313 314 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 315 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 316 317 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 318 int sc_rxdiscard; 319 int sc_rxlen; 320 struct mbuf *sc_rxhead; 321 struct mbuf *sc_rxtail; 322 struct mbuf **sc_rxtailp; 323 324 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 325 uint32_t sc_icr; /* prototype interrupt bits */ 326 uint32_t sc_tctl; /* prototype TCTL register */ 327 uint32_t sc_rctl; /* prototype RCTL register */ 328 329 int sc_mchash_type; /* multicast filter offset */ 330 331 uint16_t sc_eeprom[EEPROM_SIZE]; 332 333 krndsource_t rnd_source; /* random source */ 334 #ifdef DGE_OFFBYONE_RXBUG 335 void *sc_bugbuf; 336 SLIST_HEAD(, rxbugentry) sc_buglist; 337 bus_dmamap_t sc_bugmap; 338 struct rxbugentry *sc_entry; 339 #endif 340 }; 341 342 #define DGE_RXCHAIN_RESET(sc) \ 343 do { \ 344 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 345 *(sc)->sc_rxtailp = NULL; \ 346 (sc)->sc_rxlen = 0; \ 347 } while (/*CONSTCOND*/0) 348 349 #define DGE_RXCHAIN_LINK(sc, m) \ 350 do { \ 351 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 352 (sc)->sc_rxtailp = &(m)->m_next; \ 353 } while (/*CONSTCOND*/0) 354 355 /* sc_flags */ 356 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 357 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 358 359 #ifdef DGE_EVENT_COUNTERS 360 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 361 #else 362 #define DGE_EVCNT_INCR(ev) /* nothing */ 363 #endif 364 365 #define CSR_READ(sc, reg) \ 366 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 367 #define CSR_WRITE(sc, reg, val) \ 368 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 369 370 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 371 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 372 373 #define DGE_CDTXSYNC(sc, x, n, ops) \ 374 do { \ 375 int __x, __n; \ 376 \ 377 __x = (x); \ 378 __n = (n); \ 379 \ 380 /* If it will wrap around, sync to the end of the ring. */ \ 381 if ((__x + __n) > DGE_NTXDESC) { \ 382 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 383 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 384 (DGE_NTXDESC - __x), (ops)); \ 385 __n -= (DGE_NTXDESC - __x); \ 386 __x = 0; \ 387 } \ 388 \ 389 /* Now sync whatever is left. */ \ 390 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 391 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 392 } while (/*CONSTCOND*/0) 393 394 #define DGE_CDRXSYNC(sc, x, ops) \ 395 do { \ 396 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 397 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 398 } while (/*CONSTCOND*/0) 399 400 #ifdef DGE_OFFBYONE_RXBUG 401 #define DGE_INIT_RXDESC(sc, x) \ 402 do { \ 403 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 404 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 405 struct mbuf *__m = __rxs->rxs_mbuf; \ 406 \ 407 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 408 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 409 __rxd->dr_baddrh = 0; \ 410 __rxd->dr_len = 0; \ 411 __rxd->dr_cksum = 0; \ 412 __rxd->dr_status = 0; \ 413 __rxd->dr_errors = 0; \ 414 __rxd->dr_special = 0; \ 415 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 416 \ 417 CSR_WRITE((sc), DGE_RDT, (x)); \ 418 } while (/*CONSTCOND*/0) 419 #else 420 #define DGE_INIT_RXDESC(sc, x) \ 421 do { \ 422 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 423 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 424 struct mbuf *__m = __rxs->rxs_mbuf; \ 425 \ 426 /* \ 427 * Note: We scoot the packet forward 2 bytes in the buffer \ 428 * so that the payload after the Ethernet header is aligned \ 429 * to a 4-byte boundary. \ 430 * \ 431 * XXX BRAINDAMAGE ALERT! \ 432 * The stupid chip uses the same size for every buffer, which \ 433 * is set in the Receive Control register. We are using the 2K \ 434 * size option, but what we REALLY want is (2K - 2)! For this \ 435 * reason, we can't "scoot" packets longer than the standard \ 436 * Ethernet MTU. On strict-alignment platforms, if the total \ 437 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 438 * the upper layer copy the headers. \ 439 */ \ 440 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 441 \ 442 __rxd->dr_baddrl = \ 443 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 444 (sc)->sc_align_tweak); \ 445 __rxd->dr_baddrh = 0; \ 446 __rxd->dr_len = 0; \ 447 __rxd->dr_cksum = 0; \ 448 __rxd->dr_status = 0; \ 449 __rxd->dr_errors = 0; \ 450 __rxd->dr_special = 0; \ 451 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 452 \ 453 CSR_WRITE((sc), DGE_RDT, (x)); \ 454 } while (/*CONSTCOND*/0) 455 #endif 456 457 #ifdef DGE_OFFBYONE_RXBUG 458 /* 459 * Allocation constants. Much memory may be used for this. 460 */ 461 #ifndef DGE_BUFFER_SIZE 462 #define DGE_BUFFER_SIZE DGE_MAX_MTU 463 #endif 464 #define DGE_NBUFFERS (4*DGE_NRXDESC) 465 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 466 467 struct rxbugentry { 468 SLIST_ENTRY(rxbugentry) rb_entry; 469 int rb_slot; 470 }; 471 472 static int 473 dge_alloc_rcvmem(struct dge_softc *sc) 474 { 475 char *kva; 476 bus_dma_segment_t seg; 477 int i, rseg, state, error; 478 struct rxbugentry *entry; 479 480 state = error = 0; 481 482 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 483 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 484 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 485 return ENOBUFS; 486 } 487 488 state = 1; 489 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, 490 BUS_DMA_NOWAIT)) { 491 aprint_error_dev(sc->sc_dev, 492 "can't map DMA buffers (%d bytes)\n", (int)DGE_RXMEM); 493 error = ENOBUFS; 494 goto out; 495 } 496 497 state = 2; 498 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 499 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 500 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 501 error = ENOBUFS; 502 goto out; 503 } 504 505 state = 3; 506 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 507 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 508 aprint_error_dev(sc->sc_dev, "can't load DMA map\n"); 509 error = ENOBUFS; 510 goto out; 511 } 512 513 state = 4; 514 sc->sc_bugbuf = (void *)kva; 515 SLIST_INIT(&sc->sc_buglist); 516 517 /* 518 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 519 * in an array. 520 */ 521 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 522 M_DEVBUF, M_NOWAIT)) == NULL) { 523 error = ENOBUFS; 524 goto out; 525 } 526 sc->sc_entry = entry; 527 for (i = 0; i < DGE_NBUFFERS; i++) { 528 entry[i].rb_slot = i; 529 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 530 } 531 out: 532 if (error != 0) { 533 switch (state) { 534 case 4: 535 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 536 /* FALLTHROUGH */ 537 case 3: 538 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 539 /* FALLTHROUGH */ 540 case 2: 541 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 542 /* FALLTHROUGH */ 543 case 1: 544 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 545 break; 546 default: 547 break; 548 } 549 } 550 551 return error; 552 } 553 554 /* 555 * Allocate a jumbo buffer. 556 */ 557 static void * 558 dge_getbuf(struct dge_softc *sc) 559 { 560 struct rxbugentry *entry; 561 562 entry = SLIST_FIRST(&sc->sc_buglist); 563 564 if (entry == NULL) { 565 printf("%s: no free RX buffers\n", device_xname(sc->sc_dev)); 566 return NULL; 567 } 568 569 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 570 return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 571 } 572 573 /* 574 * Release a jumbo buffer. 575 */ 576 static void 577 dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) 578 { 579 struct rxbugentry *entry; 580 struct dge_softc *sc; 581 int i, s; 582 583 /* Extract the softc struct pointer. */ 584 sc = (struct dge_softc *)arg; 585 586 if (sc == NULL) 587 panic("dge_freebuf: can't find softc pointer!"); 588 589 /* calculate the slot this buffer belongs to */ 590 591 i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; 592 593 if ((i < 0) || (i >= DGE_NBUFFERS)) 594 panic("dge_freebuf: asked to free buffer %d!", i); 595 596 s = splvm(); 597 entry = sc->sc_entry + i; 598 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 599 600 if (__predict_true(m != NULL)) 601 pool_cache_put(mb_cache, m); 602 splx(s); 603 } 604 #endif 605 606 static void dge_start(struct ifnet *); 607 static void dge_watchdog(struct ifnet *); 608 static int dge_ioctl(struct ifnet *, u_long, void *); 609 static int dge_init(struct ifnet *); 610 static void dge_stop(struct ifnet *, int); 611 612 static bool dge_shutdown(device_t, int); 613 614 static void dge_reset(struct dge_softc *); 615 static void dge_rxdrain(struct dge_softc *); 616 static int dge_add_rxbuf(struct dge_softc *, int); 617 618 static void dge_set_filter(struct dge_softc *); 619 620 static int dge_intr(void *); 621 static void dge_txintr(struct dge_softc *); 622 static void dge_rxintr(struct dge_softc *); 623 static void dge_linkintr(struct dge_softc *, uint32_t); 624 625 static int dge_match(device_t, cfdata_t, void *); 626 static void dge_attach(device_t, device_t, void *); 627 628 static int dge_read_eeprom(struct dge_softc *sc); 629 static int dge_eeprom_clockin(struct dge_softc *sc); 630 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 631 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 632 static int dge_xgmii_mediachange(struct ifnet *); 633 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 634 static void dge_xgmii_reset(struct dge_softc *); 635 static void dge_xgmii_writereg(struct dge_softc *, int, int, int); 636 637 638 CFATTACH_DECL_NEW(dge, sizeof(struct dge_softc), 639 dge_match, dge_attach, NULL, NULL); 640 641 #ifdef DGE_EVENT_COUNTERS 642 #if DGE_NTXSEGS > 100 643 #error Update dge_txseg_evcnt_names 644 #endif 645 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 646 #endif /* DGE_EVENT_COUNTERS */ 647 648 /* 649 * Devices supported by this driver. 650 */ 651 static const struct dge_product { 652 pci_vendor_id_t dgep_vendor; 653 pci_product_id_t dgep_product; 654 const char *dgep_name; 655 int dgep_flags; 656 #define DGEP_F_10G_LR 0x01 657 #define DGEP_F_10G_SR 0x02 658 } dge_products[] = { 659 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX, 660 "Intel i82597EX 10GbE-LR Ethernet", 661 DGEP_F_10G_LR }, 662 663 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_SR, 664 "Intel i82597EX 10GbE-SR Ethernet", 665 DGEP_F_10G_SR }, 666 667 { 0, 0, 668 NULL, 669 0 }, 670 }; 671 672 static const struct dge_product * 673 dge_lookup(const struct pci_attach_args *pa) 674 { 675 const struct dge_product *dgep; 676 677 for (dgep = dge_products; dgep->dgep_name != NULL; dgep++) { 678 if (PCI_VENDOR(pa->pa_id) == dgep->dgep_vendor && 679 PCI_PRODUCT(pa->pa_id) == dgep->dgep_product) 680 return dgep; 681 } 682 return NULL; 683 } 684 685 static int 686 dge_match(device_t parent, cfdata_t cf, void *aux) 687 { 688 struct pci_attach_args *pa = aux; 689 690 if (dge_lookup(pa) != NULL) 691 return 1; 692 693 return 0; 694 } 695 696 static void 697 dge_attach(device_t parent, device_t self, void *aux) 698 { 699 struct dge_softc *sc = device_private(self); 700 struct pci_attach_args *pa = aux; 701 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 702 pci_chipset_tag_t pc = pa->pa_pc; 703 pci_intr_handle_t ih; 704 const char *intrstr = NULL; 705 bus_dma_segment_t seg; 706 int i, rseg, error; 707 uint8_t enaddr[ETHER_ADDR_LEN]; 708 pcireg_t preg, memtype; 709 uint32_t reg; 710 char intrbuf[PCI_INTRSTR_LEN]; 711 const struct dge_product *dgep; 712 713 sc->sc_dgep = dgep = dge_lookup(pa); 714 if (dgep == NULL) { 715 printf("\n"); 716 panic("dge_attach: impossible"); 717 } 718 719 sc->sc_dev = self; 720 sc->sc_dmat = pa->pa_dmat; 721 sc->sc_pc = pa->pa_pc; 722 sc->sc_pt = pa->pa_tag; 723 724 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 725 dgep->dgep_name, 1); 726 727 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 728 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 729 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 730 aprint_error_dev(sc->sc_dev, 731 "unable to map device registers\n"); 732 return; 733 } 734 735 /* Enable bus mastering */ 736 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 737 preg |= PCI_COMMAND_MASTER_ENABLE; 738 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 739 740 /* 741 * Map and establish our interrupt. 742 */ 743 if (pci_intr_map(pa, &ih)) { 744 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 745 return; 746 } 747 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 748 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, dge_intr, sc, 749 device_xname(self)); 750 if (sc->sc_ih == NULL) { 751 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 752 if (intrstr != NULL) 753 aprint_error(" at %s", intrstr); 754 aprint_error("\n"); 755 return; 756 } 757 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 758 759 /* 760 * Determine a few things about the bus we're connected to. 761 */ 762 reg = CSR_READ(sc, DGE_STATUS); 763 if (reg & STATUS_BUS64) 764 sc->sc_flags |= DGE_F_BUS64; 765 766 sc->sc_flags |= DGE_F_PCIX; 767 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 768 PCI_CAP_PCIX, 769 &sc->sc_pcix_offset, NULL) == 0) 770 aprint_error_dev(sc->sc_dev, "unable to find PCIX " 771 "capability\n"); 772 773 if (sc->sc_flags & DGE_F_PCIX) { 774 switch (reg & STATUS_PCIX_MSK) { 775 case STATUS_PCIX_66: 776 sc->sc_bus_speed = 66; 777 break; 778 case STATUS_PCIX_100: 779 sc->sc_bus_speed = 100; 780 break; 781 case STATUS_PCIX_133: 782 sc->sc_bus_speed = 133; 783 break; 784 default: 785 aprint_error_dev(sc->sc_dev, 786 "unknown PCIXSPD %d; assuming 66MHz\n", 787 reg & STATUS_PCIX_MSK); 788 sc->sc_bus_speed = 66; 789 } 790 } else 791 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 792 aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", 793 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 794 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 795 796 /* 797 * Allocate the control data structures, and create and load the 798 * DMA map for it. 799 */ 800 if ((error = bus_dmamem_alloc(sc->sc_dmat, 801 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 802 0)) != 0) { 803 aprint_error_dev(sc->sc_dev, 804 "unable to allocate control data, error = %d\n", 805 error); 806 goto fail_0; 807 } 808 809 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 810 sizeof(struct dge_control_data), (void **)&sc->sc_control_data, 811 0)) != 0) { 812 aprint_error_dev(sc->sc_dev, 813 "unable to map control data, error = %d\n", error); 814 goto fail_1; 815 } 816 817 if ((error = bus_dmamap_create(sc->sc_dmat, 818 sizeof(struct dge_control_data), 1, 819 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 820 aprint_error_dev(sc->sc_dev, "unable to create control data " 821 "DMA map, error = %d\n", error); 822 goto fail_2; 823 } 824 825 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 826 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 827 0)) != 0) { 828 aprint_error_dev(sc->sc_dev, 829 "unable to load control data DMA map, error = %d\n", 830 error); 831 goto fail_3; 832 } 833 834 #ifdef DGE_OFFBYONE_RXBUG 835 if (dge_alloc_rcvmem(sc) != 0) 836 return; /* Already complained */ 837 #endif 838 /* 839 * Create the transmit buffer DMA maps. 840 */ 841 for (i = 0; i < DGE_TXQUEUELEN; i++) { 842 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 843 DGE_NTXSEGS, MCLBYTES, 0, 0, 844 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 845 aprint_error_dev(sc->sc_dev, "unable to create Tx DMA map %d, " 846 "error = %d\n", i, error); 847 goto fail_4; 848 } 849 } 850 851 /* 852 * Create the receive buffer DMA maps. 853 */ 854 for (i = 0; i < DGE_NRXDESC; i++) { 855 #ifdef DGE_OFFBYONE_RXBUG 856 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 857 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 858 #else 859 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 860 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 861 #endif 862 aprint_error_dev(sc->sc_dev, "unable to create Rx DMA " 863 "map %d, error = %d\n", i, error); 864 goto fail_5; 865 } 866 sc->sc_rxsoft[i].rxs_mbuf = NULL; 867 } 868 869 /* 870 * Set bits in ctrl0 register. 871 * Should get the software defined pins out of EEPROM? 872 */ 873 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 874 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 875 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 876 877 /* 878 * Reset the chip to a known state. 879 */ 880 dge_reset(sc); 881 882 /* 883 * Reset the PHY. 884 */ 885 dge_xgmii_reset(sc); 886 887 /* 888 * Read in EEPROM data. 889 */ 890 if (dge_read_eeprom(sc)) { 891 aprint_error_dev(sc->sc_dev, "couldn't read EEPROM\n"); 892 return; 893 } 894 895 /* 896 * Get the ethernet address. 897 */ 898 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 899 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 900 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 901 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 902 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 903 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 904 905 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 906 ether_sprintf(enaddr)); 907 908 /* 909 * Setup media stuff. 910 */ 911 sc->sc_ethercom.ec_ifmedia = &sc->sc_media; 912 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 913 dge_xgmii_mediastatus); 914 if (dgep->dgep_flags & DGEP_F_10G_SR) { 915 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_SR, 0, NULL); 916 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10G_SR); 917 } else { /* XXX default is LR */ 918 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_LR, 0, NULL); 919 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10G_LR); 920 } 921 922 ifp = &sc->sc_ethercom.ec_if; 923 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 924 ifp->if_softc = sc; 925 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 926 ifp->if_ioctl = dge_ioctl; 927 ifp->if_start = dge_start; 928 ifp->if_watchdog = dge_watchdog; 929 ifp->if_init = dge_init; 930 ifp->if_stop = dge_stop; 931 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(DGE_IFQUEUELEN, IFQ_MAXLEN)); 932 IFQ_SET_READY(&ifp->if_snd); 933 934 sc->sc_ethercom.ec_capabilities |= 935 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 936 937 /* 938 * We can perform TCPv4 and UDPv4 checkums in-bound. 939 */ 940 ifp->if_capabilities |= 941 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 942 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 943 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 944 945 /* 946 * Attach the interface. 947 */ 948 if_attach(ifp); 949 if_deferred_start_init(ifp, NULL); 950 ether_ifattach(ifp, enaddr); 951 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 952 RND_TYPE_NET, RND_FLAG_DEFAULT); 953 954 #ifdef DGE_EVENT_COUNTERS 955 /* Fix segment event naming */ 956 if (dge_txseg_evcnt_names == NULL) { 957 dge_txseg_evcnt_names = 958 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 959 for (i = 0; i < DGE_NTXSEGS; i++) 960 snprintf((*dge_txseg_evcnt_names)[i], 961 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 962 } 963 964 /* Attach event counters. */ 965 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 966 NULL, device_xname(sc->sc_dev), "txsstall"); 967 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 968 NULL, device_xname(sc->sc_dev), "txdstall"); 969 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 970 NULL, device_xname(sc->sc_dev), "txforceintr"); 971 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 972 NULL, device_xname(sc->sc_dev), "txdw"); 973 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 974 NULL, device_xname(sc->sc_dev), "txqe"); 975 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 976 NULL, device_xname(sc->sc_dev), "rxintr"); 977 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 978 NULL, device_xname(sc->sc_dev), "linkintr"); 979 980 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 981 NULL, device_xname(sc->sc_dev), "rxipsum"); 982 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 983 NULL, device_xname(sc->sc_dev), "rxtusum"); 984 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 985 NULL, device_xname(sc->sc_dev), "txipsum"); 986 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 987 NULL, device_xname(sc->sc_dev), "txtusum"); 988 989 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 990 NULL, device_xname(sc->sc_dev), "txctx init"); 991 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 992 NULL, device_xname(sc->sc_dev), "txctx hit"); 993 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 994 NULL, device_xname(sc->sc_dev), "txctx miss"); 995 996 for (i = 0; i < DGE_NTXSEGS; i++) 997 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 998 NULL, device_xname(sc->sc_dev), (*dge_txseg_evcnt_names)[i]); 999 1000 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1001 NULL, device_xname(sc->sc_dev), "txdrop"); 1002 1003 #endif /* DGE_EVENT_COUNTERS */ 1004 1005 /* 1006 * Make sure the interface is shutdown during reboot. 1007 */ 1008 if (pmf_device_register1(self, NULL, NULL, dge_shutdown)) 1009 pmf_class_network_register(self, ifp); 1010 else 1011 aprint_error_dev(self, "couldn't establish power handler\n"); 1012 1013 return; 1014 1015 /* 1016 * Free any resources we've allocated during the failed attach 1017 * attempt. Do this in reverse order and fall through. 1018 */ 1019 fail_5: 1020 for (i = 0; i < DGE_NRXDESC; i++) { 1021 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1022 bus_dmamap_destroy(sc->sc_dmat, 1023 sc->sc_rxsoft[i].rxs_dmamap); 1024 } 1025 fail_4: 1026 for (i = 0; i < DGE_TXQUEUELEN; i++) { 1027 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1028 bus_dmamap_destroy(sc->sc_dmat, 1029 sc->sc_txsoft[i].txs_dmamap); 1030 } 1031 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1032 fail_3: 1033 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1034 fail_2: 1035 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1036 sizeof(struct dge_control_data)); 1037 fail_1: 1038 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1039 fail_0: 1040 return; 1041 } 1042 1043 /* 1044 * dge_shutdown: 1045 * 1046 * Make sure the interface is stopped at reboot time. 1047 */ 1048 static bool 1049 dge_shutdown(device_t self, int howto) 1050 { 1051 struct dge_softc *sc; 1052 1053 sc = device_private(self); 1054 dge_stop(&sc->sc_ethercom.ec_if, 1); 1055 1056 return true; 1057 } 1058 1059 /* 1060 * dge_tx_cksum: 1061 * 1062 * Set up TCP/IP checksumming parameters for the 1063 * specified packet. 1064 */ 1065 static int 1066 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1067 { 1068 struct mbuf *m0 = txs->txs_mbuf; 1069 struct dge_ctdes *t; 1070 uint32_t ipcs, tucs; 1071 struct ether_header *eh; 1072 int offset, iphl; 1073 uint8_t fields = 0; 1074 1075 /* 1076 * XXX It would be nice if the mbuf pkthdr had offset 1077 * fields for the protocol headers. 1078 */ 1079 1080 eh = mtod(m0, struct ether_header *); 1081 switch (htons(eh->ether_type)) { 1082 case ETHERTYPE_IP: 1083 offset = ETHER_HDR_LEN; 1084 break; 1085 1086 case ETHERTYPE_VLAN: 1087 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1088 break; 1089 1090 default: 1091 /* 1092 * Don't support this protocol or encapsulation. 1093 */ 1094 *fieldsp = 0; 1095 return 0; 1096 } 1097 1098 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1099 1100 /* 1101 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1102 * offload feature, if we load the context descriptor, we 1103 * MUST provide valid values for IPCSS and TUCSS fields. 1104 */ 1105 1106 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1107 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1108 fields |= TDESC_POPTS_IXSM; 1109 ipcs = DGE_TCPIP_IPCSS(offset) | 1110 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1111 DGE_TCPIP_IPCSE(offset + iphl - 1); 1112 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1113 /* Use the cached value. */ 1114 ipcs = sc->sc_txctx_ipcs; 1115 } else { 1116 /* Just initialize it to the likely value anyway. */ 1117 ipcs = DGE_TCPIP_IPCSS(offset) | 1118 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1119 DGE_TCPIP_IPCSE(offset + iphl - 1); 1120 } 1121 DPRINTF(DGE_DEBUG_CKSUM, 1122 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1123 device_xname(sc->sc_dev), offset, ipcs)); 1124 1125 offset += iphl; 1126 1127 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1128 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1129 fields |= TDESC_POPTS_TXSM; 1130 tucs = DGE_TCPIP_TUCSS(offset) | 1131 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1132 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1133 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1134 /* Use the cached value. */ 1135 tucs = sc->sc_txctx_tucs; 1136 } else { 1137 /* Just initialize it to a valid TCP context. */ 1138 tucs = DGE_TCPIP_TUCSS(offset) | 1139 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1140 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1141 } 1142 1143 DPRINTF(DGE_DEBUG_CKSUM, 1144 ("%s: CKSUM: offset %d tucs 0x%x\n", 1145 device_xname(sc->sc_dev), offset, tucs)); 1146 1147 if (sc->sc_txctx_ipcs == ipcs && 1148 sc->sc_txctx_tucs == tucs) { 1149 /* Cached context is fine. */ 1150 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1151 } else { 1152 /* Fill in the context descriptor. */ 1153 #ifdef DGE_EVENT_COUNTERS 1154 if (sc->sc_txctx_ipcs == 0xffffffff && 1155 sc->sc_txctx_tucs == 0xffffffff) 1156 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1157 else 1158 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1159 #endif 1160 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1161 t->dc_tcpip_ipcs = htole32(ipcs); 1162 t->dc_tcpip_tucs = htole32(tucs); 1163 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1164 t->dc_tcpip_seg = 0; 1165 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1166 1167 sc->sc_txctx_ipcs = ipcs; 1168 sc->sc_txctx_tucs = tucs; 1169 1170 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1171 txs->txs_ndesc++; 1172 } 1173 1174 *fieldsp = fields; 1175 1176 return 0; 1177 } 1178 1179 /* 1180 * dge_start: [ifnet interface function] 1181 * 1182 * Start packet transmission on the interface. 1183 */ 1184 static void 1185 dge_start(struct ifnet *ifp) 1186 { 1187 struct dge_softc *sc = ifp->if_softc; 1188 struct mbuf *m0; 1189 struct dge_txsoft *txs; 1190 bus_dmamap_t dmamap; 1191 int error, nexttx, lasttx = -1, ofree, seg; 1192 uint32_t cksumcmd; 1193 uint8_t cksumfields; 1194 1195 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1196 return; 1197 1198 /* 1199 * Remember the previous number of free descriptors. 1200 */ 1201 ofree = sc->sc_txfree; 1202 1203 /* 1204 * Loop through the send queue, setting up transmit descriptors 1205 * until we drain the queue, or use up all available transmit 1206 * descriptors. 1207 */ 1208 for (;;) { 1209 /* Grab a packet off the queue. */ 1210 IFQ_POLL(&ifp->if_snd, m0); 1211 if (m0 == NULL) 1212 break; 1213 1214 DPRINTF(DGE_DEBUG_TX, 1215 ("%s: TX: have packet to transmit: %p\n", 1216 device_xname(sc->sc_dev), m0)); 1217 1218 /* Get a work queue entry. */ 1219 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1220 dge_txintr(sc); 1221 if (sc->sc_txsfree == 0) { 1222 DPRINTF(DGE_DEBUG_TX, 1223 ("%s: TX: no free job descriptors\n", 1224 device_xname(sc->sc_dev))); 1225 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1226 break; 1227 } 1228 } 1229 1230 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1231 dmamap = txs->txs_dmamap; 1232 1233 /* 1234 * Load the DMA map. If this fails, the packet either 1235 * didn't fit in the allotted number of segments, or we 1236 * were short on resources. For the too-many-segments 1237 * case, we simply report an error and drop the packet, 1238 * since we can't sanely copy a jumbo packet to a single 1239 * buffer. 1240 */ 1241 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1242 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1243 if (error) { 1244 if (error == EFBIG) { 1245 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1246 printf("%s: Tx packet consumes too many " 1247 "DMA segments, dropping...\n", 1248 device_xname(sc->sc_dev)); 1249 IFQ_DEQUEUE(&ifp->if_snd, m0); 1250 m_freem(m0); 1251 continue; 1252 } 1253 /* 1254 * Short on resources, just stop for now. 1255 */ 1256 DPRINTF(DGE_DEBUG_TX, 1257 ("%s: TX: dmamap load failed: %d\n", 1258 device_xname(sc->sc_dev), error)); 1259 break; 1260 } 1261 1262 /* 1263 * Ensure we have enough descriptors free to describe 1264 * the packet. Note, we always reserve one descriptor 1265 * at the end of the ring due to the semantics of the 1266 * TDT register, plus one more in the event we need 1267 * to re-load checksum offload context. 1268 */ 1269 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1270 /* 1271 * Not enough free descriptors to transmit this 1272 * packet. We haven't committed anything yet, 1273 * so just unload the DMA map, put the packet 1274 * pack on the queue, and punt. Notify the upper 1275 * layer that there are no more slots left. 1276 */ 1277 DPRINTF(DGE_DEBUG_TX, 1278 ("%s: TX: need %d descriptors, have %d\n", 1279 device_xname(sc->sc_dev), dmamap->dm_nsegs, 1280 sc->sc_txfree - 1)); 1281 ifp->if_flags |= IFF_OACTIVE; 1282 bus_dmamap_unload(sc->sc_dmat, dmamap); 1283 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1284 break; 1285 } 1286 1287 IFQ_DEQUEUE(&ifp->if_snd, m0); 1288 1289 /* 1290 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1291 */ 1292 1293 /* Sync the DMA map. */ 1294 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1295 BUS_DMASYNC_PREWRITE); 1296 1297 DPRINTF(DGE_DEBUG_TX, 1298 ("%s: TX: packet has %d DMA segments\n", 1299 device_xname(sc->sc_dev), dmamap->dm_nsegs)); 1300 1301 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1302 1303 /* 1304 * Store a pointer to the packet so that we can free it 1305 * later. 1306 * 1307 * Initially, we consider the number of descriptors the 1308 * packet uses the number of DMA segments. This may be 1309 * incremented by 1 if we do checksum offload (a descriptor 1310 * is used to set the checksum context). 1311 */ 1312 txs->txs_mbuf = m0; 1313 txs->txs_firstdesc = sc->sc_txnext; 1314 txs->txs_ndesc = dmamap->dm_nsegs; 1315 1316 /* 1317 * Set up checksum offload parameters for 1318 * this packet. 1319 */ 1320 if (m0->m_pkthdr.csum_flags & 1321 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1322 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1323 /* Error message already displayed. */ 1324 bus_dmamap_unload(sc->sc_dmat, dmamap); 1325 continue; 1326 } 1327 } else { 1328 cksumfields = 0; 1329 } 1330 1331 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1332 1333 /* 1334 * Initialize the transmit descriptor. 1335 */ 1336 for (nexttx = sc->sc_txnext, seg = 0; 1337 seg < dmamap->dm_nsegs; 1338 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1339 /* 1340 * Note: we currently only use 32-bit DMA 1341 * addresses. 1342 */ 1343 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1344 sc->sc_txdescs[nexttx].dt_baddrl = 1345 htole32(dmamap->dm_segs[seg].ds_addr); 1346 sc->sc_txdescs[nexttx].dt_ctl = 1347 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1348 sc->sc_txdescs[nexttx].dt_status = 0; 1349 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1350 sc->sc_txdescs[nexttx].dt_vlan = 0; 1351 lasttx = nexttx; 1352 1353 DPRINTF(DGE_DEBUG_TX, 1354 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1355 device_xname(sc->sc_dev), nexttx, 1356 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_addr), 1357 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_len))); 1358 } 1359 1360 KASSERT(lasttx != -1); 1361 1362 /* 1363 * Set up the command byte on the last descriptor of 1364 * the packet. If we're in the interrupt delay window, 1365 * delay the interrupt. 1366 */ 1367 sc->sc_txdescs[lasttx].dt_ctl |= 1368 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1369 1370 txs->txs_lastdesc = lasttx; 1371 1372 DPRINTF(DGE_DEBUG_TX, 1373 ("%s: TX: desc %d: cmdlen 0x%08x\n", device_xname(sc->sc_dev), 1374 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1375 1376 /* Sync the descriptors we're using. */ 1377 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1378 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1379 1380 /* Give the packet to the chip. */ 1381 CSR_WRITE(sc, DGE_TDT, nexttx); 1382 1383 DPRINTF(DGE_DEBUG_TX, 1384 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 1385 1386 DPRINTF(DGE_DEBUG_TX, 1387 ("%s: TX: finished transmitting packet, job %d\n", 1388 device_xname(sc->sc_dev), sc->sc_txsnext)); 1389 1390 /* Advance the tx pointer. */ 1391 sc->sc_txfree -= txs->txs_ndesc; 1392 sc->sc_txnext = nexttx; 1393 1394 sc->sc_txsfree--; 1395 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1396 1397 /* Pass the packet to any BPF listeners. */ 1398 bpf_mtap(ifp, m0, BPF_D_OUT); 1399 } 1400 1401 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1402 /* No more slots; notify upper layer. */ 1403 ifp->if_flags |= IFF_OACTIVE; 1404 } 1405 1406 if (sc->sc_txfree != ofree) { 1407 /* Set a watchdog timer in case the chip flakes out. */ 1408 ifp->if_timer = 5; 1409 } 1410 } 1411 1412 /* 1413 * dge_watchdog: [ifnet interface function] 1414 * 1415 * Watchdog timer handler. 1416 */ 1417 static void 1418 dge_watchdog(struct ifnet *ifp) 1419 { 1420 struct dge_softc *sc = ifp->if_softc; 1421 1422 /* 1423 * Since we're using delayed interrupts, sweep up 1424 * before we report an error. 1425 */ 1426 dge_txintr(sc); 1427 1428 if (sc->sc_txfree != DGE_NTXDESC) { 1429 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1430 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, 1431 sc->sc_txnext); 1432 ifp->if_oerrors++; 1433 1434 /* Reset the interface. */ 1435 (void) dge_init(ifp); 1436 } 1437 1438 /* Try to get more packets going. */ 1439 dge_start(ifp); 1440 } 1441 1442 /* 1443 * dge_ioctl: [ifnet interface function] 1444 * 1445 * Handle control requests from the operator. 1446 */ 1447 static int 1448 dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1449 { 1450 struct dge_softc *sc = ifp->if_softc; 1451 struct ifreq *ifr = (struct ifreq *) data; 1452 pcireg_t preg; 1453 int s, error, mmrbc; 1454 1455 s = splnet(); 1456 1457 switch (cmd) { 1458 case SIOCSIFMTU: 1459 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) 1460 error = EINVAL; 1461 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1462 break; 1463 else if (ifp->if_flags & IFF_UP) 1464 error = (*ifp->if_init)(ifp); 1465 else 1466 error = 0; 1467 break; 1468 1469 case SIOCSIFFLAGS: 1470 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1471 break; 1472 /* extract link flags */ 1473 if ((ifp->if_flags & IFF_LINK0) == 0 && 1474 (ifp->if_flags & IFF_LINK1) == 0) 1475 mmrbc = PCIX_MMRBC_512; 1476 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1477 (ifp->if_flags & IFF_LINK1) != 0) 1478 mmrbc = PCIX_MMRBC_1024; 1479 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1480 (ifp->if_flags & IFF_LINK1) == 0) 1481 mmrbc = PCIX_MMRBC_2048; 1482 else 1483 mmrbc = PCIX_MMRBC_4096; 1484 if (mmrbc != sc->sc_mmrbc) { 1485 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1486 preg &= ~PCIX_MMRBC_MSK; 1487 preg |= mmrbc; 1488 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1489 sc->sc_mmrbc = mmrbc; 1490 } 1491 /* FALLTHROUGH */ 1492 default: 1493 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1494 break; 1495 1496 error = 0; 1497 1498 if (cmd == SIOCSIFCAP) 1499 error = (*ifp->if_init)(ifp); 1500 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1501 ; 1502 else if (ifp->if_flags & IFF_RUNNING) { 1503 /* 1504 * Multicast list has changed; set the hardware filter 1505 * accordingly. 1506 */ 1507 dge_set_filter(sc); 1508 } 1509 break; 1510 } 1511 1512 /* Try to get more packets going. */ 1513 dge_start(ifp); 1514 1515 splx(s); 1516 return error; 1517 } 1518 1519 /* 1520 * dge_intr: 1521 * 1522 * Interrupt service routine. 1523 */ 1524 static int 1525 dge_intr(void *arg) 1526 { 1527 struct dge_softc *sc = arg; 1528 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1529 uint32_t icr; 1530 int wantinit, handled = 0; 1531 1532 for (wantinit = 0; wantinit == 0;) { 1533 icr = CSR_READ(sc, DGE_ICR); 1534 if ((icr & sc->sc_icr) == 0) 1535 break; 1536 1537 rnd_add_uint32(&sc->rnd_source, icr); 1538 1539 handled = 1; 1540 1541 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1542 if (icr & (ICR_RXDMT0 | ICR_RXT0)) { 1543 DPRINTF(DGE_DEBUG_RX, 1544 ("%s: RX: got Rx intr 0x%08x\n", 1545 device_xname(sc->sc_dev), 1546 icr & (ICR_RXDMT0 | ICR_RXT0))); 1547 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1548 } 1549 #endif 1550 dge_rxintr(sc); 1551 1552 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1553 if (icr & ICR_TXDW) { 1554 DPRINTF(DGE_DEBUG_TX, 1555 ("%s: TX: got TXDW interrupt\n", 1556 device_xname(sc->sc_dev))); 1557 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1558 } 1559 if (icr & ICR_TXQE) 1560 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1561 #endif 1562 dge_txintr(sc); 1563 1564 if (icr & (ICR_LSC | ICR_RXSEQ)) { 1565 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1566 dge_linkintr(sc, icr); 1567 } 1568 1569 if (icr & ICR_RXO) { 1570 printf("%s: Receive overrun\n", 1571 device_xname(sc->sc_dev)); 1572 wantinit = 1; 1573 } 1574 } 1575 1576 if (handled) { 1577 if (wantinit) 1578 dge_init(ifp); 1579 1580 /* Try to get more packets going. */ 1581 if_schedule_deferred_start(ifp); 1582 } 1583 1584 return handled; 1585 } 1586 1587 /* 1588 * dge_txintr: 1589 * 1590 * Helper; handle transmit interrupts. 1591 */ 1592 static void 1593 dge_txintr(struct dge_softc *sc) 1594 { 1595 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1596 struct dge_txsoft *txs; 1597 uint8_t status; 1598 int i; 1599 1600 ifp->if_flags &= ~IFF_OACTIVE; 1601 1602 /* 1603 * Go through the Tx list and free mbufs for those 1604 * frames which have been transmitted. 1605 */ 1606 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1607 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1608 txs = &sc->sc_txsoft[i]; 1609 1610 DPRINTF(DGE_DEBUG_TX, 1611 ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i)); 1612 1613 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1614 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1615 1616 status = 1617 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1618 if ((status & TDESC_STA_DD) == 0) { 1619 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1620 BUS_DMASYNC_PREREAD); 1621 break; 1622 } 1623 1624 DPRINTF(DGE_DEBUG_TX, 1625 ("%s: TX: job %d done: descs %d..%d\n", 1626 device_xname(sc->sc_dev), i, txs->txs_firstdesc, 1627 txs->txs_lastdesc)); 1628 1629 ifp->if_opackets++; 1630 sc->sc_txfree += txs->txs_ndesc; 1631 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1632 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1633 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1634 m_freem(txs->txs_mbuf); 1635 txs->txs_mbuf = NULL; 1636 } 1637 1638 /* Update the dirty transmit buffer pointer. */ 1639 sc->sc_txsdirty = i; 1640 DPRINTF(DGE_DEBUG_TX, 1641 ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i)); 1642 1643 /* 1644 * If there are no more pending transmissions, cancel the watchdog 1645 * timer. 1646 */ 1647 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1648 ifp->if_timer = 0; 1649 } 1650 1651 /* 1652 * dge_rxintr: 1653 * 1654 * Helper; handle receive interrupts. 1655 */ 1656 static void 1657 dge_rxintr(struct dge_softc *sc) 1658 { 1659 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1660 struct dge_rxsoft *rxs; 1661 struct mbuf *m; 1662 int i, len; 1663 uint8_t status, errors; 1664 1665 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1666 rxs = &sc->sc_rxsoft[i]; 1667 1668 DPRINTF(DGE_DEBUG_RX, 1669 ("%s: RX: checking descriptor %d\n", 1670 device_xname(sc->sc_dev), i)); 1671 1672 DGE_CDRXSYNC(sc, i, 1673 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1674 1675 status = sc->sc_rxdescs[i].dr_status; 1676 errors = sc->sc_rxdescs[i].dr_errors; 1677 len = le16toh(sc->sc_rxdescs[i].dr_len); 1678 1679 if ((status & RDESC_STS_DD) == 0) { 1680 /* We have processed all of the receive descriptors. */ 1681 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1682 break; 1683 } 1684 1685 if (__predict_false(sc->sc_rxdiscard)) { 1686 DPRINTF(DGE_DEBUG_RX, 1687 ("%s: RX: discarding contents of descriptor %d\n", 1688 device_xname(sc->sc_dev), i)); 1689 DGE_INIT_RXDESC(sc, i); 1690 if (status & RDESC_STS_EOP) { 1691 /* Reset our state. */ 1692 DPRINTF(DGE_DEBUG_RX, 1693 ("%s: RX: resetting rxdiscard -> 0\n", 1694 device_xname(sc->sc_dev))); 1695 sc->sc_rxdiscard = 0; 1696 } 1697 continue; 1698 } 1699 1700 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1701 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1702 1703 m = rxs->rxs_mbuf; 1704 1705 /* 1706 * Add a new receive buffer to the ring. 1707 */ 1708 if (dge_add_rxbuf(sc, i) != 0) { 1709 /* 1710 * Failed, throw away what we've done so 1711 * far, and discard the rest of the packet. 1712 */ 1713 ifp->if_ierrors++; 1714 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1715 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1716 DGE_INIT_RXDESC(sc, i); 1717 if ((status & RDESC_STS_EOP) == 0) 1718 sc->sc_rxdiscard = 1; 1719 if (sc->sc_rxhead != NULL) 1720 m_freem(sc->sc_rxhead); 1721 DGE_RXCHAIN_RESET(sc); 1722 DPRINTF(DGE_DEBUG_RX, 1723 ("%s: RX: Rx buffer allocation failed, " 1724 "dropping packet%s\n", device_xname(sc->sc_dev), 1725 sc->sc_rxdiscard ? " (discard)" : "")); 1726 continue; 1727 } 1728 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1729 1730 DGE_RXCHAIN_LINK(sc, m); 1731 1732 m->m_len = len; 1733 1734 DPRINTF(DGE_DEBUG_RX, 1735 ("%s: RX: buffer at %p len %d\n", 1736 device_xname(sc->sc_dev), m->m_data, len)); 1737 1738 /* 1739 * If this is not the end of the packet, keep 1740 * looking. 1741 */ 1742 if ((status & RDESC_STS_EOP) == 0) { 1743 sc->sc_rxlen += len; 1744 DPRINTF(DGE_DEBUG_RX, 1745 ("%s: RX: not yet EOP, rxlen -> %d\n", 1746 device_xname(sc->sc_dev), sc->sc_rxlen)); 1747 continue; 1748 } 1749 1750 /* 1751 * Okay, we have the entire packet now... 1752 */ 1753 *sc->sc_rxtailp = NULL; 1754 m = sc->sc_rxhead; 1755 len += sc->sc_rxlen; 1756 1757 DGE_RXCHAIN_RESET(sc); 1758 1759 DPRINTF(DGE_DEBUG_RX, 1760 ("%s: RX: have entire packet, len -> %d\n", 1761 device_xname(sc->sc_dev), len)); 1762 1763 /* 1764 * If an error occurred, update stats and drop the packet. 1765 */ 1766 if (errors & (RDESC_ERR_CE | RDESC_ERR_SE | RDESC_ERR_P | 1767 RDESC_ERR_RXE)) { 1768 ifp->if_ierrors++; 1769 if (errors & RDESC_ERR_SE) 1770 printf("%s: symbol error\n", 1771 device_xname(sc->sc_dev)); 1772 else if (errors & RDESC_ERR_P) 1773 printf("%s: parity error\n", 1774 device_xname(sc->sc_dev)); 1775 else if (errors & RDESC_ERR_CE) 1776 printf("%s: CRC error\n", 1777 device_xname(sc->sc_dev)); 1778 m_freem(m); 1779 continue; 1780 } 1781 1782 /* 1783 * No errors. Receive the packet. 1784 */ 1785 m_set_rcvif(m, ifp); 1786 m->m_pkthdr.len = len; 1787 1788 /* 1789 * Set up checksum info for this packet. 1790 */ 1791 if (status & RDESC_STS_IPCS) { 1792 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1793 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1794 if (errors & RDESC_ERR_IPE) 1795 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1796 } 1797 if (status & RDESC_STS_TCPCS) { 1798 /* 1799 * Note: we don't know if this was TCP or UDP, 1800 * so we just set both bits, and expect the 1801 * upper layers to deal. 1802 */ 1803 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1804 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4 | M_CSUM_UDPv4; 1805 if (errors & RDESC_ERR_TCPE) 1806 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1807 } 1808 1809 /* Pass it on. */ 1810 if_percpuq_enqueue(ifp->if_percpuq, m); 1811 } 1812 1813 /* Update the receive pointer. */ 1814 sc->sc_rxptr = i; 1815 1816 DPRINTF(DGE_DEBUG_RX, 1817 ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i)); 1818 } 1819 1820 /* 1821 * dge_linkintr: 1822 * 1823 * Helper; handle link interrupts. 1824 */ 1825 static void 1826 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1827 { 1828 uint32_t status; 1829 1830 if (icr & ICR_LSC) { 1831 status = CSR_READ(sc, DGE_STATUS); 1832 if (status & STATUS_LINKUP) { 1833 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1834 device_xname(sc->sc_dev))); 1835 } else { 1836 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1837 device_xname(sc->sc_dev))); 1838 } 1839 } else if (icr & ICR_RXSEQ) { 1840 DPRINTF(DGE_DEBUG_LINK, 1841 ("%s: LINK: Receive sequence error\n", 1842 device_xname(sc->sc_dev))); 1843 } 1844 /* XXX - fix errata */ 1845 } 1846 1847 /* 1848 * dge_reset: 1849 * 1850 * Reset the i82597 chip. 1851 */ 1852 static void 1853 dge_reset(struct dge_softc *sc) 1854 { 1855 int i; 1856 1857 /* 1858 * Do a chip reset. 1859 */ 1860 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1861 1862 delay(10000); 1863 1864 for (i = 0; i < 1000; i++) { 1865 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1866 break; 1867 delay(20); 1868 } 1869 1870 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1871 printf("%s: WARNING: reset failed to complete\n", 1872 device_xname(sc->sc_dev)); 1873 /* 1874 * Reset the EEPROM logic. 1875 * This will cause the chip to reread its default values, 1876 * which doesn't happen otherwise (errata). 1877 */ 1878 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1879 delay(10000); 1880 } 1881 1882 /* 1883 * dge_init: [ifnet interface function] 1884 * 1885 * Initialize the interface. Must be called at splnet(). 1886 */ 1887 static int 1888 dge_init(struct ifnet *ifp) 1889 { 1890 struct dge_softc *sc = ifp->if_softc; 1891 struct dge_rxsoft *rxs; 1892 int i, error = 0; 1893 uint32_t reg; 1894 1895 /* 1896 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1897 * There is a small but measurable benefit to avoiding the adjusment 1898 * of the descriptor so that the headers are aligned, for normal mtu, 1899 * on such platforms. One possibility is that the DMA itself is 1900 * slightly more efficient if the front of the entire packet (instead 1901 * of the front of the headers) is aligned. 1902 * 1903 * Note we must always set align_tweak to 0 if we are using 1904 * jumbo frames. 1905 */ 1906 #ifdef __NO_STRICT_ALIGNMENT 1907 sc->sc_align_tweak = 0; 1908 #else 1909 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1910 sc->sc_align_tweak = 0; 1911 else 1912 sc->sc_align_tweak = 2; 1913 #endif /* __NO_STRICT_ALIGNMENT */ 1914 1915 /* Cancel any pending I/O. */ 1916 dge_stop(ifp, 0); 1917 1918 /* Reset the chip to a known state. */ 1919 dge_reset(sc); 1920 1921 /* Initialize the transmit descriptor ring. */ 1922 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1923 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1925 sc->sc_txfree = DGE_NTXDESC; 1926 sc->sc_txnext = 0; 1927 1928 sc->sc_txctx_ipcs = 0xffffffff; 1929 sc->sc_txctx_tucs = 0xffffffff; 1930 1931 CSR_WRITE(sc, DGE_TDBAH, 0); 1932 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1933 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1934 CSR_WRITE(sc, DGE_TDH, 0); 1935 CSR_WRITE(sc, DGE_TDT, 0); 1936 CSR_WRITE(sc, DGE_TIDV, TIDV); 1937 1938 #if 0 1939 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1940 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1941 #endif 1942 CSR_WRITE(sc, DGE_RXDCTL, 1943 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1944 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1945 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1946 1947 /* Initialize the transmit job descriptors. */ 1948 for (i = 0; i < DGE_TXQUEUELEN; i++) 1949 sc->sc_txsoft[i].txs_mbuf = NULL; 1950 sc->sc_txsfree = DGE_TXQUEUELEN; 1951 sc->sc_txsnext = 0; 1952 sc->sc_txsdirty = 0; 1953 1954 /* 1955 * Initialize the receive descriptor and receive job 1956 * descriptor rings. 1957 */ 1958 CSR_WRITE(sc, DGE_RDBAH, 0); 1959 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1960 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1961 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1962 CSR_WRITE(sc, DGE_RDT, 0); 1963 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1964 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1965 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1966 1967 for (i = 0; i < DGE_NRXDESC; i++) { 1968 rxs = &sc->sc_rxsoft[i]; 1969 if (rxs->rxs_mbuf == NULL) { 1970 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1971 printf("%s: unable to allocate or map rx " 1972 "buffer %d, error = %d\n", 1973 device_xname(sc->sc_dev), i, error); 1974 /* 1975 * XXX Should attempt to run with fewer receive 1976 * XXX buffers instead of just failing. 1977 */ 1978 dge_rxdrain(sc); 1979 goto out; 1980 } 1981 } 1982 DGE_INIT_RXDESC(sc, i); 1983 } 1984 sc->sc_rxptr = DGE_RXSPACE; 1985 sc->sc_rxdiscard = 0; 1986 DGE_RXCHAIN_RESET(sc); 1987 1988 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1989 sc->sc_ctrl0 |= CTRL0_JFE; 1990 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1991 } 1992 1993 /* Write the control registers. */ 1994 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1995 1996 /* 1997 * Set up checksum offload parameters. 1998 */ 1999 reg = CSR_READ(sc, DGE_RXCSUM); 2000 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2001 reg |= RXCSUM_IPOFL; 2002 else 2003 reg &= ~RXCSUM_IPOFL; 2004 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2005 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2006 else { 2007 reg &= ~RXCSUM_TUOFL; 2008 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2009 reg &= ~RXCSUM_IPOFL; 2010 } 2011 CSR_WRITE(sc, DGE_RXCSUM, reg); 2012 2013 /* 2014 * Set up the interrupt registers. 2015 */ 2016 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 2017 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2018 ICR_RXO | ICR_RXT0; 2019 2020 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 2021 2022 /* 2023 * Set up the transmit control register. 2024 */ 2025 sc->sc_tctl = TCTL_TCE | TCTL_TPDE | TCTL_TXEN; 2026 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 2027 2028 /* 2029 * Set up the receive control register; we actually program 2030 * the register when we set the receive filter. Use multicast 2031 * address offset type 0. 2032 */ 2033 sc->sc_mchash_type = 0; 2034 2035 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2036 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2037 2038 #ifdef DGE_OFFBYONE_RXBUG 2039 sc->sc_rctl |= RCTL_BSIZE_16k; 2040 #else 2041 switch (MCLBYTES) { 2042 case 2048: 2043 sc->sc_rctl |= RCTL_BSIZE_2k; 2044 break; 2045 case 4096: 2046 sc->sc_rctl |= RCTL_BSIZE_4k; 2047 break; 2048 case 8192: 2049 sc->sc_rctl |= RCTL_BSIZE_8k; 2050 break; 2051 case 16384: 2052 sc->sc_rctl |= RCTL_BSIZE_16k; 2053 break; 2054 default: 2055 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2056 } 2057 #endif 2058 2059 /* Set the receive filter. */ 2060 /* Also sets RCTL */ 2061 dge_set_filter(sc); 2062 2063 /* ...all done! */ 2064 ifp->if_flags |= IFF_RUNNING; 2065 ifp->if_flags &= ~IFF_OACTIVE; 2066 2067 out: 2068 if (error) 2069 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2070 return error; 2071 } 2072 2073 /* 2074 * dge_rxdrain: 2075 * 2076 * Drain the receive queue. 2077 */ 2078 static void 2079 dge_rxdrain(struct dge_softc *sc) 2080 { 2081 struct dge_rxsoft *rxs; 2082 int i; 2083 2084 for (i = 0; i < DGE_NRXDESC; i++) { 2085 rxs = &sc->sc_rxsoft[i]; 2086 if (rxs->rxs_mbuf != NULL) { 2087 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2088 m_freem(rxs->rxs_mbuf); 2089 rxs->rxs_mbuf = NULL; 2090 } 2091 } 2092 } 2093 2094 /* 2095 * dge_stop: [ifnet interface function] 2096 * 2097 * Stop transmission on the interface. 2098 */ 2099 static void 2100 dge_stop(struct ifnet *ifp, int disable) 2101 { 2102 struct dge_softc *sc = ifp->if_softc; 2103 struct dge_txsoft *txs; 2104 int i; 2105 2106 /* Stop the transmit and receive processes. */ 2107 CSR_WRITE(sc, DGE_TCTL, 0); 2108 CSR_WRITE(sc, DGE_RCTL, 0); 2109 2110 /* Release any queued transmit buffers. */ 2111 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2112 txs = &sc->sc_txsoft[i]; 2113 if (txs->txs_mbuf != NULL) { 2114 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2115 m_freem(txs->txs_mbuf); 2116 txs->txs_mbuf = NULL; 2117 } 2118 } 2119 2120 /* Mark the interface as down and cancel the watchdog timer. */ 2121 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2122 ifp->if_timer = 0; 2123 2124 if (disable) 2125 dge_rxdrain(sc); 2126 } 2127 2128 /* 2129 * dge_add_rxbuf: 2130 * 2131 * Add a receive buffer to the indiciated descriptor. 2132 */ 2133 static int 2134 dge_add_rxbuf(struct dge_softc *sc, int idx) 2135 { 2136 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2137 struct mbuf *m; 2138 int error; 2139 #ifdef DGE_OFFBYONE_RXBUG 2140 void *buf; 2141 #endif 2142 2143 MGETHDR(m, M_DONTWAIT, MT_DATA); 2144 if (m == NULL) 2145 return ENOBUFS; 2146 2147 #ifdef DGE_OFFBYONE_RXBUG 2148 if ((buf = dge_getbuf(sc)) == NULL) 2149 return ENOBUFS; 2150 2151 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2152 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2153 m->m_flags |= M_EXT_RW; 2154 2155 if (rxs->rxs_mbuf != NULL) 2156 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2157 rxs->rxs_mbuf = m; 2158 2159 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2160 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 2161 #else 2162 MCLGET(m, M_DONTWAIT); 2163 if ((m->m_flags & M_EXT) == 0) { 2164 m_freem(m); 2165 return ENOBUFS; 2166 } 2167 2168 if (rxs->rxs_mbuf != NULL) 2169 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2170 2171 rxs->rxs_mbuf = m; 2172 2173 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2174 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2175 BUS_DMA_READ | BUS_DMA_NOWAIT); 2176 #endif 2177 if (error) { 2178 printf("%s: unable to load rx DMA map %d, error = %d\n", 2179 device_xname(sc->sc_dev), idx, error); 2180 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2181 } 2182 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2183 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2184 2185 return 0; 2186 } 2187 2188 /* 2189 * dge_set_ral: 2190 * 2191 * Set an entry in the receive address list. 2192 */ 2193 static void 2194 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2195 { 2196 uint32_t ral_lo, ral_hi; 2197 2198 if (enaddr != NULL) { 2199 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2200 (enaddr[3] << 24); 2201 ral_hi = enaddr[4] | (enaddr[5] << 8); 2202 ral_hi |= RAH_AV; 2203 } else { 2204 ral_lo = 0; 2205 ral_hi = 0; 2206 } 2207 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2208 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2209 } 2210 2211 /* 2212 * dge_mchash: 2213 * 2214 * Compute the hash of the multicast address for the 4096-bit 2215 * multicast filter. 2216 */ 2217 static uint32_t 2218 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2219 { 2220 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2221 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2222 uint32_t hash; 2223 2224 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2225 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2226 2227 return (hash & 0xfff); 2228 } 2229 2230 /* 2231 * dge_set_filter: 2232 * 2233 * Set up the receive filter. 2234 */ 2235 static void 2236 dge_set_filter(struct dge_softc *sc) 2237 { 2238 struct ethercom *ec = &sc->sc_ethercom; 2239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2240 struct ether_multi *enm; 2241 struct ether_multistep step; 2242 uint32_t hash, reg, bit; 2243 int i; 2244 2245 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2246 2247 if (ifp->if_flags & IFF_BROADCAST) 2248 sc->sc_rctl |= RCTL_BAM; 2249 if (ifp->if_flags & IFF_PROMISC) { 2250 sc->sc_rctl |= RCTL_UPE; 2251 goto allmulti; 2252 } 2253 2254 /* 2255 * Set the station address in the first RAL slot, and 2256 * clear the remaining slots. 2257 */ 2258 dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 2259 for (i = 1; i < RA_TABSIZE; i++) 2260 dge_set_ral(sc, NULL, i); 2261 2262 /* Clear out the multicast table. */ 2263 for (i = 0; i < MC_TABSIZE; i++) 2264 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2265 2266 ETHER_LOCK(ec); 2267 ETHER_FIRST_MULTI(step, ec, enm); 2268 while (enm != NULL) { 2269 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2270 /* 2271 * We must listen to a range of multicast addresses. 2272 * For now, just accept all multicasts, rather than 2273 * trying to set only those filter bits needed to match 2274 * the range. (At this time, the only use of address 2275 * ranges is for IP multicast routing, for which the 2276 * range is big enough to require all bits set.) 2277 */ 2278 ETHER_UNLOCK(ec); 2279 goto allmulti; 2280 } 2281 2282 hash = dge_mchash(sc, enm->enm_addrlo); 2283 2284 reg = (hash >> 5) & 0x7f; 2285 bit = hash & 0x1f; 2286 2287 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2288 hash |= 1U << bit; 2289 2290 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2291 2292 ETHER_NEXT_MULTI(step, enm); 2293 } 2294 ETHER_UNLOCK(ec); 2295 2296 ifp->if_flags &= ~IFF_ALLMULTI; 2297 goto setit; 2298 2299 allmulti: 2300 ifp->if_flags |= IFF_ALLMULTI; 2301 sc->sc_rctl |= RCTL_MPE; 2302 2303 setit: 2304 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2305 } 2306 2307 /* 2308 * Read in the EEPROM info and verify checksum. 2309 */ 2310 int 2311 dge_read_eeprom(struct dge_softc *sc) 2312 { 2313 uint16_t cksum; 2314 int i; 2315 2316 cksum = 0; 2317 for (i = 0; i < EEPROM_SIZE; i++) { 2318 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2319 cksum += sc->sc_eeprom[i]; 2320 } 2321 return cksum != EEPROM_CKSUM; 2322 } 2323 2324 2325 /* 2326 * Read a 16-bit word from address addr in the serial EEPROM. 2327 */ 2328 uint16_t 2329 dge_eeprom_word(struct dge_softc *sc, int addr) 2330 { 2331 uint32_t reg; 2332 uint16_t rval = 0; 2333 int i; 2334 2335 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK | EECD_DI | EECD_CS); 2336 2337 /* Lower clock pulse (and data in to chip) */ 2338 CSR_WRITE(sc, DGE_EECD, reg); 2339 /* Select chip */ 2340 CSR_WRITE(sc, DGE_EECD, reg | EECD_CS); 2341 2342 /* Send read command */ 2343 dge_eeprom_clockout(sc, 1); 2344 dge_eeprom_clockout(sc, 1); 2345 dge_eeprom_clockout(sc, 0); 2346 2347 /* Send address */ 2348 for (i = 5; i >= 0; i--) 2349 dge_eeprom_clockout(sc, (addr >> i) & 1); 2350 2351 /* Read data */ 2352 for (i = 0; i < 16; i++) { 2353 rval <<= 1; 2354 rval |= dge_eeprom_clockin(sc); 2355 } 2356 2357 /* Deselect chip */ 2358 CSR_WRITE(sc, DGE_EECD, reg); 2359 2360 return rval; 2361 } 2362 2363 /* 2364 * Clock out a single bit to the EEPROM. 2365 */ 2366 void 2367 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2368 { 2369 int reg; 2370 2371 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_SK); 2372 if (bit) 2373 reg |= EECD_DI; 2374 2375 CSR_WRITE(sc, DGE_EECD, reg); 2376 delay(2); 2377 CSR_WRITE(sc, DGE_EECD, reg | EECD_SK); 2378 delay(2); 2379 CSR_WRITE(sc, DGE_EECD, reg); 2380 delay(2); 2381 } 2382 2383 /* 2384 * Clock in a single bit from EEPROM. 2385 */ 2386 int 2387 dge_eeprom_clockin(struct dge_softc *sc) 2388 { 2389 int reg, rv; 2390 2391 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_DO | EECD_SK); 2392 2393 CSR_WRITE(sc, DGE_EECD, reg | EECD_SK); /* Raise clock */ 2394 delay(2); 2395 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2396 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2397 delay(2); 2398 2399 return rv; 2400 } 2401 2402 static void 2403 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2404 { 2405 struct dge_softc *sc = ifp->if_softc; 2406 2407 ifmr->ifm_status = IFM_AVALID; 2408 if (sc->sc_dgep->dgep_flags & DGEP_F_10G_SR ) { 2409 ifmr->ifm_active = IFM_ETHER | IFM_10G_SR; 2410 } else { 2411 ifmr->ifm_active = IFM_ETHER | IFM_10G_LR; 2412 } 2413 2414 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2415 ifmr->ifm_status |= IFM_ACTIVE; 2416 } 2417 2418 static inline int 2419 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2420 { 2421 int i, mdic; 2422 2423 CSR_WRITE(sc, DGE_MDIO, 2424 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2425 for (i = 0; i < 10; i++) { 2426 delay(10); 2427 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2428 break; 2429 } 2430 return mdic; 2431 } 2432 2433 static void 2434 dge_xgmii_writereg(struct dge_softc *sc, int phy, int reg, int val) 2435 { 2436 int mdic; 2437 2438 CSR_WRITE(sc, DGE_MDIRW, val); 2439 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2440 printf("%s: address cycle timeout; phy %d reg %d\n", 2441 device_xname(sc->sc_dev), phy, reg); 2442 return; 2443 } 2444 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2445 printf("%s: write cycle timeout; phy %d reg %d\n", 2446 device_xname(sc->sc_dev), phy, reg); 2447 return; 2448 } 2449 } 2450 2451 static void 2452 dge_xgmii_reset(struct dge_softc *sc) 2453 { 2454 dge_xgmii_writereg(sc, 0, 0, BMCR_RESET); 2455 } 2456 2457 static int 2458 dge_xgmii_mediachange(struct ifnet *ifp) 2459 { 2460 return 0; 2461 } 2462