1 /* $NetBSD: if_dge.c,v 1.36 2013/10/17 21:06:15 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.36 2013/10/17 21:06:15 christos Exp $"); 84 85 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 99 #include <sys/rnd.h> 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #include <net/bpf.h> 107 108 #include <netinet/in.h> /* XXX for struct ip */ 109 #include <netinet/in_systm.h> /* XXX for struct ip */ 110 #include <netinet/ip.h> /* XXX for struct ip */ 111 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 112 113 #include <sys/bus.h> 114 #include <sys/intr.h> 115 #include <machine/endian.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 #include <dev/mii/mii_bitbang.h> 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/pci/if_dgereg.h> 126 127 /* 128 * The receive engine may sometimes become off-by-one when writing back 129 * chained descriptors. Avoid this by allocating a large chunk of 130 * memory and use if instead (to avoid chained descriptors). 131 * This only happens with chained descriptors under heavy load. 132 */ 133 #define DGE_OFFBYONE_RXBUG 134 135 #define DGE_EVENT_COUNTERS 136 #define DGE_DEBUG 137 138 #ifdef DGE_DEBUG 139 #define DGE_DEBUG_LINK 0x01 140 #define DGE_DEBUG_TX 0x02 141 #define DGE_DEBUG_RX 0x04 142 #define DGE_DEBUG_CKSUM 0x08 143 int dge_debug = 0; 144 145 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 146 #else 147 #define DPRINTF(x, y) /* nothing */ 148 #endif /* DGE_DEBUG */ 149 150 /* 151 * Transmit descriptor list size. We allow up to 100 DMA segments per 152 * packet (Intel reports of jumbo frame packets with as 153 * many as 80 DMA segments when using 16k buffers). 154 */ 155 #define DGE_NTXSEGS 100 156 #define DGE_IFQUEUELEN 20000 157 #define DGE_TXQUEUELEN 2048 158 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 159 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 160 #define DGE_NTXDESC 1024 161 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 162 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 163 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 164 165 /* 166 * Receive descriptor list size. 167 * Packet is of size MCLBYTES, and for jumbo packets buffers may 168 * be chained. Due to the nature of the card (high-speed), keep this 169 * ring large. With 2k buffers the ring can store 400 jumbo packets, 170 * which at full speed will be received in just under 3ms. 171 */ 172 #define DGE_NRXDESC 2048 173 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 174 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 175 /* 176 * # of descriptors between head and written descriptors. 177 * This is to work-around two erratas. 178 */ 179 #define DGE_RXSPACE 10 180 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 181 /* 182 * Receive descriptor fetch threshholds. These are values recommended 183 * by Intel, do not touch them unless you know what you are doing. 184 */ 185 #define RXDCTL_PTHRESH_VAL 128 186 #define RXDCTL_HTHRESH_VAL 16 187 #define RXDCTL_WTHRESH_VAL 16 188 189 190 /* 191 * Tweakable parameters; default values. 192 */ 193 #define FCRTH 0x30000 /* Send XOFF water mark */ 194 #define FCRTL 0x28000 /* Send XON water mark */ 195 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 196 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 197 198 /* 199 * Control structures are DMA'd to the i82597 chip. We allocate them in 200 * a single clump that maps to a single DMA segment to make serveral things 201 * easier. 202 */ 203 struct dge_control_data { 204 /* 205 * The transmit descriptors. 206 */ 207 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 208 209 /* 210 * The receive descriptors. 211 */ 212 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 213 }; 214 215 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 216 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 217 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 218 219 /* 220 * The DGE interface have a higher max MTU size than normal jumbo frames. 221 */ 222 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 223 224 /* 225 * Software state for transmit jobs. 226 */ 227 struct dge_txsoft { 228 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 229 bus_dmamap_t txs_dmamap; /* our DMA map */ 230 int txs_firstdesc; /* first descriptor in packet */ 231 int txs_lastdesc; /* last descriptor in packet */ 232 int txs_ndesc; /* # of descriptors used */ 233 }; 234 235 /* 236 * Software state for receive buffers. Each descriptor gets a 237 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 238 * more than one buffer, we chain them together. 239 */ 240 struct dge_rxsoft { 241 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 242 bus_dmamap_t rxs_dmamap; /* our DMA map */ 243 }; 244 245 /* 246 * Software state per device. 247 */ 248 struct dge_softc { 249 device_t sc_dev; /* generic device information */ 250 bus_space_tag_t sc_st; /* bus space tag */ 251 bus_space_handle_t sc_sh; /* bus space handle */ 252 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 253 struct ethercom sc_ethercom; /* ethernet common data */ 254 255 int sc_flags; /* flags; see below */ 256 int sc_bus_speed; /* PCI/PCIX bus speed */ 257 int sc_pcix_offset; /* PCIX capability register offset */ 258 259 pci_chipset_tag_t sc_pc; 260 pcitag_t sc_pt; 261 int sc_mmrbc; /* Max PCIX memory read byte count */ 262 263 void *sc_ih; /* interrupt cookie */ 264 265 struct ifmedia sc_media; 266 267 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 268 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 269 270 int sc_align_tweak; 271 272 /* 273 * Software state for the transmit and receive descriptors. 274 */ 275 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 276 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 277 278 /* 279 * Control data structures. 280 */ 281 struct dge_control_data *sc_control_data; 282 #define sc_txdescs sc_control_data->wcd_txdescs 283 #define sc_rxdescs sc_control_data->wcd_rxdescs 284 285 #ifdef DGE_EVENT_COUNTERS 286 /* Event counters. */ 287 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 288 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 289 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 290 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 291 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 292 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 293 struct evcnt sc_ev_linkintr; /* Link interrupts */ 294 295 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 296 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 297 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 298 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 299 300 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 301 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 302 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 303 304 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 305 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 306 #endif /* DGE_EVENT_COUNTERS */ 307 308 int sc_txfree; /* number of free Tx descriptors */ 309 int sc_txnext; /* next ready Tx descriptor */ 310 311 int sc_txsfree; /* number of free Tx jobs */ 312 int sc_txsnext; /* next free Tx job */ 313 int sc_txsdirty; /* dirty Tx jobs */ 314 315 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 316 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 317 318 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 319 int sc_rxdiscard; 320 int sc_rxlen; 321 struct mbuf *sc_rxhead; 322 struct mbuf *sc_rxtail; 323 struct mbuf **sc_rxtailp; 324 325 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 326 uint32_t sc_icr; /* prototype interrupt bits */ 327 uint32_t sc_tctl; /* prototype TCTL register */ 328 uint32_t sc_rctl; /* prototype RCTL register */ 329 330 int sc_mchash_type; /* multicast filter offset */ 331 332 uint16_t sc_eeprom[EEPROM_SIZE]; 333 334 krndsource_t rnd_source; /* random source */ 335 #ifdef DGE_OFFBYONE_RXBUG 336 void *sc_bugbuf; 337 SLIST_HEAD(, rxbugentry) sc_buglist; 338 bus_dmamap_t sc_bugmap; 339 struct rxbugentry *sc_entry; 340 #endif 341 }; 342 343 #define DGE_RXCHAIN_RESET(sc) \ 344 do { \ 345 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 346 *(sc)->sc_rxtailp = NULL; \ 347 (sc)->sc_rxlen = 0; \ 348 } while (/*CONSTCOND*/0) 349 350 #define DGE_RXCHAIN_LINK(sc, m) \ 351 do { \ 352 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 353 (sc)->sc_rxtailp = &(m)->m_next; \ 354 } while (/*CONSTCOND*/0) 355 356 /* sc_flags */ 357 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 358 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 359 360 #ifdef DGE_EVENT_COUNTERS 361 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 362 #else 363 #define DGE_EVCNT_INCR(ev) /* nothing */ 364 #endif 365 366 #define CSR_READ(sc, reg) \ 367 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 368 #define CSR_WRITE(sc, reg, val) \ 369 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 370 371 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 372 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 373 374 #define DGE_CDTXSYNC(sc, x, n, ops) \ 375 do { \ 376 int __x, __n; \ 377 \ 378 __x = (x); \ 379 __n = (n); \ 380 \ 381 /* If it will wrap around, sync to the end of the ring. */ \ 382 if ((__x + __n) > DGE_NTXDESC) { \ 383 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 384 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 385 (DGE_NTXDESC - __x), (ops)); \ 386 __n -= (DGE_NTXDESC - __x); \ 387 __x = 0; \ 388 } \ 389 \ 390 /* Now sync whatever is left. */ \ 391 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 392 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 393 } while (/*CONSTCOND*/0) 394 395 #define DGE_CDRXSYNC(sc, x, ops) \ 396 do { \ 397 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 398 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 399 } while (/*CONSTCOND*/0) 400 401 #ifdef DGE_OFFBYONE_RXBUG 402 #define DGE_INIT_RXDESC(sc, x) \ 403 do { \ 404 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 405 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 406 struct mbuf *__m = __rxs->rxs_mbuf; \ 407 \ 408 __rxd->dr_baddrl = htole32(sc->sc_bugmap->dm_segs[0].ds_addr + \ 409 (mtod((__m), char *) - (char *)sc->sc_bugbuf)); \ 410 __rxd->dr_baddrh = 0; \ 411 __rxd->dr_len = 0; \ 412 __rxd->dr_cksum = 0; \ 413 __rxd->dr_status = 0; \ 414 __rxd->dr_errors = 0; \ 415 __rxd->dr_special = 0; \ 416 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 417 \ 418 CSR_WRITE((sc), DGE_RDT, (x)); \ 419 } while (/*CONSTCOND*/0) 420 #else 421 #define DGE_INIT_RXDESC(sc, x) \ 422 do { \ 423 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 424 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 425 struct mbuf *__m = __rxs->rxs_mbuf; \ 426 \ 427 /* \ 428 * Note: We scoot the packet forward 2 bytes in the buffer \ 429 * so that the payload after the Ethernet header is aligned \ 430 * to a 4-byte boundary. \ 431 * \ 432 * XXX BRAINDAMAGE ALERT! \ 433 * The stupid chip uses the same size for every buffer, which \ 434 * is set in the Receive Control register. We are using the 2K \ 435 * size option, but what we REALLY want is (2K - 2)! For this \ 436 * reason, we can't "scoot" packets longer than the standard \ 437 * Ethernet MTU. On strict-alignment platforms, if the total \ 438 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 439 * the upper layer copy the headers. \ 440 */ \ 441 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 442 \ 443 __rxd->dr_baddrl = \ 444 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 445 (sc)->sc_align_tweak); \ 446 __rxd->dr_baddrh = 0; \ 447 __rxd->dr_len = 0; \ 448 __rxd->dr_cksum = 0; \ 449 __rxd->dr_status = 0; \ 450 __rxd->dr_errors = 0; \ 451 __rxd->dr_special = 0; \ 452 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 453 \ 454 CSR_WRITE((sc), DGE_RDT, (x)); \ 455 } while (/*CONSTCOND*/0) 456 #endif 457 458 #ifdef DGE_OFFBYONE_RXBUG 459 /* 460 * Allocation constants. Much memory may be used for this. 461 */ 462 #ifndef DGE_BUFFER_SIZE 463 #define DGE_BUFFER_SIZE DGE_MAX_MTU 464 #endif 465 #define DGE_NBUFFERS (4*DGE_NRXDESC) 466 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 467 468 struct rxbugentry { 469 SLIST_ENTRY(rxbugentry) rb_entry; 470 int rb_slot; 471 }; 472 473 static int 474 dge_alloc_rcvmem(struct dge_softc *sc) 475 { 476 char *kva; 477 bus_dma_segment_t seg; 478 int i, rseg, state, error; 479 struct rxbugentry *entry; 480 481 state = error = 0; 482 483 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 484 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 485 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 486 return ENOBUFS; 487 } 488 489 state = 1; 490 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, 491 BUS_DMA_NOWAIT)) { 492 aprint_error_dev(sc->sc_dev, "can't map DMA buffers (%d bytes)\n", 493 (int)DGE_RXMEM); 494 error = ENOBUFS; 495 goto out; 496 } 497 498 state = 2; 499 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 500 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 501 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 502 error = ENOBUFS; 503 goto out; 504 } 505 506 state = 3; 507 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 508 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 509 aprint_error_dev(sc->sc_dev, "can't load DMA map\n"); 510 error = ENOBUFS; 511 goto out; 512 } 513 514 state = 4; 515 sc->sc_bugbuf = (void *)kva; 516 SLIST_INIT(&sc->sc_buglist); 517 518 /* 519 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 520 * in an array. 521 */ 522 if ((entry = malloc(sizeof(*entry) * DGE_NBUFFERS, 523 M_DEVBUF, M_NOWAIT)) == NULL) { 524 error = ENOBUFS; 525 goto out; 526 } 527 sc->sc_entry = entry; 528 for (i = 0; i < DGE_NBUFFERS; i++) { 529 entry[i].rb_slot = i; 530 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 531 } 532 out: 533 if (error != 0) { 534 switch (state) { 535 case 4: 536 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 537 case 3: 538 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 539 case 2: 540 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 541 case 1: 542 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 543 break; 544 default: 545 break; 546 } 547 } 548 549 return error; 550 } 551 552 /* 553 * Allocate a jumbo buffer. 554 */ 555 static void * 556 dge_getbuf(struct dge_softc *sc) 557 { 558 struct rxbugentry *entry; 559 560 entry = SLIST_FIRST(&sc->sc_buglist); 561 562 if (entry == NULL) { 563 printf("%s: no free RX buffers\n", device_xname(sc->sc_dev)); 564 return(NULL); 565 } 566 567 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 568 return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 569 } 570 571 /* 572 * Release a jumbo buffer. 573 */ 574 static void 575 dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) 576 { 577 struct rxbugentry *entry; 578 struct dge_softc *sc; 579 int i, s; 580 581 /* Extract the softc struct pointer. */ 582 sc = (struct dge_softc *)arg; 583 584 if (sc == NULL) 585 panic("dge_freebuf: can't find softc pointer!"); 586 587 /* calculate the slot this buffer belongs to */ 588 589 i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; 590 591 if ((i < 0) || (i >= DGE_NBUFFERS)) 592 panic("dge_freebuf: asked to free buffer %d!", i); 593 594 s = splvm(); 595 entry = sc->sc_entry + i; 596 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 597 598 if (__predict_true(m != NULL)) 599 pool_cache_put(mb_cache, m); 600 splx(s); 601 } 602 #endif 603 604 static void dge_start(struct ifnet *); 605 static void dge_watchdog(struct ifnet *); 606 static int dge_ioctl(struct ifnet *, u_long, void *); 607 static int dge_init(struct ifnet *); 608 static void dge_stop(struct ifnet *, int); 609 610 static bool dge_shutdown(device_t, int); 611 612 static void dge_reset(struct dge_softc *); 613 static void dge_rxdrain(struct dge_softc *); 614 static int dge_add_rxbuf(struct dge_softc *, int); 615 616 static void dge_set_filter(struct dge_softc *); 617 618 static int dge_intr(void *); 619 static void dge_txintr(struct dge_softc *); 620 static void dge_rxintr(struct dge_softc *); 621 static void dge_linkintr(struct dge_softc *, uint32_t); 622 623 static int dge_match(device_t, cfdata_t, void *); 624 static void dge_attach(device_t, device_t, void *); 625 626 static int dge_read_eeprom(struct dge_softc *sc); 627 static int dge_eeprom_clockin(struct dge_softc *sc); 628 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 629 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 630 static int dge_xgmii_mediachange(struct ifnet *); 631 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 632 static void dge_xgmii_reset(struct dge_softc *); 633 static void dge_xgmii_writereg(device_t, int, int, int); 634 635 636 CFATTACH_DECL_NEW(dge, sizeof(struct dge_softc), 637 dge_match, dge_attach, NULL, NULL); 638 639 #ifdef DGE_EVENT_COUNTERS 640 #if DGE_NTXSEGS > 100 641 #error Update dge_txseg_evcnt_names 642 #endif 643 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 644 #endif /* DGE_EVENT_COUNTERS */ 645 646 static int 647 dge_match(device_t parent, cfdata_t cf, void *aux) 648 { 649 struct pci_attach_args *pa = aux; 650 651 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 652 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82597EX) 653 return (1); 654 655 return (0); 656 } 657 658 static void 659 dge_attach(device_t parent, device_t self, void *aux) 660 { 661 struct dge_softc *sc = device_private(self); 662 struct pci_attach_args *pa = aux; 663 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 664 pci_chipset_tag_t pc = pa->pa_pc; 665 pci_intr_handle_t ih; 666 const char *intrstr = NULL; 667 bus_dma_segment_t seg; 668 int i, rseg, error; 669 uint8_t enaddr[ETHER_ADDR_LEN]; 670 pcireg_t preg, memtype; 671 uint32_t reg; 672 673 sc->sc_dev = self; 674 sc->sc_dmat = pa->pa_dmat; 675 sc->sc_pc = pa->pa_pc; 676 sc->sc_pt = pa->pa_tag; 677 678 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 679 "Intel i82597EX 10GbE-LR Ethernet", 1); 680 681 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 682 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 683 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 684 aprint_error_dev(sc->sc_dev, "unable to map device registers\n"); 685 return; 686 } 687 688 /* Enable bus mastering */ 689 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 690 preg |= PCI_COMMAND_MASTER_ENABLE; 691 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 692 693 /* 694 * Map and establish our interrupt. 695 */ 696 if (pci_intr_map(pa, &ih)) { 697 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 698 return; 699 } 700 intrstr = pci_intr_string(pc, ih); 701 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dge_intr, sc); 702 if (sc->sc_ih == NULL) { 703 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 704 if (intrstr != NULL) 705 aprint_error(" at %s", intrstr); 706 aprint_error("\n"); 707 return; 708 } 709 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 710 711 /* 712 * Determine a few things about the bus we're connected to. 713 */ 714 reg = CSR_READ(sc, DGE_STATUS); 715 if (reg & STATUS_BUS64) 716 sc->sc_flags |= DGE_F_BUS64; 717 718 sc->sc_flags |= DGE_F_PCIX; 719 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 720 PCI_CAP_PCIX, 721 &sc->sc_pcix_offset, NULL) == 0) 722 aprint_error_dev(sc->sc_dev, "unable to find PCIX " 723 "capability\n"); 724 725 if (sc->sc_flags & DGE_F_PCIX) { 726 switch (reg & STATUS_PCIX_MSK) { 727 case STATUS_PCIX_66: 728 sc->sc_bus_speed = 66; 729 break; 730 case STATUS_PCIX_100: 731 sc->sc_bus_speed = 100; 732 break; 733 case STATUS_PCIX_133: 734 sc->sc_bus_speed = 133; 735 break; 736 default: 737 aprint_error_dev(sc->sc_dev, 738 "unknown PCIXSPD %d; assuming 66MHz\n", 739 reg & STATUS_PCIX_MSK); 740 sc->sc_bus_speed = 66; 741 } 742 } else 743 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 744 aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", 745 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 746 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 747 748 /* 749 * Allocate the control data structures, and create and load the 750 * DMA map for it. 751 */ 752 if ((error = bus_dmamem_alloc(sc->sc_dmat, 753 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 754 0)) != 0) { 755 aprint_error_dev(sc->sc_dev, 756 "unable to allocate control data, error = %d\n", 757 error); 758 goto fail_0; 759 } 760 761 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 762 sizeof(struct dge_control_data), (void **)&sc->sc_control_data, 763 0)) != 0) { 764 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 765 error); 766 goto fail_1; 767 } 768 769 if ((error = bus_dmamap_create(sc->sc_dmat, 770 sizeof(struct dge_control_data), 1, 771 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 772 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 773 "error = %d\n", error); 774 goto fail_2; 775 } 776 777 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 778 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 779 0)) != 0) { 780 aprint_error_dev(sc->sc_dev, 781 "unable to load control data DMA map, error = %d\n", 782 error); 783 goto fail_3; 784 } 785 786 #ifdef DGE_OFFBYONE_RXBUG 787 if (dge_alloc_rcvmem(sc) != 0) 788 return; /* Already complained */ 789 #endif 790 /* 791 * Create the transmit buffer DMA maps. 792 */ 793 for (i = 0; i < DGE_TXQUEUELEN; i++) { 794 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 795 DGE_NTXSEGS, MCLBYTES, 0, 0, 796 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 797 aprint_error_dev(sc->sc_dev, "unable to create Tx DMA map %d, " 798 "error = %d\n", i, error); 799 goto fail_4; 800 } 801 } 802 803 /* 804 * Create the receive buffer DMA maps. 805 */ 806 for (i = 0; i < DGE_NRXDESC; i++) { 807 #ifdef DGE_OFFBYONE_RXBUG 808 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 809 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 810 #else 811 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 812 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 813 #endif 814 aprint_error_dev(sc->sc_dev, "unable to create Rx DMA map %d, " 815 "error = %d\n", i, error); 816 goto fail_5; 817 } 818 sc->sc_rxsoft[i].rxs_mbuf = NULL; 819 } 820 821 /* 822 * Set bits in ctrl0 register. 823 * Should get the software defined pins out of EEPROM? 824 */ 825 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 826 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 827 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 828 829 /* 830 * Reset the chip to a known state. 831 */ 832 dge_reset(sc); 833 834 /* 835 * Reset the PHY. 836 */ 837 dge_xgmii_reset(sc); 838 839 /* 840 * Read in EEPROM data. 841 */ 842 if (dge_read_eeprom(sc)) { 843 aprint_error_dev(sc->sc_dev, "couldn't read EEPROM\n"); 844 return; 845 } 846 847 /* 848 * Get the ethernet address. 849 */ 850 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 851 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 852 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 853 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 854 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 855 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 856 857 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 858 ether_sprintf(enaddr)); 859 860 /* 861 * Setup media stuff. 862 */ 863 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 864 dge_xgmii_mediastatus); 865 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10G_LR, 0, NULL); 866 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10G_LR); 867 868 ifp = &sc->sc_ethercom.ec_if; 869 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 870 ifp->if_softc = sc; 871 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 872 ifp->if_ioctl = dge_ioctl; 873 ifp->if_start = dge_start; 874 ifp->if_watchdog = dge_watchdog; 875 ifp->if_init = dge_init; 876 ifp->if_stop = dge_stop; 877 IFQ_SET_MAXLEN(&ifp->if_snd, max(DGE_IFQUEUELEN, IFQ_MAXLEN)); 878 IFQ_SET_READY(&ifp->if_snd); 879 880 sc->sc_ethercom.ec_capabilities |= 881 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 882 883 /* 884 * We can perform TCPv4 and UDPv4 checkums in-bound. 885 */ 886 ifp->if_capabilities |= 887 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 888 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 889 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 890 891 /* 892 * Attach the interface. 893 */ 894 if_attach(ifp); 895 ether_ifattach(ifp, enaddr); 896 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 897 RND_TYPE_NET, 0); 898 899 #ifdef DGE_EVENT_COUNTERS 900 /* Fix segment event naming */ 901 if (dge_txseg_evcnt_names == NULL) { 902 dge_txseg_evcnt_names = 903 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 904 for (i = 0; i < DGE_NTXSEGS; i++) 905 snprintf((*dge_txseg_evcnt_names)[i], 906 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 907 } 908 909 /* Attach event counters. */ 910 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 911 NULL, device_xname(sc->sc_dev), "txsstall"); 912 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 913 NULL, device_xname(sc->sc_dev), "txdstall"); 914 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 915 NULL, device_xname(sc->sc_dev), "txforceintr"); 916 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 917 NULL, device_xname(sc->sc_dev), "txdw"); 918 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 919 NULL, device_xname(sc->sc_dev), "txqe"); 920 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 921 NULL, device_xname(sc->sc_dev), "rxintr"); 922 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 923 NULL, device_xname(sc->sc_dev), "linkintr"); 924 925 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 926 NULL, device_xname(sc->sc_dev), "rxipsum"); 927 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 928 NULL, device_xname(sc->sc_dev), "rxtusum"); 929 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 930 NULL, device_xname(sc->sc_dev), "txipsum"); 931 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 932 NULL, device_xname(sc->sc_dev), "txtusum"); 933 934 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 935 NULL, device_xname(sc->sc_dev), "txctx init"); 936 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 937 NULL, device_xname(sc->sc_dev), "txctx hit"); 938 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 939 NULL, device_xname(sc->sc_dev), "txctx miss"); 940 941 for (i = 0; i < DGE_NTXSEGS; i++) 942 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 943 NULL, device_xname(sc->sc_dev), (*dge_txseg_evcnt_names)[i]); 944 945 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 946 NULL, device_xname(sc->sc_dev), "txdrop"); 947 948 #endif /* DGE_EVENT_COUNTERS */ 949 950 /* 951 * Make sure the interface is shutdown during reboot. 952 */ 953 if (pmf_device_register1(self, NULL, NULL, dge_shutdown)) 954 pmf_class_network_register(self, ifp); 955 else 956 aprint_error_dev(self, "couldn't establish power handler\n"); 957 958 return; 959 960 /* 961 * Free any resources we've allocated during the failed attach 962 * attempt. Do this in reverse order and fall through. 963 */ 964 fail_5: 965 for (i = 0; i < DGE_NRXDESC; i++) { 966 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 967 bus_dmamap_destroy(sc->sc_dmat, 968 sc->sc_rxsoft[i].rxs_dmamap); 969 } 970 fail_4: 971 for (i = 0; i < DGE_TXQUEUELEN; i++) { 972 if (sc->sc_txsoft[i].txs_dmamap != NULL) 973 bus_dmamap_destroy(sc->sc_dmat, 974 sc->sc_txsoft[i].txs_dmamap); 975 } 976 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 977 fail_3: 978 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 979 fail_2: 980 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 981 sizeof(struct dge_control_data)); 982 fail_1: 983 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 984 fail_0: 985 return; 986 } 987 988 /* 989 * dge_shutdown: 990 * 991 * Make sure the interface is stopped at reboot time. 992 */ 993 static bool 994 dge_shutdown(device_t self, int howto) 995 { 996 struct dge_softc *sc; 997 998 sc = device_private(self); 999 dge_stop(&sc->sc_ethercom.ec_if, 1); 1000 1001 return true; 1002 } 1003 1004 /* 1005 * dge_tx_cksum: 1006 * 1007 * Set up TCP/IP checksumming parameters for the 1008 * specified packet. 1009 */ 1010 static int 1011 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1012 { 1013 struct mbuf *m0 = txs->txs_mbuf; 1014 struct dge_ctdes *t; 1015 uint32_t ipcs, tucs; 1016 struct ether_header *eh; 1017 int offset, iphl; 1018 uint8_t fields = 0; 1019 1020 /* 1021 * XXX It would be nice if the mbuf pkthdr had offset 1022 * fields for the protocol headers. 1023 */ 1024 1025 eh = mtod(m0, struct ether_header *); 1026 switch (htons(eh->ether_type)) { 1027 case ETHERTYPE_IP: 1028 offset = ETHER_HDR_LEN; 1029 break; 1030 1031 case ETHERTYPE_VLAN: 1032 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1033 break; 1034 1035 default: 1036 /* 1037 * Don't support this protocol or encapsulation. 1038 */ 1039 *fieldsp = 0; 1040 return (0); 1041 } 1042 1043 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1044 1045 /* 1046 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1047 * offload feature, if we load the context descriptor, we 1048 * MUST provide valid values for IPCSS and TUCSS fields. 1049 */ 1050 1051 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1052 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1053 fields |= TDESC_POPTS_IXSM; 1054 ipcs = DGE_TCPIP_IPCSS(offset) | 1055 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1056 DGE_TCPIP_IPCSE(offset + iphl - 1); 1057 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1058 /* Use the cached value. */ 1059 ipcs = sc->sc_txctx_ipcs; 1060 } else { 1061 /* Just initialize it to the likely value anyway. */ 1062 ipcs = DGE_TCPIP_IPCSS(offset) | 1063 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1064 DGE_TCPIP_IPCSE(offset + iphl - 1); 1065 } 1066 DPRINTF(DGE_DEBUG_CKSUM, 1067 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1068 device_xname(sc->sc_dev), offset, ipcs)); 1069 1070 offset += iphl; 1071 1072 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1073 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1074 fields |= TDESC_POPTS_TXSM; 1075 tucs = DGE_TCPIP_TUCSS(offset) | 1076 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1077 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1078 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1079 /* Use the cached value. */ 1080 tucs = sc->sc_txctx_tucs; 1081 } else { 1082 /* Just initialize it to a valid TCP context. */ 1083 tucs = DGE_TCPIP_TUCSS(offset) | 1084 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1085 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1086 } 1087 1088 DPRINTF(DGE_DEBUG_CKSUM, 1089 ("%s: CKSUM: offset %d tucs 0x%x\n", 1090 device_xname(sc->sc_dev), offset, tucs)); 1091 1092 if (sc->sc_txctx_ipcs == ipcs && 1093 sc->sc_txctx_tucs == tucs) { 1094 /* Cached context is fine. */ 1095 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1096 } else { 1097 /* Fill in the context descriptor. */ 1098 #ifdef DGE_EVENT_COUNTERS 1099 if (sc->sc_txctx_ipcs == 0xffffffff && 1100 sc->sc_txctx_tucs == 0xffffffff) 1101 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1102 else 1103 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1104 #endif 1105 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1106 t->dc_tcpip_ipcs = htole32(ipcs); 1107 t->dc_tcpip_tucs = htole32(tucs); 1108 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1109 t->dc_tcpip_seg = 0; 1110 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1111 1112 sc->sc_txctx_ipcs = ipcs; 1113 sc->sc_txctx_tucs = tucs; 1114 1115 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1116 txs->txs_ndesc++; 1117 } 1118 1119 *fieldsp = fields; 1120 1121 return (0); 1122 } 1123 1124 /* 1125 * dge_start: [ifnet interface function] 1126 * 1127 * Start packet transmission on the interface. 1128 */ 1129 static void 1130 dge_start(struct ifnet *ifp) 1131 { 1132 struct dge_softc *sc = ifp->if_softc; 1133 struct mbuf *m0; 1134 struct dge_txsoft *txs; 1135 bus_dmamap_t dmamap; 1136 int error, nexttx, lasttx = -1, ofree, seg; 1137 uint32_t cksumcmd; 1138 uint8_t cksumfields; 1139 1140 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1141 return; 1142 1143 /* 1144 * Remember the previous number of free descriptors. 1145 */ 1146 ofree = sc->sc_txfree; 1147 1148 /* 1149 * Loop through the send queue, setting up transmit descriptors 1150 * until we drain the queue, or use up all available transmit 1151 * descriptors. 1152 */ 1153 for (;;) { 1154 /* Grab a packet off the queue. */ 1155 IFQ_POLL(&ifp->if_snd, m0); 1156 if (m0 == NULL) 1157 break; 1158 1159 DPRINTF(DGE_DEBUG_TX, 1160 ("%s: TX: have packet to transmit: %p\n", 1161 device_xname(sc->sc_dev), m0)); 1162 1163 /* Get a work queue entry. */ 1164 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1165 dge_txintr(sc); 1166 if (sc->sc_txsfree == 0) { 1167 DPRINTF(DGE_DEBUG_TX, 1168 ("%s: TX: no free job descriptors\n", 1169 device_xname(sc->sc_dev))); 1170 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1171 break; 1172 } 1173 } 1174 1175 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1176 dmamap = txs->txs_dmamap; 1177 1178 /* 1179 * Load the DMA map. If this fails, the packet either 1180 * didn't fit in the allotted number of segments, or we 1181 * were short on resources. For the too-many-segments 1182 * case, we simply report an error and drop the packet, 1183 * since we can't sanely copy a jumbo packet to a single 1184 * buffer. 1185 */ 1186 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1187 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1188 if (error) { 1189 if (error == EFBIG) { 1190 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1191 printf("%s: Tx packet consumes too many " 1192 "DMA segments, dropping...\n", 1193 device_xname(sc->sc_dev)); 1194 IFQ_DEQUEUE(&ifp->if_snd, m0); 1195 m_freem(m0); 1196 continue; 1197 } 1198 /* 1199 * Short on resources, just stop for now. 1200 */ 1201 DPRINTF(DGE_DEBUG_TX, 1202 ("%s: TX: dmamap load failed: %d\n", 1203 device_xname(sc->sc_dev), error)); 1204 break; 1205 } 1206 1207 /* 1208 * Ensure we have enough descriptors free to describe 1209 * the packet. Note, we always reserve one descriptor 1210 * at the end of the ring due to the semantics of the 1211 * TDT register, plus one more in the event we need 1212 * to re-load checksum offload context. 1213 */ 1214 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1215 /* 1216 * Not enough free descriptors to transmit this 1217 * packet. We haven't committed anything yet, 1218 * so just unload the DMA map, put the packet 1219 * pack on the queue, and punt. Notify the upper 1220 * layer that there are no more slots left. 1221 */ 1222 DPRINTF(DGE_DEBUG_TX, 1223 ("%s: TX: need %d descriptors, have %d\n", 1224 device_xname(sc->sc_dev), dmamap->dm_nsegs, 1225 sc->sc_txfree - 1)); 1226 ifp->if_flags |= IFF_OACTIVE; 1227 bus_dmamap_unload(sc->sc_dmat, dmamap); 1228 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1229 break; 1230 } 1231 1232 IFQ_DEQUEUE(&ifp->if_snd, m0); 1233 1234 /* 1235 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1236 */ 1237 1238 /* Sync the DMA map. */ 1239 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1240 BUS_DMASYNC_PREWRITE); 1241 1242 DPRINTF(DGE_DEBUG_TX, 1243 ("%s: TX: packet has %d DMA segments\n", 1244 device_xname(sc->sc_dev), dmamap->dm_nsegs)); 1245 1246 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1247 1248 /* 1249 * Store a pointer to the packet so that we can free it 1250 * later. 1251 * 1252 * Initially, we consider the number of descriptors the 1253 * packet uses the number of DMA segments. This may be 1254 * incremented by 1 if we do checksum offload (a descriptor 1255 * is used to set the checksum context). 1256 */ 1257 txs->txs_mbuf = m0; 1258 txs->txs_firstdesc = sc->sc_txnext; 1259 txs->txs_ndesc = dmamap->dm_nsegs; 1260 1261 /* 1262 * Set up checksum offload parameters for 1263 * this packet. 1264 */ 1265 if (m0->m_pkthdr.csum_flags & 1266 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1267 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1268 /* Error message already displayed. */ 1269 bus_dmamap_unload(sc->sc_dmat, dmamap); 1270 continue; 1271 } 1272 } else { 1273 cksumfields = 0; 1274 } 1275 1276 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1277 1278 /* 1279 * Initialize the transmit descriptor. 1280 */ 1281 for (nexttx = sc->sc_txnext, seg = 0; 1282 seg < dmamap->dm_nsegs; 1283 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1284 /* 1285 * Note: we currently only use 32-bit DMA 1286 * addresses. 1287 */ 1288 sc->sc_txdescs[nexttx].dt_baddrh = 0; 1289 sc->sc_txdescs[nexttx].dt_baddrl = 1290 htole32(dmamap->dm_segs[seg].ds_addr); 1291 sc->sc_txdescs[nexttx].dt_ctl = 1292 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1293 sc->sc_txdescs[nexttx].dt_status = 0; 1294 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1295 sc->sc_txdescs[nexttx].dt_vlan = 0; 1296 lasttx = nexttx; 1297 1298 DPRINTF(DGE_DEBUG_TX, 1299 ("%s: TX: desc %d: low 0x%08lx, len 0x%04lx\n", 1300 device_xname(sc->sc_dev), nexttx, 1301 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_addr), 1302 (unsigned long)le32toh(dmamap->dm_segs[seg].ds_len))); 1303 } 1304 1305 KASSERT(lasttx != -1); 1306 1307 /* 1308 * Set up the command byte on the last descriptor of 1309 * the packet. If we're in the interrupt delay window, 1310 * delay the interrupt. 1311 */ 1312 sc->sc_txdescs[lasttx].dt_ctl |= 1313 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1314 1315 txs->txs_lastdesc = lasttx; 1316 1317 DPRINTF(DGE_DEBUG_TX, 1318 ("%s: TX: desc %d: cmdlen 0x%08x\n", device_xname(sc->sc_dev), 1319 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1320 1321 /* Sync the descriptors we're using. */ 1322 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1323 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1324 1325 /* Give the packet to the chip. */ 1326 CSR_WRITE(sc, DGE_TDT, nexttx); 1327 1328 DPRINTF(DGE_DEBUG_TX, 1329 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 1330 1331 DPRINTF(DGE_DEBUG_TX, 1332 ("%s: TX: finished transmitting packet, job %d\n", 1333 device_xname(sc->sc_dev), sc->sc_txsnext)); 1334 1335 /* Advance the tx pointer. */ 1336 sc->sc_txfree -= txs->txs_ndesc; 1337 sc->sc_txnext = nexttx; 1338 1339 sc->sc_txsfree--; 1340 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1341 1342 /* Pass the packet to any BPF listeners. */ 1343 bpf_mtap(ifp, m0); 1344 } 1345 1346 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1347 /* No more slots; notify upper layer. */ 1348 ifp->if_flags |= IFF_OACTIVE; 1349 } 1350 1351 if (sc->sc_txfree != ofree) { 1352 /* Set a watchdog timer in case the chip flakes out. */ 1353 ifp->if_timer = 5; 1354 } 1355 } 1356 1357 /* 1358 * dge_watchdog: [ifnet interface function] 1359 * 1360 * Watchdog timer handler. 1361 */ 1362 static void 1363 dge_watchdog(struct ifnet *ifp) 1364 { 1365 struct dge_softc *sc = ifp->if_softc; 1366 1367 /* 1368 * Since we're using delayed interrupts, sweep up 1369 * before we report an error. 1370 */ 1371 dge_txintr(sc); 1372 1373 if (sc->sc_txfree != DGE_NTXDESC) { 1374 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1375 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, 1376 sc->sc_txnext); 1377 ifp->if_oerrors++; 1378 1379 /* Reset the interface. */ 1380 (void) dge_init(ifp); 1381 } 1382 1383 /* Try to get more packets going. */ 1384 dge_start(ifp); 1385 } 1386 1387 /* 1388 * dge_ioctl: [ifnet interface function] 1389 * 1390 * Handle control requests from the operator. 1391 */ 1392 static int 1393 dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1394 { 1395 struct dge_softc *sc = ifp->if_softc; 1396 struct ifreq *ifr = (struct ifreq *) data; 1397 pcireg_t preg; 1398 int s, error, mmrbc; 1399 1400 s = splnet(); 1401 1402 switch (cmd) { 1403 case SIOCSIFMEDIA: 1404 case SIOCGIFMEDIA: 1405 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1406 break; 1407 1408 case SIOCSIFMTU: 1409 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) 1410 error = EINVAL; 1411 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1412 break; 1413 else if (ifp->if_flags & IFF_UP) 1414 error = (*ifp->if_init)(ifp); 1415 else 1416 error = 0; 1417 break; 1418 1419 case SIOCSIFFLAGS: 1420 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1421 break; 1422 /* extract link flags */ 1423 if ((ifp->if_flags & IFF_LINK0) == 0 && 1424 (ifp->if_flags & IFF_LINK1) == 0) 1425 mmrbc = PCIX_MMRBC_512; 1426 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1427 (ifp->if_flags & IFF_LINK1) != 0) 1428 mmrbc = PCIX_MMRBC_1024; 1429 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1430 (ifp->if_flags & IFF_LINK1) == 0) 1431 mmrbc = PCIX_MMRBC_2048; 1432 else 1433 mmrbc = PCIX_MMRBC_4096; 1434 if (mmrbc != sc->sc_mmrbc) { 1435 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1436 preg &= ~PCIX_MMRBC_MSK; 1437 preg |= mmrbc; 1438 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1439 sc->sc_mmrbc = mmrbc; 1440 } 1441 /* FALLTHROUGH */ 1442 default: 1443 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1444 break; 1445 1446 error = 0; 1447 1448 if (cmd == SIOCSIFCAP) 1449 error = (*ifp->if_init)(ifp); 1450 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1451 ; 1452 else if (ifp->if_flags & IFF_RUNNING) { 1453 /* 1454 * Multicast list has changed; set the hardware filter 1455 * accordingly. 1456 */ 1457 dge_set_filter(sc); 1458 } 1459 break; 1460 } 1461 1462 /* Try to get more packets going. */ 1463 dge_start(ifp); 1464 1465 splx(s); 1466 return (error); 1467 } 1468 1469 /* 1470 * dge_intr: 1471 * 1472 * Interrupt service routine. 1473 */ 1474 static int 1475 dge_intr(void *arg) 1476 { 1477 struct dge_softc *sc = arg; 1478 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1479 uint32_t icr; 1480 int wantinit, handled = 0; 1481 1482 for (wantinit = 0; wantinit == 0;) { 1483 icr = CSR_READ(sc, DGE_ICR); 1484 if ((icr & sc->sc_icr) == 0) 1485 break; 1486 1487 rnd_add_uint32(&sc->rnd_source, icr); 1488 1489 handled = 1; 1490 1491 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1492 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1493 DPRINTF(DGE_DEBUG_RX, 1494 ("%s: RX: got Rx intr 0x%08x\n", 1495 device_xname(sc->sc_dev), 1496 icr & (ICR_RXDMT0|ICR_RXT0))); 1497 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1498 } 1499 #endif 1500 dge_rxintr(sc); 1501 1502 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1503 if (icr & ICR_TXDW) { 1504 DPRINTF(DGE_DEBUG_TX, 1505 ("%s: TX: got TXDW interrupt\n", 1506 device_xname(sc->sc_dev))); 1507 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1508 } 1509 if (icr & ICR_TXQE) 1510 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1511 #endif 1512 dge_txintr(sc); 1513 1514 if (icr & (ICR_LSC|ICR_RXSEQ)) { 1515 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1516 dge_linkintr(sc, icr); 1517 } 1518 1519 if (icr & ICR_RXO) { 1520 printf("%s: Receive overrun\n", device_xname(sc->sc_dev)); 1521 wantinit = 1; 1522 } 1523 } 1524 1525 if (handled) { 1526 if (wantinit) 1527 dge_init(ifp); 1528 1529 /* Try to get more packets going. */ 1530 dge_start(ifp); 1531 } 1532 1533 return (handled); 1534 } 1535 1536 /* 1537 * dge_txintr: 1538 * 1539 * Helper; handle transmit interrupts. 1540 */ 1541 static void 1542 dge_txintr(struct dge_softc *sc) 1543 { 1544 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1545 struct dge_txsoft *txs; 1546 uint8_t status; 1547 int i; 1548 1549 ifp->if_flags &= ~IFF_OACTIVE; 1550 1551 /* 1552 * Go through the Tx list and free mbufs for those 1553 * frames which have been transmitted. 1554 */ 1555 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1556 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1557 txs = &sc->sc_txsoft[i]; 1558 1559 DPRINTF(DGE_DEBUG_TX, 1560 ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i)); 1561 1562 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1563 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1564 1565 status = 1566 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1567 if ((status & TDESC_STA_DD) == 0) { 1568 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1569 BUS_DMASYNC_PREREAD); 1570 break; 1571 } 1572 1573 DPRINTF(DGE_DEBUG_TX, 1574 ("%s: TX: job %d done: descs %d..%d\n", 1575 device_xname(sc->sc_dev), i, txs->txs_firstdesc, 1576 txs->txs_lastdesc)); 1577 1578 ifp->if_opackets++; 1579 sc->sc_txfree += txs->txs_ndesc; 1580 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1581 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1582 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1583 m_freem(txs->txs_mbuf); 1584 txs->txs_mbuf = NULL; 1585 } 1586 1587 /* Update the dirty transmit buffer pointer. */ 1588 sc->sc_txsdirty = i; 1589 DPRINTF(DGE_DEBUG_TX, 1590 ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i)); 1591 1592 /* 1593 * If there are no more pending transmissions, cancel the watchdog 1594 * timer. 1595 */ 1596 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1597 ifp->if_timer = 0; 1598 } 1599 1600 /* 1601 * dge_rxintr: 1602 * 1603 * Helper; handle receive interrupts. 1604 */ 1605 static void 1606 dge_rxintr(struct dge_softc *sc) 1607 { 1608 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1609 struct dge_rxsoft *rxs; 1610 struct mbuf *m; 1611 int i, len; 1612 uint8_t status, errors; 1613 1614 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1615 rxs = &sc->sc_rxsoft[i]; 1616 1617 DPRINTF(DGE_DEBUG_RX, 1618 ("%s: RX: checking descriptor %d\n", 1619 device_xname(sc->sc_dev), i)); 1620 1621 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1622 1623 status = sc->sc_rxdescs[i].dr_status; 1624 errors = sc->sc_rxdescs[i].dr_errors; 1625 len = le16toh(sc->sc_rxdescs[i].dr_len); 1626 1627 if ((status & RDESC_STS_DD) == 0) { 1628 /* 1629 * We have processed all of the receive descriptors. 1630 */ 1631 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1632 break; 1633 } 1634 1635 if (__predict_false(sc->sc_rxdiscard)) { 1636 DPRINTF(DGE_DEBUG_RX, 1637 ("%s: RX: discarding contents of descriptor %d\n", 1638 device_xname(sc->sc_dev), i)); 1639 DGE_INIT_RXDESC(sc, i); 1640 if (status & RDESC_STS_EOP) { 1641 /* Reset our state. */ 1642 DPRINTF(DGE_DEBUG_RX, 1643 ("%s: RX: resetting rxdiscard -> 0\n", 1644 device_xname(sc->sc_dev))); 1645 sc->sc_rxdiscard = 0; 1646 } 1647 continue; 1648 } 1649 1650 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1651 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1652 1653 m = rxs->rxs_mbuf; 1654 1655 /* 1656 * Add a new receive buffer to the ring. 1657 */ 1658 if (dge_add_rxbuf(sc, i) != 0) { 1659 /* 1660 * Failed, throw away what we've done so 1661 * far, and discard the rest of the packet. 1662 */ 1663 ifp->if_ierrors++; 1664 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1665 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1666 DGE_INIT_RXDESC(sc, i); 1667 if ((status & RDESC_STS_EOP) == 0) 1668 sc->sc_rxdiscard = 1; 1669 if (sc->sc_rxhead != NULL) 1670 m_freem(sc->sc_rxhead); 1671 DGE_RXCHAIN_RESET(sc); 1672 DPRINTF(DGE_DEBUG_RX, 1673 ("%s: RX: Rx buffer allocation failed, " 1674 "dropping packet%s\n", device_xname(sc->sc_dev), 1675 sc->sc_rxdiscard ? " (discard)" : "")); 1676 continue; 1677 } 1678 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1679 1680 DGE_RXCHAIN_LINK(sc, m); 1681 1682 m->m_len = len; 1683 1684 DPRINTF(DGE_DEBUG_RX, 1685 ("%s: RX: buffer at %p len %d\n", 1686 device_xname(sc->sc_dev), m->m_data, len)); 1687 1688 /* 1689 * If this is not the end of the packet, keep 1690 * looking. 1691 */ 1692 if ((status & RDESC_STS_EOP) == 0) { 1693 sc->sc_rxlen += len; 1694 DPRINTF(DGE_DEBUG_RX, 1695 ("%s: RX: not yet EOP, rxlen -> %d\n", 1696 device_xname(sc->sc_dev), sc->sc_rxlen)); 1697 continue; 1698 } 1699 1700 /* 1701 * Okay, we have the entire packet now... 1702 */ 1703 *sc->sc_rxtailp = NULL; 1704 m = sc->sc_rxhead; 1705 len += sc->sc_rxlen; 1706 1707 DGE_RXCHAIN_RESET(sc); 1708 1709 DPRINTF(DGE_DEBUG_RX, 1710 ("%s: RX: have entire packet, len -> %d\n", 1711 device_xname(sc->sc_dev), len)); 1712 1713 /* 1714 * If an error occurred, update stats and drop the packet. 1715 */ 1716 if (errors & 1717 (RDESC_ERR_CE|RDESC_ERR_SE|RDESC_ERR_P|RDESC_ERR_RXE)) { 1718 ifp->if_ierrors++; 1719 if (errors & RDESC_ERR_SE) 1720 printf("%s: symbol error\n", 1721 device_xname(sc->sc_dev)); 1722 else if (errors & RDESC_ERR_P) 1723 printf("%s: parity error\n", 1724 device_xname(sc->sc_dev)); 1725 else if (errors & RDESC_ERR_CE) 1726 printf("%s: CRC error\n", 1727 device_xname(sc->sc_dev)); 1728 m_freem(m); 1729 continue; 1730 } 1731 1732 /* 1733 * No errors. Receive the packet. 1734 */ 1735 m->m_pkthdr.rcvif = ifp; 1736 m->m_pkthdr.len = len; 1737 1738 /* 1739 * Set up checksum info for this packet. 1740 */ 1741 if (status & RDESC_STS_IPCS) { 1742 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1743 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1744 if (errors & RDESC_ERR_IPE) 1745 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1746 } 1747 if (status & RDESC_STS_TCPCS) { 1748 /* 1749 * Note: we don't know if this was TCP or UDP, 1750 * so we just set both bits, and expect the 1751 * upper layers to deal. 1752 */ 1753 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1754 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 1755 if (errors & RDESC_ERR_TCPE) 1756 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1757 } 1758 1759 ifp->if_ipackets++; 1760 1761 /* Pass this up to any BPF listeners. */ 1762 bpf_mtap(ifp, m); 1763 1764 /* Pass it on. */ 1765 (*ifp->if_input)(ifp, m); 1766 } 1767 1768 /* Update the receive pointer. */ 1769 sc->sc_rxptr = i; 1770 1771 DPRINTF(DGE_DEBUG_RX, 1772 ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i)); 1773 } 1774 1775 /* 1776 * dge_linkintr: 1777 * 1778 * Helper; handle link interrupts. 1779 */ 1780 static void 1781 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1782 { 1783 uint32_t status; 1784 1785 if (icr & ICR_LSC) { 1786 status = CSR_READ(sc, DGE_STATUS); 1787 if (status & STATUS_LINKUP) { 1788 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1789 device_xname(sc->sc_dev))); 1790 } else { 1791 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1792 device_xname(sc->sc_dev))); 1793 } 1794 } else if (icr & ICR_RXSEQ) { 1795 DPRINTF(DGE_DEBUG_LINK, 1796 ("%s: LINK: Receive sequence error\n", 1797 device_xname(sc->sc_dev))); 1798 } 1799 /* XXX - fix errata */ 1800 } 1801 1802 /* 1803 * dge_reset: 1804 * 1805 * Reset the i82597 chip. 1806 */ 1807 static void 1808 dge_reset(struct dge_softc *sc) 1809 { 1810 int i; 1811 1812 /* 1813 * Do a chip reset. 1814 */ 1815 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1816 1817 delay(10000); 1818 1819 for (i = 0; i < 1000; i++) { 1820 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1821 break; 1822 delay(20); 1823 } 1824 1825 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1826 printf("%s: WARNING: reset failed to complete\n", 1827 device_xname(sc->sc_dev)); 1828 /* 1829 * Reset the EEPROM logic. 1830 * This will cause the chip to reread its default values, 1831 * which doesn't happen otherwise (errata). 1832 */ 1833 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1834 delay(10000); 1835 } 1836 1837 /* 1838 * dge_init: [ifnet interface function] 1839 * 1840 * Initialize the interface. Must be called at splnet(). 1841 */ 1842 static int 1843 dge_init(struct ifnet *ifp) 1844 { 1845 struct dge_softc *sc = ifp->if_softc; 1846 struct dge_rxsoft *rxs; 1847 int i, error = 0; 1848 uint32_t reg; 1849 1850 /* 1851 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1852 * There is a small but measurable benefit to avoiding the adjusment 1853 * of the descriptor so that the headers are aligned, for normal mtu, 1854 * on such platforms. One possibility is that the DMA itself is 1855 * slightly more efficient if the front of the entire packet (instead 1856 * of the front of the headers) is aligned. 1857 * 1858 * Note we must always set align_tweak to 0 if we are using 1859 * jumbo frames. 1860 */ 1861 #ifdef __NO_STRICT_ALIGNMENT 1862 sc->sc_align_tweak = 0; 1863 #else 1864 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1865 sc->sc_align_tweak = 0; 1866 else 1867 sc->sc_align_tweak = 2; 1868 #endif /* __NO_STRICT_ALIGNMENT */ 1869 1870 /* Cancel any pending I/O. */ 1871 dge_stop(ifp, 0); 1872 1873 /* Reset the chip to a known state. */ 1874 dge_reset(sc); 1875 1876 /* Initialize the transmit descriptor ring. */ 1877 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1878 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1879 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1880 sc->sc_txfree = DGE_NTXDESC; 1881 sc->sc_txnext = 0; 1882 1883 sc->sc_txctx_ipcs = 0xffffffff; 1884 sc->sc_txctx_tucs = 0xffffffff; 1885 1886 CSR_WRITE(sc, DGE_TDBAH, 0); 1887 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1888 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1889 CSR_WRITE(sc, DGE_TDH, 0); 1890 CSR_WRITE(sc, DGE_TDT, 0); 1891 CSR_WRITE(sc, DGE_TIDV, TIDV); 1892 1893 #if 0 1894 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1895 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1896 #endif 1897 CSR_WRITE(sc, DGE_RXDCTL, 1898 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1899 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1900 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1901 1902 /* Initialize the transmit job descriptors. */ 1903 for (i = 0; i < DGE_TXQUEUELEN; i++) 1904 sc->sc_txsoft[i].txs_mbuf = NULL; 1905 sc->sc_txsfree = DGE_TXQUEUELEN; 1906 sc->sc_txsnext = 0; 1907 sc->sc_txsdirty = 0; 1908 1909 /* 1910 * Initialize the receive descriptor and receive job 1911 * descriptor rings. 1912 */ 1913 CSR_WRITE(sc, DGE_RDBAH, 0); 1914 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1915 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1916 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1917 CSR_WRITE(sc, DGE_RDT, 0); 1918 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1919 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1920 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1921 1922 for (i = 0; i < DGE_NRXDESC; i++) { 1923 rxs = &sc->sc_rxsoft[i]; 1924 if (rxs->rxs_mbuf == NULL) { 1925 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1926 printf("%s: unable to allocate or map rx " 1927 "buffer %d, error = %d\n", 1928 device_xname(sc->sc_dev), i, error); 1929 /* 1930 * XXX Should attempt to run with fewer receive 1931 * XXX buffers instead of just failing. 1932 */ 1933 dge_rxdrain(sc); 1934 goto out; 1935 } 1936 } 1937 DGE_INIT_RXDESC(sc, i); 1938 } 1939 sc->sc_rxptr = DGE_RXSPACE; 1940 sc->sc_rxdiscard = 0; 1941 DGE_RXCHAIN_RESET(sc); 1942 1943 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1944 sc->sc_ctrl0 |= CTRL0_JFE; 1945 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1946 } 1947 1948 /* Write the control registers. */ 1949 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1950 1951 /* 1952 * Set up checksum offload parameters. 1953 */ 1954 reg = CSR_READ(sc, DGE_RXCSUM); 1955 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1956 reg |= RXCSUM_IPOFL; 1957 else 1958 reg &= ~RXCSUM_IPOFL; 1959 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1960 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1961 else { 1962 reg &= ~RXCSUM_TUOFL; 1963 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 1964 reg &= ~RXCSUM_IPOFL; 1965 } 1966 CSR_WRITE(sc, DGE_RXCSUM, reg); 1967 1968 /* 1969 * Set up the interrupt registers. 1970 */ 1971 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 1972 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 1973 ICR_RXO | ICR_RXT0; 1974 1975 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 1976 1977 /* 1978 * Set up the transmit control register. 1979 */ 1980 sc->sc_tctl = TCTL_TCE|TCTL_TPDE|TCTL_TXEN; 1981 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 1982 1983 /* 1984 * Set up the receive control register; we actually program 1985 * the register when we set the receive filter. Use multicast 1986 * address offset type 0. 1987 */ 1988 sc->sc_mchash_type = 0; 1989 1990 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 1991 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 1992 1993 #ifdef DGE_OFFBYONE_RXBUG 1994 sc->sc_rctl |= RCTL_BSIZE_16k; 1995 #else 1996 switch(MCLBYTES) { 1997 case 2048: 1998 sc->sc_rctl |= RCTL_BSIZE_2k; 1999 break; 2000 case 4096: 2001 sc->sc_rctl |= RCTL_BSIZE_4k; 2002 break; 2003 case 8192: 2004 sc->sc_rctl |= RCTL_BSIZE_8k; 2005 break; 2006 case 16384: 2007 sc->sc_rctl |= RCTL_BSIZE_16k; 2008 break; 2009 default: 2010 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2011 } 2012 #endif 2013 2014 /* Set the receive filter. */ 2015 /* Also sets RCTL */ 2016 dge_set_filter(sc); 2017 2018 /* ...all done! */ 2019 ifp->if_flags |= IFF_RUNNING; 2020 ifp->if_flags &= ~IFF_OACTIVE; 2021 2022 out: 2023 if (error) 2024 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2025 return (error); 2026 } 2027 2028 /* 2029 * dge_rxdrain: 2030 * 2031 * Drain the receive queue. 2032 */ 2033 static void 2034 dge_rxdrain(struct dge_softc *sc) 2035 { 2036 struct dge_rxsoft *rxs; 2037 int i; 2038 2039 for (i = 0; i < DGE_NRXDESC; i++) { 2040 rxs = &sc->sc_rxsoft[i]; 2041 if (rxs->rxs_mbuf != NULL) { 2042 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2043 m_freem(rxs->rxs_mbuf); 2044 rxs->rxs_mbuf = NULL; 2045 } 2046 } 2047 } 2048 2049 /* 2050 * dge_stop: [ifnet interface function] 2051 * 2052 * Stop transmission on the interface. 2053 */ 2054 static void 2055 dge_stop(struct ifnet *ifp, int disable) 2056 { 2057 struct dge_softc *sc = ifp->if_softc; 2058 struct dge_txsoft *txs; 2059 int i; 2060 2061 /* Stop the transmit and receive processes. */ 2062 CSR_WRITE(sc, DGE_TCTL, 0); 2063 CSR_WRITE(sc, DGE_RCTL, 0); 2064 2065 /* Release any queued transmit buffers. */ 2066 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2067 txs = &sc->sc_txsoft[i]; 2068 if (txs->txs_mbuf != NULL) { 2069 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2070 m_freem(txs->txs_mbuf); 2071 txs->txs_mbuf = NULL; 2072 } 2073 } 2074 2075 /* Mark the interface as down and cancel the watchdog timer. */ 2076 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2077 ifp->if_timer = 0; 2078 2079 if (disable) 2080 dge_rxdrain(sc); 2081 } 2082 2083 /* 2084 * dge_add_rxbuf: 2085 * 2086 * Add a receive buffer to the indiciated descriptor. 2087 */ 2088 static int 2089 dge_add_rxbuf(struct dge_softc *sc, int idx) 2090 { 2091 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2092 struct mbuf *m; 2093 int error; 2094 #ifdef DGE_OFFBYONE_RXBUG 2095 void *buf; 2096 #endif 2097 2098 MGETHDR(m, M_DONTWAIT, MT_DATA); 2099 if (m == NULL) 2100 return (ENOBUFS); 2101 2102 #ifdef DGE_OFFBYONE_RXBUG 2103 if ((buf = dge_getbuf(sc)) == NULL) 2104 return ENOBUFS; 2105 2106 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2107 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2108 m->m_flags |= M_EXT_RW; 2109 2110 if (rxs->rxs_mbuf != NULL) 2111 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2112 rxs->rxs_mbuf = m; 2113 2114 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2115 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 2116 #else 2117 MCLGET(m, M_DONTWAIT); 2118 if ((m->m_flags & M_EXT) == 0) { 2119 m_freem(m); 2120 return (ENOBUFS); 2121 } 2122 2123 if (rxs->rxs_mbuf != NULL) 2124 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2125 2126 rxs->rxs_mbuf = m; 2127 2128 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2129 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2130 BUS_DMA_READ|BUS_DMA_NOWAIT); 2131 #endif 2132 if (error) { 2133 printf("%s: unable to load rx DMA map %d, error = %d\n", 2134 device_xname(sc->sc_dev), idx, error); 2135 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2136 } 2137 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2138 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2139 2140 return (0); 2141 } 2142 2143 /* 2144 * dge_set_ral: 2145 * 2146 * Set an entry in the receive address list. 2147 */ 2148 static void 2149 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2150 { 2151 uint32_t ral_lo, ral_hi; 2152 2153 if (enaddr != NULL) { 2154 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2155 (enaddr[3] << 24); 2156 ral_hi = enaddr[4] | (enaddr[5] << 8); 2157 ral_hi |= RAH_AV; 2158 } else { 2159 ral_lo = 0; 2160 ral_hi = 0; 2161 } 2162 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2163 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2164 } 2165 2166 /* 2167 * dge_mchash: 2168 * 2169 * Compute the hash of the multicast address for the 4096-bit 2170 * multicast filter. 2171 */ 2172 static uint32_t 2173 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2174 { 2175 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2176 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2177 uint32_t hash; 2178 2179 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2180 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2181 2182 return (hash & 0xfff); 2183 } 2184 2185 /* 2186 * dge_set_filter: 2187 * 2188 * Set up the receive filter. 2189 */ 2190 static void 2191 dge_set_filter(struct dge_softc *sc) 2192 { 2193 struct ethercom *ec = &sc->sc_ethercom; 2194 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2195 struct ether_multi *enm; 2196 struct ether_multistep step; 2197 uint32_t hash, reg, bit; 2198 int i; 2199 2200 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2201 2202 if (ifp->if_flags & IFF_BROADCAST) 2203 sc->sc_rctl |= RCTL_BAM; 2204 if (ifp->if_flags & IFF_PROMISC) { 2205 sc->sc_rctl |= RCTL_UPE; 2206 goto allmulti; 2207 } 2208 2209 /* 2210 * Set the station address in the first RAL slot, and 2211 * clear the remaining slots. 2212 */ 2213 dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 2214 for (i = 1; i < RA_TABSIZE; i++) 2215 dge_set_ral(sc, NULL, i); 2216 2217 /* Clear out the multicast table. */ 2218 for (i = 0; i < MC_TABSIZE; i++) 2219 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2220 2221 ETHER_FIRST_MULTI(step, ec, enm); 2222 while (enm != NULL) { 2223 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2224 /* 2225 * We must listen to a range of multicast addresses. 2226 * For now, just accept all multicasts, rather than 2227 * trying to set only those filter bits needed to match 2228 * the range. (At this time, the only use of address 2229 * ranges is for IP multicast routing, for which the 2230 * range is big enough to require all bits set.) 2231 */ 2232 goto allmulti; 2233 } 2234 2235 hash = dge_mchash(sc, enm->enm_addrlo); 2236 2237 reg = (hash >> 5) & 0x7f; 2238 bit = hash & 0x1f; 2239 2240 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2241 hash |= 1U << bit; 2242 2243 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2244 2245 ETHER_NEXT_MULTI(step, enm); 2246 } 2247 2248 ifp->if_flags &= ~IFF_ALLMULTI; 2249 goto setit; 2250 2251 allmulti: 2252 ifp->if_flags |= IFF_ALLMULTI; 2253 sc->sc_rctl |= RCTL_MPE; 2254 2255 setit: 2256 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2257 } 2258 2259 /* 2260 * Read in the EEPROM info and verify checksum. 2261 */ 2262 int 2263 dge_read_eeprom(struct dge_softc *sc) 2264 { 2265 uint16_t cksum; 2266 int i; 2267 2268 cksum = 0; 2269 for (i = 0; i < EEPROM_SIZE; i++) { 2270 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2271 cksum += sc->sc_eeprom[i]; 2272 } 2273 return cksum != EEPROM_CKSUM; 2274 } 2275 2276 2277 /* 2278 * Read a 16-bit word from address addr in the serial EEPROM. 2279 */ 2280 uint16_t 2281 dge_eeprom_word(struct dge_softc *sc, int addr) 2282 { 2283 uint32_t reg; 2284 uint16_t rval = 0; 2285 int i; 2286 2287 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK|EECD_DI|EECD_CS); 2288 2289 /* Lower clock pulse (and data in to chip) */ 2290 CSR_WRITE(sc, DGE_EECD, reg); 2291 /* Select chip */ 2292 CSR_WRITE(sc, DGE_EECD, reg|EECD_CS); 2293 2294 /* Send read command */ 2295 dge_eeprom_clockout(sc, 1); 2296 dge_eeprom_clockout(sc, 1); 2297 dge_eeprom_clockout(sc, 0); 2298 2299 /* Send address */ 2300 for (i = 5; i >= 0; i--) 2301 dge_eeprom_clockout(sc, (addr >> i) & 1); 2302 2303 /* Read data */ 2304 for (i = 0; i < 16; i++) { 2305 rval <<= 1; 2306 rval |= dge_eeprom_clockin(sc); 2307 } 2308 2309 /* Deselect chip */ 2310 CSR_WRITE(sc, DGE_EECD, reg); 2311 2312 return rval; 2313 } 2314 2315 /* 2316 * Clock out a single bit to the EEPROM. 2317 */ 2318 void 2319 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2320 { 2321 int reg; 2322 2323 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_SK); 2324 if (bit) 2325 reg |= EECD_DI; 2326 2327 CSR_WRITE(sc, DGE_EECD, reg); 2328 delay(2); 2329 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); 2330 delay(2); 2331 CSR_WRITE(sc, DGE_EECD, reg); 2332 delay(2); 2333 } 2334 2335 /* 2336 * Clock in a single bit from EEPROM. 2337 */ 2338 int 2339 dge_eeprom_clockin(struct dge_softc *sc) 2340 { 2341 int reg, rv; 2342 2343 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI|EECD_DO|EECD_SK); 2344 2345 CSR_WRITE(sc, DGE_EECD, reg|EECD_SK); /* Raise clock */ 2346 delay(2); 2347 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2348 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2349 delay(2); 2350 2351 return rv; 2352 } 2353 2354 static void 2355 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2356 { 2357 struct dge_softc *sc = ifp->if_softc; 2358 2359 ifmr->ifm_status = IFM_AVALID; 2360 ifmr->ifm_active = IFM_ETHER|IFM_10G_LR; 2361 2362 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2363 ifmr->ifm_status |= IFM_ACTIVE; 2364 } 2365 2366 static inline int 2367 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2368 { 2369 int i, mdic; 2370 2371 CSR_WRITE(sc, DGE_MDIO, 2372 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2373 for (i = 0; i < 10; i++) { 2374 delay(10); 2375 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2376 break; 2377 } 2378 return mdic; 2379 } 2380 2381 2382 static void 2383 dge_xgmii_writereg(device_t self, int phy, int reg, int val) 2384 { 2385 struct dge_softc *sc = device_private(self); 2386 int mdic; 2387 2388 CSR_WRITE(sc, DGE_MDIRW, val); 2389 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2390 printf("%s: address cycle timeout; phy %d reg %d\n", 2391 device_xname(sc->sc_dev), phy, reg); 2392 return; 2393 } 2394 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2395 printf("%s: read cycle timeout; phy %d reg %d\n", 2396 device_xname(sc->sc_dev), phy, reg); 2397 return; 2398 } 2399 } 2400 2401 static void 2402 dge_xgmii_reset(struct dge_softc *sc) 2403 { 2404 dge_xgmii_writereg((void *)sc, 0, 0, BMCR_RESET); 2405 } 2406 2407 static int 2408 dge_xgmii_mediachange(struct ifnet *ifp) 2409 { 2410 return 0; 2411 } 2412