1 /* $NetBSD: if_dge.c,v 1.58 2020/03/01 15:11:31 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2004, SUNET, Swedish University Computer Network. 5 * All rights reserved. 6 * 7 * Written by Anders Magnusson for SUNET, Swedish University Computer Network. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * SUNET, Swedish University Computer Network. 21 * 4. The name of SUNET may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. 39 * All rights reserved. 40 * 41 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed for the NetBSD Project by 54 * Wasabi Systems, Inc. 55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 56 * or promote products derived from this software without specific prior 57 * written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the Intel 82597EX Ten Gigabit Ethernet controller. 74 * 75 * TODO (in no specific order): 76 * HW VLAN support. 77 * TSE offloading (needs kernel changes...) 78 * RAIDC (receive interrupt delay adaptation) 79 * Use memory > 4GB. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_dge.c,v 1.58 2020/03/01 15:11:31 thorpej Exp $"); 84 85 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 #include <sys/rndsource.h> 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 #include <net/bpf.h> 105 106 #include <netinet/in.h> /* XXX for struct ip */ 107 #include <netinet/in_systm.h> /* XXX for struct ip */ 108 #include <netinet/ip.h> /* XXX for struct ip */ 109 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 110 111 #include <sys/bus.h> 112 #include <sys/intr.h> 113 #include <machine/endian.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/miivar.h> 117 #include <dev/mii/mii_bitbang.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pcidevs.h> 122 123 #include <dev/pci/if_dgereg.h> 124 125 /* 126 * The receive engine may sometimes become off-by-one when writing back 127 * chained descriptors. Avoid this by allocating a large chunk of 128 * memory and use if instead (to avoid chained descriptors). 129 * This only happens with chained descriptors under heavy load. 130 */ 131 #define DGE_OFFBYONE_RXBUG 132 133 #define DGE_EVENT_COUNTERS 134 #define DGE_DEBUG 135 136 #ifdef DGE_DEBUG 137 #define DGE_DEBUG_LINK 0x01 138 #define DGE_DEBUG_TX 0x02 139 #define DGE_DEBUG_RX 0x04 140 #define DGE_DEBUG_CKSUM 0x08 141 int dge_debug = 0; 142 143 #define DPRINTF(x, y) if (dge_debug & (x)) printf y 144 #else 145 #define DPRINTF(x, y) /* nothing */ 146 #endif /* DGE_DEBUG */ 147 148 /* 149 * Transmit descriptor list size. We allow up to 100 DMA segments per 150 * packet (Intel reports of jumbo frame packets with as 151 * many as 80 DMA segments when using 16k buffers). 152 */ 153 #define DGE_NTXSEGS 100 154 #define DGE_IFQUEUELEN 20000 155 #define DGE_TXQUEUELEN 2048 156 #define DGE_TXQUEUELEN_MASK (DGE_TXQUEUELEN - 1) 157 #define DGE_TXQUEUE_GC (DGE_TXQUEUELEN / 8) 158 #define DGE_NTXDESC 1024 159 #define DGE_NTXDESC_MASK (DGE_NTXDESC - 1) 160 #define DGE_NEXTTX(x) (((x) + 1) & DGE_NTXDESC_MASK) 161 #define DGE_NEXTTXS(x) (((x) + 1) & DGE_TXQUEUELEN_MASK) 162 163 /* 164 * Receive descriptor list size. 165 * Packet is of size MCLBYTES, and for jumbo packets buffers may 166 * be chained. Due to the nature of the card (high-speed), keep this 167 * ring large. With 2k buffers the ring can store 400 jumbo packets, 168 * which at full speed will be received in just under 3ms. 169 */ 170 #define DGE_NRXDESC 2048 171 #define DGE_NRXDESC_MASK (DGE_NRXDESC - 1) 172 #define DGE_NEXTRX(x) (((x) + 1) & DGE_NRXDESC_MASK) 173 /* 174 * # of descriptors between head and written descriptors. 175 * This is to work-around two erratas. 176 */ 177 #define DGE_RXSPACE 10 178 #define DGE_PREVRX(x) (((x) - DGE_RXSPACE) & DGE_NRXDESC_MASK) 179 /* 180 * Receive descriptor fetch threshholds. These are values recommended 181 * by Intel, do not touch them unless you know what you are doing. 182 */ 183 #define RXDCTL_PTHRESH_VAL 128 184 #define RXDCTL_HTHRESH_VAL 16 185 #define RXDCTL_WTHRESH_VAL 16 186 187 188 /* 189 * Tweakable parameters; default values. 190 */ 191 #define FCRTH 0x30000 /* Send XOFF water mark */ 192 #define FCRTL 0x28000 /* Send XON water mark */ 193 #define RDTR 0x20 /* Interrupt delay after receive, .8192us units */ 194 #define TIDV 0x20 /* Interrupt delay after send, .8192us units */ 195 196 /* 197 * Control structures are DMA'd to the i82597 chip. We allocate them in 198 * a single clump that maps to a single DMA segment to make serveral things 199 * easier. 200 */ 201 struct dge_control_data { 202 /* 203 * The transmit descriptors. 204 */ 205 struct dge_tdes wcd_txdescs[DGE_NTXDESC]; 206 207 /* 208 * The receive descriptors. 209 */ 210 struct dge_rdes wcd_rxdescs[DGE_NRXDESC]; 211 }; 212 213 #define DGE_CDOFF(x) offsetof(struct dge_control_data, x) 214 #define DGE_CDTXOFF(x) DGE_CDOFF(wcd_txdescs[(x)]) 215 #define DGE_CDRXOFF(x) DGE_CDOFF(wcd_rxdescs[(x)]) 216 217 /* 218 * The DGE interface have a higher max MTU size than normal jumbo frames. 219 */ 220 #define DGE_MAX_MTU 16288 /* Max MTU size for this interface */ 221 222 /* 223 * Software state for transmit jobs. 224 */ 225 struct dge_txsoft { 226 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 227 bus_dmamap_t txs_dmamap; /* our DMA map */ 228 int txs_firstdesc; /* first descriptor in packet */ 229 int txs_lastdesc; /* last descriptor in packet */ 230 int txs_ndesc; /* # of descriptors used */ 231 }; 232 233 /* 234 * Software state for receive buffers. Each descriptor gets a 235 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 236 * more than one buffer, we chain them together. 237 */ 238 struct dge_rxsoft { 239 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 240 bus_dmamap_t rxs_dmamap; /* our DMA map */ 241 }; 242 243 /* 244 * Software state per device. 245 */ 246 struct dge_softc { 247 device_t sc_dev; /* generic device information */ 248 bus_space_tag_t sc_st; /* bus space tag */ 249 bus_space_handle_t sc_sh; /* bus space handle */ 250 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 251 struct ethercom sc_ethercom; /* ethernet common data */ 252 253 int sc_flags; /* flags; see below */ 254 int sc_bus_speed; /* PCI/PCIX bus speed */ 255 int sc_pcix_offset; /* PCIX capability register offset */ 256 257 const struct dge_product *sc_dgep; /* Pointer to the dge_product entry */ 258 pci_chipset_tag_t sc_pc; 259 pcitag_t sc_pt; 260 int sc_mmrbc; /* Max PCIX memory read byte count */ 261 262 void *sc_ih; /* interrupt cookie */ 263 264 struct ifmedia sc_media; 265 266 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 267 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 268 269 int sc_align_tweak; 270 271 /* 272 * Software state for the transmit and receive descriptors. 273 */ 274 struct dge_txsoft sc_txsoft[DGE_TXQUEUELEN]; 275 struct dge_rxsoft sc_rxsoft[DGE_NRXDESC]; 276 277 /* 278 * Control data structures. 279 */ 280 struct dge_control_data *sc_control_data; 281 #define sc_txdescs sc_control_data->wcd_txdescs 282 #define sc_rxdescs sc_control_data->wcd_rxdescs 283 284 #ifdef DGE_EVENT_COUNTERS 285 /* Event counters. */ 286 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 287 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 288 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 289 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 290 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 291 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 292 struct evcnt sc_ev_linkintr; /* Link interrupts */ 293 294 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 295 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 296 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 297 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 298 299 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 300 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 301 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 302 303 struct evcnt sc_ev_txseg[DGE_NTXSEGS]; /* Tx packets w/ N segments */ 304 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 305 #endif /* DGE_EVENT_COUNTERS */ 306 307 int sc_txfree; /* number of free Tx descriptors */ 308 int sc_txnext; /* next ready Tx descriptor */ 309 310 int sc_txsfree; /* number of free Tx jobs */ 311 int sc_txsnext; /* next free Tx job */ 312 int sc_txsdirty; /* dirty Tx jobs */ 313 314 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 315 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 316 317 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 318 int sc_rxdiscard; 319 int sc_rxlen; 320 struct mbuf *sc_rxhead; 321 struct mbuf *sc_rxtail; 322 struct mbuf **sc_rxtailp; 323 324 uint32_t sc_ctrl0; /* prototype CTRL0 register */ 325 uint32_t sc_icr; /* prototype interrupt bits */ 326 uint32_t sc_tctl; /* prototype TCTL register */ 327 uint32_t sc_rctl; /* prototype RCTL register */ 328 329 int sc_mchash_type; /* multicast filter offset */ 330 331 uint16_t sc_eeprom[EEPROM_SIZE]; 332 333 krndsource_t rnd_source; /* random source */ 334 #ifdef DGE_OFFBYONE_RXBUG 335 void *sc_bugbuf; 336 SLIST_HEAD(, rxbugentry) sc_buglist; 337 bus_dmamap_t sc_bugmap; 338 struct rxbugentry *sc_entry; 339 #endif 340 }; 341 342 #define DGE_RXCHAIN_RESET(sc) \ 343 do { \ 344 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 345 *(sc)->sc_rxtailp = NULL; \ 346 (sc)->sc_rxlen = 0; \ 347 } while (/*CONSTCOND*/0) 348 349 #define DGE_RXCHAIN_LINK(sc, m) \ 350 do { \ 351 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 352 (sc)->sc_rxtailp = &(m)->m_next; \ 353 } while (/*CONSTCOND*/0) 354 355 /* sc_flags */ 356 #define DGE_F_BUS64 0x20 /* bus is 64-bit */ 357 #define DGE_F_PCIX 0x40 /* bus is PCI-X */ 358 359 #ifdef DGE_EVENT_COUNTERS 360 #define DGE_EVCNT_INCR(ev) (ev)->ev_count++ 361 #else 362 #define DGE_EVCNT_INCR(ev) /* nothing */ 363 #endif 364 365 #define CSR_READ(sc, reg) \ 366 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 367 #define CSR_WRITE(sc, reg, val) \ 368 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 369 370 #define DGE_CDTXADDR(sc, x) ((sc)->sc_cddma + DGE_CDTXOFF((x))) 371 #define DGE_CDRXADDR(sc, x) ((sc)->sc_cddma + DGE_CDRXOFF((x))) 372 373 #define DGE_CDTXSYNC(sc, x, n, ops) \ 374 do { \ 375 int __x, __n; \ 376 \ 377 __x = (x); \ 378 __n = (n); \ 379 \ 380 /* If it will wrap around, sync to the end of the ring. */ \ 381 if ((__x + __n) > DGE_NTXDESC) { \ 382 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 383 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * \ 384 (DGE_NTXDESC - __x), (ops)); \ 385 __n -= (DGE_NTXDESC - __x); \ 386 __x = 0; \ 387 } \ 388 \ 389 /* Now sync whatever is left. */ \ 390 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 391 DGE_CDTXOFF(__x), sizeof(struct dge_tdes) * __n, (ops)); \ 392 } while (/*CONSTCOND*/0) 393 394 #define DGE_CDRXSYNC(sc, x, ops) \ 395 do { \ 396 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 397 DGE_CDRXOFF((x)), sizeof(struct dge_rdes), (ops)); \ 398 } while (/*CONSTCOND*/0) 399 400 #ifdef DGE_OFFBYONE_RXBUG 401 #define DGE_INIT_RXDESC(sc, x) \ 402 do { \ 403 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 404 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 405 struct mbuf *__m = __rxs->rxs_mbuf; \ 406 const bus_addr_t __rxaddr = sc->sc_bugmap->dm_segs[0].ds_addr + \ 407 (mtod((__m), char *) - (char *)sc->sc_bugbuf); \ 408 \ 409 __rxd->dr_baddrl = htole32(__rxaddr); \ 410 __rxd->dr_baddrh = htole32(((uint64_t)__rxaddr) >> 32); \ 411 __rxd->dr_len = 0; \ 412 __rxd->dr_cksum = 0; \ 413 __rxd->dr_status = 0; \ 414 __rxd->dr_errors = 0; \ 415 __rxd->dr_special = 0; \ 416 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 417 \ 418 CSR_WRITE((sc), DGE_RDT, (x)); \ 419 } while (/*CONSTCOND*/0) 420 #else 421 #define DGE_INIT_RXDESC(sc, x) \ 422 do { \ 423 struct dge_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 424 struct dge_rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \ 425 struct mbuf *__m = __rxs->rxs_mbuf; \ 426 \ 427 /* \ 428 * Note: We scoot the packet forward 2 bytes in the buffer \ 429 * so that the payload after the Ethernet header is aligned \ 430 * to a 4-byte boundary. \ 431 * \ 432 * XXX BRAINDAMAGE ALERT! \ 433 * The stupid chip uses the same size for every buffer, which \ 434 * is set in the Receive Control register. We are using the 2K \ 435 * size option, but what we REALLY want is (2K - 2)! For this \ 436 * reason, we can't "scoot" packets longer than the standard \ 437 * Ethernet MTU. On strict-alignment platforms, if the total \ 438 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 439 * the upper layer copy the headers. \ 440 */ \ 441 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 442 \ 443 const bus_addr_t __rxaddr = \ 444 __rxs->rxs_dmamap->dm_segs[0].ds_addr + \ 445 (sc)->sc_align_tweak; \ 446 \ 447 __rxd->dr_baddrl = htole32(__rxaddr); \ 448 __rxd->dr_baddrh = htole32(((uint64_t)__rxaddr) >> 32); \ 449 __rxd->dr_len = 0; \ 450 __rxd->dr_cksum = 0; \ 451 __rxd->dr_status = 0; \ 452 __rxd->dr_errors = 0; \ 453 __rxd->dr_special = 0; \ 454 DGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 455 \ 456 CSR_WRITE((sc), DGE_RDT, (x)); \ 457 } while (/*CONSTCOND*/0) 458 #endif 459 460 #ifdef DGE_OFFBYONE_RXBUG 461 /* 462 * Allocation constants. Much memory may be used for this. 463 */ 464 #ifndef DGE_BUFFER_SIZE 465 #define DGE_BUFFER_SIZE DGE_MAX_MTU 466 #endif 467 #define DGE_NBUFFERS (4*DGE_NRXDESC) 468 #define DGE_RXMEM (DGE_NBUFFERS*DGE_BUFFER_SIZE) 469 470 struct rxbugentry { 471 SLIST_ENTRY(rxbugentry) rb_entry; 472 int rb_slot; 473 }; 474 475 static int 476 dge_alloc_rcvmem(struct dge_softc *sc) 477 { 478 char *kva; 479 bus_dma_segment_t seg; 480 int i, rseg, state, error; 481 struct rxbugentry *entry; 482 483 state = error = 0; 484 485 if (bus_dmamem_alloc(sc->sc_dmat, DGE_RXMEM, PAGE_SIZE, 0, 486 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 487 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 488 return ENOBUFS; 489 } 490 491 state = 1; 492 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, DGE_RXMEM, (void **)&kva, 493 BUS_DMA_NOWAIT)) { 494 aprint_error_dev(sc->sc_dev, 495 "can't map DMA buffers (%d bytes)\n", (int)DGE_RXMEM); 496 error = ENOBUFS; 497 goto out; 498 } 499 500 state = 2; 501 if (bus_dmamap_create(sc->sc_dmat, DGE_RXMEM, 1, DGE_RXMEM, 0, 502 BUS_DMA_NOWAIT, &sc->sc_bugmap)) { 503 aprint_error_dev(sc->sc_dev, "can't create DMA map\n"); 504 error = ENOBUFS; 505 goto out; 506 } 507 508 state = 3; 509 if (bus_dmamap_load(sc->sc_dmat, sc->sc_bugmap, 510 kva, DGE_RXMEM, NULL, BUS_DMA_NOWAIT)) { 511 aprint_error_dev(sc->sc_dev, "can't load DMA map\n"); 512 error = ENOBUFS; 513 goto out; 514 } 515 516 state = 4; 517 sc->sc_bugbuf = (void *)kva; 518 SLIST_INIT(&sc->sc_buglist); 519 520 /* 521 * Now divide it up into DGE_BUFFER_SIZE pieces and save the addresses 522 * in an array. 523 */ 524 entry = malloc(sizeof(*entry) * DGE_NBUFFERS, M_DEVBUF, M_WAITOK); 525 sc->sc_entry = entry; 526 for (i = 0; i < DGE_NBUFFERS; i++) { 527 entry[i].rb_slot = i; 528 SLIST_INSERT_HEAD(&sc->sc_buglist, &entry[i], rb_entry); 529 } 530 out: 531 if (error != 0) { 532 switch (state) { 533 case 4: 534 bus_dmamap_unload(sc->sc_dmat, sc->sc_bugmap); 535 /* FALLTHROUGH */ 536 case 3: 537 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bugmap); 538 /* FALLTHROUGH */ 539 case 2: 540 bus_dmamem_unmap(sc->sc_dmat, kva, DGE_RXMEM); 541 /* FALLTHROUGH */ 542 case 1: 543 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 544 break; 545 default: 546 break; 547 } 548 } 549 550 return error; 551 } 552 553 /* 554 * Allocate a jumbo buffer. 555 */ 556 static void * 557 dge_getbuf(struct dge_softc *sc) 558 { 559 struct rxbugentry *entry; 560 561 entry = SLIST_FIRST(&sc->sc_buglist); 562 563 if (entry == NULL) { 564 printf("%s: no free RX buffers\n", device_xname(sc->sc_dev)); 565 return NULL; 566 } 567 568 SLIST_REMOVE_HEAD(&sc->sc_buglist, rb_entry); 569 return (char *)sc->sc_bugbuf + entry->rb_slot * DGE_BUFFER_SIZE; 570 } 571 572 /* 573 * Release a jumbo buffer. 574 */ 575 static void 576 dge_freebuf(struct mbuf *m, void *buf, size_t size, void *arg) 577 { 578 struct rxbugentry *entry; 579 struct dge_softc *sc; 580 int i, s; 581 582 /* Extract the softc struct pointer. */ 583 sc = (struct dge_softc *)arg; 584 585 if (sc == NULL) 586 panic("dge_freebuf: can't find softc pointer!"); 587 588 /* calculate the slot this buffer belongs to */ 589 590 i = ((char *)buf - (char *)sc->sc_bugbuf) / DGE_BUFFER_SIZE; 591 592 if ((i < 0) || (i >= DGE_NBUFFERS)) 593 panic("dge_freebuf: asked to free buffer %d!", i); 594 595 s = splvm(); 596 entry = sc->sc_entry + i; 597 SLIST_INSERT_HEAD(&sc->sc_buglist, entry, rb_entry); 598 599 if (__predict_true(m != NULL)) 600 pool_cache_put(mb_cache, m); 601 splx(s); 602 } 603 #endif 604 605 static void dge_start(struct ifnet *); 606 static void dge_watchdog(struct ifnet *); 607 static int dge_ioctl(struct ifnet *, u_long, void *); 608 static int dge_init(struct ifnet *); 609 static void dge_stop(struct ifnet *, int); 610 611 static bool dge_shutdown(device_t, int); 612 613 static void dge_reset(struct dge_softc *); 614 static void dge_rxdrain(struct dge_softc *); 615 static int dge_add_rxbuf(struct dge_softc *, int); 616 617 static void dge_set_filter(struct dge_softc *); 618 619 static int dge_intr(void *); 620 static void dge_txintr(struct dge_softc *); 621 static void dge_rxintr(struct dge_softc *); 622 static void dge_linkintr(struct dge_softc *, uint32_t); 623 624 static int dge_match(device_t, cfdata_t, void *); 625 static void dge_attach(device_t, device_t, void *); 626 627 static int dge_read_eeprom(struct dge_softc *sc); 628 static int dge_eeprom_clockin(struct dge_softc *sc); 629 static void dge_eeprom_clockout(struct dge_softc *sc, int bit); 630 static uint16_t dge_eeprom_word(struct dge_softc *sc, int addr); 631 static int dge_xgmii_mediachange(struct ifnet *); 632 static void dge_xgmii_mediastatus(struct ifnet *, struct ifmediareq *); 633 static void dge_xgmii_reset(struct dge_softc *); 634 static void dge_xgmii_writereg(struct dge_softc *, int, int, int); 635 636 637 CFATTACH_DECL_NEW(dge, sizeof(struct dge_softc), 638 dge_match, dge_attach, NULL, NULL); 639 640 #ifdef DGE_EVENT_COUNTERS 641 #if DGE_NTXSEGS > 100 642 #error Update dge_txseg_evcnt_names 643 #endif 644 static char (*dge_txseg_evcnt_names)[DGE_NTXSEGS][8 /* "txseg00" + \0 */]; 645 #endif /* DGE_EVENT_COUNTERS */ 646 647 /* 648 * Devices supported by this driver. 649 */ 650 static const struct dge_product { 651 pci_vendor_id_t dgep_vendor; 652 pci_product_id_t dgep_product; 653 const char *dgep_name; 654 int dgep_flags; 655 #define DGEP_F_10G_LR 0x01 656 #define DGEP_F_10G_SR 0x02 657 } dge_products[] = { 658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX, 659 "Intel i82597EX 10GbE-LR Ethernet", 660 DGEP_F_10G_LR }, 661 662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82597EX_SR, 663 "Intel i82597EX 10GbE-SR Ethernet", 664 DGEP_F_10G_SR }, 665 666 { 0, 0, 667 NULL, 668 0 }, 669 }; 670 671 static const struct dge_product * 672 dge_lookup(const struct pci_attach_args *pa) 673 { 674 const struct dge_product *dgep; 675 676 for (dgep = dge_products; dgep->dgep_name != NULL; dgep++) { 677 if (PCI_VENDOR(pa->pa_id) == dgep->dgep_vendor && 678 PCI_PRODUCT(pa->pa_id) == dgep->dgep_product) 679 return dgep; 680 } 681 return NULL; 682 } 683 684 static int 685 dge_match(device_t parent, cfdata_t cf, void *aux) 686 { 687 struct pci_attach_args *pa = aux; 688 689 if (dge_lookup(pa) != NULL) 690 return 1; 691 692 return 0; 693 } 694 695 static void 696 dge_attach(device_t parent, device_t self, void *aux) 697 { 698 struct dge_softc *sc = device_private(self); 699 struct pci_attach_args *pa = aux; 700 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 701 pci_chipset_tag_t pc = pa->pa_pc; 702 pci_intr_handle_t ih; 703 const char *intrstr = NULL; 704 bus_dma_segment_t seg; 705 int i, rseg, error; 706 uint8_t enaddr[ETHER_ADDR_LEN]; 707 pcireg_t preg, memtype; 708 uint32_t reg; 709 char intrbuf[PCI_INTRSTR_LEN]; 710 const struct dge_product *dgep; 711 712 sc->sc_dgep = dgep = dge_lookup(pa); 713 if (dgep == NULL) { 714 printf("\n"); 715 panic("dge_attach: impossible"); 716 } 717 718 sc->sc_dev = self; 719 sc->sc_pc = pa->pa_pc; 720 sc->sc_pt = pa->pa_tag; 721 722 if (pci_dma64_available(pa)) 723 sc->sc_dmat = pa->pa_dmat64; 724 else 725 sc->sc_dmat = pa->pa_dmat; 726 727 pci_aprint_devinfo_fancy(pa, "Ethernet controller", 728 dgep->dgep_name, 1); 729 730 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, DGE_PCI_BAR); 731 if (pci_mapreg_map(pa, DGE_PCI_BAR, memtype, 0, 732 &sc->sc_st, &sc->sc_sh, NULL, NULL)) { 733 aprint_error_dev(sc->sc_dev, 734 "unable to map device registers\n"); 735 return; 736 } 737 738 /* Enable bus mastering */ 739 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 740 preg |= PCI_COMMAND_MASTER_ENABLE; 741 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 742 743 /* 744 * Map and establish our interrupt. 745 */ 746 if (pci_intr_map(pa, &ih)) { 747 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 748 return; 749 } 750 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 751 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, dge_intr, sc, 752 device_xname(self)); 753 if (sc->sc_ih == NULL) { 754 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 755 if (intrstr != NULL) 756 aprint_error(" at %s", intrstr); 757 aprint_error("\n"); 758 return; 759 } 760 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 761 762 /* 763 * Determine a few things about the bus we're connected to. 764 */ 765 reg = CSR_READ(sc, DGE_STATUS); 766 if (reg & STATUS_BUS64) 767 sc->sc_flags |= DGE_F_BUS64; 768 769 sc->sc_flags |= DGE_F_PCIX; 770 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 771 PCI_CAP_PCIX, 772 &sc->sc_pcix_offset, NULL) == 0) 773 aprint_error_dev(sc->sc_dev, "unable to find PCIX " 774 "capability\n"); 775 776 if (sc->sc_flags & DGE_F_PCIX) { 777 switch (reg & STATUS_PCIX_MSK) { 778 case STATUS_PCIX_66: 779 sc->sc_bus_speed = 66; 780 break; 781 case STATUS_PCIX_100: 782 sc->sc_bus_speed = 100; 783 break; 784 case STATUS_PCIX_133: 785 sc->sc_bus_speed = 133; 786 break; 787 default: 788 aprint_error_dev(sc->sc_dev, 789 "unknown PCIXSPD %d; assuming 66MHz\n", 790 reg & STATUS_PCIX_MSK); 791 sc->sc_bus_speed = 66; 792 } 793 } else 794 sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33; 795 aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", 796 (sc->sc_flags & DGE_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 797 (sc->sc_flags & DGE_F_PCIX) ? "PCIX" : "PCI"); 798 799 /* 800 * Allocate the control data structures, and create and load the 801 * DMA map for it. 802 */ 803 if ((error = bus_dmamem_alloc(sc->sc_dmat, 804 sizeof(struct dge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 805 0)) != 0) { 806 aprint_error_dev(sc->sc_dev, 807 "unable to allocate control data, error = %d\n", 808 error); 809 goto fail_0; 810 } 811 812 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 813 sizeof(struct dge_control_data), (void **)&sc->sc_control_data, 814 0)) != 0) { 815 aprint_error_dev(sc->sc_dev, 816 "unable to map control data, error = %d\n", error); 817 goto fail_1; 818 } 819 820 if ((error = bus_dmamap_create(sc->sc_dmat, 821 sizeof(struct dge_control_data), 1, 822 sizeof(struct dge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 823 aprint_error_dev(sc->sc_dev, "unable to create control data " 824 "DMA map, error = %d\n", error); 825 goto fail_2; 826 } 827 828 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 829 sc->sc_control_data, sizeof(struct dge_control_data), NULL, 830 0)) != 0) { 831 aprint_error_dev(sc->sc_dev, 832 "unable to load control data DMA map, error = %d\n", 833 error); 834 goto fail_3; 835 } 836 837 #ifdef DGE_OFFBYONE_RXBUG 838 if (dge_alloc_rcvmem(sc) != 0) 839 return; /* Already complained */ 840 #endif 841 /* 842 * Create the transmit buffer DMA maps. 843 */ 844 for (i = 0; i < DGE_TXQUEUELEN; i++) { 845 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_MAX_MTU, 846 DGE_NTXSEGS, MCLBYTES, 0, 0, 847 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 848 aprint_error_dev(sc->sc_dev, "unable to create Tx DMA map %d, " 849 "error = %d\n", i, error); 850 goto fail_4; 851 } 852 } 853 854 /* 855 * Create the receive buffer DMA maps. 856 */ 857 for (i = 0; i < DGE_NRXDESC; i++) { 858 #ifdef DGE_OFFBYONE_RXBUG 859 if ((error = bus_dmamap_create(sc->sc_dmat, DGE_BUFFER_SIZE, 1, 860 DGE_BUFFER_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 861 #else 862 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 863 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 864 #endif 865 aprint_error_dev(sc->sc_dev, "unable to create Rx DMA " 866 "map %d, error = %d\n", i, error); 867 goto fail_5; 868 } 869 sc->sc_rxsoft[i].rxs_mbuf = NULL; 870 } 871 872 /* 873 * Set bits in ctrl0 register. 874 * Should get the software defined pins out of EEPROM? 875 */ 876 sc->sc_ctrl0 |= CTRL0_RPE | CTRL0_TPE; /* XON/XOFF */ 877 sc->sc_ctrl0 |= CTRL0_SDP3_DIR | CTRL0_SDP2_DIR | CTRL0_SDP1_DIR | 878 CTRL0_SDP0_DIR | CTRL0_SDP3 | CTRL0_SDP2 | CTRL0_SDP0; 879 880 /* 881 * Reset the chip to a known state. 882 */ 883 dge_reset(sc); 884 885 /* 886 * Reset the PHY. 887 */ 888 dge_xgmii_reset(sc); 889 890 /* 891 * Read in EEPROM data. 892 */ 893 if (dge_read_eeprom(sc)) { 894 aprint_error_dev(sc->sc_dev, "couldn't read EEPROM\n"); 895 return; 896 } 897 898 /* 899 * Get the ethernet address. 900 */ 901 enaddr[0] = sc->sc_eeprom[EE_ADDR01] & 0377; 902 enaddr[1] = sc->sc_eeprom[EE_ADDR01] >> 8; 903 enaddr[2] = sc->sc_eeprom[EE_ADDR23] & 0377; 904 enaddr[3] = sc->sc_eeprom[EE_ADDR23] >> 8; 905 enaddr[4] = sc->sc_eeprom[EE_ADDR45] & 0377; 906 enaddr[5] = sc->sc_eeprom[EE_ADDR45] >> 8; 907 908 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 909 ether_sprintf(enaddr)); 910 911 /* 912 * Setup media stuff. 913 */ 914 sc->sc_ethercom.ec_ifmedia = &sc->sc_media; 915 ifmedia_init(&sc->sc_media, IFM_IMASK, dge_xgmii_mediachange, 916 dge_xgmii_mediastatus); 917 if (dgep->dgep_flags & DGEP_F_10G_SR) { 918 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_SR, 0, NULL); 919 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10G_SR); 920 } else { /* XXX default is LR */ 921 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_LR, 0, NULL); 922 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10G_LR); 923 } 924 925 ifp = &sc->sc_ethercom.ec_if; 926 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 927 ifp->if_softc = sc; 928 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 929 ifp->if_ioctl = dge_ioctl; 930 ifp->if_start = dge_start; 931 ifp->if_watchdog = dge_watchdog; 932 ifp->if_init = dge_init; 933 ifp->if_stop = dge_stop; 934 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(DGE_IFQUEUELEN, IFQ_MAXLEN)); 935 IFQ_SET_READY(&ifp->if_snd); 936 937 sc->sc_ethercom.ec_capabilities |= 938 ETHERCAP_JUMBO_MTU | ETHERCAP_VLAN_MTU; 939 940 /* 941 * We can perform TCPv4 and UDPv4 checkums in-bound. 942 */ 943 ifp->if_capabilities |= 944 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 945 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 946 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 947 948 /* 949 * Attach the interface. 950 */ 951 if_attach(ifp); 952 if_deferred_start_init(ifp, NULL); 953 ether_ifattach(ifp, enaddr); 954 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 955 RND_TYPE_NET, RND_FLAG_DEFAULT); 956 957 #ifdef DGE_EVENT_COUNTERS 958 /* Fix segment event naming */ 959 if (dge_txseg_evcnt_names == NULL) { 960 dge_txseg_evcnt_names = 961 malloc(sizeof(*dge_txseg_evcnt_names), M_DEVBUF, M_WAITOK); 962 for (i = 0; i < DGE_NTXSEGS; i++) 963 snprintf((*dge_txseg_evcnt_names)[i], 964 sizeof((*dge_txseg_evcnt_names)[i]), "txseg%d", i); 965 } 966 967 /* Attach event counters. */ 968 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 969 NULL, device_xname(sc->sc_dev), "txsstall"); 970 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 971 NULL, device_xname(sc->sc_dev), "txdstall"); 972 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC, 973 NULL, device_xname(sc->sc_dev), "txforceintr"); 974 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 975 NULL, device_xname(sc->sc_dev), "txdw"); 976 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 977 NULL, device_xname(sc->sc_dev), "txqe"); 978 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 979 NULL, device_xname(sc->sc_dev), "rxintr"); 980 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 981 NULL, device_xname(sc->sc_dev), "linkintr"); 982 983 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 984 NULL, device_xname(sc->sc_dev), "rxipsum"); 985 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 986 NULL, device_xname(sc->sc_dev), "rxtusum"); 987 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 988 NULL, device_xname(sc->sc_dev), "txipsum"); 989 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 990 NULL, device_xname(sc->sc_dev), "txtusum"); 991 992 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 993 NULL, device_xname(sc->sc_dev), "txctx init"); 994 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 995 NULL, device_xname(sc->sc_dev), "txctx hit"); 996 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 997 NULL, device_xname(sc->sc_dev), "txctx miss"); 998 999 for (i = 0; i < DGE_NTXSEGS; i++) 1000 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1001 NULL, device_xname(sc->sc_dev), (*dge_txseg_evcnt_names)[i]); 1002 1003 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1004 NULL, device_xname(sc->sc_dev), "txdrop"); 1005 1006 #endif /* DGE_EVENT_COUNTERS */ 1007 1008 /* 1009 * Make sure the interface is shutdown during reboot. 1010 */ 1011 if (pmf_device_register1(self, NULL, NULL, dge_shutdown)) 1012 pmf_class_network_register(self, ifp); 1013 else 1014 aprint_error_dev(self, "couldn't establish power handler\n"); 1015 1016 return; 1017 1018 /* 1019 * Free any resources we've allocated during the failed attach 1020 * attempt. Do this in reverse order and fall through. 1021 */ 1022 fail_5: 1023 for (i = 0; i < DGE_NRXDESC; i++) { 1024 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1025 bus_dmamap_destroy(sc->sc_dmat, 1026 sc->sc_rxsoft[i].rxs_dmamap); 1027 } 1028 fail_4: 1029 for (i = 0; i < DGE_TXQUEUELEN; i++) { 1030 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1031 bus_dmamap_destroy(sc->sc_dmat, 1032 sc->sc_txsoft[i].txs_dmamap); 1033 } 1034 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1035 fail_3: 1036 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1037 fail_2: 1038 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1039 sizeof(struct dge_control_data)); 1040 fail_1: 1041 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1042 fail_0: 1043 return; 1044 } 1045 1046 /* 1047 * dge_shutdown: 1048 * 1049 * Make sure the interface is stopped at reboot time. 1050 */ 1051 static bool 1052 dge_shutdown(device_t self, int howto) 1053 { 1054 struct dge_softc *sc; 1055 1056 sc = device_private(self); 1057 dge_stop(&sc->sc_ethercom.ec_if, 1); 1058 1059 return true; 1060 } 1061 1062 /* 1063 * dge_tx_cksum: 1064 * 1065 * Set up TCP/IP checksumming parameters for the 1066 * specified packet. 1067 */ 1068 static int 1069 dge_tx_cksum(struct dge_softc *sc, struct dge_txsoft *txs, uint8_t *fieldsp) 1070 { 1071 struct mbuf *m0 = txs->txs_mbuf; 1072 struct dge_ctdes *t; 1073 uint32_t ipcs, tucs; 1074 struct ether_header *eh; 1075 int offset, iphl; 1076 uint8_t fields = 0; 1077 1078 /* 1079 * XXX It would be nice if the mbuf pkthdr had offset 1080 * fields for the protocol headers. 1081 */ 1082 1083 eh = mtod(m0, struct ether_header *); 1084 switch (htons(eh->ether_type)) { 1085 case ETHERTYPE_IP: 1086 offset = ETHER_HDR_LEN; 1087 break; 1088 1089 case ETHERTYPE_VLAN: 1090 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1091 break; 1092 1093 default: 1094 /* 1095 * Don't support this protocol or encapsulation. 1096 */ 1097 *fieldsp = 0; 1098 return 0; 1099 } 1100 1101 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1102 1103 /* 1104 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1105 * offload feature, if we load the context descriptor, we 1106 * MUST provide valid values for IPCSS and TUCSS fields. 1107 */ 1108 1109 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1110 DGE_EVCNT_INCR(&sc->sc_ev_txipsum); 1111 fields |= TDESC_POPTS_IXSM; 1112 ipcs = DGE_TCPIP_IPCSS(offset) | 1113 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1114 DGE_TCPIP_IPCSE(offset + iphl - 1); 1115 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1116 /* Use the cached value. */ 1117 ipcs = sc->sc_txctx_ipcs; 1118 } else { 1119 /* Just initialize it to the likely value anyway. */ 1120 ipcs = DGE_TCPIP_IPCSS(offset) | 1121 DGE_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1122 DGE_TCPIP_IPCSE(offset + iphl - 1); 1123 } 1124 DPRINTF(DGE_DEBUG_CKSUM, 1125 ("%s: CKSUM: offset %d ipcs 0x%x\n", 1126 device_xname(sc->sc_dev), offset, ipcs)); 1127 1128 offset += iphl; 1129 1130 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1131 DGE_EVCNT_INCR(&sc->sc_ev_txtusum); 1132 fields |= TDESC_POPTS_TXSM; 1133 tucs = DGE_TCPIP_TUCSS(offset) | 1134 DGE_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1135 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1136 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1137 /* Use the cached value. */ 1138 tucs = sc->sc_txctx_tucs; 1139 } else { 1140 /* Just initialize it to a valid TCP context. */ 1141 tucs = DGE_TCPIP_TUCSS(offset) | 1142 DGE_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1143 DGE_TCPIP_TUCSE(0) /* rest of packet */; 1144 } 1145 1146 DPRINTF(DGE_DEBUG_CKSUM, 1147 ("%s: CKSUM: offset %d tucs 0x%x\n", 1148 device_xname(sc->sc_dev), offset, tucs)); 1149 1150 if (sc->sc_txctx_ipcs == ipcs && 1151 sc->sc_txctx_tucs == tucs) { 1152 /* Cached context is fine. */ 1153 DGE_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1154 } else { 1155 /* Fill in the context descriptor. */ 1156 #ifdef DGE_EVENT_COUNTERS 1157 if (sc->sc_txctx_ipcs == 0xffffffff && 1158 sc->sc_txctx_tucs == 0xffffffff) 1159 DGE_EVCNT_INCR(&sc->sc_ev_txctx_init); 1160 else 1161 DGE_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1162 #endif 1163 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext]; 1164 t->dc_tcpip_ipcs = htole32(ipcs); 1165 t->dc_tcpip_tucs = htole32(tucs); 1166 t->dc_tcpip_cmdlen = htole32(TDESC_DTYP_CTD); 1167 t->dc_tcpip_seg = 0; 1168 DGE_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1169 1170 sc->sc_txctx_ipcs = ipcs; 1171 sc->sc_txctx_tucs = tucs; 1172 1173 sc->sc_txnext = DGE_NEXTTX(sc->sc_txnext); 1174 txs->txs_ndesc++; 1175 } 1176 1177 *fieldsp = fields; 1178 1179 return 0; 1180 } 1181 1182 /* 1183 * dge_start: [ifnet interface function] 1184 * 1185 * Start packet transmission on the interface. 1186 */ 1187 static void 1188 dge_start(struct ifnet *ifp) 1189 { 1190 struct dge_softc *sc = ifp->if_softc; 1191 struct mbuf *m0; 1192 struct dge_txsoft *txs; 1193 bus_dmamap_t dmamap; 1194 int error, nexttx, lasttx = -1, ofree, seg; 1195 uint32_t cksumcmd; 1196 uint8_t cksumfields; 1197 1198 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1199 return; 1200 1201 /* 1202 * Remember the previous number of free descriptors. 1203 */ 1204 ofree = sc->sc_txfree; 1205 1206 /* 1207 * Loop through the send queue, setting up transmit descriptors 1208 * until we drain the queue, or use up all available transmit 1209 * descriptors. 1210 */ 1211 for (;;) { 1212 /* Grab a packet off the queue. */ 1213 IFQ_POLL(&ifp->if_snd, m0); 1214 if (m0 == NULL) 1215 break; 1216 1217 DPRINTF(DGE_DEBUG_TX, 1218 ("%s: TX: have packet to transmit: %p\n", 1219 device_xname(sc->sc_dev), m0)); 1220 1221 /* Get a work queue entry. */ 1222 if (sc->sc_txsfree < DGE_TXQUEUE_GC) { 1223 dge_txintr(sc); 1224 if (sc->sc_txsfree == 0) { 1225 DPRINTF(DGE_DEBUG_TX, 1226 ("%s: TX: no free job descriptors\n", 1227 device_xname(sc->sc_dev))); 1228 DGE_EVCNT_INCR(&sc->sc_ev_txsstall); 1229 break; 1230 } 1231 } 1232 1233 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1234 dmamap = txs->txs_dmamap; 1235 1236 /* 1237 * Load the DMA map. If this fails, the packet either 1238 * didn't fit in the allotted number of segments, or we 1239 * were short on resources. For the too-many-segments 1240 * case, we simply report an error and drop the packet, 1241 * since we can't sanely copy a jumbo packet to a single 1242 * buffer. 1243 */ 1244 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1245 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1246 if (error) { 1247 if (error == EFBIG) { 1248 DGE_EVCNT_INCR(&sc->sc_ev_txdrop); 1249 printf("%s: Tx packet consumes too many " 1250 "DMA segments, dropping...\n", 1251 device_xname(sc->sc_dev)); 1252 IFQ_DEQUEUE(&ifp->if_snd, m0); 1253 m_freem(m0); 1254 continue; 1255 } 1256 /* 1257 * Short on resources, just stop for now. 1258 */ 1259 DPRINTF(DGE_DEBUG_TX, 1260 ("%s: TX: dmamap load failed: %d\n", 1261 device_xname(sc->sc_dev), error)); 1262 break; 1263 } 1264 1265 /* 1266 * Ensure we have enough descriptors free to describe 1267 * the packet. Note, we always reserve one descriptor 1268 * at the end of the ring due to the semantics of the 1269 * TDT register, plus one more in the event we need 1270 * to re-load checksum offload context. 1271 */ 1272 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1273 /* 1274 * Not enough free descriptors to transmit this 1275 * packet. We haven't committed anything yet, 1276 * so just unload the DMA map, put the packet 1277 * pack on the queue, and punt. Notify the upper 1278 * layer that there are no more slots left. 1279 */ 1280 DPRINTF(DGE_DEBUG_TX, 1281 ("%s: TX: need %d descriptors, have %d\n", 1282 device_xname(sc->sc_dev), dmamap->dm_nsegs, 1283 sc->sc_txfree - 1)); 1284 ifp->if_flags |= IFF_OACTIVE; 1285 bus_dmamap_unload(sc->sc_dmat, dmamap); 1286 DGE_EVCNT_INCR(&sc->sc_ev_txdstall); 1287 break; 1288 } 1289 1290 IFQ_DEQUEUE(&ifp->if_snd, m0); 1291 1292 /* 1293 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1294 */ 1295 1296 /* Sync the DMA map. */ 1297 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1298 BUS_DMASYNC_PREWRITE); 1299 1300 DPRINTF(DGE_DEBUG_TX, 1301 ("%s: TX: packet has %d DMA segments\n", 1302 device_xname(sc->sc_dev), dmamap->dm_nsegs)); 1303 1304 DGE_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1305 1306 /* 1307 * Store a pointer to the packet so that we can free it 1308 * later. 1309 * 1310 * Initially, we consider the number of descriptors the 1311 * packet uses the number of DMA segments. This may be 1312 * incremented by 1 if we do checksum offload (a descriptor 1313 * is used to set the checksum context). 1314 */ 1315 txs->txs_mbuf = m0; 1316 txs->txs_firstdesc = sc->sc_txnext; 1317 txs->txs_ndesc = dmamap->dm_nsegs; 1318 1319 /* 1320 * Set up checksum offload parameters for 1321 * this packet. 1322 */ 1323 if (m0->m_pkthdr.csum_flags & 1324 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1325 if (dge_tx_cksum(sc, txs, &cksumfields) != 0) { 1326 /* Error message already displayed. */ 1327 bus_dmamap_unload(sc->sc_dmat, dmamap); 1328 continue; 1329 } 1330 } else { 1331 cksumfields = 0; 1332 } 1333 1334 cksumcmd = TDESC_DCMD_IDE | TDESC_DTYP_DATA; 1335 1336 /* 1337 * Initialize the transmit descriptor. 1338 */ 1339 for (nexttx = sc->sc_txnext, seg = 0; 1340 seg < dmamap->dm_nsegs; 1341 seg++, nexttx = DGE_NEXTTX(nexttx)) { 1342 sc->sc_txdescs[nexttx].dt_baddrh = 1343 htole32(((uint64_t)dmamap->dm_segs[seg].ds_addr) >> 32); 1344 sc->sc_txdescs[nexttx].dt_baddrl = 1345 htole32(dmamap->dm_segs[seg].ds_addr); 1346 sc->sc_txdescs[nexttx].dt_ctl = 1347 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1348 sc->sc_txdescs[nexttx].dt_status = 0; 1349 sc->sc_txdescs[nexttx].dt_popts = cksumfields; 1350 sc->sc_txdescs[nexttx].dt_vlan = 0; 1351 lasttx = nexttx; 1352 1353 DPRINTF(DGE_DEBUG_TX, 1354 ("%s: TX: desc %d: high 0x%08lx, low 0x%08lx, len 0x%04lx\n", 1355 device_xname(sc->sc_dev), nexttx, 1356 (unsigned long)(((uint64_t)dmamap->dm_segs[seg].ds_addr) >> 32), 1357 (unsigned long)((uint32_t)dmamap->dm_segs[seg].ds_addr), 1358 (unsigned long)dmamap->dm_segs[seg].ds_len)); 1359 } 1360 1361 KASSERT(lasttx != -1); 1362 1363 /* 1364 * Set up the command byte on the last descriptor of 1365 * the packet. If we're in the interrupt delay window, 1366 * delay the interrupt. 1367 */ 1368 sc->sc_txdescs[lasttx].dt_ctl |= 1369 htole32(TDESC_DCMD_EOP | TDESC_DCMD_RS); 1370 1371 txs->txs_lastdesc = lasttx; 1372 1373 DPRINTF(DGE_DEBUG_TX, 1374 ("%s: TX: desc %d: cmdlen 0x%08x\n", device_xname(sc->sc_dev), 1375 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl))); 1376 1377 /* Sync the descriptors we're using. */ 1378 DGE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1379 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1380 1381 /* Give the packet to the chip. */ 1382 CSR_WRITE(sc, DGE_TDT, nexttx); 1383 1384 DPRINTF(DGE_DEBUG_TX, 1385 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 1386 1387 DPRINTF(DGE_DEBUG_TX, 1388 ("%s: TX: finished transmitting packet, job %d\n", 1389 device_xname(sc->sc_dev), sc->sc_txsnext)); 1390 1391 /* Advance the tx pointer. */ 1392 sc->sc_txfree -= txs->txs_ndesc; 1393 sc->sc_txnext = nexttx; 1394 1395 sc->sc_txsfree--; 1396 sc->sc_txsnext = DGE_NEXTTXS(sc->sc_txsnext); 1397 1398 /* Pass the packet to any BPF listeners. */ 1399 bpf_mtap(ifp, m0, BPF_D_OUT); 1400 } 1401 1402 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1403 /* No more slots; notify upper layer. */ 1404 ifp->if_flags |= IFF_OACTIVE; 1405 } 1406 1407 if (sc->sc_txfree != ofree) { 1408 /* Set a watchdog timer in case the chip flakes out. */ 1409 ifp->if_timer = 5; 1410 } 1411 } 1412 1413 /* 1414 * dge_watchdog: [ifnet interface function] 1415 * 1416 * Watchdog timer handler. 1417 */ 1418 static void 1419 dge_watchdog(struct ifnet *ifp) 1420 { 1421 struct dge_softc *sc = ifp->if_softc; 1422 1423 /* 1424 * Since we're using delayed interrupts, sweep up 1425 * before we report an error. 1426 */ 1427 dge_txintr(sc); 1428 1429 if (sc->sc_txfree != DGE_NTXDESC) { 1430 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1431 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree, 1432 sc->sc_txnext); 1433 if_statinc(ifp, if_oerrors); 1434 1435 /* Reset the interface. */ 1436 (void) dge_init(ifp); 1437 } 1438 1439 /* Try to get more packets going. */ 1440 dge_start(ifp); 1441 } 1442 1443 /* 1444 * dge_ioctl: [ifnet interface function] 1445 * 1446 * Handle control requests from the operator. 1447 */ 1448 static int 1449 dge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1450 { 1451 struct dge_softc *sc = ifp->if_softc; 1452 struct ifreq *ifr = (struct ifreq *) data; 1453 pcireg_t preg; 1454 int s, error, mmrbc; 1455 1456 s = splnet(); 1457 1458 switch (cmd) { 1459 case SIOCSIFMTU: 1460 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > DGE_MAX_MTU) 1461 error = EINVAL; 1462 else if ((error = ifioctl_common(ifp, cmd, data)) != ENETRESET) 1463 break; 1464 else if (ifp->if_flags & IFF_UP) 1465 error = (*ifp->if_init)(ifp); 1466 else 1467 error = 0; 1468 break; 1469 1470 case SIOCSIFFLAGS: 1471 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1472 break; 1473 /* extract link flags */ 1474 if ((ifp->if_flags & IFF_LINK0) == 0 && 1475 (ifp->if_flags & IFF_LINK1) == 0) 1476 mmrbc = PCIX_MMRBC_512; 1477 else if ((ifp->if_flags & IFF_LINK0) == 0 && 1478 (ifp->if_flags & IFF_LINK1) != 0) 1479 mmrbc = PCIX_MMRBC_1024; 1480 else if ((ifp->if_flags & IFF_LINK0) != 0 && 1481 (ifp->if_flags & IFF_LINK1) == 0) 1482 mmrbc = PCIX_MMRBC_2048; 1483 else 1484 mmrbc = PCIX_MMRBC_4096; 1485 if (mmrbc != sc->sc_mmrbc) { 1486 preg = pci_conf_read(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD); 1487 preg &= ~PCIX_MMRBC_MSK; 1488 preg |= mmrbc; 1489 pci_conf_write(sc->sc_pc, sc->sc_pt,DGE_PCIX_CMD, preg); 1490 sc->sc_mmrbc = mmrbc; 1491 } 1492 /* FALLTHROUGH */ 1493 default: 1494 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1495 break; 1496 1497 error = 0; 1498 1499 if (cmd == SIOCSIFCAP) 1500 error = (*ifp->if_init)(ifp); 1501 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1502 ; 1503 else if (ifp->if_flags & IFF_RUNNING) { 1504 /* 1505 * Multicast list has changed; set the hardware filter 1506 * accordingly. 1507 */ 1508 dge_set_filter(sc); 1509 } 1510 break; 1511 } 1512 1513 /* Try to get more packets going. */ 1514 dge_start(ifp); 1515 1516 splx(s); 1517 return error; 1518 } 1519 1520 /* 1521 * dge_intr: 1522 * 1523 * Interrupt service routine. 1524 */ 1525 static int 1526 dge_intr(void *arg) 1527 { 1528 struct dge_softc *sc = arg; 1529 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1530 uint32_t icr; 1531 int wantinit, handled = 0; 1532 1533 for (wantinit = 0; wantinit == 0;) { 1534 icr = CSR_READ(sc, DGE_ICR); 1535 if ((icr & sc->sc_icr) == 0) 1536 break; 1537 1538 rnd_add_uint32(&sc->rnd_source, icr); 1539 1540 handled = 1; 1541 1542 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1543 if (icr & (ICR_RXDMT0 | ICR_RXT0)) { 1544 DPRINTF(DGE_DEBUG_RX, 1545 ("%s: RX: got Rx intr 0x%08x\n", 1546 device_xname(sc->sc_dev), 1547 icr & (ICR_RXDMT0 | ICR_RXT0))); 1548 DGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1549 } 1550 #endif 1551 dge_rxintr(sc); 1552 1553 #if defined(DGE_DEBUG) || defined(DGE_EVENT_COUNTERS) 1554 if (icr & ICR_TXDW) { 1555 DPRINTF(DGE_DEBUG_TX, 1556 ("%s: TX: got TXDW interrupt\n", 1557 device_xname(sc->sc_dev))); 1558 DGE_EVCNT_INCR(&sc->sc_ev_txdw); 1559 } 1560 if (icr & ICR_TXQE) 1561 DGE_EVCNT_INCR(&sc->sc_ev_txqe); 1562 #endif 1563 dge_txintr(sc); 1564 1565 if (icr & (ICR_LSC | ICR_RXSEQ)) { 1566 DGE_EVCNT_INCR(&sc->sc_ev_linkintr); 1567 dge_linkintr(sc, icr); 1568 } 1569 1570 if (icr & ICR_RXO) { 1571 printf("%s: Receive overrun\n", 1572 device_xname(sc->sc_dev)); 1573 wantinit = 1; 1574 } 1575 } 1576 1577 if (handled) { 1578 if (wantinit) 1579 dge_init(ifp); 1580 1581 /* Try to get more packets going. */ 1582 if_schedule_deferred_start(ifp); 1583 } 1584 1585 return handled; 1586 } 1587 1588 /* 1589 * dge_txintr: 1590 * 1591 * Helper; handle transmit interrupts. 1592 */ 1593 static void 1594 dge_txintr(struct dge_softc *sc) 1595 { 1596 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1597 struct dge_txsoft *txs; 1598 uint8_t status; 1599 int i; 1600 1601 ifp->if_flags &= ~IFF_OACTIVE; 1602 1603 /* 1604 * Go through the Tx list and free mbufs for those 1605 * frames which have been transmitted. 1606 */ 1607 for (i = sc->sc_txsdirty; sc->sc_txsfree != DGE_TXQUEUELEN; 1608 i = DGE_NEXTTXS(i), sc->sc_txsfree++) { 1609 txs = &sc->sc_txsoft[i]; 1610 1611 DPRINTF(DGE_DEBUG_TX, 1612 ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i)); 1613 1614 DGE_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1616 1617 status = 1618 sc->sc_txdescs[txs->txs_lastdesc].dt_status; 1619 if ((status & TDESC_STA_DD) == 0) { 1620 DGE_CDTXSYNC(sc, txs->txs_lastdesc, 1, 1621 BUS_DMASYNC_PREREAD); 1622 break; 1623 } 1624 1625 DPRINTF(DGE_DEBUG_TX, 1626 ("%s: TX: job %d done: descs %d..%d\n", 1627 device_xname(sc->sc_dev), i, txs->txs_firstdesc, 1628 txs->txs_lastdesc)); 1629 1630 if_statinc(ifp, if_opackets); 1631 sc->sc_txfree += txs->txs_ndesc; 1632 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1633 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1634 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1635 m_freem(txs->txs_mbuf); 1636 txs->txs_mbuf = NULL; 1637 } 1638 1639 /* Update the dirty transmit buffer pointer. */ 1640 sc->sc_txsdirty = i; 1641 DPRINTF(DGE_DEBUG_TX, 1642 ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i)); 1643 1644 /* 1645 * If there are no more pending transmissions, cancel the watchdog 1646 * timer. 1647 */ 1648 if (sc->sc_txsfree == DGE_TXQUEUELEN) 1649 ifp->if_timer = 0; 1650 } 1651 1652 /* 1653 * dge_rxintr: 1654 * 1655 * Helper; handle receive interrupts. 1656 */ 1657 static void 1658 dge_rxintr(struct dge_softc *sc) 1659 { 1660 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1661 struct dge_rxsoft *rxs; 1662 struct mbuf *m; 1663 int i, len; 1664 uint8_t status, errors; 1665 1666 for (i = sc->sc_rxptr;; i = DGE_NEXTRX(i)) { 1667 rxs = &sc->sc_rxsoft[i]; 1668 1669 DPRINTF(DGE_DEBUG_RX, 1670 ("%s: RX: checking descriptor %d\n", 1671 device_xname(sc->sc_dev), i)); 1672 1673 DGE_CDRXSYNC(sc, i, 1674 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1675 1676 status = sc->sc_rxdescs[i].dr_status; 1677 errors = sc->sc_rxdescs[i].dr_errors; 1678 len = le16toh(sc->sc_rxdescs[i].dr_len); 1679 1680 if ((status & RDESC_STS_DD) == 0) { 1681 /* We have processed all of the receive descriptors. */ 1682 DGE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1683 break; 1684 } 1685 1686 if (__predict_false(sc->sc_rxdiscard)) { 1687 DPRINTF(DGE_DEBUG_RX, 1688 ("%s: RX: discarding contents of descriptor %d\n", 1689 device_xname(sc->sc_dev), i)); 1690 DGE_INIT_RXDESC(sc, i); 1691 if (status & RDESC_STS_EOP) { 1692 /* Reset our state. */ 1693 DPRINTF(DGE_DEBUG_RX, 1694 ("%s: RX: resetting rxdiscard -> 0\n", 1695 device_xname(sc->sc_dev))); 1696 sc->sc_rxdiscard = 0; 1697 } 1698 continue; 1699 } 1700 1701 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1702 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1703 1704 m = rxs->rxs_mbuf; 1705 1706 /* 1707 * Add a new receive buffer to the ring. 1708 */ 1709 if (dge_add_rxbuf(sc, i) != 0) { 1710 /* 1711 * Failed, throw away what we've done so 1712 * far, and discard the rest of the packet. 1713 */ 1714 if_statinc(ifp, if_ierrors); 1715 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1716 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1717 DGE_INIT_RXDESC(sc, i); 1718 if ((status & RDESC_STS_EOP) == 0) 1719 sc->sc_rxdiscard = 1; 1720 if (sc->sc_rxhead != NULL) 1721 m_freem(sc->sc_rxhead); 1722 DGE_RXCHAIN_RESET(sc); 1723 DPRINTF(DGE_DEBUG_RX, 1724 ("%s: RX: Rx buffer allocation failed, " 1725 "dropping packet%s\n", device_xname(sc->sc_dev), 1726 sc->sc_rxdiscard ? " (discard)" : "")); 1727 continue; 1728 } 1729 DGE_INIT_RXDESC(sc, DGE_PREVRX(i)); /* Write the descriptor */ 1730 1731 DGE_RXCHAIN_LINK(sc, m); 1732 1733 m->m_len = len; 1734 1735 DPRINTF(DGE_DEBUG_RX, 1736 ("%s: RX: buffer at %p len %d\n", 1737 device_xname(sc->sc_dev), m->m_data, len)); 1738 1739 /* 1740 * If this is not the end of the packet, keep 1741 * looking. 1742 */ 1743 if ((status & RDESC_STS_EOP) == 0) { 1744 sc->sc_rxlen += len; 1745 DPRINTF(DGE_DEBUG_RX, 1746 ("%s: RX: not yet EOP, rxlen -> %d\n", 1747 device_xname(sc->sc_dev), sc->sc_rxlen)); 1748 continue; 1749 } 1750 1751 /* 1752 * Okay, we have the entire packet now... 1753 */ 1754 *sc->sc_rxtailp = NULL; 1755 m = sc->sc_rxhead; 1756 len += sc->sc_rxlen; 1757 1758 DGE_RXCHAIN_RESET(sc); 1759 1760 DPRINTF(DGE_DEBUG_RX, 1761 ("%s: RX: have entire packet, len -> %d\n", 1762 device_xname(sc->sc_dev), len)); 1763 1764 /* 1765 * If an error occurred, update stats and drop the packet. 1766 */ 1767 if (errors & (RDESC_ERR_CE | RDESC_ERR_SE | RDESC_ERR_P | 1768 RDESC_ERR_RXE)) { 1769 if_statinc(ifp, if_ierrors); 1770 if (errors & RDESC_ERR_SE) 1771 printf("%s: symbol error\n", 1772 device_xname(sc->sc_dev)); 1773 else if (errors & RDESC_ERR_P) 1774 printf("%s: parity error\n", 1775 device_xname(sc->sc_dev)); 1776 else if (errors & RDESC_ERR_CE) 1777 printf("%s: CRC error\n", 1778 device_xname(sc->sc_dev)); 1779 m_freem(m); 1780 continue; 1781 } 1782 1783 /* 1784 * No errors. Receive the packet. 1785 */ 1786 m_set_rcvif(m, ifp); 1787 m->m_pkthdr.len = len; 1788 1789 /* 1790 * Set up checksum info for this packet. 1791 */ 1792 if (status & RDESC_STS_IPCS) { 1793 DGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1794 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1795 if (errors & RDESC_ERR_IPE) 1796 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1797 } 1798 if (status & RDESC_STS_TCPCS) { 1799 /* 1800 * Note: we don't know if this was TCP or UDP, 1801 * so we just set both bits, and expect the 1802 * upper layers to deal. 1803 */ 1804 DGE_EVCNT_INCR(&sc->sc_ev_rxtusum); 1805 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4 | M_CSUM_UDPv4; 1806 if (errors & RDESC_ERR_TCPE) 1807 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1808 } 1809 1810 /* Pass it on. */ 1811 if_percpuq_enqueue(ifp->if_percpuq, m); 1812 } 1813 1814 /* Update the receive pointer. */ 1815 sc->sc_rxptr = i; 1816 1817 DPRINTF(DGE_DEBUG_RX, 1818 ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i)); 1819 } 1820 1821 /* 1822 * dge_linkintr: 1823 * 1824 * Helper; handle link interrupts. 1825 */ 1826 static void 1827 dge_linkintr(struct dge_softc *sc, uint32_t icr) 1828 { 1829 uint32_t status; 1830 1831 if (icr & ICR_LSC) { 1832 status = CSR_READ(sc, DGE_STATUS); 1833 if (status & STATUS_LINKUP) { 1834 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> up\n", 1835 device_xname(sc->sc_dev))); 1836 } else { 1837 DPRINTF(DGE_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 1838 device_xname(sc->sc_dev))); 1839 } 1840 } else if (icr & ICR_RXSEQ) { 1841 DPRINTF(DGE_DEBUG_LINK, 1842 ("%s: LINK: Receive sequence error\n", 1843 device_xname(sc->sc_dev))); 1844 } 1845 /* XXX - fix errata */ 1846 } 1847 1848 /* 1849 * dge_reset: 1850 * 1851 * Reset the i82597 chip. 1852 */ 1853 static void 1854 dge_reset(struct dge_softc *sc) 1855 { 1856 int i; 1857 1858 /* 1859 * Do a chip reset. 1860 */ 1861 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0); 1862 1863 delay(10000); 1864 1865 for (i = 0; i < 1000; i++) { 1866 if ((CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) == 0) 1867 break; 1868 delay(20); 1869 } 1870 1871 if (CSR_READ(sc, DGE_CTRL0) & CTRL0_RST) 1872 printf("%s: WARNING: reset failed to complete\n", 1873 device_xname(sc->sc_dev)); 1874 /* 1875 * Reset the EEPROM logic. 1876 * This will cause the chip to reread its default values, 1877 * which doesn't happen otherwise (errata). 1878 */ 1879 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST); 1880 delay(10000); 1881 } 1882 1883 /* 1884 * dge_init: [ifnet interface function] 1885 * 1886 * Initialize the interface. Must be called at splnet(). 1887 */ 1888 static int 1889 dge_init(struct ifnet *ifp) 1890 { 1891 struct dge_softc *sc = ifp->if_softc; 1892 struct dge_rxsoft *rxs; 1893 int i, error = 0; 1894 uint32_t reg; 1895 1896 /* 1897 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 1898 * There is a small but measurable benefit to avoiding the adjusment 1899 * of the descriptor so that the headers are aligned, for normal mtu, 1900 * on such platforms. One possibility is that the DMA itself is 1901 * slightly more efficient if the front of the entire packet (instead 1902 * of the front of the headers) is aligned. 1903 * 1904 * Note we must always set align_tweak to 0 if we are using 1905 * jumbo frames. 1906 */ 1907 #ifdef __NO_STRICT_ALIGNMENT 1908 sc->sc_align_tweak = 0; 1909 #else 1910 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 1911 sc->sc_align_tweak = 0; 1912 else 1913 sc->sc_align_tweak = 2; 1914 #endif /* __NO_STRICT_ALIGNMENT */ 1915 1916 /* Cancel any pending I/O. */ 1917 dge_stop(ifp, 0); 1918 1919 /* Reset the chip to a known state. */ 1920 dge_reset(sc); 1921 1922 /* Initialize the transmit descriptor ring. */ 1923 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1924 DGE_CDTXSYNC(sc, 0, DGE_NTXDESC, 1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1926 sc->sc_txfree = DGE_NTXDESC; 1927 sc->sc_txnext = 0; 1928 1929 sc->sc_txctx_ipcs = 0xffffffff; 1930 sc->sc_txctx_tucs = 0xffffffff; 1931 1932 CSR_WRITE(sc, DGE_TDBAH, ((uint64_t)DGE_CDTXADDR(sc, 0)) >> 32); 1933 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0)); 1934 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs)); 1935 CSR_WRITE(sc, DGE_TDH, 0); 1936 CSR_WRITE(sc, DGE_TDT, 0); 1937 CSR_WRITE(sc, DGE_TIDV, TIDV); 1938 1939 #if 0 1940 CSR_WRITE(sc, DGE_TXDCTL, TXDCTL_PTHRESH(0) | 1941 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 1942 #endif 1943 CSR_WRITE(sc, DGE_RXDCTL, 1944 RXDCTL_PTHRESH(RXDCTL_PTHRESH_VAL) | 1945 RXDCTL_HTHRESH(RXDCTL_HTHRESH_VAL) | 1946 RXDCTL_WTHRESH(RXDCTL_WTHRESH_VAL)); 1947 1948 /* Initialize the transmit job descriptors. */ 1949 for (i = 0; i < DGE_TXQUEUELEN; i++) 1950 sc->sc_txsoft[i].txs_mbuf = NULL; 1951 sc->sc_txsfree = DGE_TXQUEUELEN; 1952 sc->sc_txsnext = 0; 1953 sc->sc_txsdirty = 0; 1954 1955 /* 1956 * Initialize the receive descriptor and receive job 1957 * descriptor rings. 1958 */ 1959 CSR_WRITE(sc, DGE_RDBAH, ((uint64_t)DGE_CDRXADDR(sc, 0)) >> 32); 1960 CSR_WRITE(sc, DGE_RDBAL, DGE_CDRXADDR(sc, 0)); 1961 CSR_WRITE(sc, DGE_RDLEN, sizeof(sc->sc_rxdescs)); 1962 CSR_WRITE(sc, DGE_RDH, DGE_RXSPACE); 1963 CSR_WRITE(sc, DGE_RDT, 0); 1964 CSR_WRITE(sc, DGE_RDTR, RDTR | 0x80000000); 1965 CSR_WRITE(sc, DGE_FCRTL, FCRTL | FCRTL_XONE); 1966 CSR_WRITE(sc, DGE_FCRTH, FCRTH); 1967 1968 for (i = 0; i < DGE_NRXDESC; i++) { 1969 rxs = &sc->sc_rxsoft[i]; 1970 if (rxs->rxs_mbuf == NULL) { 1971 if ((error = dge_add_rxbuf(sc, i)) != 0) { 1972 printf("%s: unable to allocate or map rx " 1973 "buffer %d, error = %d\n", 1974 device_xname(sc->sc_dev), i, error); 1975 /* 1976 * XXX Should attempt to run with fewer receive 1977 * XXX buffers instead of just failing. 1978 */ 1979 dge_rxdrain(sc); 1980 goto out; 1981 } 1982 } 1983 DGE_INIT_RXDESC(sc, i); 1984 } 1985 sc->sc_rxptr = DGE_RXSPACE; 1986 sc->sc_rxdiscard = 0; 1987 DGE_RXCHAIN_RESET(sc); 1988 1989 if (sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) { 1990 sc->sc_ctrl0 |= CTRL0_JFE; 1991 CSR_WRITE(sc, DGE_MFS, ETHER_MAX_LEN_JUMBO << 16); 1992 } 1993 1994 /* Write the control registers. */ 1995 CSR_WRITE(sc, DGE_CTRL0, sc->sc_ctrl0); 1996 1997 /* 1998 * Set up checksum offload parameters. 1999 */ 2000 reg = CSR_READ(sc, DGE_RXCSUM); 2001 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2002 reg |= RXCSUM_IPOFL; 2003 else 2004 reg &= ~RXCSUM_IPOFL; 2005 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2006 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2007 else { 2008 reg &= ~RXCSUM_TUOFL; 2009 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2010 reg &= ~RXCSUM_IPOFL; 2011 } 2012 CSR_WRITE(sc, DGE_RXCSUM, reg); 2013 2014 /* 2015 * Set up the interrupt registers. 2016 */ 2017 CSR_WRITE(sc, DGE_IMC, 0xffffffffU); 2018 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2019 ICR_RXO | ICR_RXT0; 2020 2021 CSR_WRITE(sc, DGE_IMS, sc->sc_icr); 2022 2023 /* 2024 * Set up the transmit control register. 2025 */ 2026 sc->sc_tctl = TCTL_TCE | TCTL_TPDE | TCTL_TXEN; 2027 CSR_WRITE(sc, DGE_TCTL, sc->sc_tctl); 2028 2029 /* 2030 * Set up the receive control register; we actually program 2031 * the register when we set the receive filter. Use multicast 2032 * address offset type 0. 2033 */ 2034 sc->sc_mchash_type = 0; 2035 2036 sc->sc_rctl = RCTL_RXEN | RCTL_RDMTS_12 | RCTL_RPDA_MC | 2037 RCTL_CFF | RCTL_SECRC | RCTL_MO(sc->sc_mchash_type); 2038 2039 #ifdef DGE_OFFBYONE_RXBUG 2040 sc->sc_rctl |= RCTL_BSIZE_16k; 2041 #else 2042 switch (MCLBYTES) { 2043 case 2048: 2044 sc->sc_rctl |= RCTL_BSIZE_2k; 2045 break; 2046 case 4096: 2047 sc->sc_rctl |= RCTL_BSIZE_4k; 2048 break; 2049 case 8192: 2050 sc->sc_rctl |= RCTL_BSIZE_8k; 2051 break; 2052 case 16384: 2053 sc->sc_rctl |= RCTL_BSIZE_16k; 2054 break; 2055 default: 2056 panic("dge_init: MCLBYTES %d unsupported", MCLBYTES); 2057 } 2058 #endif 2059 2060 /* Set the receive filter. */ 2061 /* Also sets RCTL */ 2062 dge_set_filter(sc); 2063 2064 /* ...all done! */ 2065 ifp->if_flags |= IFF_RUNNING; 2066 ifp->if_flags &= ~IFF_OACTIVE; 2067 2068 out: 2069 if (error) 2070 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2071 return error; 2072 } 2073 2074 /* 2075 * dge_rxdrain: 2076 * 2077 * Drain the receive queue. 2078 */ 2079 static void 2080 dge_rxdrain(struct dge_softc *sc) 2081 { 2082 struct dge_rxsoft *rxs; 2083 int i; 2084 2085 for (i = 0; i < DGE_NRXDESC; i++) { 2086 rxs = &sc->sc_rxsoft[i]; 2087 if (rxs->rxs_mbuf != NULL) { 2088 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2089 m_freem(rxs->rxs_mbuf); 2090 rxs->rxs_mbuf = NULL; 2091 } 2092 } 2093 } 2094 2095 /* 2096 * dge_stop: [ifnet interface function] 2097 * 2098 * Stop transmission on the interface. 2099 */ 2100 static void 2101 dge_stop(struct ifnet *ifp, int disable) 2102 { 2103 struct dge_softc *sc = ifp->if_softc; 2104 struct dge_txsoft *txs; 2105 int i; 2106 2107 /* Stop the transmit and receive processes. */ 2108 CSR_WRITE(sc, DGE_TCTL, 0); 2109 CSR_WRITE(sc, DGE_RCTL, 0); 2110 2111 /* Release any queued transmit buffers. */ 2112 for (i = 0; i < DGE_TXQUEUELEN; i++) { 2113 txs = &sc->sc_txsoft[i]; 2114 if (txs->txs_mbuf != NULL) { 2115 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2116 m_freem(txs->txs_mbuf); 2117 txs->txs_mbuf = NULL; 2118 } 2119 } 2120 2121 /* Mark the interface as down and cancel the watchdog timer. */ 2122 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2123 ifp->if_timer = 0; 2124 2125 if (disable) 2126 dge_rxdrain(sc); 2127 } 2128 2129 /* 2130 * dge_add_rxbuf: 2131 * 2132 * Add a receive buffer to the indiciated descriptor. 2133 */ 2134 static int 2135 dge_add_rxbuf(struct dge_softc *sc, int idx) 2136 { 2137 struct dge_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2138 struct mbuf *m; 2139 int error; 2140 #ifdef DGE_OFFBYONE_RXBUG 2141 void *buf; 2142 #endif 2143 2144 MGETHDR(m, M_DONTWAIT, MT_DATA); 2145 if (m == NULL) 2146 return ENOBUFS; 2147 2148 #ifdef DGE_OFFBYONE_RXBUG 2149 if ((buf = dge_getbuf(sc)) == NULL) 2150 return ENOBUFS; 2151 2152 m->m_len = m->m_pkthdr.len = DGE_BUFFER_SIZE; 2153 MEXTADD(m, buf, DGE_BUFFER_SIZE, M_DEVBUF, dge_freebuf, sc); 2154 m->m_flags |= M_EXT_RW; 2155 2156 if (rxs->rxs_mbuf != NULL) 2157 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2158 rxs->rxs_mbuf = m; 2159 2160 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, buf, 2161 DGE_BUFFER_SIZE, NULL, BUS_DMA_READ | BUS_DMA_NOWAIT); 2162 #else 2163 MCLGET(m, M_DONTWAIT); 2164 if ((m->m_flags & M_EXT) == 0) { 2165 m_freem(m); 2166 return ENOBUFS; 2167 } 2168 2169 if (rxs->rxs_mbuf != NULL) 2170 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2171 2172 rxs->rxs_mbuf = m; 2173 2174 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2175 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 2176 BUS_DMA_READ | BUS_DMA_NOWAIT); 2177 #endif 2178 if (error) { 2179 printf("%s: unable to load rx DMA map %d, error = %d\n", 2180 device_xname(sc->sc_dev), idx, error); 2181 panic("dge_add_rxbuf"); /* XXX XXX XXX */ 2182 } 2183 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2184 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2185 2186 return 0; 2187 } 2188 2189 /* 2190 * dge_set_ral: 2191 * 2192 * Set an entry in the receive address list. 2193 */ 2194 static void 2195 dge_set_ral(struct dge_softc *sc, const uint8_t *enaddr, int idx) 2196 { 2197 uint32_t ral_lo, ral_hi; 2198 2199 if (enaddr != NULL) { 2200 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 2201 (enaddr[3] << 24); 2202 ral_hi = enaddr[4] | (enaddr[5] << 8); 2203 ral_hi |= RAH_AV; 2204 } else { 2205 ral_lo = 0; 2206 ral_hi = 0; 2207 } 2208 CSR_WRITE(sc, RA_ADDR(DGE_RAL, idx), ral_lo); 2209 CSR_WRITE(sc, RA_ADDR(DGE_RAH, idx), ral_hi); 2210 } 2211 2212 /* 2213 * dge_mchash: 2214 * 2215 * Compute the hash of the multicast address for the 4096-bit 2216 * multicast filter. 2217 */ 2218 static uint32_t 2219 dge_mchash(struct dge_softc *sc, const uint8_t *enaddr) 2220 { 2221 static const int lo_shift[4] = { 4, 3, 2, 0 }; 2222 static const int hi_shift[4] = { 4, 5, 6, 8 }; 2223 uint32_t hash; 2224 2225 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 2226 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 2227 2228 return (hash & 0xfff); 2229 } 2230 2231 /* 2232 * dge_set_filter: 2233 * 2234 * Set up the receive filter. 2235 */ 2236 static void 2237 dge_set_filter(struct dge_softc *sc) 2238 { 2239 struct ethercom *ec = &sc->sc_ethercom; 2240 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2241 struct ether_multi *enm; 2242 struct ether_multistep step; 2243 uint32_t hash, reg, bit; 2244 int i; 2245 2246 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 2247 2248 if (ifp->if_flags & IFF_BROADCAST) 2249 sc->sc_rctl |= RCTL_BAM; 2250 if (ifp->if_flags & IFF_PROMISC) { 2251 sc->sc_rctl |= RCTL_UPE; 2252 goto allmulti; 2253 } 2254 2255 /* 2256 * Set the station address in the first RAL slot, and 2257 * clear the remaining slots. 2258 */ 2259 dge_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 2260 for (i = 1; i < RA_TABSIZE; i++) 2261 dge_set_ral(sc, NULL, i); 2262 2263 /* Clear out the multicast table. */ 2264 for (i = 0; i < MC_TABSIZE; i++) 2265 CSR_WRITE(sc, DGE_MTA + (i << 2), 0); 2266 2267 ETHER_LOCK(ec); 2268 ETHER_FIRST_MULTI(step, ec, enm); 2269 while (enm != NULL) { 2270 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2271 /* 2272 * We must listen to a range of multicast addresses. 2273 * For now, just accept all multicasts, rather than 2274 * trying to set only those filter bits needed to match 2275 * the range. (At this time, the only use of address 2276 * ranges is for IP multicast routing, for which the 2277 * range is big enough to require all bits set.) 2278 */ 2279 ETHER_UNLOCK(ec); 2280 goto allmulti; 2281 } 2282 2283 hash = dge_mchash(sc, enm->enm_addrlo); 2284 2285 reg = (hash >> 5) & 0x7f; 2286 bit = hash & 0x1f; 2287 2288 hash = CSR_READ(sc, DGE_MTA + (reg << 2)); 2289 hash |= 1U << bit; 2290 2291 CSR_WRITE(sc, DGE_MTA + (reg << 2), hash); 2292 2293 ETHER_NEXT_MULTI(step, enm); 2294 } 2295 ETHER_UNLOCK(ec); 2296 2297 ifp->if_flags &= ~IFF_ALLMULTI; 2298 goto setit; 2299 2300 allmulti: 2301 ifp->if_flags |= IFF_ALLMULTI; 2302 sc->sc_rctl |= RCTL_MPE; 2303 2304 setit: 2305 CSR_WRITE(sc, DGE_RCTL, sc->sc_rctl); 2306 } 2307 2308 /* 2309 * Read in the EEPROM info and verify checksum. 2310 */ 2311 int 2312 dge_read_eeprom(struct dge_softc *sc) 2313 { 2314 uint16_t cksum; 2315 int i; 2316 2317 cksum = 0; 2318 for (i = 0; i < EEPROM_SIZE; i++) { 2319 sc->sc_eeprom[i] = dge_eeprom_word(sc, i); 2320 cksum += sc->sc_eeprom[i]; 2321 } 2322 return cksum != EEPROM_CKSUM; 2323 } 2324 2325 2326 /* 2327 * Read a 16-bit word from address addr in the serial EEPROM. 2328 */ 2329 uint16_t 2330 dge_eeprom_word(struct dge_softc *sc, int addr) 2331 { 2332 uint32_t reg; 2333 uint16_t rval = 0; 2334 int i; 2335 2336 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK | EECD_DI | EECD_CS); 2337 2338 /* Lower clock pulse (and data in to chip) */ 2339 CSR_WRITE(sc, DGE_EECD, reg); 2340 /* Select chip */ 2341 CSR_WRITE(sc, DGE_EECD, reg | EECD_CS); 2342 2343 /* Send read command */ 2344 dge_eeprom_clockout(sc, 1); 2345 dge_eeprom_clockout(sc, 1); 2346 dge_eeprom_clockout(sc, 0); 2347 2348 /* Send address */ 2349 for (i = 5; i >= 0; i--) 2350 dge_eeprom_clockout(sc, (addr >> i) & 1); 2351 2352 /* Read data */ 2353 for (i = 0; i < 16; i++) { 2354 rval <<= 1; 2355 rval |= dge_eeprom_clockin(sc); 2356 } 2357 2358 /* Deselect chip */ 2359 CSR_WRITE(sc, DGE_EECD, reg); 2360 2361 return rval; 2362 } 2363 2364 /* 2365 * Clock out a single bit to the EEPROM. 2366 */ 2367 void 2368 dge_eeprom_clockout(struct dge_softc *sc, int bit) 2369 { 2370 int reg; 2371 2372 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_SK); 2373 if (bit) 2374 reg |= EECD_DI; 2375 2376 CSR_WRITE(sc, DGE_EECD, reg); 2377 delay(2); 2378 CSR_WRITE(sc, DGE_EECD, reg | EECD_SK); 2379 delay(2); 2380 CSR_WRITE(sc, DGE_EECD, reg); 2381 delay(2); 2382 } 2383 2384 /* 2385 * Clock in a single bit from EEPROM. 2386 */ 2387 int 2388 dge_eeprom_clockin(struct dge_softc *sc) 2389 { 2390 int reg, rv; 2391 2392 reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_DO | EECD_SK); 2393 2394 CSR_WRITE(sc, DGE_EECD, reg | EECD_SK); /* Raise clock */ 2395 delay(2); 2396 rv = (CSR_READ(sc, DGE_EECD) & EECD_DO) != 0; /* Get bit */ 2397 CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */ 2398 delay(2); 2399 2400 return rv; 2401 } 2402 2403 static void 2404 dge_xgmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2405 { 2406 struct dge_softc *sc = ifp->if_softc; 2407 2408 ifmr->ifm_status = IFM_AVALID; 2409 if (sc->sc_dgep->dgep_flags & DGEP_F_10G_SR ) { 2410 ifmr->ifm_active = IFM_ETHER | IFM_10G_SR; 2411 } else { 2412 ifmr->ifm_active = IFM_ETHER | IFM_10G_LR; 2413 } 2414 2415 if (CSR_READ(sc, DGE_STATUS) & STATUS_LINKUP) 2416 ifmr->ifm_status |= IFM_ACTIVE; 2417 } 2418 2419 static inline int 2420 phwait(struct dge_softc *sc, int p, int r, int d, int type) 2421 { 2422 int i, mdic; 2423 2424 CSR_WRITE(sc, DGE_MDIO, 2425 MDIO_PHY(p) | MDIO_REG(r) | MDIO_DEV(d) | type | MDIO_CMD); 2426 for (i = 0; i < 10; i++) { 2427 delay(10); 2428 if (((mdic = CSR_READ(sc, DGE_MDIO)) & MDIO_CMD) == 0) 2429 break; 2430 } 2431 return mdic; 2432 } 2433 2434 static void 2435 dge_xgmii_writereg(struct dge_softc *sc, int phy, int reg, int val) 2436 { 2437 int mdic; 2438 2439 CSR_WRITE(sc, DGE_MDIRW, val); 2440 if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) { 2441 printf("%s: address cycle timeout; phy %d reg %d\n", 2442 device_xname(sc->sc_dev), phy, reg); 2443 return; 2444 } 2445 if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) { 2446 printf("%s: write cycle timeout; phy %d reg %d\n", 2447 device_xname(sc->sc_dev), phy, reg); 2448 return; 2449 } 2450 } 2451 2452 static void 2453 dge_xgmii_reset(struct dge_softc *sc) 2454 { 2455 dge_xgmii_writereg(sc, 0, 0, BMCR_RESET); 2456 } 2457 2458 static int 2459 dge_xgmii_mediachange(struct ifnet *ifp) 2460 { 2461 return 0; 2462 } 2463