1 /* $NetBSD: if_cas.c,v 1.27 2018/06/26 06:48:01 msaitoh Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.27 2018/06/26 06:48:01 msaitoh Exp $"); 48 49 #ifndef _MODULE 50 #include "opt_inet.h" 51 #endif 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/module.h> 65 66 #include <machine/endian.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #include <net/bpf.h> 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 #include <sys/rndsource.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/mii_bitbang.h> 91 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcidevs.h> 95 #include <prop/proplib.h> 96 97 #include <dev/pci/if_casreg.h> 98 #include <dev/pci/if_casvar.h> 99 100 #define TRIES 10000 101 102 static bool cas_estintr(struct cas_softc *sc, int); 103 bool cas_shutdown(device_t, int); 104 static bool cas_suspend(device_t, const pmf_qual_t *); 105 static bool cas_resume(device_t, const pmf_qual_t *); 106 static int cas_detach(device_t, int); 107 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 108 109 int cas_match(device_t, cfdata_t, void *); 110 void cas_attach(device_t, device_t, void *); 111 112 113 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 114 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 115 DVF_DETACH_SHUTDOWN); 116 117 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 118 119 void cas_config(struct cas_softc *, const uint8_t *); 120 void cas_start(struct ifnet *); 121 void cas_stop(struct ifnet *, int); 122 int cas_ioctl(struct ifnet *, u_long, void *); 123 void cas_tick(void *); 124 void cas_watchdog(struct ifnet *); 125 int cas_init(struct ifnet *); 126 void cas_init_regs(struct cas_softc *); 127 int cas_ringsize(int); 128 int cas_cringsize(int); 129 int cas_meminit(struct cas_softc *); 130 void cas_mifinit(struct cas_softc *); 131 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 132 u_int32_t, u_int32_t); 133 void cas_reset(struct cas_softc *); 134 int cas_reset_rx(struct cas_softc *); 135 int cas_reset_tx(struct cas_softc *); 136 int cas_disable_rx(struct cas_softc *); 137 int cas_disable_tx(struct cas_softc *); 138 void cas_rxdrain(struct cas_softc *); 139 int cas_add_rxbuf(struct cas_softc *, int idx); 140 void cas_iff(struct cas_softc *); 141 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 142 143 /* MII methods & callbacks */ 144 int cas_mii_readreg(device_t, int, int); 145 void cas_mii_writereg(device_t, int, int, int); 146 void cas_mii_statchg(struct ifnet *); 147 int cas_pcs_readreg(device_t, int, int); 148 void cas_pcs_writereg(device_t, int, int, int); 149 150 int cas_mediachange(struct ifnet *); 151 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 152 153 int cas_eint(struct cas_softc *, u_int); 154 int cas_rint(struct cas_softc *); 155 int cas_tint(struct cas_softc *, u_int32_t); 156 int cas_pint(struct cas_softc *); 157 int cas_intr(void *); 158 159 #ifdef CAS_DEBUG 160 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 161 printf x 162 #else 163 #define DPRINTF(sc, x) /* nothing */ 164 #endif 165 166 int 167 cas_match(device_t parent, cfdata_t cf, void *aux) 168 { 169 struct pci_attach_args *pa = aux; 170 171 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 172 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 173 return 1; 174 175 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 176 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 177 return 1; 178 179 return 0; 180 } 181 182 #define PROMHDR_PTR_DATA 0x18 183 #define PROMDATA_PTR_VPD 0x08 184 #define PROMDATA_DATA2 0x0a 185 186 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 187 static const u_int8_t cas_promdat[] = { 188 'P', 'C', 'I', 'R', 189 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 190 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 191 }; 192 static const u_int8_t cas_promdat_ns[] = { 193 'P', 'C', 'I', 'R', 194 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 195 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 196 }; 197 198 static const u_int8_t cas_promdat2[] = { 199 0x18, 0x00, /* structure length */ 200 0x00, /* structure revision */ 201 0x00, /* interface revision */ 202 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 203 PCI_CLASS_NETWORK /* class code */ 204 }; 205 206 int 207 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 208 uint8_t *enaddr) 209 { 210 struct pci_vpd_largeres *res; 211 struct pci_vpd *vpd; 212 bus_space_handle_t romh; 213 bus_space_tag_t romt; 214 bus_size_t romsize = 0; 215 u_int8_t buf[32], *desc; 216 pcireg_t address; 217 int dataoff, vpdoff, len; 218 int rv = -1; 219 220 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 221 &romt, &romh, NULL, &romsize)) 222 return (-1); 223 224 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 225 address |= PCI_MAPREG_ROM_ENABLE; 226 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 227 228 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 229 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 230 goto fail; 231 232 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 233 if (dataoff < 0x1c) 234 goto fail; 235 236 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 237 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 238 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 239 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 240 goto fail; 241 242 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 243 if (vpdoff < 0x1c) 244 goto fail; 245 246 next: 247 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 248 if (!PCI_VPDRES_ISLARGE(buf[0])) 249 goto fail; 250 251 res = (struct pci_vpd_largeres *)buf; 252 vpdoff += sizeof(*res); 253 254 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 255 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 256 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 257 /* Skip identifier string. */ 258 vpdoff += len; 259 goto next; 260 261 case PCI_VPDRES_TYPE_VPD: 262 while (len > 0) { 263 bus_space_read_region_1(romt, romh, vpdoff, 264 buf, sizeof(buf)); 265 266 vpd = (struct pci_vpd *)buf; 267 vpdoff += sizeof(*vpd) + vpd->vpd_len; 268 len -= sizeof(*vpd) + vpd->vpd_len; 269 270 /* 271 * We're looking for an "Enhanced" VPD... 272 */ 273 if (vpd->vpd_key0 != 'Z') 274 continue; 275 276 desc = buf + sizeof(*vpd); 277 278 /* 279 * ...which is an instance property... 280 */ 281 if (desc[0] != 'I') 282 continue; 283 desc += 3; 284 285 /* 286 * ...that's a byte array with the proper 287 * length for a MAC address... 288 */ 289 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 290 continue; 291 desc += 2; 292 293 /* 294 * ...named "local-mac-address". 295 */ 296 if (strcmp(desc, "local-mac-address") != 0) 297 continue; 298 desc += strlen("local-mac-address") + 1; 299 300 memcpy(enaddr, desc, ETHER_ADDR_LEN); 301 rv = 0; 302 } 303 break; 304 305 default: 306 goto fail; 307 } 308 309 fail: 310 if (romsize != 0) 311 bus_space_unmap(romt, romh, romsize); 312 313 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 314 address &= ~PCI_MAPREG_ROM_ENABLE; 315 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 316 317 return (rv); 318 } 319 320 void 321 cas_attach(device_t parent, device_t self, void *aux) 322 { 323 struct pci_attach_args *pa = aux; 324 struct cas_softc *sc = device_private(self); 325 prop_data_t data; 326 uint8_t enaddr[ETHER_ADDR_LEN]; 327 328 sc->sc_dev = self; 329 pci_aprint_devinfo(pa, NULL); 330 sc->sc_rev = PCI_REVISION(pa->pa_class); 331 sc->sc_dmatag = pa->pa_dmat; 332 333 #define PCI_CAS_BASEADDR 0x10 334 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 335 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 336 aprint_error_dev(sc->sc_dev, 337 "unable to map device registers\n"); 338 return; 339 } 340 341 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 342 "mac-address")) != NULL) 343 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 344 else if (cas_pci_enaddr(sc, pa, enaddr) != 0) { 345 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 346 memset(enaddr, 0, sizeof(enaddr)); 347 } 348 349 sc->sc_burst = 16; /* XXX */ 350 351 sc->sc_att_stage = CAS_ATT_BACKEND_0; 352 353 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 354 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 355 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 356 return; 357 } 358 sc->sc_pc = pa->pa_pc; 359 if (!cas_estintr(sc, CAS_INTR_PCI)) { 360 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 361 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 362 return; 363 } 364 365 sc->sc_att_stage = CAS_ATT_BACKEND_1; 366 367 /* 368 * call the main configure 369 */ 370 cas_config(sc, enaddr); 371 372 if (pmf_device_register1(sc->sc_dev, 373 cas_suspend, cas_resume, cas_shutdown)) 374 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 375 else 376 aprint_error_dev(sc->sc_dev, 377 "could not establish power handlers\n"); 378 379 sc->sc_att_stage = CAS_ATT_FINISHED; 380 /*FALLTHROUGH*/ 381 } 382 383 /* 384 * cas_config: 385 * 386 * Attach a Cassini interface to the system. 387 */ 388 void 389 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 390 { 391 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 392 struct mii_data *mii = &sc->sc_mii; 393 struct mii_softc *child; 394 int i, error; 395 396 /* Make sure the chip is stopped. */ 397 ifp->if_softc = sc; 398 cas_reset(sc); 399 400 /* 401 * Allocate the control data structures, and create and load the 402 * DMA map for it. 403 */ 404 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 405 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 406 1, &sc->sc_cdnseg, 0)) != 0) { 407 aprint_error_dev(sc->sc_dev, 408 "unable to allocate control data, error = %d\n", 409 error); 410 cas_partial_detach(sc, CAS_ATT_0); 411 } 412 413 /* XXX should map this in with correct endianness */ 414 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 415 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 416 BUS_DMA_COHERENT)) != 0) { 417 aprint_error_dev(sc->sc_dev, 418 "unable to map control data, error = %d\n", error); 419 cas_partial_detach(sc, CAS_ATT_1); 420 } 421 422 if ((error = bus_dmamap_create(sc->sc_dmatag, 423 sizeof(struct cas_control_data), 1, 424 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 425 aprint_error_dev(sc->sc_dev, 426 "unable to create control data DMA map, error = %d\n", error); 427 cas_partial_detach(sc, CAS_ATT_2); 428 } 429 430 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 431 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 432 0)) != 0) { 433 aprint_error_dev(sc->sc_dev, 434 "unable to load control data DMA map, error = %d\n", 435 error); 436 cas_partial_detach(sc, CAS_ATT_3); 437 } 438 439 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 440 441 /* 442 * Create the receive buffer DMA maps. 443 */ 444 for (i = 0; i < CAS_NRXDESC; i++) { 445 bus_dma_segment_t seg; 446 char *kva; 447 int rseg; 448 449 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 450 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 451 aprint_error_dev(sc->sc_dev, 452 "unable to alloc rx DMA mem %d, error = %d\n", 453 i, error); 454 cas_partial_detach(sc, CAS_ATT_5); 455 } 456 sc->sc_rxsoft[i].rxs_dmaseg = seg; 457 458 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 459 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 460 aprint_error_dev(sc->sc_dev, 461 "unable to alloc rx DMA mem %d, error = %d\n", 462 i, error); 463 cas_partial_detach(sc, CAS_ATT_5); 464 } 465 sc->sc_rxsoft[i].rxs_kva = kva; 466 467 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 468 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 469 aprint_error_dev(sc->sc_dev, 470 "unable to create rx DMA map %d, error = %d\n", 471 i, error); 472 cas_partial_detach(sc, CAS_ATT_5); 473 } 474 475 if ((error = bus_dmamap_load(sc->sc_dmatag, 476 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 477 BUS_DMA_NOWAIT)) != 0) { 478 aprint_error_dev(sc->sc_dev, 479 "unable to load rx DMA map %d, error = %d\n", 480 i, error); 481 cas_partial_detach(sc, CAS_ATT_5); 482 } 483 } 484 485 /* 486 * Create the transmit buffer DMA maps. 487 */ 488 for (i = 0; i < CAS_NTXDESC; i++) { 489 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 490 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 491 &sc->sc_txd[i].sd_map)) != 0) { 492 aprint_error_dev(sc->sc_dev, 493 "unable to create tx DMA map %d, error = %d\n", 494 i, error); 495 cas_partial_detach(sc, CAS_ATT_6); 496 } 497 sc->sc_txd[i].sd_mbuf = NULL; 498 } 499 500 /* 501 * From this point forward, the attachment cannot fail. A failure 502 * before this point releases all resources that may have been 503 * allocated. 504 */ 505 506 /* Announce ourselves. */ 507 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 508 ether_sprintf(enaddr)); 509 aprint_naive(": Ethernet controller\n"); 510 511 /* Get RX FIFO size */ 512 sc->sc_rxfifosize = 16 * 1024; 513 514 /* Initialize ifnet structure. */ 515 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 516 ifp->if_softc = sc; 517 ifp->if_flags = 518 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 519 ifp->if_start = cas_start; 520 ifp->if_ioctl = cas_ioctl; 521 ifp->if_watchdog = cas_watchdog; 522 ifp->if_stop = cas_stop; 523 ifp->if_init = cas_init; 524 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 525 IFQ_SET_READY(&ifp->if_snd); 526 527 /* Initialize ifmedia structures and MII info */ 528 mii->mii_ifp = ifp; 529 mii->mii_readreg = cas_mii_readreg; 530 mii->mii_writereg = cas_mii_writereg; 531 mii->mii_statchg = cas_mii_statchg; 532 533 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 534 sc->sc_ethercom.ec_mii = mii; 535 536 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 537 538 cas_mifinit(sc); 539 540 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 541 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 542 bus_space_write_4(sc->sc_memt, sc->sc_memh, 543 CAS_MIF_CONFIG, sc->sc_mif_config); 544 } 545 546 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 547 MII_OFFSET_ANY, 0); 548 549 child = LIST_FIRST(&mii->mii_phys); 550 if (child == NULL && 551 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 552 /* 553 * Try the external PCS SERDES if we didn't find any 554 * MII devices. 555 */ 556 bus_space_write_4(sc->sc_memt, sc->sc_memh, 557 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 558 559 bus_space_write_4(sc->sc_memt, sc->sc_memh, 560 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 561 562 mii->mii_readreg = cas_pcs_readreg; 563 mii->mii_writereg = cas_pcs_writereg; 564 565 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 566 MII_OFFSET_ANY, MIIF_NOISOLATE); 567 } 568 569 child = LIST_FIRST(&mii->mii_phys); 570 if (child == NULL) { 571 /* No PHY attached */ 572 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 573 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 574 } else { 575 /* 576 * Walk along the list of attached MII devices and 577 * establish an `MII instance' to `phy number' 578 * mapping. We'll use this mapping in media change 579 * requests to determine which phy to use to program 580 * the MIF configuration register. 581 */ 582 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 583 /* 584 * Note: we support just two PHYs: the built-in 585 * internal device and an external on the MII 586 * connector. 587 */ 588 if (child->mii_phy > 1 || child->mii_inst > 1) { 589 aprint_error_dev(sc->sc_dev, 590 "cannot accommodate MII device %s" 591 " at phy %d, instance %d\n", 592 device_xname(child->mii_dev), 593 child->mii_phy, child->mii_inst); 594 continue; 595 } 596 597 sc->sc_phys[child->mii_inst] = child->mii_phy; 598 } 599 600 /* 601 * XXX - we can really do the following ONLY if the 602 * phy indeed has the auto negotiation capability!! 603 */ 604 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 605 } 606 607 /* claim 802.1q capability */ 608 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 609 610 /* Attach the interface. */ 611 if_attach(ifp); 612 if_deferred_start_init(ifp, NULL); 613 ether_ifattach(ifp, enaddr); 614 615 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 616 RND_TYPE_NET, RND_FLAG_DEFAULT); 617 618 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 619 NULL, device_xname(sc->sc_dev), "interrupts"); 620 621 callout_init(&sc->sc_tick_ch, 0); 622 623 return; 624 } 625 626 int 627 cas_detach(device_t self, int flags) 628 { 629 int i; 630 struct cas_softc *sc = device_private(self); 631 bus_space_tag_t t = sc->sc_memt; 632 bus_space_handle_t h = sc->sc_memh; 633 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 634 635 /* 636 * Free any resources we've allocated during the failed attach 637 * attempt. Do this in reverse order and fall through. 638 */ 639 switch (sc->sc_att_stage) { 640 case CAS_ATT_FINISHED: 641 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 642 pmf_device_deregister(self); 643 cas_stop(&sc->sc_ethercom.ec_if, 1); 644 evcnt_detach(&sc->sc_ev_intr); 645 646 rnd_detach_source(&sc->rnd_source); 647 648 ether_ifdetach(ifp); 649 if_detach(ifp); 650 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 651 652 callout_destroy(&sc->sc_tick_ch); 653 654 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 655 656 /*FALLTHROUGH*/ 657 case CAS_ATT_MII: 658 case CAS_ATT_7: 659 case CAS_ATT_6: 660 for (i = 0; i < CAS_NTXDESC; i++) { 661 if (sc->sc_txd[i].sd_map != NULL) 662 bus_dmamap_destroy(sc->sc_dmatag, 663 sc->sc_txd[i].sd_map); 664 } 665 /*FALLTHROUGH*/ 666 case CAS_ATT_5: 667 for (i = 0; i < CAS_NRXDESC; i++) { 668 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 669 bus_dmamap_unload(sc->sc_dmatag, 670 sc->sc_rxsoft[i].rxs_dmamap); 671 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 672 bus_dmamap_destroy(sc->sc_dmatag, 673 sc->sc_rxsoft[i].rxs_dmamap); 674 if (sc->sc_rxsoft[i].rxs_kva != NULL) 675 bus_dmamem_unmap(sc->sc_dmatag, 676 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 677 /* XXX need to check that bus_dmamem_alloc suceeded 678 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 679 */ 680 bus_dmamem_free(sc->sc_dmatag, 681 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 682 } 683 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 684 /*FALLTHROUGH*/ 685 case CAS_ATT_4: 686 case CAS_ATT_3: 687 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 688 /*FALLTHROUGH*/ 689 case CAS_ATT_2: 690 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 691 sizeof(struct cas_control_data)); 692 /*FALLTHROUGH*/ 693 case CAS_ATT_1: 694 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 695 /*FALLTHROUGH*/ 696 case CAS_ATT_0: 697 sc->sc_att_stage = CAS_ATT_0; 698 /*FALLTHROUGH*/ 699 case CAS_ATT_BACKEND_2: 700 case CAS_ATT_BACKEND_1: 701 if (sc->sc_ih != NULL) { 702 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 703 sc->sc_ih = NULL; 704 } 705 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 706 /*FALLTHROUGH*/ 707 case CAS_ATT_BACKEND_0: 708 break; 709 } 710 return 0; 711 } 712 713 static void 714 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 715 { 716 cfattach_t ca = device_cfattach(sc->sc_dev); 717 718 sc->sc_att_stage = stage; 719 (*ca->ca_detach)(sc->sc_dev, 0); 720 } 721 722 void 723 cas_tick(void *arg) 724 { 725 struct cas_softc *sc = arg; 726 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 727 bus_space_tag_t t = sc->sc_memt; 728 bus_space_handle_t mac = sc->sc_memh; 729 int s; 730 u_int32_t v; 731 732 /* unload collisions counters */ 733 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 734 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 735 ifp->if_collisions += v + 736 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 737 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 738 ifp->if_oerrors += v; 739 740 /* read error counters */ 741 ifp->if_ierrors += 742 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 743 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 744 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 745 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 746 747 /* clear the hardware counters */ 748 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 749 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 750 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 751 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 752 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 753 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 754 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 755 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 756 757 s = splnet(); 758 mii_tick(&sc->sc_mii); 759 splx(s); 760 761 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 762 } 763 764 int 765 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 766 u_int32_t clr, u_int32_t set) 767 { 768 int i; 769 u_int32_t reg; 770 771 for (i = TRIES; i--; DELAY(100)) { 772 reg = bus_space_read_4(sc->sc_memt, h, r); 773 if ((reg & clr) == 0 && (reg & set) == set) 774 return (1); 775 } 776 777 return (0); 778 } 779 780 void 781 cas_reset(struct cas_softc *sc) 782 { 783 bus_space_tag_t t = sc->sc_memt; 784 bus_space_handle_t h = sc->sc_memh; 785 int s; 786 787 s = splnet(); 788 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 789 cas_reset_rx(sc); 790 cas_reset_tx(sc); 791 792 /* Disable interrupts */ 793 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 794 795 /* Do a full reset */ 796 bus_space_write_4(t, h, CAS_RESET, 797 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 798 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 799 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 800 splx(s); 801 } 802 803 804 /* 805 * cas_rxdrain: 806 * 807 * Drain the receive queue. 808 */ 809 void 810 cas_rxdrain(struct cas_softc *sc) 811 { 812 /* Nothing to do yet. */ 813 } 814 815 /* 816 * Reset the whole thing. 817 */ 818 void 819 cas_stop(struct ifnet *ifp, int disable) 820 { 821 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 822 struct cas_sxd *sd; 823 u_int32_t i; 824 825 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 826 827 callout_stop(&sc->sc_tick_ch); 828 829 /* 830 * Mark the interface down and cancel the watchdog timer. 831 */ 832 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 833 ifp->if_timer = 0; 834 835 mii_down(&sc->sc_mii); 836 837 cas_reset_rx(sc); 838 cas_reset_tx(sc); 839 840 /* 841 * Release any queued transmit buffers. 842 */ 843 for (i = 0; i < CAS_NTXDESC; i++) { 844 sd = &sc->sc_txd[i]; 845 if (sd->sd_mbuf != NULL) { 846 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 847 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 848 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 849 m_freem(sd->sd_mbuf); 850 sd->sd_mbuf = NULL; 851 } 852 } 853 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 854 855 if (disable) 856 cas_rxdrain(sc); 857 } 858 859 860 /* 861 * Reset the receiver 862 */ 863 int 864 cas_reset_rx(struct cas_softc *sc) 865 { 866 bus_space_tag_t t = sc->sc_memt; 867 bus_space_handle_t h = sc->sc_memh; 868 869 /* 870 * Resetting while DMA is in progress can cause a bus hang, so we 871 * disable DMA first. 872 */ 873 cas_disable_rx(sc); 874 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 875 /* Wait till it finishes */ 876 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 877 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 878 /* Wait 5ms extra. */ 879 delay(5000); 880 881 /* Finally, reset the ERX */ 882 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 883 /* Wait till it finishes */ 884 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 885 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 886 return (1); 887 } 888 return (0); 889 } 890 891 892 /* 893 * Reset the transmitter 894 */ 895 int 896 cas_reset_tx(struct cas_softc *sc) 897 { 898 bus_space_tag_t t = sc->sc_memt; 899 bus_space_handle_t h = sc->sc_memh; 900 901 /* 902 * Resetting while DMA is in progress can cause a bus hang, so we 903 * disable DMA first. 904 */ 905 cas_disable_tx(sc); 906 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 907 /* Wait till it finishes */ 908 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 909 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 910 /* Wait 5ms extra. */ 911 delay(5000); 912 913 /* Finally, reset the ETX */ 914 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 915 /* Wait till it finishes */ 916 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 917 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 918 return (1); 919 } 920 return (0); 921 } 922 923 /* 924 * Disable receiver. 925 */ 926 int 927 cas_disable_rx(struct cas_softc *sc) 928 { 929 bus_space_tag_t t = sc->sc_memt; 930 bus_space_handle_t h = sc->sc_memh; 931 u_int32_t cfg; 932 933 /* Flip the enable bit */ 934 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 935 cfg &= ~CAS_MAC_RX_ENABLE; 936 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 937 938 /* Wait for it to finish */ 939 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 940 } 941 942 /* 943 * Disable transmitter. 944 */ 945 int 946 cas_disable_tx(struct cas_softc *sc) 947 { 948 bus_space_tag_t t = sc->sc_memt; 949 bus_space_handle_t h = sc->sc_memh; 950 u_int32_t cfg; 951 952 /* Flip the enable bit */ 953 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 954 cfg &= ~CAS_MAC_TX_ENABLE; 955 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 956 957 /* Wait for it to finish */ 958 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 959 } 960 961 /* 962 * Initialize interface. 963 */ 964 int 965 cas_meminit(struct cas_softc *sc) 966 { 967 int i; 968 969 /* 970 * Initialize the transmit descriptor ring. 971 */ 972 for (i = 0; i < CAS_NTXDESC; i++) { 973 sc->sc_txdescs[i].cd_flags = 0; 974 sc->sc_txdescs[i].cd_addr = 0; 975 } 976 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 977 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 978 979 /* 980 * Initialize the receive descriptor and receive job 981 * descriptor rings. 982 */ 983 for (i = 0; i < CAS_NRXDESC; i++) 984 CAS_INIT_RXDESC(sc, i, i); 985 sc->sc_rxdptr = 0; 986 sc->sc_rxptr = 0; 987 988 /* 989 * Initialize the receive completion ring. 990 */ 991 for (i = 0; i < CAS_NRXCOMP; i++) { 992 sc->sc_rxcomps[i].cc_word[0] = 0; 993 sc->sc_rxcomps[i].cc_word[1] = 0; 994 sc->sc_rxcomps[i].cc_word[2] = 0; 995 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 996 CAS_CDRXCSYNC(sc, i, 997 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 998 } 999 1000 return (0); 1001 } 1002 1003 int 1004 cas_ringsize(int sz) 1005 { 1006 switch (sz) { 1007 case 32: 1008 return CAS_RING_SZ_32; 1009 case 64: 1010 return CAS_RING_SZ_64; 1011 case 128: 1012 return CAS_RING_SZ_128; 1013 case 256: 1014 return CAS_RING_SZ_256; 1015 case 512: 1016 return CAS_RING_SZ_512; 1017 case 1024: 1018 return CAS_RING_SZ_1024; 1019 case 2048: 1020 return CAS_RING_SZ_2048; 1021 case 4096: 1022 return CAS_RING_SZ_4096; 1023 case 8192: 1024 return CAS_RING_SZ_8192; 1025 default: 1026 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1027 sz); 1028 return CAS_RING_SZ_32; 1029 } 1030 } 1031 1032 int 1033 cas_cringsize(int sz) 1034 { 1035 int i; 1036 1037 for (i = 0; i < 9; i++) 1038 if (sz == (128 << i)) 1039 return i; 1040 1041 aprint_error("cas: invalid completion ring size %d\n", sz); 1042 return 128; 1043 } 1044 1045 /* 1046 * Initialization of interface; set up initialization block 1047 * and transmit/receive descriptor rings. 1048 */ 1049 int 1050 cas_init(struct ifnet *ifp) 1051 { 1052 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1053 bus_space_tag_t t = sc->sc_memt; 1054 bus_space_handle_t h = sc->sc_memh; 1055 int s; 1056 u_int max_frame_size; 1057 u_int32_t v; 1058 1059 s = splnet(); 1060 1061 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1062 /* 1063 * Initialization sequence. The numbered steps below correspond 1064 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1065 * Channel Engine manual (part of the PCIO manual). 1066 * See also the STP2002-STQ document from Sun Microsystems. 1067 */ 1068 1069 /* step 1 & 2. Reset the Ethernet Channel */ 1070 cas_stop(ifp, 0); 1071 cas_reset(sc); 1072 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1073 1074 /* Re-initialize the MIF */ 1075 cas_mifinit(sc); 1076 1077 /* step 3. Setup data structures in host memory */ 1078 cas_meminit(sc); 1079 1080 /* step 4. TX MAC registers & counters */ 1081 cas_init_regs(sc); 1082 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1083 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1084 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1085 1086 /* step 5. RX MAC registers & counters */ 1087 cas_iff(sc); 1088 1089 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1090 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1091 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1092 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1093 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1094 1095 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1096 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1097 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1098 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1099 1100 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1101 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1102 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1103 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1104 1105 if (CAS_PLUS(sc)) { 1106 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1107 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1108 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1109 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1110 CAS_CDRXADDR2(sc, 0)); 1111 } 1112 1113 /* step 8. Global Configuration & Interrupt Mask */ 1114 cas_estintr(sc, CAS_INTR_REG); 1115 1116 /* step 9. ETX Configuration: use mostly default values */ 1117 1118 /* Enable DMA */ 1119 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1120 bus_space_write_4(t, h, CAS_TX_CONFIG, 1121 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1122 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1123 1124 /* step 10. ERX Configuration */ 1125 1126 /* Encode Receive Descriptor ring size */ 1127 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1128 if (CAS_PLUS(sc)) 1129 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1130 1131 /* Encode Receive Completion ring size */ 1132 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1133 1134 /* Enable DMA */ 1135 bus_space_write_4(t, h, CAS_RX_CONFIG, 1136 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1137 1138 /* 1139 * The following value is for an OFF Threshold of about 3/4 full 1140 * and an ON Threshold of 1/4 full. 1141 */ 1142 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1143 (3 * sc->sc_rxfifosize / 256) | 1144 ((sc->sc_rxfifosize / 256) << 12)); 1145 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1146 1147 /* step 11. Configure Media */ 1148 mii_ifmedia_change(&sc->sc_mii); 1149 1150 /* step 12. RX_MAC Configuration Register */ 1151 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1152 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1153 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1154 1155 /* step 14. Issue Transmit Pending command */ 1156 1157 /* step 15. Give the receiver a swift kick */ 1158 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1159 if (CAS_PLUS(sc)) 1160 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1161 1162 /* Start the one second timer. */ 1163 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1164 1165 ifp->if_flags |= IFF_RUNNING; 1166 ifp->if_flags &= ~IFF_OACTIVE; 1167 ifp->if_timer = 0; 1168 splx(s); 1169 1170 return (0); 1171 } 1172 1173 void 1174 cas_init_regs(struct cas_softc *sc) 1175 { 1176 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1177 bus_space_tag_t t = sc->sc_memt; 1178 bus_space_handle_t h = sc->sc_memh; 1179 const u_char *laddr = CLLADDR(ifp->if_sadl); 1180 u_int32_t v, r; 1181 1182 /* These regs are not cleared on reset */ 1183 sc->sc_inited = 0; 1184 if (!sc->sc_inited) { 1185 /* Load recommended values */ 1186 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1187 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1188 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1189 1190 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1191 /* Max frame and max burst size */ 1192 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1193 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1194 1195 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1196 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1197 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1198 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1199 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1200 ((laddr[5]<<8)|laddr[4])&0x3ff); 1201 1202 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1203 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1204 bus_space_write_4(t, h, r, 0); 1205 1206 /* MAC control addr set to 0:1:c2:0:1:80 */ 1207 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1208 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1209 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1210 1211 /* MAC filter addr set to 0:0:0:0:0:0 */ 1212 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1213 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1214 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1215 1216 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1217 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1218 1219 /* Hash table initialized to 0 */ 1220 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1221 bus_space_write_4(t, h, r, 0); 1222 1223 sc->sc_inited = 1; 1224 } 1225 1226 /* Counters need to be zeroed */ 1227 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1228 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1229 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1230 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1231 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1232 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1233 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1234 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1235 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1236 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1237 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1238 1239 /* Un-pause stuff */ 1240 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1241 1242 /* 1243 * Set the station address. 1244 */ 1245 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1246 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1247 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1248 } 1249 1250 /* 1251 * Receive interrupt. 1252 */ 1253 int 1254 cas_rint(struct cas_softc *sc) 1255 { 1256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1257 bus_space_tag_t t = sc->sc_memt; 1258 bus_space_handle_t h = sc->sc_memh; 1259 struct cas_rxsoft *rxs; 1260 struct mbuf *m; 1261 u_int64_t word[4]; 1262 int len, off, idx; 1263 int i, skip; 1264 void *cp; 1265 1266 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1267 CAS_CDRXCSYNC(sc, i, 1268 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1269 1270 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1271 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1272 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1273 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1274 1275 /* Stop if the hardware still owns the descriptor. */ 1276 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1277 break; 1278 1279 len = CAS_RC1_HDR_LEN(word[1]); 1280 if (len > 0) { 1281 off = CAS_RC1_HDR_OFF(word[1]); 1282 idx = CAS_RC1_HDR_IDX(word[1]); 1283 rxs = &sc->sc_rxsoft[idx]; 1284 1285 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1286 idx, off, len)); 1287 1288 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1289 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1290 1291 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1292 m = m_devget(cp, len, 0, ifp, NULL); 1293 1294 if (word[0] & CAS_RC0_RELEASE_HDR) 1295 cas_add_rxbuf(sc, idx); 1296 1297 if (m != NULL) { 1298 1299 /* 1300 * Pass this up to any BPF listeners, but only 1301 * pass it up the stack if its for us. 1302 */ 1303 m->m_pkthdr.csum_flags = 0; 1304 if_percpuq_enqueue(ifp->if_percpuq, m); 1305 } else 1306 ifp->if_ierrors++; 1307 } 1308 1309 len = CAS_RC0_DATA_LEN(word[0]); 1310 if (len > 0) { 1311 off = CAS_RC0_DATA_OFF(word[0]); 1312 idx = CAS_RC0_DATA_IDX(word[0]); 1313 rxs = &sc->sc_rxsoft[idx]; 1314 1315 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1316 idx, off, len)); 1317 1318 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1319 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1320 1321 /* XXX We should not be copying the packet here. */ 1322 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1323 m = m_devget(cp, len, 0, ifp, NULL); 1324 1325 if (word[0] & CAS_RC0_RELEASE_DATA) 1326 cas_add_rxbuf(sc, idx); 1327 1328 if (m != NULL) { 1329 /* 1330 * Pass this up to any BPF listeners, but only 1331 * pass it up the stack if its for us. 1332 */ 1333 m->m_pkthdr.csum_flags = 0; 1334 if_percpuq_enqueue(ifp->if_percpuq, m); 1335 } else 1336 ifp->if_ierrors++; 1337 } 1338 1339 if (word[0] & CAS_RC0_SPLIT) 1340 aprint_error_dev(sc->sc_dev, "split packet\n"); 1341 1342 skip = CAS_RC0_SKIP(word[0]); 1343 } 1344 1345 while (sc->sc_rxptr != i) { 1346 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1347 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1348 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1349 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1350 CAS_DMA_WRITE(CAS_RC3_OWN); 1351 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1352 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1353 1354 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1355 } 1356 1357 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1358 1359 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1360 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1361 1362 return (1); 1363 } 1364 1365 /* 1366 * cas_add_rxbuf: 1367 * 1368 * Add a receive buffer to the indicated descriptor. 1369 */ 1370 int 1371 cas_add_rxbuf(struct cas_softc *sc, int idx) 1372 { 1373 bus_space_tag_t t = sc->sc_memt; 1374 bus_space_handle_t h = sc->sc_memh; 1375 1376 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1377 1378 if ((sc->sc_rxdptr % 4) == 0) 1379 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1380 1381 if (++sc->sc_rxdptr == CAS_NRXDESC) 1382 sc->sc_rxdptr = 0; 1383 1384 return (0); 1385 } 1386 1387 int 1388 cas_eint(struct cas_softc *sc, u_int status) 1389 { 1390 char bits[128]; 1391 if ((status & CAS_INTR_MIF) != 0) { 1392 DPRINTF(sc, ("%s: link status changed\n", 1393 device_xname(sc->sc_dev))); 1394 return (1); 1395 } 1396 1397 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1398 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1399 return (1); 1400 } 1401 1402 int 1403 cas_pint(struct cas_softc *sc) 1404 { 1405 bus_space_tag_t t = sc->sc_memt; 1406 bus_space_handle_t seb = sc->sc_memh; 1407 u_int32_t status; 1408 1409 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1410 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1411 #ifdef CAS_DEBUG 1412 if (status) 1413 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1414 #endif 1415 return (1); 1416 } 1417 1418 int 1419 cas_intr(void *v) 1420 { 1421 struct cas_softc *sc = (struct cas_softc *)v; 1422 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1423 bus_space_tag_t t = sc->sc_memt; 1424 bus_space_handle_t seb = sc->sc_memh; 1425 u_int32_t status; 1426 int r = 0; 1427 #ifdef CAS_DEBUG 1428 char bits[128]; 1429 #endif 1430 1431 sc->sc_ev_intr.ev_count++; 1432 1433 status = bus_space_read_4(t, seb, CAS_STATUS); 1434 #ifdef CAS_DEBUG 1435 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1436 #endif 1437 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1438 device_xname(sc->sc_dev), (status>>19), bits)); 1439 1440 if ((status & CAS_INTR_PCS) != 0) 1441 r |= cas_pint(sc); 1442 1443 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1444 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1445 r |= cas_eint(sc, status); 1446 1447 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1448 r |= cas_tint(sc, status); 1449 1450 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1451 r |= cas_rint(sc); 1452 1453 /* We should eventually do more than just print out error stats. */ 1454 if (status & CAS_INTR_TX_MAC) { 1455 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1456 #ifdef CAS_DEBUG 1457 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1458 printf("%s: MAC tx fault, status %x\n", 1459 device_xname(sc->sc_dev), txstat); 1460 #endif 1461 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1462 cas_init(ifp); 1463 } 1464 if (status & CAS_INTR_RX_MAC) { 1465 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1466 #ifdef CAS_DEBUG 1467 if (rxstat & ~CAS_MAC_RX_DONE) 1468 printf("%s: MAC rx fault, status %x\n", 1469 device_xname(sc->sc_dev), rxstat); 1470 #endif 1471 /* 1472 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1473 * due to a silicon bug so handle them silently. 1474 */ 1475 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1476 ifp->if_ierrors++; 1477 cas_init(ifp); 1478 } 1479 #ifdef CAS_DEBUG 1480 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1481 printf("%s: MAC rx fault, status %x\n", 1482 device_xname(sc->sc_dev), rxstat); 1483 #endif 1484 } 1485 rnd_add_uint32(&sc->rnd_source, status); 1486 return (r); 1487 } 1488 1489 1490 void 1491 cas_watchdog(struct ifnet *ifp) 1492 { 1493 struct cas_softc *sc = ifp->if_softc; 1494 1495 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1496 "CAS_MAC_RX_CONFIG %x\n", 1497 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1498 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1499 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1500 1501 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1502 ++ifp->if_oerrors; 1503 1504 /* Try to get more packets going. */ 1505 cas_init(ifp); 1506 } 1507 1508 /* 1509 * Initialize the MII Management Interface 1510 */ 1511 void 1512 cas_mifinit(struct cas_softc *sc) 1513 { 1514 bus_space_tag_t t = sc->sc_memt; 1515 bus_space_handle_t mif = sc->sc_memh; 1516 1517 /* Configure the MIF in frame mode */ 1518 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1519 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1520 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1521 } 1522 1523 /* 1524 * MII interface 1525 * 1526 * The Cassini MII interface supports at least three different operating modes: 1527 * 1528 * Bitbang mode is implemented using data, clock and output enable registers. 1529 * 1530 * Frame mode is implemented by loading a complete frame into the frame 1531 * register and polling the valid bit for completion. 1532 * 1533 * Polling mode uses the frame register but completion is indicated by 1534 * an interrupt. 1535 * 1536 */ 1537 int 1538 cas_mii_readreg(device_t self, int phy, int reg) 1539 { 1540 struct cas_softc *sc = device_private(self); 1541 bus_space_tag_t t = sc->sc_memt; 1542 bus_space_handle_t mif = sc->sc_memh; 1543 int n; 1544 u_int32_t v; 1545 1546 #ifdef CAS_DEBUG 1547 if (sc->sc_debug) 1548 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1549 #endif 1550 1551 /* Construct the frame command */ 1552 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1553 CAS_MIF_FRAME_READ; 1554 1555 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1556 for (n = 0; n < 100; n++) { 1557 DELAY(1); 1558 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1559 if (v & CAS_MIF_FRAME_TA0) 1560 return (v & CAS_MIF_FRAME_DATA); 1561 } 1562 1563 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1564 return (0); 1565 } 1566 1567 void 1568 cas_mii_writereg(device_t self, int phy, int reg, int val) 1569 { 1570 struct cas_softc *sc = device_private(self); 1571 bus_space_tag_t t = sc->sc_memt; 1572 bus_space_handle_t mif = sc->sc_memh; 1573 int n; 1574 u_int32_t v; 1575 1576 #ifdef CAS_DEBUG 1577 if (sc->sc_debug) 1578 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1579 phy, reg, val); 1580 #endif 1581 1582 /* Construct the frame command */ 1583 v = CAS_MIF_FRAME_WRITE | 1584 (phy << CAS_MIF_PHY_SHIFT) | 1585 (reg << CAS_MIF_REG_SHIFT) | 1586 (val & CAS_MIF_FRAME_DATA); 1587 1588 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1589 for (n = 0; n < 100; n++) { 1590 DELAY(1); 1591 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1592 if (v & CAS_MIF_FRAME_TA0) 1593 return; 1594 } 1595 1596 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1597 } 1598 1599 void 1600 cas_mii_statchg(struct ifnet *ifp) 1601 { 1602 struct cas_softc *sc = ifp->if_softc; 1603 #ifdef CAS_DEBUG 1604 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1605 #endif 1606 bus_space_tag_t t = sc->sc_memt; 1607 bus_space_handle_t mac = sc->sc_memh; 1608 u_int32_t v; 1609 1610 #ifdef CAS_DEBUG 1611 if (sc->sc_debug) 1612 printf("cas_mii_statchg: status change: phy = %d\n", 1613 sc->sc_phys[instance]); 1614 #endif 1615 1616 /* Set tx full duplex options */ 1617 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1618 delay(10000); /* reg must be cleared and delay before changing. */ 1619 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1620 CAS_MAC_TX_ENABLE; 1621 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1622 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1623 } 1624 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1625 1626 /* XIF Configuration */ 1627 v = CAS_MAC_XIF_TX_MII_ENA; 1628 v |= CAS_MAC_XIF_LINK_LED; 1629 1630 /* MII needs echo disable if half duplex. */ 1631 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1632 /* turn on full duplex LED */ 1633 v |= CAS_MAC_XIF_FDPLX_LED; 1634 else 1635 /* half duplex -- disable echo */ 1636 v |= CAS_MAC_XIF_ECHO_DISABL; 1637 1638 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1639 case IFM_1000_T: /* Gigabit using GMII interface */ 1640 case IFM_1000_SX: 1641 v |= CAS_MAC_XIF_GMII_MODE; 1642 break; 1643 default: 1644 v &= ~CAS_MAC_XIF_GMII_MODE; 1645 } 1646 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1647 } 1648 1649 int 1650 cas_pcs_readreg(device_t self, int phy, int reg) 1651 { 1652 struct cas_softc *sc = device_private(self); 1653 bus_space_tag_t t = sc->sc_memt; 1654 bus_space_handle_t pcs = sc->sc_memh; 1655 1656 #ifdef CAS_DEBUG 1657 if (sc->sc_debug) 1658 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1659 #endif 1660 1661 if (phy != CAS_PHYAD_EXTERNAL) 1662 return (0); 1663 1664 switch (reg) { 1665 case MII_BMCR: 1666 reg = CAS_MII_CONTROL; 1667 break; 1668 case MII_BMSR: 1669 reg = CAS_MII_STATUS; 1670 break; 1671 case MII_ANAR: 1672 reg = CAS_MII_ANAR; 1673 break; 1674 case MII_ANLPAR: 1675 reg = CAS_MII_ANLPAR; 1676 break; 1677 case MII_EXTSR: 1678 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1679 default: 1680 return (0); 1681 } 1682 1683 return bus_space_read_4(t, pcs, reg); 1684 } 1685 1686 void 1687 cas_pcs_writereg(device_t self, int phy, int reg, int val) 1688 { 1689 struct cas_softc *sc = device_private(self); 1690 bus_space_tag_t t = sc->sc_memt; 1691 bus_space_handle_t pcs = sc->sc_memh; 1692 int reset = 0; 1693 1694 #ifdef CAS_DEBUG 1695 if (sc->sc_debug) 1696 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1697 phy, reg, val); 1698 #endif 1699 1700 if (phy != CAS_PHYAD_EXTERNAL) 1701 return; 1702 1703 if (reg == MII_ANAR) 1704 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1705 1706 switch (reg) { 1707 case MII_BMCR: 1708 reset = (val & CAS_MII_CONTROL_RESET); 1709 reg = CAS_MII_CONTROL; 1710 break; 1711 case MII_BMSR: 1712 reg = CAS_MII_STATUS; 1713 break; 1714 case MII_ANAR: 1715 reg = CAS_MII_ANAR; 1716 break; 1717 case MII_ANLPAR: 1718 reg = CAS_MII_ANLPAR; 1719 break; 1720 default: 1721 return; 1722 } 1723 1724 bus_space_write_4(t, pcs, reg, val); 1725 1726 if (reset) 1727 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1728 1729 if (reg == CAS_MII_ANAR || reset) 1730 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1731 CAS_MII_CONFIG_ENABLE); 1732 } 1733 1734 int 1735 cas_mediachange(struct ifnet *ifp) 1736 { 1737 struct cas_softc *sc = ifp->if_softc; 1738 struct mii_data *mii = &sc->sc_mii; 1739 1740 if (mii->mii_instance) { 1741 struct mii_softc *miisc; 1742 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1743 mii_phy_reset(miisc); 1744 } 1745 1746 return (mii_mediachg(&sc->sc_mii)); 1747 } 1748 1749 void 1750 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1751 { 1752 struct cas_softc *sc = ifp->if_softc; 1753 1754 mii_pollstat(&sc->sc_mii); 1755 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1756 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1757 } 1758 1759 /* 1760 * Process an ioctl request. 1761 */ 1762 int 1763 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1764 { 1765 struct cas_softc *sc = ifp->if_softc; 1766 int s, error = 0; 1767 1768 s = splnet(); 1769 1770 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1771 error = 0; 1772 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1773 ; 1774 else if (ifp->if_flags & IFF_RUNNING) { 1775 /* 1776 * Multicast list has changed; set the hardware filter 1777 * accordingly. 1778 */ 1779 cas_iff(sc); 1780 } 1781 } 1782 1783 splx(s); 1784 return (error); 1785 } 1786 1787 static bool 1788 cas_suspend(device_t self, const pmf_qual_t *qual) 1789 { 1790 struct cas_softc *sc = device_private(self); 1791 bus_space_tag_t t = sc->sc_memt; 1792 bus_space_handle_t h = sc->sc_memh; 1793 1794 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1795 if (sc->sc_ih != NULL) { 1796 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1797 sc->sc_ih = NULL; 1798 } 1799 1800 return true; 1801 } 1802 1803 static bool 1804 cas_resume(device_t self, const pmf_qual_t *qual) 1805 { 1806 struct cas_softc *sc = device_private(self); 1807 1808 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1809 } 1810 1811 static bool 1812 cas_estintr(struct cas_softc *sc, int what) 1813 { 1814 bus_space_tag_t t = sc->sc_memt; 1815 bus_space_handle_t h = sc->sc_memh; 1816 const char *intrstr = NULL; 1817 char intrbuf[PCI_INTRSTR_LEN]; 1818 1819 /* PCI interrupts */ 1820 if (what & CAS_INTR_PCI) { 1821 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle, intrbuf, sizeof(intrbuf)); 1822 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1823 IPL_NET, cas_intr, sc); 1824 if (sc->sc_ih == NULL) { 1825 aprint_error_dev(sc->sc_dev, 1826 "unable to establish interrupt"); 1827 if (intrstr != NULL) 1828 aprint_error(" at %s", intrstr); 1829 aprint_error("\n"); 1830 return false; 1831 } 1832 1833 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1834 } 1835 1836 /* Interrupt register */ 1837 if (what & CAS_INTR_REG) { 1838 bus_space_write_4(t, h, CAS_INTMASK, 1839 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1840 CAS_INTR_TX_TAG_ERR| 1841 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1842 CAS_INTR_RX_TAG_ERR| 1843 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1844 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1845 CAS_INTR_BERR)); 1846 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1847 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1848 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1849 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1850 } 1851 return true; 1852 } 1853 1854 bool 1855 cas_shutdown(device_t self, int howto) 1856 { 1857 struct cas_softc *sc = device_private(self); 1858 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1859 1860 cas_stop(ifp, 1); 1861 1862 return true; 1863 } 1864 1865 void 1866 cas_iff(struct cas_softc *sc) 1867 { 1868 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1869 struct ethercom *ec = &sc->sc_ethercom; 1870 struct ether_multi *enm; 1871 struct ether_multistep step; 1872 bus_space_tag_t t = sc->sc_memt; 1873 bus_space_handle_t h = sc->sc_memh; 1874 u_int32_t crc, hash[16], rxcfg; 1875 int i; 1876 1877 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1878 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1879 CAS_MAC_RX_PROMISC_GRP); 1880 ifp->if_flags &= ~IFF_ALLMULTI; 1881 1882 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1883 ifp->if_flags |= IFF_ALLMULTI; 1884 if (ifp->if_flags & IFF_PROMISC) 1885 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1886 else 1887 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1888 } else { 1889 /* 1890 * Set up multicast address filter by passing all multicast 1891 * addresses through a crc generator, and then using the 1892 * high order 8 bits as an index into the 256 bit logical 1893 * address filter. The high order 4 bits selects the word, 1894 * while the other 4 bits select the bit within the word 1895 * (where bit 0 is the MSB). 1896 */ 1897 1898 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1899 1900 /* Clear hash table */ 1901 for (i = 0; i < 16; i++) 1902 hash[i] = 0; 1903 1904 ETHER_FIRST_MULTI(step, ec, enm); 1905 while (enm != NULL) { 1906 crc = ether_crc32_le(enm->enm_addrlo, 1907 ETHER_ADDR_LEN); 1908 1909 /* Just want the 8 most significant bits. */ 1910 crc >>= 24; 1911 1912 /* Set the corresponding bit in the filter. */ 1913 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1914 1915 ETHER_NEXT_MULTI(step, enm); 1916 } 1917 1918 /* Now load the hash table into the chip (if we are using it) */ 1919 for (i = 0; i < 16; i++) { 1920 bus_space_write_4(t, h, 1921 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1922 hash[i]); 1923 } 1924 } 1925 1926 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1927 } 1928 1929 int 1930 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1931 { 1932 u_int64_t flags; 1933 u_int32_t cur, frag, i; 1934 bus_dmamap_t map; 1935 1936 cur = frag = *bixp; 1937 map = sc->sc_txd[cur].sd_map; 1938 1939 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1940 BUS_DMA_NOWAIT) != 0) { 1941 return (ENOBUFS); 1942 } 1943 1944 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1945 bus_dmamap_unload(sc->sc_dmatag, map); 1946 return (ENOBUFS); 1947 } 1948 1949 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1950 BUS_DMASYNC_PREWRITE); 1951 1952 for (i = 0; i < map->dm_nsegs; i++) { 1953 sc->sc_txdescs[frag].cd_addr = 1954 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1955 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1956 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1957 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1958 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1959 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1960 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1961 BUS_DMASYNC_PREWRITE); 1962 cur = frag; 1963 if (++frag == CAS_NTXDESC) 1964 frag = 0; 1965 } 1966 1967 sc->sc_tx_cnt += map->dm_nsegs; 1968 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1969 sc->sc_txd[cur].sd_map = map; 1970 sc->sc_txd[cur].sd_mbuf = mhead; 1971 1972 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1973 1974 *bixp = frag; 1975 1976 /* sync descriptors */ 1977 1978 return (0); 1979 } 1980 1981 /* 1982 * Transmit interrupt. 1983 */ 1984 int 1985 cas_tint(struct cas_softc *sc, u_int32_t status) 1986 { 1987 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1988 struct cas_sxd *sd; 1989 u_int32_t cons, comp; 1990 1991 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 1992 cons = sc->sc_tx_cons; 1993 while (cons != comp) { 1994 sd = &sc->sc_txd[cons]; 1995 if (sd->sd_mbuf != NULL) { 1996 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1997 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1998 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1999 m_freem(sd->sd_mbuf); 2000 sd->sd_mbuf = NULL; 2001 ifp->if_opackets++; 2002 } 2003 sc->sc_tx_cnt--; 2004 if (++cons == CAS_NTXDESC) 2005 cons = 0; 2006 } 2007 sc->sc_tx_cons = cons; 2008 2009 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2010 ifp->if_flags &= ~IFF_OACTIVE; 2011 if (sc->sc_tx_cnt == 0) 2012 ifp->if_timer = 0; 2013 2014 if_schedule_deferred_start(ifp); 2015 2016 return (1); 2017 } 2018 2019 void 2020 cas_start(struct ifnet *ifp) 2021 { 2022 struct cas_softc *sc = ifp->if_softc; 2023 struct mbuf *m; 2024 u_int32_t bix; 2025 2026 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2027 return; 2028 2029 bix = sc->sc_tx_prod; 2030 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2031 IFQ_POLL(&ifp->if_snd, m); 2032 if (m == NULL) 2033 break; 2034 2035 /* 2036 * If BPF is listening on this interface, let it see the 2037 * packet before we commit it to the wire. 2038 */ 2039 bpf_mtap(ifp, m, BPF_D_OUT); 2040 2041 /* 2042 * Encapsulate this packet and start it going... 2043 * or fail... 2044 */ 2045 if (cas_encap(sc, m, &bix)) { 2046 ifp->if_flags |= IFF_OACTIVE; 2047 break; 2048 } 2049 2050 IFQ_DEQUEUE(&ifp->if_snd, m); 2051 ifp->if_timer = 5; 2052 } 2053 2054 sc->sc_tx_prod = bix; 2055 } 2056 2057 MODULE(MODULE_CLASS_DRIVER, if_cas, "pci"); 2058 2059 #ifdef _MODULE 2060 #include "ioconf.c" 2061 #endif 2062 2063 static int 2064 if_cas_modcmd(modcmd_t cmd, void *opaque) 2065 { 2066 int error = 0; 2067 2068 switch (cmd) { 2069 case MODULE_CMD_INIT: 2070 #ifdef _MODULE 2071 error = config_init_component(cfdriver_ioconf_cas, 2072 cfattach_ioconf_cas, cfdata_ioconf_cas); 2073 #endif 2074 return error; 2075 case MODULE_CMD_FINI: 2076 #ifdef _MODULE 2077 error = config_fini_component(cfdriver_ioconf_cas, 2078 cfattach_ioconf_cas, cfdata_ioconf_cas); 2079 #endif 2080 return error; 2081 default: 2082 return ENOTTY; 2083 } 2084 } 2085