1 /* $NetBSD: if_cas.c,v 1.18 2012/07/22 14:33:02 matt Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.18 2012/07/22 14:33:02 matt Exp $"); 48 49 #ifndef _MODULE 50 #include "opt_inet.h" 51 #endif 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/module.h> 65 66 #include <machine/endian.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #include <net/bpf.h> 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 #include <sys/rnd.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/mii_bitbang.h> 91 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcidevs.h> 95 #include <prop/proplib.h> 96 97 #include <dev/pci/if_casreg.h> 98 #include <dev/pci/if_casvar.h> 99 100 #define TRIES 10000 101 102 static bool cas_estintr(struct cas_softc *sc, int); 103 bool cas_shutdown(device_t, int); 104 static bool cas_suspend(device_t, const pmf_qual_t *); 105 static bool cas_resume(device_t, const pmf_qual_t *); 106 static int cas_detach(device_t, int); 107 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 108 109 int cas_match(device_t, cfdata_t, void *); 110 void cas_attach(device_t, device_t, void *); 111 112 113 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 114 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 115 DVF_DETACH_SHUTDOWN); 116 117 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 118 119 void cas_config(struct cas_softc *, const uint8_t *); 120 void cas_start(struct ifnet *); 121 void cas_stop(struct ifnet *, int); 122 int cas_ioctl(struct ifnet *, u_long, void *); 123 void cas_tick(void *); 124 void cas_watchdog(struct ifnet *); 125 int cas_init(struct ifnet *); 126 void cas_init_regs(struct cas_softc *); 127 int cas_ringsize(int); 128 int cas_cringsize(int); 129 int cas_meminit(struct cas_softc *); 130 void cas_mifinit(struct cas_softc *); 131 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 132 u_int32_t, u_int32_t); 133 void cas_reset(struct cas_softc *); 134 int cas_reset_rx(struct cas_softc *); 135 int cas_reset_tx(struct cas_softc *); 136 int cas_disable_rx(struct cas_softc *); 137 int cas_disable_tx(struct cas_softc *); 138 void cas_rxdrain(struct cas_softc *); 139 int cas_add_rxbuf(struct cas_softc *, int idx); 140 void cas_iff(struct cas_softc *); 141 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 142 143 /* MII methods & callbacks */ 144 int cas_mii_readreg(device_t, int, int); 145 void cas_mii_writereg(device_t, int, int, int); 146 void cas_mii_statchg(struct ifnet *); 147 int cas_pcs_readreg(device_t, int, int); 148 void cas_pcs_writereg(device_t, int, int, int); 149 150 int cas_mediachange(struct ifnet *); 151 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 152 153 int cas_eint(struct cas_softc *, u_int); 154 int cas_rint(struct cas_softc *); 155 int cas_tint(struct cas_softc *, u_int32_t); 156 int cas_pint(struct cas_softc *); 157 int cas_intr(void *); 158 159 #ifdef CAS_DEBUG 160 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 161 printf x 162 #else 163 #define DPRINTF(sc, x) /* nothing */ 164 #endif 165 166 int 167 cas_match(device_t parent, cfdata_t cf, void *aux) 168 { 169 struct pci_attach_args *pa = aux; 170 171 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 172 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 173 return 1; 174 175 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 176 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 177 return 1; 178 179 return 0; 180 } 181 182 #define PROMHDR_PTR_DATA 0x18 183 #define PROMDATA_PTR_VPD 0x08 184 #define PROMDATA_DATA2 0x0a 185 186 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 187 static const u_int8_t cas_promdat[] = { 188 'P', 'C', 'I', 'R', 189 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 190 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 191 }; 192 static const u_int8_t cas_promdat_ns[] = { 193 'P', 'C', 'I', 'R', 194 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 195 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 196 }; 197 198 static const u_int8_t cas_promdat2[] = { 199 0x18, 0x00, /* structure length */ 200 0x00, /* structure revision */ 201 0x00, /* interface revision */ 202 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 203 PCI_CLASS_NETWORK /* class code */ 204 }; 205 206 int 207 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 208 uint8_t *enaddr) 209 { 210 struct pci_vpd_largeres *res; 211 struct pci_vpd *vpd; 212 bus_space_handle_t romh; 213 bus_space_tag_t romt; 214 bus_size_t romsize = 0; 215 u_int8_t buf[32], *desc; 216 pcireg_t address; 217 int dataoff, vpdoff, len; 218 int rv = -1; 219 220 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 221 &romt, &romh, NULL, &romsize)) 222 return (-1); 223 224 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 225 address |= PCI_MAPREG_ROM_ENABLE; 226 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 227 228 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 229 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 230 goto fail; 231 232 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 233 if (dataoff < 0x1c) 234 goto fail; 235 236 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 237 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 238 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 239 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 240 goto fail; 241 242 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 243 if (vpdoff < 0x1c) 244 goto fail; 245 246 next: 247 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 248 if (!PCI_VPDRES_ISLARGE(buf[0])) 249 goto fail; 250 251 res = (struct pci_vpd_largeres *)buf; 252 vpdoff += sizeof(*res); 253 254 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 255 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 256 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 257 /* Skip identifier string. */ 258 vpdoff += len; 259 goto next; 260 261 case PCI_VPDRES_TYPE_VPD: 262 while (len > 0) { 263 bus_space_read_region_1(romt, romh, vpdoff, 264 buf, sizeof(buf)); 265 266 vpd = (struct pci_vpd *)buf; 267 vpdoff += sizeof(*vpd) + vpd->vpd_len; 268 len -= sizeof(*vpd) + vpd->vpd_len; 269 270 /* 271 * We're looking for an "Enhanced" VPD... 272 */ 273 if (vpd->vpd_key0 != 'Z') 274 continue; 275 276 desc = buf + sizeof(*vpd); 277 278 /* 279 * ...which is an instance property... 280 */ 281 if (desc[0] != 'I') 282 continue; 283 desc += 3; 284 285 /* 286 * ...that's a byte array with the proper 287 * length for a MAC address... 288 */ 289 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 290 continue; 291 desc += 2; 292 293 /* 294 * ...named "local-mac-address". 295 */ 296 if (strcmp(desc, "local-mac-address") != 0) 297 continue; 298 desc += strlen("local-mac-address") + 1; 299 300 memcpy(enaddr, desc, ETHER_ADDR_LEN); 301 rv = 0; 302 } 303 break; 304 305 default: 306 goto fail; 307 } 308 309 fail: 310 if (romsize != 0) 311 bus_space_unmap(romt, romh, romsize); 312 313 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 314 address &= ~PCI_MAPREG_ROM_ENABLE; 315 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 316 317 return (rv); 318 } 319 320 void 321 cas_attach(device_t parent, device_t self, void *aux) 322 { 323 struct pci_attach_args *pa = aux; 324 struct cas_softc *sc = device_private(self); 325 prop_data_t data; 326 uint8_t enaddr[ETHER_ADDR_LEN]; 327 328 sc->sc_dev = self; 329 pci_aprint_devinfo(pa, NULL); 330 sc->sc_rev = PCI_REVISION(pa->pa_class); 331 sc->sc_dmatag = pa->pa_dmat; 332 333 #define PCI_CAS_BASEADDR 0x10 334 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 335 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 336 aprint_error_dev(sc->sc_dev, 337 "unable to map device registers\n"); 338 return; 339 } 340 341 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 342 "mac-address")) != NULL) 343 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 344 else if (cas_pci_enaddr(sc, pa, enaddr) != 0) { 345 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 346 memset(enaddr, 0, sizeof(enaddr)); 347 } 348 349 sc->sc_burst = 16; /* XXX */ 350 351 sc->sc_att_stage = CAS_ATT_BACKEND_0; 352 353 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 354 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 355 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 356 return; 357 } 358 sc->sc_pc = pa->pa_pc; 359 if (!cas_estintr(sc, CAS_INTR_PCI)) { 360 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 361 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 362 return; 363 } 364 365 sc->sc_att_stage = CAS_ATT_BACKEND_1; 366 367 /* 368 * call the main configure 369 */ 370 cas_config(sc, enaddr); 371 372 if (pmf_device_register1(sc->sc_dev, 373 cas_suspend, cas_resume, cas_shutdown)) 374 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 375 else 376 aprint_error_dev(sc->sc_dev, 377 "could not establish power handlers\n"); 378 379 sc->sc_att_stage = CAS_ATT_FINISHED; 380 /*FALLTHROUGH*/ 381 } 382 383 /* 384 * cas_config: 385 * 386 * Attach a Cassini interface to the system. 387 */ 388 void 389 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 390 { 391 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 392 struct mii_data *mii = &sc->sc_mii; 393 struct mii_softc *child; 394 int i, error; 395 396 /* Make sure the chip is stopped. */ 397 ifp->if_softc = sc; 398 cas_reset(sc); 399 400 /* 401 * Allocate the control data structures, and create and load the 402 * DMA map for it. 403 */ 404 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 405 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 406 1, &sc->sc_cdnseg, 0)) != 0) { 407 aprint_error_dev(sc->sc_dev, 408 "unable to allocate control data, error = %d\n", 409 error); 410 cas_partial_detach(sc, CAS_ATT_0); 411 } 412 413 /* XXX should map this in with correct endianness */ 414 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 415 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 416 BUS_DMA_COHERENT)) != 0) { 417 aprint_error_dev(sc->sc_dev, 418 "unable to map control data, error = %d\n", error); 419 cas_partial_detach(sc, CAS_ATT_1); 420 } 421 422 if ((error = bus_dmamap_create(sc->sc_dmatag, 423 sizeof(struct cas_control_data), 1, 424 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 425 aprint_error_dev(sc->sc_dev, 426 "unable to create control data DMA map, error = %d\n", error); 427 cas_partial_detach(sc, CAS_ATT_2); 428 } 429 430 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 431 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 432 0)) != 0) { 433 aprint_error_dev(sc->sc_dev, 434 "unable to load control data DMA map, error = %d\n", 435 error); 436 cas_partial_detach(sc, CAS_ATT_3); 437 } 438 439 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 440 441 /* 442 * Create the receive buffer DMA maps. 443 */ 444 for (i = 0; i < CAS_NRXDESC; i++) { 445 bus_dma_segment_t seg; 446 char *kva; 447 int rseg; 448 449 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 450 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 451 aprint_error_dev(sc->sc_dev, 452 "unable to alloc rx DMA mem %d, error = %d\n", 453 i, error); 454 cas_partial_detach(sc, CAS_ATT_5); 455 } 456 sc->sc_rxsoft[i].rxs_dmaseg = seg; 457 458 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 459 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 460 aprint_error_dev(sc->sc_dev, 461 "unable to alloc rx DMA mem %d, error = %d\n", 462 i, error); 463 cas_partial_detach(sc, CAS_ATT_5); 464 } 465 sc->sc_rxsoft[i].rxs_kva = kva; 466 467 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 468 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 469 aprint_error_dev(sc->sc_dev, 470 "unable to create rx DMA map %d, error = %d\n", 471 i, error); 472 cas_partial_detach(sc, CAS_ATT_5); 473 } 474 475 if ((error = bus_dmamap_load(sc->sc_dmatag, 476 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 477 BUS_DMA_NOWAIT)) != 0) { 478 aprint_error_dev(sc->sc_dev, 479 "unable to load rx DMA map %d, error = %d\n", 480 i, error); 481 cas_partial_detach(sc, CAS_ATT_5); 482 } 483 } 484 485 /* 486 * Create the transmit buffer DMA maps. 487 */ 488 for (i = 0; i < CAS_NTXDESC; i++) { 489 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 490 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 491 &sc->sc_txd[i].sd_map)) != 0) { 492 aprint_error_dev(sc->sc_dev, 493 "unable to create tx DMA map %d, error = %d\n", 494 i, error); 495 cas_partial_detach(sc, CAS_ATT_6); 496 } 497 sc->sc_txd[i].sd_mbuf = NULL; 498 } 499 500 /* 501 * From this point forward, the attachment cannot fail. A failure 502 * before this point releases all resources that may have been 503 * allocated. 504 */ 505 506 /* Announce ourselves. */ 507 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 508 ether_sprintf(enaddr)); 509 aprint_naive(": Ethernet controller\n"); 510 511 /* Get RX FIFO size */ 512 sc->sc_rxfifosize = 16 * 1024; 513 514 /* Initialize ifnet structure. */ 515 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 516 ifp->if_softc = sc; 517 ifp->if_flags = 518 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 519 ifp->if_start = cas_start; 520 ifp->if_ioctl = cas_ioctl; 521 ifp->if_watchdog = cas_watchdog; 522 ifp->if_stop = cas_stop; 523 ifp->if_init = cas_init; 524 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 525 IFQ_SET_READY(&ifp->if_snd); 526 527 /* Initialize ifmedia structures and MII info */ 528 mii->mii_ifp = ifp; 529 mii->mii_readreg = cas_mii_readreg; 530 mii->mii_writereg = cas_mii_writereg; 531 mii->mii_statchg = cas_mii_statchg; 532 533 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 534 sc->sc_ethercom.ec_mii = mii; 535 536 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 537 538 cas_mifinit(sc); 539 540 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 541 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 542 bus_space_write_4(sc->sc_memt, sc->sc_memh, 543 CAS_MIF_CONFIG, sc->sc_mif_config); 544 } 545 546 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 547 MII_OFFSET_ANY, 0); 548 549 child = LIST_FIRST(&mii->mii_phys); 550 if (child == NULL && 551 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 552 /* 553 * Try the external PCS SERDES if we didn't find any 554 * MII devices. 555 */ 556 bus_space_write_4(sc->sc_memt, sc->sc_memh, 557 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 558 559 bus_space_write_4(sc->sc_memt, sc->sc_memh, 560 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 561 562 mii->mii_readreg = cas_pcs_readreg; 563 mii->mii_writereg = cas_pcs_writereg; 564 565 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 566 MII_OFFSET_ANY, MIIF_NOISOLATE); 567 } 568 569 child = LIST_FIRST(&mii->mii_phys); 570 if (child == NULL) { 571 /* No PHY attached */ 572 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 573 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 574 } else { 575 /* 576 * Walk along the list of attached MII devices and 577 * establish an `MII instance' to `phy number' 578 * mapping. We'll use this mapping in media change 579 * requests to determine which phy to use to program 580 * the MIF configuration register. 581 */ 582 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 583 /* 584 * Note: we support just two PHYs: the built-in 585 * internal device and an external on the MII 586 * connector. 587 */ 588 if (child->mii_phy > 1 || child->mii_inst > 1) { 589 aprint_error_dev(sc->sc_dev, 590 "cannot accommodate MII device %s" 591 " at phy %d, instance %d\n", 592 device_xname(child->mii_dev), 593 child->mii_phy, child->mii_inst); 594 continue; 595 } 596 597 sc->sc_phys[child->mii_inst] = child->mii_phy; 598 } 599 600 /* 601 * XXX - we can really do the following ONLY if the 602 * phy indeed has the auto negotiation capability!! 603 */ 604 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 605 } 606 607 /* claim 802.1q capability */ 608 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 609 610 /* Attach the interface. */ 611 if_attach(ifp); 612 ether_ifattach(ifp, enaddr); 613 614 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 615 RND_TYPE_NET, 0); 616 617 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 618 NULL, device_xname(sc->sc_dev), "interrupts"); 619 620 callout_init(&sc->sc_tick_ch, 0); 621 622 return; 623 } 624 625 int 626 cas_detach(device_t self, int flags) 627 { 628 int i; 629 struct cas_softc *sc = device_private(self); 630 bus_space_tag_t t = sc->sc_memt; 631 bus_space_handle_t h = sc->sc_memh; 632 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 633 634 /* 635 * Free any resources we've allocated during the failed attach 636 * attempt. Do this in reverse order and fall through. 637 */ 638 switch (sc->sc_att_stage) { 639 case CAS_ATT_FINISHED: 640 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 641 pmf_device_deregister(self); 642 cas_stop(&sc->sc_ethercom.ec_if, 1); 643 evcnt_detach(&sc->sc_ev_intr); 644 645 rnd_detach_source(&sc->rnd_source); 646 647 ether_ifdetach(ifp); 648 if_detach(ifp); 649 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 650 651 callout_destroy(&sc->sc_tick_ch); 652 653 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 654 655 /*FALLTHROUGH*/ 656 case CAS_ATT_MII: 657 case CAS_ATT_7: 658 case CAS_ATT_6: 659 for (i = 0; i < CAS_NTXDESC; i++) { 660 if (sc->sc_txd[i].sd_map != NULL) 661 bus_dmamap_destroy(sc->sc_dmatag, 662 sc->sc_txd[i].sd_map); 663 } 664 /*FALLTHROUGH*/ 665 case CAS_ATT_5: 666 for (i = 0; i < CAS_NRXDESC; i++) { 667 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 668 bus_dmamap_unload(sc->sc_dmatag, 669 sc->sc_rxsoft[i].rxs_dmamap); 670 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 671 bus_dmamap_destroy(sc->sc_dmatag, 672 sc->sc_rxsoft[i].rxs_dmamap); 673 if (sc->sc_rxsoft[i].rxs_kva != NULL) 674 bus_dmamem_unmap(sc->sc_dmatag, 675 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 676 /* XXX need to check that bus_dmamem_alloc suceeded 677 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 678 */ 679 bus_dmamem_free(sc->sc_dmatag, 680 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 681 } 682 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 683 /*FALLTHROUGH*/ 684 case CAS_ATT_4: 685 case CAS_ATT_3: 686 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 687 /*FALLTHROUGH*/ 688 case CAS_ATT_2: 689 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 690 sizeof(struct cas_control_data)); 691 /*FALLTHROUGH*/ 692 case CAS_ATT_1: 693 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 694 /*FALLTHROUGH*/ 695 case CAS_ATT_0: 696 sc->sc_att_stage = CAS_ATT_0; 697 /*FALLTHROUGH*/ 698 case CAS_ATT_BACKEND_2: 699 case CAS_ATT_BACKEND_1: 700 if (sc->sc_ih != NULL) { 701 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 702 sc->sc_ih = NULL; 703 } 704 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 705 /*FALLTHROUGH*/ 706 case CAS_ATT_BACKEND_0: 707 break; 708 } 709 return 0; 710 } 711 712 static void 713 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 714 { 715 cfattach_t ca = device_cfattach(sc->sc_dev); 716 717 sc->sc_att_stage = stage; 718 (*ca->ca_detach)(sc->sc_dev, 0); 719 } 720 721 void 722 cas_tick(void *arg) 723 { 724 struct cas_softc *sc = arg; 725 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 726 bus_space_tag_t t = sc->sc_memt; 727 bus_space_handle_t mac = sc->sc_memh; 728 int s; 729 u_int32_t v; 730 731 /* unload collisions counters */ 732 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 733 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 734 ifp->if_collisions += v + 735 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 736 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 737 ifp->if_oerrors += v; 738 739 /* read error counters */ 740 ifp->if_ierrors += 741 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 742 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 743 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 744 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 745 746 /* clear the hardware counters */ 747 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 748 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 749 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 750 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 751 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 752 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 753 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 754 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 755 756 s = splnet(); 757 mii_tick(&sc->sc_mii); 758 splx(s); 759 760 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 761 } 762 763 int 764 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 765 u_int32_t clr, u_int32_t set) 766 { 767 int i; 768 u_int32_t reg; 769 770 for (i = TRIES; i--; DELAY(100)) { 771 reg = bus_space_read_4(sc->sc_memt, h, r); 772 if ((reg & clr) == 0 && (reg & set) == set) 773 return (1); 774 } 775 776 return (0); 777 } 778 779 void 780 cas_reset(struct cas_softc *sc) 781 { 782 bus_space_tag_t t = sc->sc_memt; 783 bus_space_handle_t h = sc->sc_memh; 784 int s; 785 786 s = splnet(); 787 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 788 cas_reset_rx(sc); 789 cas_reset_tx(sc); 790 791 /* Disable interrupts */ 792 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 793 794 /* Do a full reset */ 795 bus_space_write_4(t, h, CAS_RESET, 796 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 797 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 798 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 799 splx(s); 800 } 801 802 803 /* 804 * cas_rxdrain: 805 * 806 * Drain the receive queue. 807 */ 808 void 809 cas_rxdrain(struct cas_softc *sc) 810 { 811 /* Nothing to do yet. */ 812 } 813 814 /* 815 * Reset the whole thing. 816 */ 817 void 818 cas_stop(struct ifnet *ifp, int disable) 819 { 820 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 821 struct cas_sxd *sd; 822 u_int32_t i; 823 824 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 825 826 callout_stop(&sc->sc_tick_ch); 827 828 /* 829 * Mark the interface down and cancel the watchdog timer. 830 */ 831 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 832 ifp->if_timer = 0; 833 834 mii_down(&sc->sc_mii); 835 836 cas_reset_rx(sc); 837 cas_reset_tx(sc); 838 839 /* 840 * Release any queued transmit buffers. 841 */ 842 for (i = 0; i < CAS_NTXDESC; i++) { 843 sd = &sc->sc_txd[i]; 844 if (sd->sd_mbuf != NULL) { 845 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 846 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 847 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 848 m_freem(sd->sd_mbuf); 849 sd->sd_mbuf = NULL; 850 } 851 } 852 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 853 854 if (disable) 855 cas_rxdrain(sc); 856 } 857 858 859 /* 860 * Reset the receiver 861 */ 862 int 863 cas_reset_rx(struct cas_softc *sc) 864 { 865 bus_space_tag_t t = sc->sc_memt; 866 bus_space_handle_t h = sc->sc_memh; 867 868 /* 869 * Resetting while DMA is in progress can cause a bus hang, so we 870 * disable DMA first. 871 */ 872 cas_disable_rx(sc); 873 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 874 /* Wait till it finishes */ 875 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 876 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 877 /* Wait 5ms extra. */ 878 delay(5000); 879 880 /* Finally, reset the ERX */ 881 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 882 /* Wait till it finishes */ 883 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 884 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 885 return (1); 886 } 887 return (0); 888 } 889 890 891 /* 892 * Reset the transmitter 893 */ 894 int 895 cas_reset_tx(struct cas_softc *sc) 896 { 897 bus_space_tag_t t = sc->sc_memt; 898 bus_space_handle_t h = sc->sc_memh; 899 900 /* 901 * Resetting while DMA is in progress can cause a bus hang, so we 902 * disable DMA first. 903 */ 904 cas_disable_tx(sc); 905 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 906 /* Wait till it finishes */ 907 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 908 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 909 /* Wait 5ms extra. */ 910 delay(5000); 911 912 /* Finally, reset the ETX */ 913 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 914 /* Wait till it finishes */ 915 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 916 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 917 return (1); 918 } 919 return (0); 920 } 921 922 /* 923 * Disable receiver. 924 */ 925 int 926 cas_disable_rx(struct cas_softc *sc) 927 { 928 bus_space_tag_t t = sc->sc_memt; 929 bus_space_handle_t h = sc->sc_memh; 930 u_int32_t cfg; 931 932 /* Flip the enable bit */ 933 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 934 cfg &= ~CAS_MAC_RX_ENABLE; 935 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 936 937 /* Wait for it to finish */ 938 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 939 } 940 941 /* 942 * Disable transmitter. 943 */ 944 int 945 cas_disable_tx(struct cas_softc *sc) 946 { 947 bus_space_tag_t t = sc->sc_memt; 948 bus_space_handle_t h = sc->sc_memh; 949 u_int32_t cfg; 950 951 /* Flip the enable bit */ 952 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 953 cfg &= ~CAS_MAC_TX_ENABLE; 954 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 955 956 /* Wait for it to finish */ 957 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 958 } 959 960 /* 961 * Initialize interface. 962 */ 963 int 964 cas_meminit(struct cas_softc *sc) 965 { 966 struct cas_rxsoft *rxs; 967 int i, error; 968 969 rxs = (void *)&error; 970 971 /* 972 * Initialize the transmit descriptor ring. 973 */ 974 for (i = 0; i < CAS_NTXDESC; i++) { 975 sc->sc_txdescs[i].cd_flags = 0; 976 sc->sc_txdescs[i].cd_addr = 0; 977 } 978 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 979 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 980 981 /* 982 * Initialize the receive descriptor and receive job 983 * descriptor rings. 984 */ 985 for (i = 0; i < CAS_NRXDESC; i++) 986 CAS_INIT_RXDESC(sc, i, i); 987 sc->sc_rxdptr = 0; 988 sc->sc_rxptr = 0; 989 990 /* 991 * Initialize the receive completion ring. 992 */ 993 for (i = 0; i < CAS_NRXCOMP; i++) { 994 sc->sc_rxcomps[i].cc_word[0] = 0; 995 sc->sc_rxcomps[i].cc_word[1] = 0; 996 sc->sc_rxcomps[i].cc_word[2] = 0; 997 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 998 CAS_CDRXCSYNC(sc, i, 999 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1000 } 1001 1002 return (0); 1003 } 1004 1005 int 1006 cas_ringsize(int sz) 1007 { 1008 switch (sz) { 1009 case 32: 1010 return CAS_RING_SZ_32; 1011 case 64: 1012 return CAS_RING_SZ_64; 1013 case 128: 1014 return CAS_RING_SZ_128; 1015 case 256: 1016 return CAS_RING_SZ_256; 1017 case 512: 1018 return CAS_RING_SZ_512; 1019 case 1024: 1020 return CAS_RING_SZ_1024; 1021 case 2048: 1022 return CAS_RING_SZ_2048; 1023 case 4096: 1024 return CAS_RING_SZ_4096; 1025 case 8192: 1026 return CAS_RING_SZ_8192; 1027 default: 1028 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1029 sz); 1030 return CAS_RING_SZ_32; 1031 } 1032 } 1033 1034 int 1035 cas_cringsize(int sz) 1036 { 1037 int i; 1038 1039 for (i = 0; i < 9; i++) 1040 if (sz == (128 << i)) 1041 return i; 1042 1043 aprint_error("cas: invalid completion ring size %d\n", sz); 1044 return 128; 1045 } 1046 1047 /* 1048 * Initialization of interface; set up initialization block 1049 * and transmit/receive descriptor rings. 1050 */ 1051 int 1052 cas_init(struct ifnet *ifp) 1053 { 1054 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1055 bus_space_tag_t t = sc->sc_memt; 1056 bus_space_handle_t h = sc->sc_memh; 1057 int s; 1058 u_int max_frame_size; 1059 u_int32_t v; 1060 1061 s = splnet(); 1062 1063 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1064 /* 1065 * Initialization sequence. The numbered steps below correspond 1066 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1067 * Channel Engine manual (part of the PCIO manual). 1068 * See also the STP2002-STQ document from Sun Microsystems. 1069 */ 1070 1071 /* step 1 & 2. Reset the Ethernet Channel */ 1072 cas_stop(ifp, 0); 1073 cas_reset(sc); 1074 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1075 1076 /* Re-initialize the MIF */ 1077 cas_mifinit(sc); 1078 1079 /* step 3. Setup data structures in host memory */ 1080 cas_meminit(sc); 1081 1082 /* step 4. TX MAC registers & counters */ 1083 cas_init_regs(sc); 1084 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1085 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1086 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1087 1088 /* step 5. RX MAC registers & counters */ 1089 cas_iff(sc); 1090 1091 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1092 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1093 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1094 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1095 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1096 1097 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1098 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1099 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1100 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1101 1102 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1103 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1104 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1105 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1106 1107 if (CAS_PLUS(sc)) { 1108 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1109 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1110 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1111 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1112 CAS_CDRXADDR2(sc, 0)); 1113 } 1114 1115 /* step 8. Global Configuration & Interrupt Mask */ 1116 cas_estintr(sc, CAS_INTR_REG); 1117 1118 /* step 9. ETX Configuration: use mostly default values */ 1119 1120 /* Enable DMA */ 1121 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1122 bus_space_write_4(t, h, CAS_TX_CONFIG, 1123 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1124 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1125 1126 /* step 10. ERX Configuration */ 1127 1128 /* Encode Receive Descriptor ring size */ 1129 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1130 if (CAS_PLUS(sc)) 1131 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1132 1133 /* Encode Receive Completion ring size */ 1134 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1135 1136 /* Enable DMA */ 1137 bus_space_write_4(t, h, CAS_RX_CONFIG, 1138 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1139 1140 /* 1141 * The following value is for an OFF Threshold of about 3/4 full 1142 * and an ON Threshold of 1/4 full. 1143 */ 1144 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1145 (3 * sc->sc_rxfifosize / 256) | 1146 ((sc->sc_rxfifosize / 256) << 12)); 1147 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1148 1149 /* step 11. Configure Media */ 1150 mii_ifmedia_change(&sc->sc_mii); 1151 1152 /* step 12. RX_MAC Configuration Register */ 1153 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1154 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1155 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1156 1157 /* step 14. Issue Transmit Pending command */ 1158 1159 /* step 15. Give the receiver a swift kick */ 1160 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1161 if (CAS_PLUS(sc)) 1162 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1163 1164 /* Start the one second timer. */ 1165 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1166 1167 ifp->if_flags |= IFF_RUNNING; 1168 ifp->if_flags &= ~IFF_OACTIVE; 1169 ifp->if_timer = 0; 1170 splx(s); 1171 1172 return (0); 1173 } 1174 1175 void 1176 cas_init_regs(struct cas_softc *sc) 1177 { 1178 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1179 bus_space_tag_t t = sc->sc_memt; 1180 bus_space_handle_t h = sc->sc_memh; 1181 const u_char *laddr = CLLADDR(ifp->if_sadl); 1182 u_int32_t v, r; 1183 1184 /* These regs are not cleared on reset */ 1185 sc->sc_inited = 0; 1186 if (!sc->sc_inited) { 1187 /* Load recommended values */ 1188 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1189 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1190 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1191 1192 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1193 /* Max frame and max burst size */ 1194 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1195 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1196 1197 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1198 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1199 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1200 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1201 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1202 ((laddr[5]<<8)|laddr[4])&0x3ff); 1203 1204 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1205 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1206 bus_space_write_4(t, h, r, 0); 1207 1208 /* MAC control addr set to 0:1:c2:0:1:80 */ 1209 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1210 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1211 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1212 1213 /* MAC filter addr set to 0:0:0:0:0:0 */ 1214 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1215 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1216 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1217 1218 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1219 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1220 1221 /* Hash table initialized to 0 */ 1222 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1223 bus_space_write_4(t, h, r, 0); 1224 1225 sc->sc_inited = 1; 1226 } 1227 1228 /* Counters need to be zeroed */ 1229 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1230 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1231 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1232 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1233 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1234 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1235 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1236 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1237 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1238 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1239 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1240 1241 /* Un-pause stuff */ 1242 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1243 1244 /* 1245 * Set the station address. 1246 */ 1247 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1248 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1249 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1250 } 1251 1252 /* 1253 * Receive interrupt. 1254 */ 1255 int 1256 cas_rint(struct cas_softc *sc) 1257 { 1258 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1259 bus_space_tag_t t = sc->sc_memt; 1260 bus_space_handle_t h = sc->sc_memh; 1261 struct cas_rxsoft *rxs; 1262 struct mbuf *m; 1263 u_int64_t word[4]; 1264 int len, off, idx; 1265 int i, skip; 1266 void *cp; 1267 1268 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1269 CAS_CDRXCSYNC(sc, i, 1270 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1271 1272 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1273 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1274 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1275 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1276 1277 /* Stop if the hardware still owns the descriptor. */ 1278 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1279 break; 1280 1281 len = CAS_RC1_HDR_LEN(word[1]); 1282 if (len > 0) { 1283 off = CAS_RC1_HDR_OFF(word[1]); 1284 idx = CAS_RC1_HDR_IDX(word[1]); 1285 rxs = &sc->sc_rxsoft[idx]; 1286 1287 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1288 idx, off, len)); 1289 1290 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1291 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1292 1293 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1294 m = m_devget(cp, len, 0, ifp, NULL); 1295 1296 if (word[0] & CAS_RC0_RELEASE_HDR) 1297 cas_add_rxbuf(sc, idx); 1298 1299 if (m != NULL) { 1300 1301 /* 1302 * Pass this up to any BPF listeners, but only 1303 * pass it up the stack if its for us. 1304 */ 1305 bpf_mtap(ifp, m); 1306 1307 ifp->if_ipackets++; 1308 m->m_pkthdr.csum_flags = 0; 1309 (*ifp->if_input)(ifp, m); 1310 } else 1311 ifp->if_ierrors++; 1312 } 1313 1314 len = CAS_RC0_DATA_LEN(word[0]); 1315 if (len > 0) { 1316 off = CAS_RC0_DATA_OFF(word[0]); 1317 idx = CAS_RC0_DATA_IDX(word[0]); 1318 rxs = &sc->sc_rxsoft[idx]; 1319 1320 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1321 idx, off, len)); 1322 1323 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1324 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1325 1326 /* XXX We should not be copying the packet here. */ 1327 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1328 m = m_devget(cp, len, 0, ifp, NULL); 1329 1330 if (word[0] & CAS_RC0_RELEASE_DATA) 1331 cas_add_rxbuf(sc, idx); 1332 1333 if (m != NULL) { 1334 /* 1335 * Pass this up to any BPF listeners, but only 1336 * pass it up the stack if its for us. 1337 */ 1338 bpf_mtap(ifp, m); 1339 1340 ifp->if_ipackets++; 1341 m->m_pkthdr.csum_flags = 0; 1342 (*ifp->if_input)(ifp, m); 1343 } else 1344 ifp->if_ierrors++; 1345 } 1346 1347 if (word[0] & CAS_RC0_SPLIT) 1348 aprint_error_dev(sc->sc_dev, "split packet\n"); 1349 1350 skip = CAS_RC0_SKIP(word[0]); 1351 } 1352 1353 while (sc->sc_rxptr != i) { 1354 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1355 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1356 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1357 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1358 CAS_DMA_WRITE(CAS_RC3_OWN); 1359 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1360 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1361 1362 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1363 } 1364 1365 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1366 1367 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1368 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1369 1370 return (1); 1371 } 1372 1373 /* 1374 * cas_add_rxbuf: 1375 * 1376 * Add a receive buffer to the indicated descriptor. 1377 */ 1378 int 1379 cas_add_rxbuf(struct cas_softc *sc, int idx) 1380 { 1381 bus_space_tag_t t = sc->sc_memt; 1382 bus_space_handle_t h = sc->sc_memh; 1383 1384 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1385 1386 if ((sc->sc_rxdptr % 4) == 0) 1387 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1388 1389 if (++sc->sc_rxdptr == CAS_NRXDESC) 1390 sc->sc_rxdptr = 0; 1391 1392 return (0); 1393 } 1394 1395 int 1396 cas_eint(struct cas_softc *sc, u_int status) 1397 { 1398 char bits[128]; 1399 if ((status & CAS_INTR_MIF) != 0) { 1400 DPRINTF(sc, ("%s: link status changed\n", 1401 device_xname(sc->sc_dev))); 1402 return (1); 1403 } 1404 1405 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1406 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1407 return (1); 1408 } 1409 1410 int 1411 cas_pint(struct cas_softc *sc) 1412 { 1413 bus_space_tag_t t = sc->sc_memt; 1414 bus_space_handle_t seb = sc->sc_memh; 1415 u_int32_t status; 1416 1417 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1418 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1419 #ifdef CAS_DEBUG 1420 if (status) 1421 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1422 #endif 1423 return (1); 1424 } 1425 1426 int 1427 cas_intr(void *v) 1428 { 1429 struct cas_softc *sc = (struct cas_softc *)v; 1430 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1431 bus_space_tag_t t = sc->sc_memt; 1432 bus_space_handle_t seb = sc->sc_memh; 1433 u_int32_t status; 1434 int r = 0; 1435 #ifdef CAS_DEBUG 1436 char bits[128]; 1437 #endif 1438 1439 sc->sc_ev_intr.ev_count++; 1440 1441 status = bus_space_read_4(t, seb, CAS_STATUS); 1442 #ifdef CAS_DEBUG 1443 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1444 #endif 1445 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1446 device_xname(sc->sc_dev), (status>>19), bits)); 1447 1448 if ((status & CAS_INTR_PCS) != 0) 1449 r |= cas_pint(sc); 1450 1451 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1452 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1453 r |= cas_eint(sc, status); 1454 1455 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1456 r |= cas_tint(sc, status); 1457 1458 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1459 r |= cas_rint(sc); 1460 1461 /* We should eventually do more than just print out error stats. */ 1462 if (status & CAS_INTR_TX_MAC) { 1463 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1464 #ifdef CAS_DEBUG 1465 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1466 printf("%s: MAC tx fault, status %x\n", 1467 device_xname(sc->sc_dev), txstat); 1468 #endif 1469 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1470 cas_init(ifp); 1471 } 1472 if (status & CAS_INTR_RX_MAC) { 1473 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1474 #ifdef CAS_DEBUG 1475 if (rxstat & ~CAS_MAC_RX_DONE) 1476 printf("%s: MAC rx fault, status %x\n", 1477 device_xname(sc->sc_dev), rxstat); 1478 #endif 1479 /* 1480 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1481 * due to a silicon bug so handle them silently. 1482 */ 1483 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1484 ifp->if_ierrors++; 1485 cas_init(ifp); 1486 } 1487 #ifdef CAS_DEBUG 1488 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1489 printf("%s: MAC rx fault, status %x\n", 1490 device_xname(sc->sc_dev), rxstat); 1491 #endif 1492 } 1493 rnd_add_uint32(&sc->rnd_source, status); 1494 return (r); 1495 } 1496 1497 1498 void 1499 cas_watchdog(struct ifnet *ifp) 1500 { 1501 struct cas_softc *sc = ifp->if_softc; 1502 1503 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1504 "CAS_MAC_RX_CONFIG %x\n", 1505 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1506 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1507 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1508 1509 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1510 ++ifp->if_oerrors; 1511 1512 /* Try to get more packets going. */ 1513 cas_init(ifp); 1514 } 1515 1516 /* 1517 * Initialize the MII Management Interface 1518 */ 1519 void 1520 cas_mifinit(struct cas_softc *sc) 1521 { 1522 bus_space_tag_t t = sc->sc_memt; 1523 bus_space_handle_t mif = sc->sc_memh; 1524 1525 /* Configure the MIF in frame mode */ 1526 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1527 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1528 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1529 } 1530 1531 /* 1532 * MII interface 1533 * 1534 * The Cassini MII interface supports at least three different operating modes: 1535 * 1536 * Bitbang mode is implemented using data, clock and output enable registers. 1537 * 1538 * Frame mode is implemented by loading a complete frame into the frame 1539 * register and polling the valid bit for completion. 1540 * 1541 * Polling mode uses the frame register but completion is indicated by 1542 * an interrupt. 1543 * 1544 */ 1545 int 1546 cas_mii_readreg(device_t self, int phy, int reg) 1547 { 1548 struct cas_softc *sc = device_private(self); 1549 bus_space_tag_t t = sc->sc_memt; 1550 bus_space_handle_t mif = sc->sc_memh; 1551 int n; 1552 u_int32_t v; 1553 1554 #ifdef CAS_DEBUG 1555 if (sc->sc_debug) 1556 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1557 #endif 1558 1559 /* Construct the frame command */ 1560 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1561 CAS_MIF_FRAME_READ; 1562 1563 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1564 for (n = 0; n < 100; n++) { 1565 DELAY(1); 1566 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1567 if (v & CAS_MIF_FRAME_TA0) 1568 return (v & CAS_MIF_FRAME_DATA); 1569 } 1570 1571 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1572 return (0); 1573 } 1574 1575 void 1576 cas_mii_writereg(device_t self, int phy, int reg, int val) 1577 { 1578 struct cas_softc *sc = device_private(self); 1579 bus_space_tag_t t = sc->sc_memt; 1580 bus_space_handle_t mif = sc->sc_memh; 1581 int n; 1582 u_int32_t v; 1583 1584 #ifdef CAS_DEBUG 1585 if (sc->sc_debug) 1586 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1587 phy, reg, val); 1588 #endif 1589 1590 /* Construct the frame command */ 1591 v = CAS_MIF_FRAME_WRITE | 1592 (phy << CAS_MIF_PHY_SHIFT) | 1593 (reg << CAS_MIF_REG_SHIFT) | 1594 (val & CAS_MIF_FRAME_DATA); 1595 1596 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1597 for (n = 0; n < 100; n++) { 1598 DELAY(1); 1599 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1600 if (v & CAS_MIF_FRAME_TA0) 1601 return; 1602 } 1603 1604 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1605 } 1606 1607 void 1608 cas_mii_statchg(struct ifnet *ifp) 1609 { 1610 struct cas_softc *sc = ifp->if_softc; 1611 #ifdef CAS_DEBUG 1612 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1613 #endif 1614 bus_space_tag_t t = sc->sc_memt; 1615 bus_space_handle_t mac = sc->sc_memh; 1616 u_int32_t v; 1617 1618 #ifdef CAS_DEBUG 1619 if (sc->sc_debug) 1620 printf("cas_mii_statchg: status change: phy = %d\n", 1621 sc->sc_phys[instance]); 1622 #endif 1623 1624 /* Set tx full duplex options */ 1625 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1626 delay(10000); /* reg must be cleared and delay before changing. */ 1627 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1628 CAS_MAC_TX_ENABLE; 1629 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1630 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1631 } 1632 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1633 1634 /* XIF Configuration */ 1635 v = CAS_MAC_XIF_TX_MII_ENA; 1636 v |= CAS_MAC_XIF_LINK_LED; 1637 1638 /* MII needs echo disable if half duplex. */ 1639 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1640 /* turn on full duplex LED */ 1641 v |= CAS_MAC_XIF_FDPLX_LED; 1642 else 1643 /* half duplex -- disable echo */ 1644 v |= CAS_MAC_XIF_ECHO_DISABL; 1645 1646 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1647 case IFM_1000_T: /* Gigabit using GMII interface */ 1648 case IFM_1000_SX: 1649 v |= CAS_MAC_XIF_GMII_MODE; 1650 break; 1651 default: 1652 v &= ~CAS_MAC_XIF_GMII_MODE; 1653 } 1654 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1655 } 1656 1657 int 1658 cas_pcs_readreg(device_t self, int phy, int reg) 1659 { 1660 struct cas_softc *sc = device_private(self); 1661 bus_space_tag_t t = sc->sc_memt; 1662 bus_space_handle_t pcs = sc->sc_memh; 1663 1664 #ifdef CAS_DEBUG 1665 if (sc->sc_debug) 1666 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1667 #endif 1668 1669 if (phy != CAS_PHYAD_EXTERNAL) 1670 return (0); 1671 1672 switch (reg) { 1673 case MII_BMCR: 1674 reg = CAS_MII_CONTROL; 1675 break; 1676 case MII_BMSR: 1677 reg = CAS_MII_STATUS; 1678 break; 1679 case MII_ANAR: 1680 reg = CAS_MII_ANAR; 1681 break; 1682 case MII_ANLPAR: 1683 reg = CAS_MII_ANLPAR; 1684 break; 1685 case MII_EXTSR: 1686 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1687 default: 1688 return (0); 1689 } 1690 1691 return bus_space_read_4(t, pcs, reg); 1692 } 1693 1694 void 1695 cas_pcs_writereg(device_t self, int phy, int reg, int val) 1696 { 1697 struct cas_softc *sc = device_private(self); 1698 bus_space_tag_t t = sc->sc_memt; 1699 bus_space_handle_t pcs = sc->sc_memh; 1700 int reset = 0; 1701 1702 #ifdef CAS_DEBUG 1703 if (sc->sc_debug) 1704 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1705 phy, reg, val); 1706 #endif 1707 1708 if (phy != CAS_PHYAD_EXTERNAL) 1709 return; 1710 1711 if (reg == MII_ANAR) 1712 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1713 1714 switch (reg) { 1715 case MII_BMCR: 1716 reset = (val & CAS_MII_CONTROL_RESET); 1717 reg = CAS_MII_CONTROL; 1718 break; 1719 case MII_BMSR: 1720 reg = CAS_MII_STATUS; 1721 break; 1722 case MII_ANAR: 1723 reg = CAS_MII_ANAR; 1724 break; 1725 case MII_ANLPAR: 1726 reg = CAS_MII_ANLPAR; 1727 break; 1728 default: 1729 return; 1730 } 1731 1732 bus_space_write_4(t, pcs, reg, val); 1733 1734 if (reset) 1735 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1736 1737 if (reg == CAS_MII_ANAR || reset) 1738 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1739 CAS_MII_CONFIG_ENABLE); 1740 } 1741 1742 int 1743 cas_mediachange(struct ifnet *ifp) 1744 { 1745 struct cas_softc *sc = ifp->if_softc; 1746 struct mii_data *mii = &sc->sc_mii; 1747 1748 if (mii->mii_instance) { 1749 struct mii_softc *miisc; 1750 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1751 mii_phy_reset(miisc); 1752 } 1753 1754 return (mii_mediachg(&sc->sc_mii)); 1755 } 1756 1757 void 1758 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1759 { 1760 struct cas_softc *sc = ifp->if_softc; 1761 1762 mii_pollstat(&sc->sc_mii); 1763 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1764 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1765 } 1766 1767 /* 1768 * Process an ioctl request. 1769 */ 1770 int 1771 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1772 { 1773 struct cas_softc *sc = ifp->if_softc; 1774 int s, error = 0; 1775 1776 s = splnet(); 1777 1778 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1779 error = 0; 1780 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1781 ; 1782 else if (ifp->if_flags & IFF_RUNNING) { 1783 /* 1784 * Multicast list has changed; set the hardware filter 1785 * accordingly. 1786 */ 1787 cas_iff(sc); 1788 } 1789 } 1790 1791 splx(s); 1792 return (error); 1793 } 1794 1795 static bool 1796 cas_suspend(device_t self, const pmf_qual_t *qual) 1797 { 1798 struct cas_softc *sc = device_private(self); 1799 bus_space_tag_t t = sc->sc_memt; 1800 bus_space_handle_t h = sc->sc_memh; 1801 1802 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1803 if (sc->sc_ih != NULL) { 1804 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1805 sc->sc_ih = NULL; 1806 } 1807 1808 return true; 1809 } 1810 1811 static bool 1812 cas_resume(device_t self, const pmf_qual_t *qual) 1813 { 1814 struct cas_softc *sc = device_private(self); 1815 1816 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1817 } 1818 1819 static bool 1820 cas_estintr(struct cas_softc *sc, int what) 1821 { 1822 bus_space_tag_t t = sc->sc_memt; 1823 bus_space_handle_t h = sc->sc_memh; 1824 const char *intrstr = NULL; 1825 1826 /* PCI interrupts */ 1827 if (what & CAS_INTR_PCI) { 1828 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle); 1829 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1830 IPL_NET, cas_intr, sc); 1831 if (sc->sc_ih == NULL) { 1832 aprint_error_dev(sc->sc_dev, 1833 "unable to establish interrupt"); 1834 if (intrstr != NULL) 1835 aprint_error(" at %s", intrstr); 1836 aprint_error("\n"); 1837 return false; 1838 } 1839 1840 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1841 } 1842 1843 /* Interrupt register */ 1844 if (what & CAS_INTR_REG) { 1845 bus_space_write_4(t, h, CAS_INTMASK, 1846 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1847 CAS_INTR_TX_TAG_ERR| 1848 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1849 CAS_INTR_RX_TAG_ERR| 1850 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1851 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1852 CAS_INTR_BERR)); 1853 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1854 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1855 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1856 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1857 } 1858 return true; 1859 } 1860 1861 bool 1862 cas_shutdown(device_t self, int howto) 1863 { 1864 struct cas_softc *sc = device_private(self); 1865 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1866 1867 cas_stop(ifp, 1); 1868 1869 return true; 1870 } 1871 1872 void 1873 cas_iff(struct cas_softc *sc) 1874 { 1875 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1876 struct ethercom *ec = &sc->sc_ethercom; 1877 struct ether_multi *enm; 1878 struct ether_multistep step; 1879 bus_space_tag_t t = sc->sc_memt; 1880 bus_space_handle_t h = sc->sc_memh; 1881 u_int32_t crc, hash[16], rxcfg; 1882 int i; 1883 1884 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1885 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1886 CAS_MAC_RX_PROMISC_GRP); 1887 ifp->if_flags &= ~IFF_ALLMULTI; 1888 1889 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1890 ifp->if_flags |= IFF_ALLMULTI; 1891 if (ifp->if_flags & IFF_PROMISC) 1892 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1893 else 1894 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1895 } else { 1896 /* 1897 * Set up multicast address filter by passing all multicast 1898 * addresses through a crc generator, and then using the 1899 * high order 8 bits as an index into the 256 bit logical 1900 * address filter. The high order 4 bits selects the word, 1901 * while the other 4 bits select the bit within the word 1902 * (where bit 0 is the MSB). 1903 */ 1904 1905 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1906 1907 /* Clear hash table */ 1908 for (i = 0; i < 16; i++) 1909 hash[i] = 0; 1910 1911 ETHER_FIRST_MULTI(step, ec, enm); 1912 while (enm != NULL) { 1913 crc = ether_crc32_le(enm->enm_addrlo, 1914 ETHER_ADDR_LEN); 1915 1916 /* Just want the 8 most significant bits. */ 1917 crc >>= 24; 1918 1919 /* Set the corresponding bit in the filter. */ 1920 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1921 1922 ETHER_NEXT_MULTI(step, enm); 1923 } 1924 1925 /* Now load the hash table into the chip (if we are using it) */ 1926 for (i = 0; i < 16; i++) { 1927 bus_space_write_4(t, h, 1928 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1929 hash[i]); 1930 } 1931 } 1932 1933 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1934 } 1935 1936 int 1937 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1938 { 1939 u_int64_t flags; 1940 u_int32_t cur, frag, i; 1941 bus_dmamap_t map; 1942 1943 cur = frag = *bixp; 1944 map = sc->sc_txd[cur].sd_map; 1945 1946 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1947 BUS_DMA_NOWAIT) != 0) { 1948 return (ENOBUFS); 1949 } 1950 1951 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1952 bus_dmamap_unload(sc->sc_dmatag, map); 1953 return (ENOBUFS); 1954 } 1955 1956 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1957 BUS_DMASYNC_PREWRITE); 1958 1959 for (i = 0; i < map->dm_nsegs; i++) { 1960 sc->sc_txdescs[frag].cd_addr = 1961 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1962 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1963 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1964 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1965 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1966 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1967 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1968 BUS_DMASYNC_PREWRITE); 1969 cur = frag; 1970 if (++frag == CAS_NTXDESC) 1971 frag = 0; 1972 } 1973 1974 sc->sc_tx_cnt += map->dm_nsegs; 1975 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1976 sc->sc_txd[cur].sd_map = map; 1977 sc->sc_txd[cur].sd_mbuf = mhead; 1978 1979 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1980 1981 *bixp = frag; 1982 1983 /* sync descriptors */ 1984 1985 return (0); 1986 } 1987 1988 /* 1989 * Transmit interrupt. 1990 */ 1991 int 1992 cas_tint(struct cas_softc *sc, u_int32_t status) 1993 { 1994 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1995 struct cas_sxd *sd; 1996 u_int32_t cons, comp; 1997 1998 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 1999 cons = sc->sc_tx_cons; 2000 while (cons != comp) { 2001 sd = &sc->sc_txd[cons]; 2002 if (sd->sd_mbuf != NULL) { 2003 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2004 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2005 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2006 m_freem(sd->sd_mbuf); 2007 sd->sd_mbuf = NULL; 2008 ifp->if_opackets++; 2009 } 2010 sc->sc_tx_cnt--; 2011 if (++cons == CAS_NTXDESC) 2012 cons = 0; 2013 } 2014 sc->sc_tx_cons = cons; 2015 2016 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2017 ifp->if_flags &= ~IFF_OACTIVE; 2018 if (sc->sc_tx_cnt == 0) 2019 ifp->if_timer = 0; 2020 2021 cas_start(ifp); 2022 2023 return (1); 2024 } 2025 2026 void 2027 cas_start(struct ifnet *ifp) 2028 { 2029 struct cas_softc *sc = ifp->if_softc; 2030 struct mbuf *m; 2031 u_int32_t bix; 2032 2033 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2034 return; 2035 2036 bix = sc->sc_tx_prod; 2037 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2038 IFQ_POLL(&ifp->if_snd, m); 2039 if (m == NULL) 2040 break; 2041 2042 /* 2043 * If BPF is listening on this interface, let it see the 2044 * packet before we commit it to the wire. 2045 */ 2046 bpf_mtap(ifp, m); 2047 2048 /* 2049 * Encapsulate this packet and start it going... 2050 * or fail... 2051 */ 2052 if (cas_encap(sc, m, &bix)) { 2053 ifp->if_flags |= IFF_OACTIVE; 2054 break; 2055 } 2056 2057 IFQ_DEQUEUE(&ifp->if_snd, m); 2058 ifp->if_timer = 5; 2059 } 2060 2061 sc->sc_tx_prod = bix; 2062 } 2063 2064 MODULE(MODULE_CLASS_DRIVER, if_cas, "pci"); 2065 2066 #ifdef _MODULE 2067 #include "ioconf.c" 2068 #endif 2069 2070 static int 2071 if_cas_modcmd(modcmd_t cmd, void *opaque) 2072 { 2073 int error = 0; 2074 2075 switch (cmd) { 2076 case MODULE_CMD_INIT: 2077 #ifdef _MODULE 2078 error = config_init_component(cfdriver_ioconf_cas, 2079 cfattach_ioconf_cas, cfdata_ioconf_cas); 2080 #endif 2081 return error; 2082 case MODULE_CMD_FINI: 2083 #ifdef _MODULE 2084 error = config_fini_component(cfdriver_ioconf_cas, 2085 cfattach_ioconf_cas, cfdata_ioconf_cas); 2086 #endif 2087 return error; 2088 default: 2089 return ENOTTY; 2090 } 2091 } 2092