1 /* $NetBSD: if_cas.c,v 1.44 2020/09/15 08:33:40 mrg Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.44 2020/09/15 08:33:40 mrg Exp $"); 48 49 #ifndef _MODULE 50 #include "opt_inet.h" 51 #endif 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/module.h> 65 66 #include <machine/endian.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #include <net/bpf.h> 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 #include <sys/rndsource.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/mii_bitbang.h> 91 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcidevs.h> 95 #include <prop/proplib.h> 96 97 #include <dev/pci/if_casreg.h> 98 #include <dev/pci/if_casvar.h> 99 100 #define TRIES 10000 101 102 static bool cas_estintr(struct cas_softc *sc, int); 103 bool cas_shutdown(device_t, int); 104 static bool cas_suspend(device_t, const pmf_qual_t *); 105 static bool cas_resume(device_t, const pmf_qual_t *); 106 static int cas_detach(device_t, int); 107 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 108 109 int cas_match(device_t, cfdata_t, void *); 110 void cas_attach(device_t, device_t, void *); 111 112 113 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 114 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 115 DVF_DETACH_SHUTDOWN); 116 117 int cas_pci_readvpd(struct cas_softc *, struct pci_attach_args *, uint8_t *); 118 119 void cas_config(struct cas_softc *, const uint8_t *); 120 void cas_start(struct ifnet *); 121 void cas_stop(struct ifnet *, int); 122 int cas_ioctl(struct ifnet *, u_long, void *); 123 void cas_tick(void *); 124 void cas_watchdog(struct ifnet *); 125 int cas_init(struct ifnet *); 126 void cas_init_regs(struct cas_softc *); 127 int cas_ringsize(int); 128 int cas_cringsize(int); 129 int cas_meminit(struct cas_softc *); 130 void cas_mifinit(struct cas_softc *); 131 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 132 uint32_t, uint32_t); 133 void cas_reset(struct cas_softc *); 134 int cas_reset_rx(struct cas_softc *); 135 int cas_reset_tx(struct cas_softc *); 136 int cas_disable_rx(struct cas_softc *); 137 int cas_disable_tx(struct cas_softc *); 138 void cas_rxdrain(struct cas_softc *); 139 int cas_add_rxbuf(struct cas_softc *, int); 140 void cas_iff(struct cas_softc *); 141 int cas_encap(struct cas_softc *, struct mbuf *, uint32_t *); 142 143 /* MII methods & callbacks */ 144 int cas_mii_readreg(device_t, int, int, uint16_t*); 145 int cas_mii_writereg(device_t, int, int, uint16_t); 146 void cas_mii_statchg(struct ifnet *); 147 int cas_pcs_readreg(device_t, int, int, uint16_t *); 148 int cas_pcs_writereg(device_t, int, int, uint16_t); 149 150 int cas_mediachange(struct ifnet *); 151 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 152 153 int cas_eint(struct cas_softc *, u_int); 154 int cas_rint(struct cas_softc *); 155 int cas_tint(struct cas_softc *, uint32_t); 156 int cas_pint(struct cas_softc *); 157 int cas_intr(void *); 158 159 #ifdef CAS_DEBUG 160 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 161 printf x 162 #else 163 #define DPRINTF(sc, x) /* nothing */ 164 #endif 165 166 static const struct cas_pci_dev { 167 uint16_t cpd_vendor; 168 uint16_t cpd_device; 169 int cpd_variant; 170 } cas_pci_devlist[] = { 171 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_CASSINI, CAS_CAS }, 172 { PCI_VENDOR_NS, PCI_PRODUCT_NS_SATURN, CAS_SATURN }, 173 { 0, 0, 0 } 174 }; 175 176 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 177 #define CAS_PHY_INTERFACE "phy-interface" 178 #define CAS_PHY_TYPE "phy-type" 179 #define CAS_PHY_TYPE_PCS "pcs" 180 181 int 182 cas_match(device_t parent, cfdata_t cf, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 int i; 186 187 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 188 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 189 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) 190 return 1; 191 } 192 193 return 0; 194 } 195 196 #define PROMHDR_PTR_DATA 0x18 197 #define PROMDATA_PTR_VPD 0x08 198 #define PROMDATA_DATA2 0x0a 199 200 static const uint8_t cas_promhdr[] = { 0x55, 0xaa }; 201 static const uint8_t cas_promdat[] = { 202 'P', 'C', 'I', 'R', 203 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 204 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 205 }; 206 static const uint8_t cas_promdat_ns[] = { 207 'P', 'C', 'I', 'R', 208 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 209 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 210 }; 211 212 static const uint8_t cas_promdat2[] = { 213 0x18, 0x00, /* structure length */ 214 0x00, /* structure revision */ 215 0x00, /* interface revision */ 216 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 217 PCI_CLASS_NETWORK /* class code */ 218 }; 219 220 #define CAS_LMA_MAXNUM 4 221 int 222 cas_pci_readvpd(struct cas_softc *sc, struct pci_attach_args *pa, 223 uint8_t *enaddr) 224 { 225 struct pci_vpd_largeres *res; 226 struct pci_vpd *vpd; 227 bus_space_handle_t romh; 228 bus_space_tag_t romt; 229 bus_size_t romsize = 0; 230 uint8_t enaddrs[CAS_LMA_MAXNUM][ETHER_ADDR_LEN]; 231 bool pcs[4] = {false, false, false, false}; 232 uint8_t buf[32], *desc; 233 pcireg_t address; 234 int dataoff, vpdoff, len, lma = 0, phy = 0; 235 int i, rv = -1; 236 237 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 238 &romt, &romh, NULL, &romsize)) 239 return (-1); 240 241 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 242 address |= PCI_MAPREG_ROM_ENABLE; 243 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 244 245 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 246 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 247 goto fail; 248 249 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 250 if (dataoff < 0x1c) 251 goto fail; 252 253 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 254 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 255 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 256 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 257 goto fail; 258 259 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 260 if (vpdoff < 0x1c) 261 goto fail; 262 263 next: 264 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 265 if (!PCI_VPDRES_ISLARGE(buf[0])) 266 goto fail; 267 268 res = (struct pci_vpd_largeres *)buf; 269 vpdoff += sizeof(*res); 270 271 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 272 switch (PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 273 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 274 /* Skip identifier string. */ 275 vpdoff += len; 276 goto next; 277 278 case PCI_VPDRES_TYPE_VPD: 279 #ifdef CAS_DEBUG 280 printf("\n"); 281 for (i = 0; i < len; i++) { 282 uint8_t byte; 283 if (i % 16 == 0) 284 printf("%04x :", i); 285 byte = bus_space_read_1(romt, romh, vpdoff + i); 286 printf(" %02x", byte); 287 if (i % 16 == 15) 288 printf("\n"); 289 } 290 printf("\n"); 291 #endif 292 293 while (len > 0) { 294 bus_space_read_region_1(romt, romh, vpdoff, 295 buf, sizeof(buf)); 296 297 vpd = (struct pci_vpd *)buf; 298 vpdoff += sizeof(*vpd) + vpd->vpd_len; 299 len -= sizeof(*vpd) + vpd->vpd_len; 300 301 /* 302 * We're looking for an "Enhanced" VPD... 303 */ 304 if (vpd->vpd_key0 != 'Z') 305 continue; 306 307 desc = buf + sizeof(*vpd); 308 309 /* 310 * ...which is an instance property... 311 */ 312 if (desc[0] != 'I') 313 continue; 314 desc += 3; 315 316 if (desc[0] == 'B' || desc[1] == ETHER_ADDR_LEN) { 317 /* 318 * ...that's a byte array with the proper 319 * length for a MAC address... 320 */ 321 desc += 2; 322 323 /* 324 * ...named "local-mac-address". 325 */ 326 if (strcmp(desc, CAS_LOCAL_MAC_ADDRESS) != 0) 327 continue; 328 desc += sizeof(CAS_LOCAL_MAC_ADDRESS); 329 330 if (lma == CAS_LMA_MAXNUM) 331 continue; 332 333 memcpy(enaddrs[lma], desc, ETHER_ADDR_LEN); 334 lma++; 335 rv = 0; 336 continue; 337 } else if (desc[0] == 'S') { 338 size_t k; 339 340 /* String */ 341 desc += 2; 342 #ifdef CAS_DEBUG 343 /* ...named "pcs". */ 344 printf("STR: \"%s\"\n", desc); 345 if (strcmp(desc, CAS_PHY_TYPE_PCS) != 0) 346 continue; 347 desc += sizeof(CAS_PHY_TYPE_PCS); 348 printf("STR: \"%s\"\n", desc); 349 #endif 350 /* ...named "phy-interface" or "phy-type". */ 351 if (strcmp(desc, CAS_PHY_INTERFACE) == 0) 352 k = sizeof(CAS_PHY_INTERFACE); 353 else if (strcmp(desc, CAS_PHY_TYPE) == 0) 354 k = sizeof(CAS_PHY_TYPE); 355 else 356 continue; 357 358 desc += k; 359 #ifdef CAS_DEBUG 360 printf("STR: \"%s\"\n", desc); 361 #endif 362 if (strcmp(desc, CAS_PHY_TYPE_PCS) == 0) 363 pcs[phy] = true; 364 phy++; 365 continue; 366 } 367 } 368 break; 369 370 default: 371 goto fail; 372 } 373 374 /* 375 * Multi port card has bridge chip. The device number is fixed: 376 * e.g. 377 * p0: 005:00:0 378 * p1: 005:01:0 379 * p2: 006:02:0 380 * p3: 006:03:0 381 */ 382 if (enaddr != 0) { 383 i = 0; 384 if ((lma > 1) && (pa->pa_device < CAS_LMA_MAXNUM) 385 && (pa->pa_device < lma)) 386 i = pa->pa_device; 387 memcpy(enaddr, enaddrs[i], ETHER_ADDR_LEN); 388 } 389 if (pcs[pa->pa_device]) 390 sc->sc_flags |= CAS_SERDES; 391 fail: 392 if (romsize != 0) 393 bus_space_unmap(romt, romh, romsize); 394 395 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 396 address &= ~PCI_MAPREG_ROM_ENABLE; 397 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 398 399 return (rv); 400 } 401 402 void 403 cas_attach(device_t parent, device_t self, void *aux) 404 { 405 struct pci_attach_args *pa = aux; 406 struct cas_softc *sc = device_private(self); 407 int i; 408 prop_data_t data; 409 uint8_t enaddr[ETHER_ADDR_LEN]; 410 411 sc->sc_dev = self; 412 pci_aprint_devinfo(pa, NULL); 413 sc->sc_rev = PCI_REVISION(pa->pa_class); 414 415 if (pci_dma64_available(pa)) 416 sc->sc_dmatag = pa->pa_dmat64; 417 else 418 sc->sc_dmatag = pa->pa_dmat; 419 420 sc->sc_variant = CAS_UNKNOWN; 421 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 422 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 423 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) { 424 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 425 break; 426 } 427 } 428 aprint_debug_dev(sc->sc_dev, "variant = %d\n", sc->sc_variant); 429 if (sc->sc_variant == CAS_UNKNOWN) { 430 aprint_error_dev(sc->sc_dev, "unknown adaptor\n"); 431 return; 432 } 433 434 #define PCI_CAS_BASEADDR 0x10 435 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 436 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 437 aprint_error_dev(sc->sc_dev, 438 "unable to map device registers\n"); 439 return; 440 } 441 442 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 443 "mac-address")) != NULL) 444 memcpy(enaddr, prop_data_value(data), ETHER_ADDR_LEN); 445 if (cas_pci_readvpd(sc, pa, (data == NULL) ? enaddr : 0) != 0) { 446 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 447 memset(enaddr, 0, sizeof(enaddr)); 448 } 449 450 sc->sc_burst = 16; /* XXX */ 451 452 sc->sc_att_stage = CAS_ATT_BACKEND_0; 453 454 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 455 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 456 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 457 return; 458 } 459 sc->sc_pc = pa->pa_pc; 460 if (!cas_estintr(sc, CAS_INTR_PCI)) { 461 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 462 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 463 return; 464 } 465 466 sc->sc_att_stage = CAS_ATT_BACKEND_1; 467 468 /* 469 * call the main configure 470 */ 471 cas_config(sc, enaddr); 472 473 if (pmf_device_register1(sc->sc_dev, 474 cas_suspend, cas_resume, cas_shutdown)) 475 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 476 else 477 aprint_error_dev(sc->sc_dev, 478 "could not establish power handlers\n"); 479 480 sc->sc_att_stage = CAS_ATT_FINISHED; 481 /*FALLTHROUGH*/ 482 } 483 484 /* 485 * cas_config: 486 * 487 * Attach a Cassini interface to the system. 488 */ 489 void 490 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 491 { 492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 493 struct mii_data *mii = &sc->sc_mii; 494 struct mii_softc *child; 495 uint32_t reg; 496 int i, error; 497 498 /* Make sure the chip is stopped. */ 499 ifp->if_softc = sc; 500 cas_reset(sc); 501 502 /* 503 * Allocate the control data structures, and create and load the 504 * DMA map for it. 505 */ 506 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 507 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 508 1, &sc->sc_cdnseg, 0)) != 0) { 509 aprint_error_dev(sc->sc_dev, 510 "unable to allocate control data, error = %d\n", 511 error); 512 cas_partial_detach(sc, CAS_ATT_0); 513 } 514 515 /* XXX should map this in with correct endianness */ 516 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, 517 sc->sc_cdnseg, sizeof(struct cas_control_data), 518 (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) { 519 aprint_error_dev(sc->sc_dev, 520 "unable to map control data, error = %d\n", error); 521 cas_partial_detach(sc, CAS_ATT_1); 522 } 523 524 if ((error = bus_dmamap_create(sc->sc_dmatag, 525 sizeof(struct cas_control_data), 1, 526 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 527 aprint_error_dev(sc->sc_dev, 528 "unable to create control data DMA map, error = %d\n", 529 error); 530 cas_partial_detach(sc, CAS_ATT_2); 531 } 532 533 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 534 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 535 0)) != 0) { 536 aprint_error_dev(sc->sc_dev, 537 "unable to load control data DMA map, error = %d\n", 538 error); 539 cas_partial_detach(sc, CAS_ATT_3); 540 } 541 542 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 543 544 /* 545 * Create the receive buffer DMA maps. 546 */ 547 for (i = 0; i < CAS_NRXDESC; i++) { 548 bus_dma_segment_t seg; 549 char *kva; 550 int rseg; 551 552 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 553 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 554 aprint_error_dev(sc->sc_dev, 555 "unable to alloc rx DMA mem %d, error = %d\n", 556 i, error); 557 cas_partial_detach(sc, CAS_ATT_5); 558 } 559 sc->sc_rxsoft[i].rxs_dmaseg = seg; 560 561 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 562 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 563 aprint_error_dev(sc->sc_dev, 564 "unable to alloc rx DMA mem %d, error = %d\n", 565 i, error); 566 cas_partial_detach(sc, CAS_ATT_5); 567 } 568 sc->sc_rxsoft[i].rxs_kva = kva; 569 570 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 571 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 aprint_error_dev(sc->sc_dev, 573 "unable to create rx DMA map %d, error = %d\n", 574 i, error); 575 cas_partial_detach(sc, CAS_ATT_5); 576 } 577 578 if ((error = bus_dmamap_load(sc->sc_dmatag, 579 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 580 BUS_DMA_NOWAIT)) != 0) { 581 aprint_error_dev(sc->sc_dev, 582 "unable to load rx DMA map %d, error = %d\n", 583 i, error); 584 cas_partial_detach(sc, CAS_ATT_5); 585 } 586 } 587 588 /* 589 * Create the transmit buffer DMA maps. 590 */ 591 for (i = 0; i < CAS_NTXDESC; i++) { 592 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 593 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 594 &sc->sc_txd[i].sd_map)) != 0) { 595 aprint_error_dev(sc->sc_dev, 596 "unable to create tx DMA map %d, error = %d\n", 597 i, error); 598 cas_partial_detach(sc, CAS_ATT_6); 599 } 600 sc->sc_txd[i].sd_mbuf = NULL; 601 } 602 603 /* 604 * From this point forward, the attachment cannot fail. A failure 605 * before this point releases all resources that may have been 606 * allocated. 607 */ 608 609 /* Announce ourselves. */ 610 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 611 ether_sprintf(enaddr)); 612 aprint_naive(": Ethernet controller\n"); 613 614 /* Get RX FIFO size */ 615 sc->sc_rxfifosize = 16 * 1024; 616 617 /* Initialize ifnet structure. */ 618 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 619 ifp->if_softc = sc; 620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 621 ifp->if_start = cas_start; 622 ifp->if_ioctl = cas_ioctl; 623 ifp->if_watchdog = cas_watchdog; 624 ifp->if_stop = cas_stop; 625 ifp->if_init = cas_init; 626 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 627 IFQ_SET_READY(&ifp->if_snd); 628 629 /* Initialize ifmedia structures and MII info */ 630 mii->mii_ifp = ifp; 631 mii->mii_readreg = cas_mii_readreg; 632 mii->mii_writereg = cas_mii_writereg; 633 mii->mii_statchg = cas_mii_statchg; 634 635 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 636 sc->sc_ethercom.ec_mii = mii; 637 638 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 639 640 cas_mifinit(sc); 641 642 if (sc->sc_mif_config & (CAS_MIF_CONFIG_MDI1 | CAS_MIF_CONFIG_MDI0)) { 643 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 644 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 645 bus_space_write_4(sc->sc_memt, sc->sc_memh, 646 CAS_MIF_CONFIG, sc->sc_mif_config); 647 } 648 /* Enable/unfreeze the GMII pins of Saturn. */ 649 if (sc->sc_variant == CAS_SATURN) { 650 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 651 CAS_SATURN_PCFG) & ~CAS_SATURN_PCFG_FSI; 652 if ((sc->sc_mif_config & CAS_MIF_CONFIG_MDI0) != 0) 653 reg |= CAS_SATURN_PCFG_FSI; 654 bus_space_write_4(sc->sc_memt, sc->sc_memh, 655 CAS_SATURN_PCFG, reg); 656 /* Read to flush */ 657 bus_space_read_4(sc->sc_memt, sc->sc_memh, 658 CAS_SATURN_PCFG); 659 DELAY(10000); 660 } 661 } 662 663 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 664 MII_OFFSET_ANY, 0); 665 666 child = LIST_FIRST(&mii->mii_phys); 667 if (child == NULL && 668 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0 | CAS_MIF_CONFIG_MDI1)) { 669 /* 670 * Try the external PCS SERDES if we didn't find any 671 * MII devices. 672 */ 673 bus_space_write_4(sc->sc_memt, sc->sc_memh, 674 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 675 676 bus_space_write_4(sc->sc_memt, sc->sc_memh, 677 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 678 679 mii->mii_readreg = cas_pcs_readreg; 680 mii->mii_writereg = cas_pcs_writereg; 681 682 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 683 MII_OFFSET_ANY, MIIF_NOISOLATE); 684 } 685 686 child = LIST_FIRST(&mii->mii_phys); 687 if (child == NULL) { 688 /* No PHY attached */ 689 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 690 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 691 } else { 692 /* 693 * Walk along the list of attached MII devices and 694 * establish an `MII instance' to `phy number' 695 * mapping. We'll use this mapping in media change 696 * requests to determine which phy to use to program 697 * the MIF configuration register. 698 */ 699 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 700 /* 701 * Note: we support just two PHYs: the built-in 702 * internal device and an external on the MII 703 * connector. 704 */ 705 if (child->mii_phy > 1 || child->mii_inst > 1) { 706 aprint_error_dev(sc->sc_dev, 707 "cannot accommodate MII device %s" 708 " at phy %d, instance %d\n", 709 device_xname(child->mii_dev), 710 child->mii_phy, child->mii_inst); 711 continue; 712 } 713 714 sc->sc_phys[child->mii_inst] = child->mii_phy; 715 } 716 717 /* 718 * XXX - we can really do the following ONLY if the 719 * phy indeed has the auto negotiation capability!! 720 */ 721 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 722 } 723 724 /* claim 802.1q capability */ 725 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 726 727 /* Attach the interface. */ 728 if_attach(ifp); 729 if_deferred_start_init(ifp, NULL); 730 ether_ifattach(ifp, enaddr); 731 732 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 733 RND_TYPE_NET, RND_FLAG_DEFAULT); 734 735 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 736 NULL, device_xname(sc->sc_dev), "interrupts"); 737 738 callout_init(&sc->sc_tick_ch, 0); 739 callout_setfunc(&sc->sc_tick_ch, cas_tick, sc); 740 741 return; 742 } 743 744 int 745 cas_detach(device_t self, int flags) 746 { 747 int i; 748 struct cas_softc *sc = device_private(self); 749 bus_space_tag_t t = sc->sc_memt; 750 bus_space_handle_t h = sc->sc_memh; 751 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 752 753 /* 754 * Free any resources we've allocated during the failed attach 755 * attempt. Do this in reverse order and fall through. 756 */ 757 switch (sc->sc_att_stage) { 758 case CAS_ATT_FINISHED: 759 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 760 pmf_device_deregister(self); 761 cas_stop(&sc->sc_ethercom.ec_if, 1); 762 evcnt_detach(&sc->sc_ev_intr); 763 764 rnd_detach_source(&sc->rnd_source); 765 766 ether_ifdetach(ifp); 767 if_detach(ifp); 768 769 callout_destroy(&sc->sc_tick_ch); 770 771 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 772 773 ifmedia_fini(&sc->sc_mii.mii_media); 774 775 /*FALLTHROUGH*/ 776 case CAS_ATT_MII: 777 case CAS_ATT_7: 778 case CAS_ATT_6: 779 for (i = 0; i < CAS_NTXDESC; i++) { 780 if (sc->sc_txd[i].sd_map != NULL) 781 bus_dmamap_destroy(sc->sc_dmatag, 782 sc->sc_txd[i].sd_map); 783 } 784 /*FALLTHROUGH*/ 785 case CAS_ATT_5: 786 for (i = 0; i < CAS_NRXDESC; i++) { 787 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 788 bus_dmamap_unload(sc->sc_dmatag, 789 sc->sc_rxsoft[i].rxs_dmamap); 790 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 791 bus_dmamap_destroy(sc->sc_dmatag, 792 sc->sc_rxsoft[i].rxs_dmamap); 793 if (sc->sc_rxsoft[i].rxs_kva != NULL) 794 bus_dmamem_unmap(sc->sc_dmatag, 795 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 796 /* XXX need to check that bus_dmamem_alloc suceeded 797 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 798 */ 799 bus_dmamem_free(sc->sc_dmatag, 800 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 801 } 802 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 803 /*FALLTHROUGH*/ 804 case CAS_ATT_4: 805 case CAS_ATT_3: 806 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 807 /*FALLTHROUGH*/ 808 case CAS_ATT_2: 809 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 810 sizeof(struct cas_control_data)); 811 /*FALLTHROUGH*/ 812 case CAS_ATT_1: 813 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 814 /*FALLTHROUGH*/ 815 case CAS_ATT_0: 816 sc->sc_att_stage = CAS_ATT_0; 817 /*FALLTHROUGH*/ 818 case CAS_ATT_BACKEND_2: 819 case CAS_ATT_BACKEND_1: 820 if (sc->sc_ih != NULL) { 821 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 822 sc->sc_ih = NULL; 823 } 824 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 825 /*FALLTHROUGH*/ 826 case CAS_ATT_BACKEND_0: 827 break; 828 } 829 return 0; 830 } 831 832 static void 833 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 834 { 835 cfattach_t ca = device_cfattach(sc->sc_dev); 836 837 sc->sc_att_stage = stage; 838 (*ca->ca_detach)(sc->sc_dev, 0); 839 } 840 841 void 842 cas_tick(void *arg) 843 { 844 struct cas_softc *sc = arg; 845 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 846 bus_space_tag_t t = sc->sc_memt; 847 bus_space_handle_t mac = sc->sc_memh; 848 int s; 849 uint32_t v; 850 851 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 852 853 /* unload collisions counters */ 854 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 855 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 856 if_statadd_ref(nsr, if_collisions, v + 857 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 858 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT)); 859 if_statadd_ref(nsr, if_oerrors, v); 860 861 /* read error counters */ 862 if_statadd_ref(nsr, if_ierrors, 863 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 864 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 865 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 866 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL)); 867 868 IF_STAT_PUTREF(ifp); 869 870 /* clear the hardware counters */ 871 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 872 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 873 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 874 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 875 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 876 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 877 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 878 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 879 880 s = splnet(); 881 mii_tick(&sc->sc_mii); 882 splx(s); 883 884 callout_schedule(&sc->sc_tick_ch, hz); 885 } 886 887 int 888 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 889 uint32_t clr, uint32_t set) 890 { 891 int i; 892 uint32_t reg; 893 894 for (i = TRIES; i--; DELAY(100)) { 895 reg = bus_space_read_4(sc->sc_memt, h, r); 896 if ((reg & clr) == 0 && (reg & set) == set) 897 return (1); 898 } 899 900 return (0); 901 } 902 903 void 904 cas_reset(struct cas_softc *sc) 905 { 906 bus_space_tag_t t = sc->sc_memt; 907 bus_space_handle_t h = sc->sc_memh; 908 int s; 909 910 s = splnet(); 911 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 912 cas_reset_rx(sc); 913 cas_reset_tx(sc); 914 915 /* Disable interrupts */ 916 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 917 918 /* Do a full reset */ 919 bus_space_write_4(t, h, CAS_RESET, 920 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 921 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 922 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 923 splx(s); 924 } 925 926 927 /* 928 * cas_rxdrain: 929 * 930 * Drain the receive queue. 931 */ 932 void 933 cas_rxdrain(struct cas_softc *sc) 934 { 935 /* Nothing to do yet. */ 936 } 937 938 /* 939 * Reset the whole thing. 940 */ 941 void 942 cas_stop(struct ifnet *ifp, int disable) 943 { 944 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 945 struct cas_sxd *sd; 946 uint32_t i; 947 948 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 949 950 callout_stop(&sc->sc_tick_ch); 951 952 /* 953 * Mark the interface down and cancel the watchdog timer. 954 */ 955 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 956 ifp->if_timer = 0; 957 958 mii_down(&sc->sc_mii); 959 960 cas_reset_rx(sc); 961 cas_reset_tx(sc); 962 963 /* 964 * Release any queued transmit buffers. 965 */ 966 for (i = 0; i < CAS_NTXDESC; i++) { 967 sd = &sc->sc_txd[i]; 968 if (sd->sd_mbuf != NULL) { 969 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 970 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 971 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 972 m_freem(sd->sd_mbuf); 973 sd->sd_mbuf = NULL; 974 } 975 } 976 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 977 978 if (disable) 979 cas_rxdrain(sc); 980 } 981 982 983 /* 984 * Reset the receiver 985 */ 986 int 987 cas_reset_rx(struct cas_softc *sc) 988 { 989 bus_space_tag_t t = sc->sc_memt; 990 bus_space_handle_t h = sc->sc_memh; 991 992 /* 993 * Resetting while DMA is in progress can cause a bus hang, so we 994 * disable DMA first. 995 */ 996 cas_disable_rx(sc); 997 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 998 /* Wait till it finishes */ 999 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 1000 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 1001 /* Wait 5ms extra. */ 1002 delay(5000); 1003 1004 /* Finally, reset the ERX */ 1005 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 1006 /* Wait till it finishes */ 1007 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 1008 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 1009 return (1); 1010 } 1011 return (0); 1012 } 1013 1014 1015 /* 1016 * Reset the transmitter 1017 */ 1018 int 1019 cas_reset_tx(struct cas_softc *sc) 1020 { 1021 bus_space_tag_t t = sc->sc_memt; 1022 bus_space_handle_t h = sc->sc_memh; 1023 1024 /* 1025 * Resetting while DMA is in progress can cause a bus hang, so we 1026 * disable DMA first. 1027 */ 1028 cas_disable_tx(sc); 1029 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 1030 /* Wait till it finishes */ 1031 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 1032 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 1033 /* Wait 5ms extra. */ 1034 delay(5000); 1035 1036 /* Finally, reset the ETX */ 1037 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 1038 /* Wait till it finishes */ 1039 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 1040 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 1041 return (1); 1042 } 1043 return (0); 1044 } 1045 1046 /* 1047 * Disable receiver. 1048 */ 1049 int 1050 cas_disable_rx(struct cas_softc *sc) 1051 { 1052 bus_space_tag_t t = sc->sc_memt; 1053 bus_space_handle_t h = sc->sc_memh; 1054 uint32_t cfg; 1055 1056 /* Flip the enable bit */ 1057 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1058 cfg &= ~CAS_MAC_RX_ENABLE; 1059 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 1060 1061 /* Wait for it to finish */ 1062 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 1063 } 1064 1065 /* 1066 * Disable transmitter. 1067 */ 1068 int 1069 cas_disable_tx(struct cas_softc *sc) 1070 { 1071 bus_space_tag_t t = sc->sc_memt; 1072 bus_space_handle_t h = sc->sc_memh; 1073 uint32_t cfg; 1074 1075 /* Flip the enable bit */ 1076 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 1077 cfg &= ~CAS_MAC_TX_ENABLE; 1078 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 1079 1080 /* Wait for it to finish */ 1081 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 1082 } 1083 1084 /* 1085 * Initialize interface. 1086 */ 1087 int 1088 cas_meminit(struct cas_softc *sc) 1089 { 1090 int i; 1091 1092 /* 1093 * Initialize the transmit descriptor ring. 1094 */ 1095 for (i = 0; i < CAS_NTXDESC; i++) { 1096 sc->sc_txdescs[i].cd_flags = 0; 1097 sc->sc_txdescs[i].cd_addr = 0; 1098 } 1099 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 1100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1101 1102 /* 1103 * Initialize the receive descriptor and receive job 1104 * descriptor rings. 1105 */ 1106 for (i = 0; i < CAS_NRXDESC; i++) 1107 CAS_INIT_RXDESC(sc, i, i); 1108 sc->sc_rxdptr = 0; 1109 sc->sc_rxptr = 0; 1110 1111 /* 1112 * Initialize the receive completion ring. 1113 */ 1114 for (i = 0; i < CAS_NRXCOMP; i++) { 1115 sc->sc_rxcomps[i].cc_word[0] = 0; 1116 sc->sc_rxcomps[i].cc_word[1] = 0; 1117 sc->sc_rxcomps[i].cc_word[2] = 0; 1118 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1119 CAS_CDRXCSYNC(sc, i, 1120 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1121 } 1122 1123 return (0); 1124 } 1125 1126 int 1127 cas_ringsize(int sz) 1128 { 1129 switch (sz) { 1130 case 32: 1131 return CAS_RING_SZ_32; 1132 case 64: 1133 return CAS_RING_SZ_64; 1134 case 128: 1135 return CAS_RING_SZ_128; 1136 case 256: 1137 return CAS_RING_SZ_256; 1138 case 512: 1139 return CAS_RING_SZ_512; 1140 case 1024: 1141 return CAS_RING_SZ_1024; 1142 case 2048: 1143 return CAS_RING_SZ_2048; 1144 case 4096: 1145 return CAS_RING_SZ_4096; 1146 case 8192: 1147 return CAS_RING_SZ_8192; 1148 default: 1149 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1150 sz); 1151 return CAS_RING_SZ_32; 1152 } 1153 } 1154 1155 int 1156 cas_cringsize(int sz) 1157 { 1158 int i; 1159 1160 for (i = 0; i < 9; i++) 1161 if (sz == (128 << i)) 1162 return i; 1163 1164 aprint_error("cas: invalid completion ring size %d\n", sz); 1165 return 128; 1166 } 1167 1168 /* 1169 * Initialization of interface; set up initialization block 1170 * and transmit/receive descriptor rings. 1171 */ 1172 int 1173 cas_init(struct ifnet *ifp) 1174 { 1175 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1176 bus_space_tag_t t = sc->sc_memt; 1177 bus_space_handle_t h = sc->sc_memh; 1178 int s; 1179 u_int max_frame_size; 1180 uint32_t v; 1181 1182 s = splnet(); 1183 1184 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1185 /* 1186 * Initialization sequence. The numbered steps below correspond 1187 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1188 * Channel Engine manual (part of the PCIO manual). 1189 * See also the STP2002-STQ document from Sun Microsystems. 1190 */ 1191 1192 /* step 1 & 2. Reset the Ethernet Channel */ 1193 cas_stop(ifp, 0); 1194 cas_reset(sc); 1195 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1196 1197 /* Re-initialize the MIF */ 1198 cas_mifinit(sc); 1199 1200 /* step 3. Setup data structures in host memory */ 1201 cas_meminit(sc); 1202 1203 /* step 4. TX MAC registers & counters */ 1204 cas_init_regs(sc); 1205 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1206 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1207 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1208 1209 /* step 5. RX MAC registers & counters */ 1210 cas_iff(sc); 1211 1212 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1213 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1214 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1215 BUS_ADDR_HI32(CAS_CDTXADDR(sc, 0))); 1216 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, 1217 BUS_ADDR_LO32(CAS_CDTXADDR(sc, 0))); 1218 1219 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1220 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1221 BUS_ADDR_HI32(CAS_CDRXADDR(sc, 0))); 1222 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, 1223 BUS_ADDR_LO32(CAS_CDRXADDR(sc, 0))); 1224 1225 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1226 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1227 BUS_ADDR_HI32(CAS_CDRXCADDR(sc, 0))); 1228 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, 1229 BUS_ADDR_LO32(CAS_CDRXCADDR(sc, 0))); 1230 1231 if (CAS_PLUS(sc)) { 1232 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1233 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1234 BUS_ADDR_HI32(CAS_CDRXADDR2(sc, 0))); 1235 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1236 BUS_ADDR_LO32(CAS_CDRXADDR2(sc, 0))); 1237 } 1238 1239 /* step 8. Global Configuration & Interrupt Mask */ 1240 cas_estintr(sc, CAS_INTR_REG); 1241 1242 /* step 9. ETX Configuration: use mostly default values */ 1243 1244 /* Enable DMA */ 1245 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1246 bus_space_write_4(t, h, CAS_TX_CONFIG, 1247 v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29)); 1248 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1249 1250 /* step 10. ERX Configuration */ 1251 1252 /* Encode Receive Descriptor ring size */ 1253 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1254 if (CAS_PLUS(sc)) 1255 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1256 1257 /* Encode Receive Completion ring size */ 1258 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1259 1260 /* Enable DMA */ 1261 bus_space_write_4(t, h, CAS_RX_CONFIG, 1262 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT) | CAS_RX_CONFIG_RXDMA_EN); 1263 1264 /* 1265 * The following value is for an OFF Threshold of about 3/4 full 1266 * and an ON Threshold of 1/4 full. 1267 */ 1268 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1269 (3 * sc->sc_rxfifosize / 256) | 1270 ((sc->sc_rxfifosize / 256) << 12)); 1271 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1272 1273 /* step 11. Configure Media */ 1274 mii_ifmedia_change(&sc->sc_mii); 1275 1276 /* step 12. RX_MAC Configuration Register */ 1277 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1278 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1279 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1280 1281 /* step 14. Issue Transmit Pending command */ 1282 1283 /* step 15. Give the receiver a swift kick */ 1284 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1285 if (CAS_PLUS(sc)) 1286 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1287 1288 /* Start the one second timer. */ 1289 callout_schedule(&sc->sc_tick_ch, hz); 1290 1291 ifp->if_flags |= IFF_RUNNING; 1292 ifp->if_flags &= ~IFF_OACTIVE; 1293 ifp->if_timer = 0; 1294 splx(s); 1295 1296 return (0); 1297 } 1298 1299 void 1300 cas_init_regs(struct cas_softc *sc) 1301 { 1302 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1303 bus_space_tag_t t = sc->sc_memt; 1304 bus_space_handle_t h = sc->sc_memh; 1305 const u_char *laddr = CLLADDR(ifp->if_sadl); 1306 uint32_t v, r; 1307 1308 /* These regs are not cleared on reset */ 1309 sc->sc_inited = 0; 1310 if (!sc->sc_inited) { 1311 /* Load recommended values */ 1312 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1313 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1314 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1315 1316 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1317 /* Max frame and max burst size */ 1318 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1319 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1320 1321 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1322 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1323 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1324 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1325 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1326 ((laddr[5]<<8)|laddr[4])&0x3ff); 1327 1328 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1329 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1330 bus_space_write_4(t, h, r, 0); 1331 1332 /* MAC control addr set to 0:1:c2:0:1:80 */ 1333 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1334 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1335 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1336 1337 /* MAC filter addr set to 0:0:0:0:0:0 */ 1338 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1339 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1340 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1341 1342 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1343 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1344 1345 /* Hash table initialized to 0 */ 1346 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1347 bus_space_write_4(t, h, r, 0); 1348 1349 sc->sc_inited = 1; 1350 } 1351 1352 /* Counters need to be zeroed */ 1353 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1354 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1355 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1356 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1357 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1358 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1359 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1360 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1361 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1362 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1363 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1364 1365 /* Un-pause stuff */ 1366 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1367 1368 /* 1369 * Set the station address. 1370 */ 1371 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1372 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1373 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1374 } 1375 1376 /* 1377 * Receive interrupt. 1378 */ 1379 int 1380 cas_rint(struct cas_softc *sc) 1381 { 1382 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1383 bus_space_tag_t t = sc->sc_memt; 1384 bus_space_handle_t h = sc->sc_memh; 1385 struct cas_rxsoft *rxs; 1386 struct mbuf *m; 1387 uint64_t word[4]; 1388 int len, off, idx; 1389 int i, skip; 1390 void *cp; 1391 1392 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1393 CAS_CDRXCSYNC(sc, i, 1394 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1395 1396 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1397 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1398 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1399 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1400 1401 /* Stop if the hardware still owns the descriptor. */ 1402 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1403 break; 1404 1405 len = CAS_RC1_HDR_LEN(word[1]); 1406 if (len > 0) { 1407 off = CAS_RC1_HDR_OFF(word[1]); 1408 idx = CAS_RC1_HDR_IDX(word[1]); 1409 rxs = &sc->sc_rxsoft[idx]; 1410 1411 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1412 idx, off, len)); 1413 1414 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1415 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1416 1417 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1418 m = m_devget(cp, len, 0, ifp); 1419 1420 if (word[0] & CAS_RC0_RELEASE_HDR) 1421 cas_add_rxbuf(sc, idx); 1422 1423 if (m != NULL) { 1424 1425 /* 1426 * Pass this up to any BPF listeners, but only 1427 * pass it up the stack if its for us. 1428 */ 1429 m->m_pkthdr.csum_flags = 0; 1430 if_percpuq_enqueue(ifp->if_percpuq, m); 1431 } else 1432 if_statinc(ifp, if_ierrors); 1433 } 1434 1435 len = CAS_RC0_DATA_LEN(word[0]); 1436 if (len > 0) { 1437 off = CAS_RC0_DATA_OFF(word[0]); 1438 idx = CAS_RC0_DATA_IDX(word[0]); 1439 rxs = &sc->sc_rxsoft[idx]; 1440 1441 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1442 idx, off, len)); 1443 1444 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1445 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1446 1447 /* XXX We should not be copying the packet here. */ 1448 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1449 m = m_devget(cp, len, 0, ifp); 1450 1451 if (word[0] & CAS_RC0_RELEASE_DATA) 1452 cas_add_rxbuf(sc, idx); 1453 1454 if (m != NULL) { 1455 /* 1456 * Pass this up to any BPF listeners, but only 1457 * pass it up the stack if its for us. 1458 */ 1459 m->m_pkthdr.csum_flags = 0; 1460 if_percpuq_enqueue(ifp->if_percpuq, m); 1461 } else 1462 if_statinc(ifp, if_ierrors); 1463 } 1464 1465 if (word[0] & CAS_RC0_SPLIT) 1466 aprint_error_dev(sc->sc_dev, "split packet\n"); 1467 1468 skip = CAS_RC0_SKIP(word[0]); 1469 } 1470 1471 while (sc->sc_rxptr != i) { 1472 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1473 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1474 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1475 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1476 CAS_DMA_WRITE(CAS_RC3_OWN); 1477 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1478 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1479 1480 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1481 } 1482 1483 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1484 1485 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1486 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1487 1488 return (1); 1489 } 1490 1491 /* 1492 * cas_add_rxbuf: 1493 * 1494 * Add a receive buffer to the indicated descriptor. 1495 */ 1496 int 1497 cas_add_rxbuf(struct cas_softc *sc, int idx) 1498 { 1499 bus_space_tag_t t = sc->sc_memt; 1500 bus_space_handle_t h = sc->sc_memh; 1501 1502 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1503 1504 if ((sc->sc_rxdptr % 4) == 0) 1505 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1506 1507 if (++sc->sc_rxdptr == CAS_NRXDESC) 1508 sc->sc_rxdptr = 0; 1509 1510 return (0); 1511 } 1512 1513 int 1514 cas_eint(struct cas_softc *sc, u_int status) 1515 { 1516 char bits[128]; 1517 if ((status & CAS_INTR_MIF) != 0) { 1518 DPRINTF(sc, ("%s: link status changed\n", 1519 device_xname(sc->sc_dev))); 1520 return (1); 1521 } 1522 1523 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1524 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1525 return (1); 1526 } 1527 1528 int 1529 cas_pint(struct cas_softc *sc) 1530 { 1531 bus_space_tag_t t = sc->sc_memt; 1532 bus_space_handle_t seb = sc->sc_memh; 1533 uint32_t status; 1534 1535 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1536 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1537 #ifdef CAS_DEBUG 1538 if (status) 1539 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1540 #endif 1541 return (1); 1542 } 1543 1544 int 1545 cas_intr(void *v) 1546 { 1547 struct cas_softc *sc = (struct cas_softc *)v; 1548 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1549 bus_space_tag_t t = sc->sc_memt; 1550 bus_space_handle_t seb = sc->sc_memh; 1551 uint32_t status; 1552 int r = 0; 1553 #ifdef CAS_DEBUG 1554 char bits[128]; 1555 #endif 1556 1557 sc->sc_ev_intr.ev_count++; 1558 1559 status = bus_space_read_4(t, seb, CAS_STATUS); 1560 #ifdef CAS_DEBUG 1561 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1562 #endif 1563 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1564 device_xname(sc->sc_dev), (status>>19), bits)); 1565 1566 if ((status & CAS_INTR_PCS) != 0) 1567 r |= cas_pint(sc); 1568 1569 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1570 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1571 r |= cas_eint(sc, status); 1572 1573 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1574 r |= cas_tint(sc, status); 1575 1576 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1577 r |= cas_rint(sc); 1578 1579 /* We should eventually do more than just print out error stats. */ 1580 if (status & CAS_INTR_TX_MAC) { 1581 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1582 #ifdef CAS_DEBUG 1583 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1584 printf("%s: MAC tx fault, status %x\n", 1585 device_xname(sc->sc_dev), txstat); 1586 #endif 1587 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1588 cas_init(ifp); 1589 } 1590 if (status & CAS_INTR_RX_MAC) { 1591 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1592 #ifdef CAS_DEBUG 1593 if (rxstat & ~CAS_MAC_RX_DONE) 1594 printf("%s: MAC rx fault, status %x\n", 1595 device_xname(sc->sc_dev), rxstat); 1596 #endif 1597 /* 1598 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1599 * due to a silicon bug so handle them silently. 1600 */ 1601 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1602 if_statinc(ifp, if_ierrors); 1603 cas_init(ifp); 1604 } 1605 #ifdef CAS_DEBUG 1606 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1607 printf("%s: MAC rx fault, status %x\n", 1608 device_xname(sc->sc_dev), rxstat); 1609 #endif 1610 } 1611 rnd_add_uint32(&sc->rnd_source, status); 1612 return (r); 1613 } 1614 1615 1616 void 1617 cas_watchdog(struct ifnet *ifp) 1618 { 1619 struct cas_softc *sc = ifp->if_softc; 1620 1621 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1622 "CAS_MAC_RX_CONFIG %x\n", 1623 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1624 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1625 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1626 1627 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1628 if_statinc(ifp, if_oerrors); 1629 1630 /* Try to get more packets going. */ 1631 cas_init(ifp); 1632 } 1633 1634 /* 1635 * Initialize the MII Management Interface 1636 */ 1637 void 1638 cas_mifinit(struct cas_softc *sc) 1639 { 1640 bus_space_tag_t t = sc->sc_memt; 1641 bus_space_handle_t mif = sc->sc_memh; 1642 1643 /* Configure the MIF in frame mode */ 1644 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1645 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1646 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1647 } 1648 1649 /* 1650 * MII interface 1651 * 1652 * The Cassini MII interface supports at least three different operating modes: 1653 * 1654 * Bitbang mode is implemented using data, clock and output enable registers. 1655 * 1656 * Frame mode is implemented by loading a complete frame into the frame 1657 * register and polling the valid bit for completion. 1658 * 1659 * Polling mode uses the frame register but completion is indicated by 1660 * an interrupt. 1661 * 1662 */ 1663 int 1664 cas_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1665 { 1666 struct cas_softc *sc = device_private(self); 1667 bus_space_tag_t t = sc->sc_memt; 1668 bus_space_handle_t mif = sc->sc_memh; 1669 int n; 1670 uint32_t v; 1671 1672 #ifdef CAS_DEBUG 1673 if (sc->sc_debug) 1674 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1675 #endif 1676 1677 /* Construct the frame command */ 1678 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1679 CAS_MIF_FRAME_READ; 1680 1681 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1682 for (n = 0; n < 100; n++) { 1683 DELAY(1); 1684 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1685 if (v & CAS_MIF_FRAME_TA0) { 1686 *val = v & CAS_MIF_FRAME_DATA; 1687 return 0; 1688 } 1689 } 1690 1691 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1692 return ETIMEDOUT; 1693 } 1694 1695 int 1696 cas_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1697 { 1698 struct cas_softc *sc = device_private(self); 1699 bus_space_tag_t t = sc->sc_memt; 1700 bus_space_handle_t mif = sc->sc_memh; 1701 int n; 1702 uint32_t v; 1703 1704 #ifdef CAS_DEBUG 1705 if (sc->sc_debug) 1706 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1707 phy, reg, val); 1708 #endif 1709 1710 /* Construct the frame command */ 1711 v = CAS_MIF_FRAME_WRITE | 1712 (phy << CAS_MIF_PHY_SHIFT) | 1713 (reg << CAS_MIF_REG_SHIFT) | 1714 (val & CAS_MIF_FRAME_DATA); 1715 1716 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1717 for (n = 0; n < 100; n++) { 1718 DELAY(1); 1719 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1720 if (v & CAS_MIF_FRAME_TA0) 1721 return 0; 1722 } 1723 1724 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1725 return ETIMEDOUT; 1726 } 1727 1728 void 1729 cas_mii_statchg(struct ifnet *ifp) 1730 { 1731 struct cas_softc *sc = ifp->if_softc; 1732 #ifdef CAS_DEBUG 1733 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1734 #endif 1735 bus_space_tag_t t = sc->sc_memt; 1736 bus_space_handle_t mac = sc->sc_memh; 1737 uint32_t v; 1738 1739 #ifdef CAS_DEBUG 1740 if (sc->sc_debug) 1741 printf("cas_mii_statchg: status change: phy = %d\n", 1742 sc->sc_phys[instance]); 1743 #endif 1744 1745 /* Set tx full duplex options */ 1746 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1747 delay(10000); /* reg must be cleared and delay before changing. */ 1748 v = CAS_MAC_TX_ENA_IPG0 | CAS_MAC_TX_NGU | CAS_MAC_TX_NGU_LIMIT | 1749 CAS_MAC_TX_ENABLE; 1750 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1751 v |= CAS_MAC_TX_IGN_CARRIER | CAS_MAC_TX_IGN_COLLIS; 1752 } 1753 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1754 1755 /* XIF Configuration */ 1756 v = CAS_MAC_XIF_TX_MII_ENA; 1757 v |= CAS_MAC_XIF_LINK_LED; 1758 1759 /* MII needs echo disable if half duplex. */ 1760 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1761 /* turn on full duplex LED */ 1762 v |= CAS_MAC_XIF_FDPLX_LED; 1763 else 1764 /* half duplex -- disable echo */ 1765 v |= CAS_MAC_XIF_ECHO_DISABL; 1766 1767 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1768 case IFM_1000_T: /* Gigabit using GMII interface */ 1769 case IFM_1000_SX: 1770 v |= CAS_MAC_XIF_GMII_MODE; 1771 break; 1772 default: 1773 v &= ~CAS_MAC_XIF_GMII_MODE; 1774 } 1775 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1776 } 1777 1778 int 1779 cas_pcs_readreg(device_t self, int phy, int reg, uint16_t *val) 1780 { 1781 struct cas_softc *sc = device_private(self); 1782 bus_space_tag_t t = sc->sc_memt; 1783 bus_space_handle_t pcs = sc->sc_memh; 1784 1785 #ifdef CAS_DEBUG 1786 if (sc->sc_debug) 1787 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1788 #endif 1789 1790 if (phy != CAS_PHYAD_EXTERNAL) 1791 return -1; 1792 1793 switch (reg) { 1794 case MII_BMCR: 1795 reg = CAS_MII_CONTROL; 1796 break; 1797 case MII_BMSR: 1798 reg = CAS_MII_STATUS; 1799 break; 1800 case MII_ANAR: 1801 reg = CAS_MII_ANAR; 1802 break; 1803 case MII_ANLPAR: 1804 reg = CAS_MII_ANLPAR; 1805 break; 1806 case MII_EXTSR: 1807 *val = EXTSR_1000XFDX | EXTSR_1000XHDX; 1808 return 0; 1809 default: 1810 return (0); 1811 } 1812 1813 *val = bus_space_read_4(t, pcs, reg) & 0xffff; 1814 return 0; 1815 } 1816 1817 int 1818 cas_pcs_writereg(device_t self, int phy, int reg, uint16_t val) 1819 { 1820 struct cas_softc *sc = device_private(self); 1821 bus_space_tag_t t = sc->sc_memt; 1822 bus_space_handle_t pcs = sc->sc_memh; 1823 int reset = 0; 1824 1825 #ifdef CAS_DEBUG 1826 if (sc->sc_debug) 1827 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1828 phy, reg, val); 1829 #endif 1830 1831 if (phy != CAS_PHYAD_EXTERNAL) 1832 return -1; 1833 1834 if (reg == MII_ANAR) 1835 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1836 1837 switch (reg) { 1838 case MII_BMCR: 1839 reset = (val & CAS_MII_CONTROL_RESET); 1840 reg = CAS_MII_CONTROL; 1841 break; 1842 case MII_BMSR: 1843 reg = CAS_MII_STATUS; 1844 break; 1845 case MII_ANAR: 1846 reg = CAS_MII_ANAR; 1847 break; 1848 case MII_ANLPAR: 1849 reg = CAS_MII_ANLPAR; 1850 break; 1851 default: 1852 return 0; 1853 } 1854 1855 bus_space_write_4(t, pcs, reg, val); 1856 1857 if (reset) 1858 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1859 1860 if (reg == CAS_MII_ANAR || reset) 1861 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1862 CAS_MII_CONFIG_ENABLE); 1863 1864 return 0; 1865 } 1866 1867 int 1868 cas_mediachange(struct ifnet *ifp) 1869 { 1870 struct cas_softc *sc = ifp->if_softc; 1871 struct mii_data *mii = &sc->sc_mii; 1872 1873 if (mii->mii_instance) { 1874 struct mii_softc *miisc; 1875 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1876 mii_phy_reset(miisc); 1877 } 1878 1879 return (mii_mediachg(&sc->sc_mii)); 1880 } 1881 1882 void 1883 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1884 { 1885 struct cas_softc *sc = ifp->if_softc; 1886 1887 mii_pollstat(&sc->sc_mii); 1888 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1889 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1890 } 1891 1892 /* 1893 * Process an ioctl request. 1894 */ 1895 int 1896 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1897 { 1898 struct cas_softc *sc = ifp->if_softc; 1899 int s, error = 0; 1900 1901 s = splnet(); 1902 1903 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1904 error = 0; 1905 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1906 ; 1907 else if (ifp->if_flags & IFF_RUNNING) { 1908 /* 1909 * Multicast list has changed; set the hardware filter 1910 * accordingly. 1911 */ 1912 cas_iff(sc); 1913 } 1914 } 1915 1916 splx(s); 1917 return (error); 1918 } 1919 1920 static bool 1921 cas_suspend(device_t self, const pmf_qual_t *qual) 1922 { 1923 struct cas_softc *sc = device_private(self); 1924 bus_space_tag_t t = sc->sc_memt; 1925 bus_space_handle_t h = sc->sc_memh; 1926 1927 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1928 if (sc->sc_ih != NULL) { 1929 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1930 sc->sc_ih = NULL; 1931 } 1932 1933 return true; 1934 } 1935 1936 static bool 1937 cas_resume(device_t self, const pmf_qual_t *qual) 1938 { 1939 struct cas_softc *sc = device_private(self); 1940 1941 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1942 } 1943 1944 static bool 1945 cas_estintr(struct cas_softc *sc, int what) 1946 { 1947 bus_space_tag_t t = sc->sc_memt; 1948 bus_space_handle_t h = sc->sc_memh; 1949 const char *intrstr = NULL; 1950 char intrbuf[PCI_INTRSTR_LEN]; 1951 1952 /* PCI interrupts */ 1953 if (what & CAS_INTR_PCI) { 1954 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle, intrbuf, 1955 sizeof(intrbuf)); 1956 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_handle, 1957 IPL_NET, cas_intr, sc, device_xname(sc->sc_dev)); 1958 if (sc->sc_ih == NULL) { 1959 aprint_error_dev(sc->sc_dev, 1960 "unable to establish interrupt"); 1961 if (intrstr != NULL) 1962 aprint_error(" at %s", intrstr); 1963 aprint_error("\n"); 1964 return false; 1965 } 1966 1967 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1968 } 1969 1970 /* Interrupt register */ 1971 if (what & CAS_INTR_REG) { 1972 bus_space_write_4(t, h, CAS_INTMASK, 1973 ~(CAS_INTR_TX_INTME | CAS_INTR_TX_EMPTY | 1974 CAS_INTR_TX_TAG_ERR | 1975 CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF | 1976 CAS_INTR_RX_TAG_ERR | 1977 CAS_INTR_RX_COMP_FULL | CAS_INTR_PCS | 1978 CAS_INTR_MAC_CONTROL | CAS_INTR_MIF | 1979 CAS_INTR_BERR)); 1980 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1981 CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT); 1982 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1983 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1984 } 1985 return true; 1986 } 1987 1988 bool 1989 cas_shutdown(device_t self, int howto) 1990 { 1991 struct cas_softc *sc = device_private(self); 1992 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1993 1994 cas_stop(ifp, 1); 1995 1996 return true; 1997 } 1998 1999 void 2000 cas_iff(struct cas_softc *sc) 2001 { 2002 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2003 struct ethercom *ec = &sc->sc_ethercom; 2004 struct ether_multi *enm; 2005 struct ether_multistep step; 2006 bus_space_tag_t t = sc->sc_memt; 2007 bus_space_handle_t h = sc->sc_memh; 2008 uint32_t crc, hash[16], rxcfg; 2009 int i; 2010 2011 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 2012 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 2013 CAS_MAC_RX_PROMISC_GRP); 2014 ifp->if_flags &= ~IFF_ALLMULTI; 2015 2016 if ((ifp->if_flags & IFF_PROMISC) != 0) 2017 goto update; 2018 2019 /* 2020 * Set up multicast address filter by passing all multicast 2021 * addresses through a crc generator, and then using the 2022 * high order 8 bits as an index into the 256 bit logical 2023 * address filter. The high order 4 bits selects the word, 2024 * while the other 4 bits select the bit within the word 2025 * (where bit 0 is the MSB). 2026 */ 2027 2028 /* Clear hash table */ 2029 for (i = 0; i < 16; i++) 2030 hash[i] = 0; 2031 2032 ETHER_LOCK(ec); 2033 ETHER_FIRST_MULTI(step, ec, enm); 2034 while (enm != NULL) { 2035 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2036 /* XXX Use ETHER_F_ALLMULTI in future. */ 2037 ifp->if_flags |= IFF_ALLMULTI; 2038 ETHER_UNLOCK(ec); 2039 goto update; 2040 } 2041 2042 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2043 2044 /* Just want the 8 most significant bits. */ 2045 crc >>= 24; 2046 2047 /* Set the corresponding bit in the filter. */ 2048 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2049 2050 ETHER_NEXT_MULTI(step, enm); 2051 } 2052 ETHER_UNLOCK(ec); 2053 2054 rxcfg |= CAS_MAC_RX_HASH_FILTER; 2055 2056 /* Now load the hash table into the chip (if we are using it) */ 2057 for (i = 0; i < 16; i++) { 2058 bus_space_write_4(t, h, 2059 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2060 hash[i]); 2061 } 2062 2063 update: 2064 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2065 if (ifp->if_flags & IFF_PROMISC) { 2066 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 2067 /* XXX Use ETHER_F_ALLMULTI in future. */ 2068 ifp->if_flags |= IFF_ALLMULTI; 2069 } else 2070 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 2071 } 2072 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 2073 } 2074 2075 int 2076 cas_encap(struct cas_softc *sc, struct mbuf *mhead, uint32_t *bixp) 2077 { 2078 uint64_t flags; 2079 uint32_t cur, frag, i; 2080 bus_dmamap_t map; 2081 2082 cur = frag = *bixp; 2083 map = sc->sc_txd[cur].sd_map; 2084 2085 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 2086 BUS_DMA_NOWAIT) != 0) { 2087 return (ENOBUFS); 2088 } 2089 2090 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 2091 bus_dmamap_unload(sc->sc_dmatag, map); 2092 return (ENOBUFS); 2093 } 2094 2095 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 2096 BUS_DMASYNC_PREWRITE); 2097 2098 for (i = 0; i < map->dm_nsegs; i++) { 2099 sc->sc_txdescs[frag].cd_addr = 2100 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 2101 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 2102 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 2103 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 2104 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 2105 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 2106 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 2107 BUS_DMASYNC_PREWRITE); 2108 cur = frag; 2109 if (++frag == CAS_NTXDESC) 2110 frag = 0; 2111 } 2112 2113 sc->sc_tx_cnt += map->dm_nsegs; 2114 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 2115 sc->sc_txd[cur].sd_map = map; 2116 sc->sc_txd[cur].sd_mbuf = mhead; 2117 2118 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 2119 2120 *bixp = frag; 2121 2122 /* sync descriptors */ 2123 2124 return (0); 2125 } 2126 2127 /* 2128 * Transmit interrupt. 2129 */ 2130 int 2131 cas_tint(struct cas_softc *sc, uint32_t status) 2132 { 2133 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2134 struct cas_sxd *sd; 2135 uint32_t cons, comp; 2136 2137 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2138 cons = sc->sc_tx_cons; 2139 while (cons != comp) { 2140 sd = &sc->sc_txd[cons]; 2141 if (sd->sd_mbuf != NULL) { 2142 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2143 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2144 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2145 m_freem(sd->sd_mbuf); 2146 sd->sd_mbuf = NULL; 2147 if_statinc(ifp, if_opackets); 2148 } 2149 sc->sc_tx_cnt--; 2150 if (++cons == CAS_NTXDESC) 2151 cons = 0; 2152 } 2153 sc->sc_tx_cons = cons; 2154 2155 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2156 ifp->if_flags &= ~IFF_OACTIVE; 2157 if (sc->sc_tx_cnt == 0) 2158 ifp->if_timer = 0; 2159 2160 if_schedule_deferred_start(ifp); 2161 2162 return (1); 2163 } 2164 2165 void 2166 cas_start(struct ifnet *ifp) 2167 { 2168 struct cas_softc *sc = ifp->if_softc; 2169 struct mbuf *m; 2170 uint32_t bix; 2171 2172 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2173 return; 2174 2175 bix = sc->sc_tx_prod; 2176 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2177 IFQ_POLL(&ifp->if_snd, m); 2178 if (m == NULL) 2179 break; 2180 2181 /* 2182 * If BPF is listening on this interface, let it see the 2183 * packet before we commit it to the wire. 2184 */ 2185 bpf_mtap(ifp, m, BPF_D_OUT); 2186 2187 /* 2188 * Encapsulate this packet and start it going... 2189 * or fail... 2190 */ 2191 if (cas_encap(sc, m, &bix)) { 2192 ifp->if_flags |= IFF_OACTIVE; 2193 break; 2194 } 2195 2196 IFQ_DEQUEUE(&ifp->if_snd, m); 2197 ifp->if_timer = 5; 2198 } 2199 2200 sc->sc_tx_prod = bix; 2201 } 2202 2203 MODULE(MODULE_CLASS_DRIVER, if_cas, "pci"); 2204 2205 #ifdef _MODULE 2206 #include "ioconf.c" 2207 #endif 2208 2209 static int 2210 if_cas_modcmd(modcmd_t cmd, void *opaque) 2211 { 2212 int error = 0; 2213 2214 switch (cmd) { 2215 case MODULE_CMD_INIT: 2216 #ifdef _MODULE 2217 error = config_init_component(cfdriver_ioconf_cas, 2218 cfattach_ioconf_cas, cfdata_ioconf_cas); 2219 #endif 2220 return error; 2221 case MODULE_CMD_FINI: 2222 #ifdef _MODULE 2223 error = config_fini_component(cfdriver_ioconf_cas, 2224 cfattach_ioconf_cas, cfdata_ioconf_cas); 2225 #endif 2226 return error; 2227 default: 2228 return ENOTTY; 2229 } 2230 } 2231