1 /* $NetBSD: if_cas.c,v 1.12 2010/11/13 13:52:06 uebayasi Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.12 2010/11/13 13:52:06 uebayasi Exp $"); 48 49 #include "opt_inet.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/syslog.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/socket.h> 59 #include <sys/ioctl.h> 60 #include <sys/errno.h> 61 #include <sys/device.h> 62 63 #include <machine/endian.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_ether.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #include <netinet/tcp.h> 76 #include <netinet/udp.h> 77 #endif 78 79 #include <net/bpf.h> 80 81 #include <sys/bus.h> 82 #include <sys/intr.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 #include <dev/mii/mii_bitbang.h> 87 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcidevs.h> 91 #include <prop/proplib.h> 92 93 #include <dev/pci/if_casreg.h> 94 #include <dev/pci/if_casvar.h> 95 96 #define TRIES 10000 97 98 static bool cas_estintr(struct cas_softc *sc, int); 99 bool cas_shutdown(device_t, int); 100 static bool cas_suspend(device_t, const pmf_qual_t *); 101 static bool cas_resume(device_t, const pmf_qual_t *); 102 static int cas_detach(device_t, int); 103 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 104 105 int cas_match(device_t, cfdata_t, void *); 106 void cas_attach(device_t, device_t, void *); 107 108 109 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 110 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 111 DVF_DETACH_SHUTDOWN); 112 113 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 114 115 void cas_config(struct cas_softc *, const uint8_t *); 116 void cas_start(struct ifnet *); 117 void cas_stop(struct ifnet *, int); 118 int cas_ioctl(struct ifnet *, u_long, void *); 119 void cas_tick(void *); 120 void cas_watchdog(struct ifnet *); 121 int cas_init(struct ifnet *); 122 void cas_init_regs(struct cas_softc *); 123 int cas_ringsize(int); 124 int cas_cringsize(int); 125 int cas_meminit(struct cas_softc *); 126 void cas_mifinit(struct cas_softc *); 127 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 128 u_int32_t, u_int32_t); 129 void cas_reset(struct cas_softc *); 130 int cas_reset_rx(struct cas_softc *); 131 int cas_reset_tx(struct cas_softc *); 132 int cas_disable_rx(struct cas_softc *); 133 int cas_disable_tx(struct cas_softc *); 134 void cas_rxdrain(struct cas_softc *); 135 int cas_add_rxbuf(struct cas_softc *, int idx); 136 void cas_iff(struct cas_softc *); 137 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 138 139 /* MII methods & callbacks */ 140 int cas_mii_readreg(device_t, int, int); 141 void cas_mii_writereg(device_t, int, int, int); 142 void cas_mii_statchg(device_t); 143 int cas_pcs_readreg(device_t, int, int); 144 void cas_pcs_writereg(device_t, int, int, int); 145 146 int cas_mediachange(struct ifnet *); 147 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 148 149 int cas_eint(struct cas_softc *, u_int); 150 int cas_rint(struct cas_softc *); 151 int cas_tint(struct cas_softc *, u_int32_t); 152 int cas_pint(struct cas_softc *); 153 int cas_intr(void *); 154 155 #ifdef CAS_DEBUG 156 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 157 printf x 158 #else 159 #define DPRINTF(sc, x) /* nothing */ 160 #endif 161 162 int 163 cas_match(device_t parent, cfdata_t cf, void *aux) 164 { 165 struct pci_attach_args *pa = aux; 166 167 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 168 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 169 return 1; 170 171 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 172 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 173 return 1; 174 175 return 0; 176 } 177 178 #define PROMHDR_PTR_DATA 0x18 179 #define PROMDATA_PTR_VPD 0x08 180 #define PROMDATA_DATA2 0x0a 181 182 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 183 static const u_int8_t cas_promdat[] = { 184 'P', 'C', 'I', 'R', 185 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 186 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 187 }; 188 static const u_int8_t cas_promdat_ns[] = { 189 'P', 'C', 'I', 'R', 190 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 191 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 192 }; 193 194 static const u_int8_t cas_promdat2[] = { 195 0x18, 0x00, /* structure length */ 196 0x00, /* structure revision */ 197 0x00, /* interface revision */ 198 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 199 PCI_CLASS_NETWORK /* class code */ 200 }; 201 202 int 203 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 204 uint8_t *enaddr) 205 { 206 struct pci_vpd_largeres *res; 207 struct pci_vpd *vpd; 208 bus_space_handle_t romh; 209 bus_space_tag_t romt; 210 bus_size_t romsize = 0; 211 u_int8_t buf[32], *desc; 212 pcireg_t address; 213 int dataoff, vpdoff, len; 214 int rv = -1; 215 216 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 217 &romt, &romh, NULL, &romsize)) 218 return (-1); 219 220 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 221 address |= PCI_MAPREG_ROM_ENABLE; 222 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 223 224 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 225 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 226 goto fail; 227 228 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 229 if (dataoff < 0x1c) 230 goto fail; 231 232 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 233 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 234 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 235 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 236 goto fail; 237 238 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 239 if (vpdoff < 0x1c) 240 goto fail; 241 242 next: 243 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 244 if (!PCI_VPDRES_ISLARGE(buf[0])) 245 goto fail; 246 247 res = (struct pci_vpd_largeres *)buf; 248 vpdoff += sizeof(*res); 249 250 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 251 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 252 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 253 /* Skip identifier string. */ 254 vpdoff += len; 255 goto next; 256 257 case PCI_VPDRES_TYPE_VPD: 258 while (len > 0) { 259 bus_space_read_region_1(romt, romh, vpdoff, 260 buf, sizeof(buf)); 261 262 vpd = (struct pci_vpd *)buf; 263 vpdoff += sizeof(*vpd) + vpd->vpd_len; 264 len -= sizeof(*vpd) + vpd->vpd_len; 265 266 /* 267 * We're looking for an "Enhanced" VPD... 268 */ 269 if (vpd->vpd_key0 != 'Z') 270 continue; 271 272 desc = buf + sizeof(*vpd); 273 274 /* 275 * ...which is an instance property... 276 */ 277 if (desc[0] != 'I') 278 continue; 279 desc += 3; 280 281 /* 282 * ...that's a byte array with the proper 283 * length for a MAC address... 284 */ 285 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 286 continue; 287 desc += 2; 288 289 /* 290 * ...named "local-mac-address". 291 */ 292 if (strcmp(desc, "local-mac-address") != 0) 293 continue; 294 desc += strlen("local-mac-address") + 1; 295 296 memcpy(enaddr, desc, ETHER_ADDR_LEN); 297 rv = 0; 298 } 299 break; 300 301 default: 302 goto fail; 303 } 304 305 fail: 306 if (romsize != 0) 307 bus_space_unmap(romt, romh, romsize); 308 309 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 310 address &= ~PCI_MAPREG_ROM_ENABLE; 311 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 312 313 return (rv); 314 } 315 316 void 317 cas_attach(device_t parent, device_t self, void *aux) 318 { 319 struct pci_attach_args *pa = aux; 320 struct cas_softc *sc = device_private(self); 321 char devinfo[256]; 322 prop_data_t data; 323 uint8_t enaddr[ETHER_ADDR_LEN]; 324 325 sc->sc_dev = self; 326 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 327 sc->sc_rev = PCI_REVISION(pa->pa_class); 328 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, sc->sc_rev); 329 sc->sc_dmatag = pa->pa_dmat; 330 331 #define PCI_CAS_BASEADDR 0x10 332 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 333 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 334 aprint_error_dev(sc->sc_dev, 335 "unable to map device registers\n"); 336 return; 337 } 338 339 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 340 "mac-address")) != NULL) 341 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 342 else if (cas_pci_enaddr(sc, pa, enaddr) != 0) { 343 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 344 memset(enaddr, 0, sizeof(enaddr)); 345 } 346 347 sc->sc_burst = 16; /* XXX */ 348 349 sc->sc_att_stage = CAS_ATT_BACKEND_0; 350 351 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 352 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 353 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 354 return; 355 } 356 sc->sc_pc = pa->pa_pc; 357 if (!cas_estintr(sc, CAS_INTR_PCI)) { 358 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 359 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 360 return; 361 } 362 363 sc->sc_att_stage = CAS_ATT_BACKEND_1; 364 365 /* 366 * call the main configure 367 */ 368 cas_config(sc, enaddr); 369 370 if (pmf_device_register1(sc->sc_dev, 371 cas_suspend, cas_resume, cas_shutdown)) 372 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 373 else 374 aprint_error_dev(sc->sc_dev, 375 "could not establish power handlers\n"); 376 377 sc->sc_att_stage = CAS_ATT_FINISHED; 378 /*FALLTHROUGH*/ 379 } 380 381 /* 382 * cas_config: 383 * 384 * Attach a Cassini interface to the system. 385 */ 386 void 387 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 388 { 389 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 390 struct mii_data *mii = &sc->sc_mii; 391 struct mii_softc *child; 392 int i, error; 393 394 /* Make sure the chip is stopped. */ 395 ifp->if_softc = sc; 396 cas_reset(sc); 397 398 /* 399 * Allocate the control data structures, and create and load the 400 * DMA map for it. 401 */ 402 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 403 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 404 1, &sc->sc_cdnseg, 0)) != 0) { 405 aprint_error_dev(sc->sc_dev, 406 "unable to allocate control data, error = %d\n", 407 error); 408 cas_partial_detach(sc, CAS_ATT_0); 409 } 410 411 /* XXX should map this in with correct endianness */ 412 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 413 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 414 BUS_DMA_COHERENT)) != 0) { 415 aprint_error_dev(sc->sc_dev, 416 "unable to map control data, error = %d\n", error); 417 cas_partial_detach(sc, CAS_ATT_1); 418 } 419 420 if ((error = bus_dmamap_create(sc->sc_dmatag, 421 sizeof(struct cas_control_data), 1, 422 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 423 aprint_error_dev(sc->sc_dev, 424 "unable to create control data DMA map, error = %d\n", error); 425 cas_partial_detach(sc, CAS_ATT_2); 426 } 427 428 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 429 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 430 0)) != 0) { 431 aprint_error_dev(sc->sc_dev, 432 "unable to load control data DMA map, error = %d\n", 433 error); 434 cas_partial_detach(sc, CAS_ATT_3); 435 } 436 437 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 438 439 /* 440 * Create the receive buffer DMA maps. 441 */ 442 for (i = 0; i < CAS_NRXDESC; i++) { 443 bus_dma_segment_t seg; 444 char *kva; 445 int rseg; 446 447 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 448 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 449 aprint_error_dev(sc->sc_dev, 450 "unable to alloc rx DMA mem %d, error = %d\n", 451 i, error); 452 cas_partial_detach(sc, CAS_ATT_5); 453 } 454 sc->sc_rxsoft[i].rxs_dmaseg = seg; 455 456 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 457 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 458 aprint_error_dev(sc->sc_dev, 459 "unable to alloc rx DMA mem %d, error = %d\n", 460 i, error); 461 cas_partial_detach(sc, CAS_ATT_5); 462 } 463 sc->sc_rxsoft[i].rxs_kva = kva; 464 465 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 466 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 467 aprint_error_dev(sc->sc_dev, 468 "unable to create rx DMA map %d, error = %d\n", 469 i, error); 470 cas_partial_detach(sc, CAS_ATT_5); 471 } 472 473 if ((error = bus_dmamap_load(sc->sc_dmatag, 474 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 475 BUS_DMA_NOWAIT)) != 0) { 476 aprint_error_dev(sc->sc_dev, 477 "unable to load rx DMA map %d, error = %d\n", 478 i, error); 479 cas_partial_detach(sc, CAS_ATT_5); 480 } 481 } 482 483 /* 484 * Create the transmit buffer DMA maps. 485 */ 486 for (i = 0; i < CAS_NTXDESC; i++) { 487 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 488 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 489 &sc->sc_txd[i].sd_map)) != 0) { 490 aprint_error_dev(sc->sc_dev, 491 "unable to create tx DMA map %d, error = %d\n", 492 i, error); 493 cas_partial_detach(sc, CAS_ATT_6); 494 } 495 sc->sc_txd[i].sd_mbuf = NULL; 496 } 497 498 /* 499 * From this point forward, the attachment cannot fail. A failure 500 * before this point releases all resources that may have been 501 * allocated. 502 */ 503 504 /* Announce ourselves. */ 505 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 506 ether_sprintf(enaddr)); 507 aprint_naive(": Ethernet controller\n"); 508 509 /* Get RX FIFO size */ 510 sc->sc_rxfifosize = 16 * 1024; 511 512 /* Initialize ifnet structure. */ 513 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 514 ifp->if_softc = sc; 515 ifp->if_flags = 516 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 517 ifp->if_start = cas_start; 518 ifp->if_ioctl = cas_ioctl; 519 ifp->if_watchdog = cas_watchdog; 520 ifp->if_stop = cas_stop; 521 ifp->if_init = cas_init; 522 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 523 IFQ_SET_READY(&ifp->if_snd); 524 525 /* Initialize ifmedia structures and MII info */ 526 mii->mii_ifp = ifp; 527 mii->mii_readreg = cas_mii_readreg; 528 mii->mii_writereg = cas_mii_writereg; 529 mii->mii_statchg = cas_mii_statchg; 530 531 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 532 sc->sc_ethercom.ec_mii = mii; 533 534 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 535 536 cas_mifinit(sc); 537 538 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 539 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 540 bus_space_write_4(sc->sc_memt, sc->sc_memh, 541 CAS_MIF_CONFIG, sc->sc_mif_config); 542 } 543 544 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 545 MII_OFFSET_ANY, 0); 546 547 child = LIST_FIRST(&mii->mii_phys); 548 if (child == NULL && 549 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 550 /* 551 * Try the external PCS SERDES if we didn't find any 552 * MII devices. 553 */ 554 bus_space_write_4(sc->sc_memt, sc->sc_memh, 555 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 556 557 bus_space_write_4(sc->sc_memt, sc->sc_memh, 558 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 559 560 mii->mii_readreg = cas_pcs_readreg; 561 mii->mii_writereg = cas_pcs_writereg; 562 563 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 564 MII_OFFSET_ANY, MIIF_NOISOLATE); 565 } 566 567 child = LIST_FIRST(&mii->mii_phys); 568 if (child == NULL) { 569 /* No PHY attached */ 570 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 571 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 572 } else { 573 /* 574 * Walk along the list of attached MII devices and 575 * establish an `MII instance' to `phy number' 576 * mapping. We'll use this mapping in media change 577 * requests to determine which phy to use to program 578 * the MIF configuration register. 579 */ 580 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 581 /* 582 * Note: we support just two PHYs: the built-in 583 * internal device and an external on the MII 584 * connector. 585 */ 586 if (child->mii_phy > 1 || child->mii_inst > 1) { 587 aprint_error_dev(sc->sc_dev, 588 "cannot accommodate MII device %s" 589 " at phy %d, instance %d\n", 590 device_xname(child->mii_dev), 591 child->mii_phy, child->mii_inst); 592 continue; 593 } 594 595 sc->sc_phys[child->mii_inst] = child->mii_phy; 596 } 597 598 /* 599 * XXX - we can really do the following ONLY if the 600 * phy indeed has the auto negotiation capability!! 601 */ 602 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 603 } 604 605 /* claim 802.1q capability */ 606 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 607 608 /* Attach the interface. */ 609 if_attach(ifp); 610 ether_ifattach(ifp, enaddr); 611 612 #if NRND > 0 613 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 614 RND_TYPE_NET, 0); 615 #endif 616 617 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 618 NULL, device_xname(sc->sc_dev), "interrupts"); 619 620 callout_init(&sc->sc_tick_ch, 0); 621 622 return; 623 } 624 625 int 626 cas_detach(device_t self, int flags) 627 { 628 int i; 629 struct cas_softc *sc = device_private(self); 630 bus_space_tag_t t = sc->sc_memt; 631 bus_space_handle_t h = sc->sc_memh; 632 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 633 634 /* 635 * Free any resources we've allocated during the failed attach 636 * attempt. Do this in reverse order and fall through. 637 */ 638 switch (sc->sc_att_stage) { 639 case CAS_ATT_FINISHED: 640 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 641 pmf_device_deregister(self); 642 cas_stop(&sc->sc_ethercom.ec_if, 1); 643 evcnt_detach(&sc->sc_ev_intr); 644 645 #if NRND > 0 646 rnd_detach_source(&sc->rnd_source); 647 #endif 648 649 ether_ifdetach(ifp); 650 if_detach(ifp); 651 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 652 653 callout_destroy(&sc->sc_tick_ch); 654 655 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 656 657 /*FALLTHROUGH*/ 658 case CAS_ATT_MII: 659 case CAS_ATT_7: 660 case CAS_ATT_6: 661 for (i = 0; i < CAS_NTXDESC; i++) { 662 if (sc->sc_txd[i].sd_map != NULL) 663 bus_dmamap_destroy(sc->sc_dmatag, 664 sc->sc_txd[i].sd_map); 665 } 666 /*FALLTHROUGH*/ 667 case CAS_ATT_5: 668 for (i = 0; i < CAS_NRXDESC; i++) { 669 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 670 bus_dmamap_unload(sc->sc_dmatag, 671 sc->sc_rxsoft[i].rxs_dmamap); 672 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 673 bus_dmamap_destroy(sc->sc_dmatag, 674 sc->sc_rxsoft[i].rxs_dmamap); 675 if (sc->sc_rxsoft[i].rxs_kva != NULL) 676 bus_dmamem_unmap(sc->sc_dmatag, 677 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 678 /* XXX need to check that bus_dmamem_alloc suceeded 679 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 680 */ 681 bus_dmamem_free(sc->sc_dmatag, 682 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 683 } 684 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 685 /*FALLTHROUGH*/ 686 case CAS_ATT_4: 687 case CAS_ATT_3: 688 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 689 /*FALLTHROUGH*/ 690 case CAS_ATT_2: 691 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 692 sizeof(struct cas_control_data)); 693 /*FALLTHROUGH*/ 694 case CAS_ATT_1: 695 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 696 /*FALLTHROUGH*/ 697 case CAS_ATT_0: 698 sc->sc_att_stage = CAS_ATT_0; 699 /*FALLTHROUGH*/ 700 case CAS_ATT_BACKEND_2: 701 case CAS_ATT_BACKEND_1: 702 if (sc->sc_ih != NULL) { 703 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 704 sc->sc_ih = NULL; 705 } 706 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 707 /*FALLTHROUGH*/ 708 case CAS_ATT_BACKEND_0: 709 break; 710 } 711 return 0; 712 } 713 714 static void 715 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 716 { 717 cfattach_t ca = device_cfattach(sc->sc_dev); 718 719 sc->sc_att_stage = stage; 720 (*ca->ca_detach)(sc->sc_dev, 0); 721 } 722 723 void 724 cas_tick(void *arg) 725 { 726 struct cas_softc *sc = arg; 727 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 728 bus_space_tag_t t = sc->sc_memt; 729 bus_space_handle_t mac = sc->sc_memh; 730 int s; 731 u_int32_t v; 732 733 /* unload collisions counters */ 734 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 735 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 736 ifp->if_collisions += v + 737 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 738 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 739 ifp->if_oerrors += v; 740 741 /* read error counters */ 742 ifp->if_ierrors += 743 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 744 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 745 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 746 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 747 748 /* clear the hardware counters */ 749 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 750 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 751 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 752 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 753 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 754 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 755 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 756 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 757 758 s = splnet(); 759 mii_tick(&sc->sc_mii); 760 splx(s); 761 762 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 763 } 764 765 int 766 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 767 u_int32_t clr, u_int32_t set) 768 { 769 int i; 770 u_int32_t reg; 771 772 for (i = TRIES; i--; DELAY(100)) { 773 reg = bus_space_read_4(sc->sc_memt, h, r); 774 if ((reg & clr) == 0 && (reg & set) == set) 775 return (1); 776 } 777 778 return (0); 779 } 780 781 void 782 cas_reset(struct cas_softc *sc) 783 { 784 bus_space_tag_t t = sc->sc_memt; 785 bus_space_handle_t h = sc->sc_memh; 786 int s; 787 788 s = splnet(); 789 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 790 cas_reset_rx(sc); 791 cas_reset_tx(sc); 792 793 /* Disable interrupts */ 794 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 795 796 /* Do a full reset */ 797 bus_space_write_4(t, h, CAS_RESET, 798 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 799 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 800 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 801 splx(s); 802 } 803 804 805 /* 806 * cas_rxdrain: 807 * 808 * Drain the receive queue. 809 */ 810 void 811 cas_rxdrain(struct cas_softc *sc) 812 { 813 /* Nothing to do yet. */ 814 } 815 816 /* 817 * Reset the whole thing. 818 */ 819 void 820 cas_stop(struct ifnet *ifp, int disable) 821 { 822 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 823 struct cas_sxd *sd; 824 u_int32_t i; 825 826 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 827 828 callout_stop(&sc->sc_tick_ch); 829 830 /* 831 * Mark the interface down and cancel the watchdog timer. 832 */ 833 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 834 ifp->if_timer = 0; 835 836 mii_down(&sc->sc_mii); 837 838 cas_reset_rx(sc); 839 cas_reset_tx(sc); 840 841 /* 842 * Release any queued transmit buffers. 843 */ 844 for (i = 0; i < CAS_NTXDESC; i++) { 845 sd = &sc->sc_txd[i]; 846 if (sd->sd_mbuf != NULL) { 847 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 848 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 849 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 850 m_freem(sd->sd_mbuf); 851 sd->sd_mbuf = NULL; 852 } 853 } 854 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 855 856 if (disable) 857 cas_rxdrain(sc); 858 } 859 860 861 /* 862 * Reset the receiver 863 */ 864 int 865 cas_reset_rx(struct cas_softc *sc) 866 { 867 bus_space_tag_t t = sc->sc_memt; 868 bus_space_handle_t h = sc->sc_memh; 869 870 /* 871 * Resetting while DMA is in progress can cause a bus hang, so we 872 * disable DMA first. 873 */ 874 cas_disable_rx(sc); 875 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 876 /* Wait till it finishes */ 877 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 878 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 879 /* Wait 5ms extra. */ 880 delay(5000); 881 882 /* Finally, reset the ERX */ 883 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 884 /* Wait till it finishes */ 885 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 886 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 887 return (1); 888 } 889 return (0); 890 } 891 892 893 /* 894 * Reset the transmitter 895 */ 896 int 897 cas_reset_tx(struct cas_softc *sc) 898 { 899 bus_space_tag_t t = sc->sc_memt; 900 bus_space_handle_t h = sc->sc_memh; 901 902 /* 903 * Resetting while DMA is in progress can cause a bus hang, so we 904 * disable DMA first. 905 */ 906 cas_disable_tx(sc); 907 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 908 /* Wait till it finishes */ 909 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 910 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 911 /* Wait 5ms extra. */ 912 delay(5000); 913 914 /* Finally, reset the ETX */ 915 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 916 /* Wait till it finishes */ 917 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 918 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 919 return (1); 920 } 921 return (0); 922 } 923 924 /* 925 * Disable receiver. 926 */ 927 int 928 cas_disable_rx(struct cas_softc *sc) 929 { 930 bus_space_tag_t t = sc->sc_memt; 931 bus_space_handle_t h = sc->sc_memh; 932 u_int32_t cfg; 933 934 /* Flip the enable bit */ 935 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 936 cfg &= ~CAS_MAC_RX_ENABLE; 937 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 938 939 /* Wait for it to finish */ 940 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 941 } 942 943 /* 944 * Disable transmitter. 945 */ 946 int 947 cas_disable_tx(struct cas_softc *sc) 948 { 949 bus_space_tag_t t = sc->sc_memt; 950 bus_space_handle_t h = sc->sc_memh; 951 u_int32_t cfg; 952 953 /* Flip the enable bit */ 954 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 955 cfg &= ~CAS_MAC_TX_ENABLE; 956 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 957 958 /* Wait for it to finish */ 959 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 960 } 961 962 /* 963 * Initialize interface. 964 */ 965 int 966 cas_meminit(struct cas_softc *sc) 967 { 968 struct cas_rxsoft *rxs; 969 int i, error; 970 971 rxs = (void *)&error; 972 973 /* 974 * Initialize the transmit descriptor ring. 975 */ 976 for (i = 0; i < CAS_NTXDESC; i++) { 977 sc->sc_txdescs[i].cd_flags = 0; 978 sc->sc_txdescs[i].cd_addr = 0; 979 } 980 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 981 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 982 983 /* 984 * Initialize the receive descriptor and receive job 985 * descriptor rings. 986 */ 987 for (i = 0; i < CAS_NRXDESC; i++) 988 CAS_INIT_RXDESC(sc, i, i); 989 sc->sc_rxdptr = 0; 990 sc->sc_rxptr = 0; 991 992 /* 993 * Initialize the receive completion ring. 994 */ 995 for (i = 0; i < CAS_NRXCOMP; i++) { 996 sc->sc_rxcomps[i].cc_word[0] = 0; 997 sc->sc_rxcomps[i].cc_word[1] = 0; 998 sc->sc_rxcomps[i].cc_word[2] = 0; 999 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1000 CAS_CDRXCSYNC(sc, i, 1001 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1002 } 1003 1004 return (0); 1005 } 1006 1007 int 1008 cas_ringsize(int sz) 1009 { 1010 switch (sz) { 1011 case 32: 1012 return CAS_RING_SZ_32; 1013 case 64: 1014 return CAS_RING_SZ_64; 1015 case 128: 1016 return CAS_RING_SZ_128; 1017 case 256: 1018 return CAS_RING_SZ_256; 1019 case 512: 1020 return CAS_RING_SZ_512; 1021 case 1024: 1022 return CAS_RING_SZ_1024; 1023 case 2048: 1024 return CAS_RING_SZ_2048; 1025 case 4096: 1026 return CAS_RING_SZ_4096; 1027 case 8192: 1028 return CAS_RING_SZ_8192; 1029 default: 1030 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1031 sz); 1032 return CAS_RING_SZ_32; 1033 } 1034 } 1035 1036 int 1037 cas_cringsize(int sz) 1038 { 1039 int i; 1040 1041 for (i = 0; i < 9; i++) 1042 if (sz == (128 << i)) 1043 return i; 1044 1045 aprint_error("cas: invalid completion ring size %d\n", sz); 1046 return 128; 1047 } 1048 1049 /* 1050 * Initialization of interface; set up initialization block 1051 * and transmit/receive descriptor rings. 1052 */ 1053 int 1054 cas_init(struct ifnet *ifp) 1055 { 1056 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1057 bus_space_tag_t t = sc->sc_memt; 1058 bus_space_handle_t h = sc->sc_memh; 1059 int s; 1060 u_int max_frame_size; 1061 u_int32_t v; 1062 1063 s = splnet(); 1064 1065 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1066 /* 1067 * Initialization sequence. The numbered steps below correspond 1068 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1069 * Channel Engine manual (part of the PCIO manual). 1070 * See also the STP2002-STQ document from Sun Microsystems. 1071 */ 1072 1073 /* step 1 & 2. Reset the Ethernet Channel */ 1074 cas_stop(ifp, 0); 1075 cas_reset(sc); 1076 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1077 1078 /* Re-initialize the MIF */ 1079 cas_mifinit(sc); 1080 1081 /* step 3. Setup data structures in host memory */ 1082 cas_meminit(sc); 1083 1084 /* step 4. TX MAC registers & counters */ 1085 cas_init_regs(sc); 1086 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1087 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1088 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1089 1090 /* step 5. RX MAC registers & counters */ 1091 cas_iff(sc); 1092 1093 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1094 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1095 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1096 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1097 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1098 1099 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1100 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1101 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1102 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1103 1104 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1105 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1106 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1107 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1108 1109 if (CAS_PLUS(sc)) { 1110 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1111 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1112 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1113 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1114 CAS_CDRXADDR2(sc, 0)); 1115 } 1116 1117 /* step 8. Global Configuration & Interrupt Mask */ 1118 cas_estintr(sc, CAS_INTR_REG); 1119 1120 /* step 9. ETX Configuration: use mostly default values */ 1121 1122 /* Enable DMA */ 1123 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1124 bus_space_write_4(t, h, CAS_TX_CONFIG, 1125 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1126 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1127 1128 /* step 10. ERX Configuration */ 1129 1130 /* Encode Receive Descriptor ring size */ 1131 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1132 if (CAS_PLUS(sc)) 1133 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1134 1135 /* Encode Receive Completion ring size */ 1136 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1137 1138 /* Enable DMA */ 1139 bus_space_write_4(t, h, CAS_RX_CONFIG, 1140 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1141 1142 /* 1143 * The following value is for an OFF Threshold of about 3/4 full 1144 * and an ON Threshold of 1/4 full. 1145 */ 1146 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1147 (3 * sc->sc_rxfifosize / 256) | 1148 ((sc->sc_rxfifosize / 256) << 12)); 1149 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1150 1151 /* step 11. Configure Media */ 1152 mii_ifmedia_change(&sc->sc_mii); 1153 1154 /* step 12. RX_MAC Configuration Register */ 1155 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1156 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1157 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1158 1159 /* step 14. Issue Transmit Pending command */ 1160 1161 /* step 15. Give the receiver a swift kick */ 1162 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1163 if (CAS_PLUS(sc)) 1164 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1165 1166 /* Start the one second timer. */ 1167 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1168 1169 ifp->if_flags |= IFF_RUNNING; 1170 ifp->if_flags &= ~IFF_OACTIVE; 1171 ifp->if_timer = 0; 1172 splx(s); 1173 1174 return (0); 1175 } 1176 1177 void 1178 cas_init_regs(struct cas_softc *sc) 1179 { 1180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1181 bus_space_tag_t t = sc->sc_memt; 1182 bus_space_handle_t h = sc->sc_memh; 1183 const u_char *laddr = CLLADDR(ifp->if_sadl); 1184 u_int32_t v, r; 1185 1186 /* These regs are not cleared on reset */ 1187 sc->sc_inited = 0; 1188 if (!sc->sc_inited) { 1189 /* Load recommended values */ 1190 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1191 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1192 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1193 1194 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1195 /* Max frame and max burst size */ 1196 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1197 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1198 1199 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1200 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1201 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1202 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1203 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1204 ((laddr[5]<<8)|laddr[4])&0x3ff); 1205 1206 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1207 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1208 bus_space_write_4(t, h, r, 0); 1209 1210 /* MAC control addr set to 0:1:c2:0:1:80 */ 1211 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1212 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1213 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1214 1215 /* MAC filter addr set to 0:0:0:0:0:0 */ 1216 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1217 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1218 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1219 1220 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1221 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1222 1223 /* Hash table initialized to 0 */ 1224 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1225 bus_space_write_4(t, h, r, 0); 1226 1227 sc->sc_inited = 1; 1228 } 1229 1230 /* Counters need to be zeroed */ 1231 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1232 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1233 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1234 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1235 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1236 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1237 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1238 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1239 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1240 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1241 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1242 1243 /* Un-pause stuff */ 1244 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1245 1246 /* 1247 * Set the station address. 1248 */ 1249 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1250 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1251 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1252 } 1253 1254 /* 1255 * Receive interrupt. 1256 */ 1257 int 1258 cas_rint(struct cas_softc *sc) 1259 { 1260 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1261 bus_space_tag_t t = sc->sc_memt; 1262 bus_space_handle_t h = sc->sc_memh; 1263 struct cas_rxsoft *rxs; 1264 struct mbuf *m; 1265 u_int64_t word[4]; 1266 int len, off, idx; 1267 int i, skip; 1268 void *cp; 1269 1270 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1271 CAS_CDRXCSYNC(sc, i, 1272 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1273 1274 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1275 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1276 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1277 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1278 1279 /* Stop if the hardware still owns the descriptor. */ 1280 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1281 break; 1282 1283 len = CAS_RC1_HDR_LEN(word[1]); 1284 if (len > 0) { 1285 off = CAS_RC1_HDR_OFF(word[1]); 1286 idx = CAS_RC1_HDR_IDX(word[1]); 1287 rxs = &sc->sc_rxsoft[idx]; 1288 1289 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1290 idx, off, len)); 1291 1292 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1293 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1294 1295 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1296 m = m_devget(cp, len, 0, ifp, NULL); 1297 1298 if (word[0] & CAS_RC0_RELEASE_HDR) 1299 cas_add_rxbuf(sc, idx); 1300 1301 if (m != NULL) { 1302 1303 /* 1304 * Pass this up to any BPF listeners, but only 1305 * pass it up the stack if its for us. 1306 */ 1307 bpf_mtap(ifp, m); 1308 1309 ifp->if_ipackets++; 1310 m->m_pkthdr.csum_flags = 0; 1311 (*ifp->if_input)(ifp, m); 1312 } else 1313 ifp->if_ierrors++; 1314 } 1315 1316 len = CAS_RC0_DATA_LEN(word[0]); 1317 if (len > 0) { 1318 off = CAS_RC0_DATA_OFF(word[0]); 1319 idx = CAS_RC0_DATA_IDX(word[0]); 1320 rxs = &sc->sc_rxsoft[idx]; 1321 1322 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1323 idx, off, len)); 1324 1325 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1326 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1327 1328 /* XXX We should not be copying the packet here. */ 1329 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1330 m = m_devget(cp, len, 0, ifp, NULL); 1331 1332 if (word[0] & CAS_RC0_RELEASE_DATA) 1333 cas_add_rxbuf(sc, idx); 1334 1335 if (m != NULL) { 1336 /* 1337 * Pass this up to any BPF listeners, but only 1338 * pass it up the stack if its for us. 1339 */ 1340 bpf_mtap(ifp, m); 1341 1342 ifp->if_ipackets++; 1343 m->m_pkthdr.csum_flags = 0; 1344 (*ifp->if_input)(ifp, m); 1345 } else 1346 ifp->if_ierrors++; 1347 } 1348 1349 if (word[0] & CAS_RC0_SPLIT) 1350 aprint_error_dev(sc->sc_dev, "split packet\n"); 1351 1352 skip = CAS_RC0_SKIP(word[0]); 1353 } 1354 1355 while (sc->sc_rxptr != i) { 1356 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1357 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1358 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1359 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1360 CAS_DMA_WRITE(CAS_RC3_OWN); 1361 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1362 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1363 1364 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1365 } 1366 1367 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1368 1369 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1370 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1371 1372 return (1); 1373 } 1374 1375 /* 1376 * cas_add_rxbuf: 1377 * 1378 * Add a receive buffer to the indicated descriptor. 1379 */ 1380 int 1381 cas_add_rxbuf(struct cas_softc *sc, int idx) 1382 { 1383 bus_space_tag_t t = sc->sc_memt; 1384 bus_space_handle_t h = sc->sc_memh; 1385 1386 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1387 1388 if ((sc->sc_rxdptr % 4) == 0) 1389 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1390 1391 if (++sc->sc_rxdptr == CAS_NRXDESC) 1392 sc->sc_rxdptr = 0; 1393 1394 return (0); 1395 } 1396 1397 int 1398 cas_eint(struct cas_softc *sc, u_int status) 1399 { 1400 char bits[128]; 1401 if ((status & CAS_INTR_MIF) != 0) { 1402 DPRINTF(sc, ("%s: link status changed\n", 1403 device_xname(sc->sc_dev))); 1404 return (1); 1405 } 1406 1407 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1408 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1409 return (1); 1410 } 1411 1412 int 1413 cas_pint(struct cas_softc *sc) 1414 { 1415 bus_space_tag_t t = sc->sc_memt; 1416 bus_space_handle_t seb = sc->sc_memh; 1417 u_int32_t status; 1418 1419 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1420 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1421 #ifdef CAS_DEBUG 1422 if (status) 1423 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1424 #endif 1425 return (1); 1426 } 1427 1428 int 1429 cas_intr(void *v) 1430 { 1431 struct cas_softc *sc = (struct cas_softc *)v; 1432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1433 bus_space_tag_t t = sc->sc_memt; 1434 bus_space_handle_t seb = sc->sc_memh; 1435 u_int32_t status; 1436 int r = 0; 1437 #ifdef CAS_DEBUG 1438 char bits[128]; 1439 #endif 1440 1441 sc->sc_ev_intr.ev_count++; 1442 1443 status = bus_space_read_4(t, seb, CAS_STATUS); 1444 #ifdef CAS_DEBUG 1445 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1446 #endif 1447 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1448 device_xname(sc->sc_dev), (status>>19), bits)); 1449 1450 if ((status & CAS_INTR_PCS) != 0) 1451 r |= cas_pint(sc); 1452 1453 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1454 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1455 r |= cas_eint(sc, status); 1456 1457 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1458 r |= cas_tint(sc, status); 1459 1460 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1461 r |= cas_rint(sc); 1462 1463 /* We should eventually do more than just print out error stats. */ 1464 if (status & CAS_INTR_TX_MAC) { 1465 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1466 #ifdef CAS_DEBUG 1467 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1468 printf("%s: MAC tx fault, status %x\n", 1469 device_xname(sc->sc_dev), txstat); 1470 #endif 1471 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1472 cas_init(ifp); 1473 } 1474 if (status & CAS_INTR_RX_MAC) { 1475 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1476 #ifdef CAS_DEBUG 1477 if (rxstat & ~CAS_MAC_RX_DONE) 1478 printf("%s: MAC rx fault, status %x\n", 1479 device_xname(sc->sc_dev), rxstat); 1480 #endif 1481 /* 1482 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1483 * due to a silicon bug so handle them silently. 1484 */ 1485 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1486 ifp->if_ierrors++; 1487 cas_init(ifp); 1488 } 1489 #ifdef CAS_DEBUG 1490 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1491 printf("%s: MAC rx fault, status %x\n", 1492 device_xname(sc->sc_dev), rxstat); 1493 #endif 1494 } 1495 #if NRND > 0 1496 rnd_add_uint32(&sc->rnd_source, status); 1497 #endif 1498 return (r); 1499 } 1500 1501 1502 void 1503 cas_watchdog(struct ifnet *ifp) 1504 { 1505 struct cas_softc *sc = ifp->if_softc; 1506 1507 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1508 "CAS_MAC_RX_CONFIG %x\n", 1509 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1510 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1511 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1512 1513 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1514 ++ifp->if_oerrors; 1515 1516 /* Try to get more packets going. */ 1517 cas_init(ifp); 1518 } 1519 1520 /* 1521 * Initialize the MII Management Interface 1522 */ 1523 void 1524 cas_mifinit(struct cas_softc *sc) 1525 { 1526 bus_space_tag_t t = sc->sc_memt; 1527 bus_space_handle_t mif = sc->sc_memh; 1528 1529 /* Configure the MIF in frame mode */ 1530 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1531 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1532 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1533 } 1534 1535 /* 1536 * MII interface 1537 * 1538 * The Cassini MII interface supports at least three different operating modes: 1539 * 1540 * Bitbang mode is implemented using data, clock and output enable registers. 1541 * 1542 * Frame mode is implemented by loading a complete frame into the frame 1543 * register and polling the valid bit for completion. 1544 * 1545 * Polling mode uses the frame register but completion is indicated by 1546 * an interrupt. 1547 * 1548 */ 1549 int 1550 cas_mii_readreg(device_t self, int phy, int reg) 1551 { 1552 struct cas_softc *sc = device_private(self); 1553 bus_space_tag_t t = sc->sc_memt; 1554 bus_space_handle_t mif = sc->sc_memh; 1555 int n; 1556 u_int32_t v; 1557 1558 #ifdef CAS_DEBUG 1559 if (sc->sc_debug) 1560 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1561 #endif 1562 1563 /* Construct the frame command */ 1564 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1565 CAS_MIF_FRAME_READ; 1566 1567 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1568 for (n = 0; n < 100; n++) { 1569 DELAY(1); 1570 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1571 if (v & CAS_MIF_FRAME_TA0) 1572 return (v & CAS_MIF_FRAME_DATA); 1573 } 1574 1575 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1576 return (0); 1577 } 1578 1579 void 1580 cas_mii_writereg(device_t self, int phy, int reg, int val) 1581 { 1582 struct cas_softc *sc = device_private(self); 1583 bus_space_tag_t t = sc->sc_memt; 1584 bus_space_handle_t mif = sc->sc_memh; 1585 int n; 1586 u_int32_t v; 1587 1588 #ifdef CAS_DEBUG 1589 if (sc->sc_debug) 1590 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1591 phy, reg, val); 1592 #endif 1593 1594 /* Construct the frame command */ 1595 v = CAS_MIF_FRAME_WRITE | 1596 (phy << CAS_MIF_PHY_SHIFT) | 1597 (reg << CAS_MIF_REG_SHIFT) | 1598 (val & CAS_MIF_FRAME_DATA); 1599 1600 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1601 for (n = 0; n < 100; n++) { 1602 DELAY(1); 1603 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1604 if (v & CAS_MIF_FRAME_TA0) 1605 return; 1606 } 1607 1608 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1609 } 1610 1611 void 1612 cas_mii_statchg(device_t self) 1613 { 1614 struct cas_softc *sc = device_private(self); 1615 #ifdef CAS_DEBUG 1616 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1617 #endif 1618 bus_space_tag_t t = sc->sc_memt; 1619 bus_space_handle_t mac = sc->sc_memh; 1620 u_int32_t v; 1621 1622 #ifdef CAS_DEBUG 1623 if (sc->sc_debug) 1624 printf("cas_mii_statchg: status change: phy = %d\n", 1625 sc->sc_phys[instance]); 1626 #endif 1627 1628 /* Set tx full duplex options */ 1629 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1630 delay(10000); /* reg must be cleared and delay before changing. */ 1631 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1632 CAS_MAC_TX_ENABLE; 1633 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1634 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1635 } 1636 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1637 1638 /* XIF Configuration */ 1639 v = CAS_MAC_XIF_TX_MII_ENA; 1640 v |= CAS_MAC_XIF_LINK_LED; 1641 1642 /* MII needs echo disable if half duplex. */ 1643 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1644 /* turn on full duplex LED */ 1645 v |= CAS_MAC_XIF_FDPLX_LED; 1646 else 1647 /* half duplex -- disable echo */ 1648 v |= CAS_MAC_XIF_ECHO_DISABL; 1649 1650 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1651 case IFM_1000_T: /* Gigabit using GMII interface */ 1652 case IFM_1000_SX: 1653 v |= CAS_MAC_XIF_GMII_MODE; 1654 break; 1655 default: 1656 v &= ~CAS_MAC_XIF_GMII_MODE; 1657 } 1658 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1659 } 1660 1661 int 1662 cas_pcs_readreg(device_t self, int phy, int reg) 1663 { 1664 struct cas_softc *sc = device_private(self); 1665 bus_space_tag_t t = sc->sc_memt; 1666 bus_space_handle_t pcs = sc->sc_memh; 1667 1668 #ifdef CAS_DEBUG 1669 if (sc->sc_debug) 1670 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1671 #endif 1672 1673 if (phy != CAS_PHYAD_EXTERNAL) 1674 return (0); 1675 1676 switch (reg) { 1677 case MII_BMCR: 1678 reg = CAS_MII_CONTROL; 1679 break; 1680 case MII_BMSR: 1681 reg = CAS_MII_STATUS; 1682 break; 1683 case MII_ANAR: 1684 reg = CAS_MII_ANAR; 1685 break; 1686 case MII_ANLPAR: 1687 reg = CAS_MII_ANLPAR; 1688 break; 1689 case MII_EXTSR: 1690 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1691 default: 1692 return (0); 1693 } 1694 1695 return bus_space_read_4(t, pcs, reg); 1696 } 1697 1698 void 1699 cas_pcs_writereg(device_t self, int phy, int reg, int val) 1700 { 1701 struct cas_softc *sc = device_private(self); 1702 bus_space_tag_t t = sc->sc_memt; 1703 bus_space_handle_t pcs = sc->sc_memh; 1704 int reset = 0; 1705 1706 #ifdef CAS_DEBUG 1707 if (sc->sc_debug) 1708 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1709 phy, reg, val); 1710 #endif 1711 1712 if (phy != CAS_PHYAD_EXTERNAL) 1713 return; 1714 1715 if (reg == MII_ANAR) 1716 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1717 1718 switch (reg) { 1719 case MII_BMCR: 1720 reset = (val & CAS_MII_CONTROL_RESET); 1721 reg = CAS_MII_CONTROL; 1722 break; 1723 case MII_BMSR: 1724 reg = CAS_MII_STATUS; 1725 break; 1726 case MII_ANAR: 1727 reg = CAS_MII_ANAR; 1728 break; 1729 case MII_ANLPAR: 1730 reg = CAS_MII_ANLPAR; 1731 break; 1732 default: 1733 return; 1734 } 1735 1736 bus_space_write_4(t, pcs, reg, val); 1737 1738 if (reset) 1739 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1740 1741 if (reg == CAS_MII_ANAR || reset) 1742 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1743 CAS_MII_CONFIG_ENABLE); 1744 } 1745 1746 int 1747 cas_mediachange(struct ifnet *ifp) 1748 { 1749 struct cas_softc *sc = ifp->if_softc; 1750 struct mii_data *mii = &sc->sc_mii; 1751 1752 if (mii->mii_instance) { 1753 struct mii_softc *miisc; 1754 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1755 mii_phy_reset(miisc); 1756 } 1757 1758 return (mii_mediachg(&sc->sc_mii)); 1759 } 1760 1761 void 1762 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1763 { 1764 struct cas_softc *sc = ifp->if_softc; 1765 1766 mii_pollstat(&sc->sc_mii); 1767 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1768 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1769 } 1770 1771 /* 1772 * Process an ioctl request. 1773 */ 1774 int 1775 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1776 { 1777 struct cas_softc *sc = ifp->if_softc; 1778 int s, error = 0; 1779 1780 s = splnet(); 1781 1782 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1783 error = 0; 1784 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1785 ; 1786 else if (ifp->if_flags & IFF_RUNNING) { 1787 /* 1788 * Multicast list has changed; set the hardware filter 1789 * accordingly. 1790 */ 1791 cas_iff(sc); 1792 } 1793 } 1794 1795 splx(s); 1796 return (error); 1797 } 1798 1799 static bool 1800 cas_suspend(device_t self, const pmf_qual_t *qual) 1801 { 1802 struct cas_softc *sc = device_private(self); 1803 bus_space_tag_t t = sc->sc_memt; 1804 bus_space_handle_t h = sc->sc_memh; 1805 1806 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1807 if (sc->sc_ih != NULL) { 1808 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1809 sc->sc_ih = NULL; 1810 } 1811 1812 return true; 1813 } 1814 1815 static bool 1816 cas_resume(device_t self, const pmf_qual_t *qual) 1817 { 1818 struct cas_softc *sc = device_private(self); 1819 1820 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1821 } 1822 1823 static bool 1824 cas_estintr(struct cas_softc *sc, int what) 1825 { 1826 bus_space_tag_t t = sc->sc_memt; 1827 bus_space_handle_t h = sc->sc_memh; 1828 const char *intrstr = NULL; 1829 1830 /* PCI interrupts */ 1831 if (what & CAS_INTR_PCI) { 1832 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle); 1833 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1834 IPL_NET, cas_intr, sc); 1835 if (sc->sc_ih == NULL) { 1836 aprint_error_dev(sc->sc_dev, 1837 "unable to establish interrupt"); 1838 if (intrstr != NULL) 1839 aprint_error(" at %s", intrstr); 1840 aprint_error("\n"); 1841 return false; 1842 } 1843 1844 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1845 } 1846 1847 /* Interrupt register */ 1848 if (what & CAS_INTR_REG) { 1849 bus_space_write_4(t, h, CAS_INTMASK, 1850 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1851 CAS_INTR_TX_TAG_ERR| 1852 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1853 CAS_INTR_RX_TAG_ERR| 1854 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1855 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1856 CAS_INTR_BERR)); 1857 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1858 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1859 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1860 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1861 } 1862 return true; 1863 } 1864 1865 bool 1866 cas_shutdown(device_t self, int howto) 1867 { 1868 struct cas_softc *sc = device_private(self); 1869 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1870 1871 cas_stop(ifp, 1); 1872 1873 return true; 1874 } 1875 1876 void 1877 cas_iff(struct cas_softc *sc) 1878 { 1879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1880 struct ethercom *ec = &sc->sc_ethercom; 1881 struct ether_multi *enm; 1882 struct ether_multistep step; 1883 bus_space_tag_t t = sc->sc_memt; 1884 bus_space_handle_t h = sc->sc_memh; 1885 u_int32_t crc, hash[16], rxcfg; 1886 int i; 1887 1888 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1889 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1890 CAS_MAC_RX_PROMISC_GRP); 1891 ifp->if_flags &= ~IFF_ALLMULTI; 1892 1893 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1894 ifp->if_flags |= IFF_ALLMULTI; 1895 if (ifp->if_flags & IFF_PROMISC) 1896 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1897 else 1898 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1899 } else { 1900 /* 1901 * Set up multicast address filter by passing all multicast 1902 * addresses through a crc generator, and then using the 1903 * high order 8 bits as an index into the 256 bit logical 1904 * address filter. The high order 4 bits selects the word, 1905 * while the other 4 bits select the bit within the word 1906 * (where bit 0 is the MSB). 1907 */ 1908 1909 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1910 1911 /* Clear hash table */ 1912 for (i = 0; i < 16; i++) 1913 hash[i] = 0; 1914 1915 ETHER_FIRST_MULTI(step, ec, enm); 1916 while (enm != NULL) { 1917 crc = ether_crc32_le(enm->enm_addrlo, 1918 ETHER_ADDR_LEN); 1919 1920 /* Just want the 8 most significant bits. */ 1921 crc >>= 24; 1922 1923 /* Set the corresponding bit in the filter. */ 1924 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1925 1926 ETHER_NEXT_MULTI(step, enm); 1927 } 1928 1929 /* Now load the hash table into the chip (if we are using it) */ 1930 for (i = 0; i < 16; i++) { 1931 bus_space_write_4(t, h, 1932 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1933 hash[i]); 1934 } 1935 } 1936 1937 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1938 } 1939 1940 int 1941 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1942 { 1943 u_int64_t flags; 1944 u_int32_t cur, frag, i; 1945 bus_dmamap_t map; 1946 1947 cur = frag = *bixp; 1948 map = sc->sc_txd[cur].sd_map; 1949 1950 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1951 BUS_DMA_NOWAIT) != 0) { 1952 return (ENOBUFS); 1953 } 1954 1955 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1956 bus_dmamap_unload(sc->sc_dmatag, map); 1957 return (ENOBUFS); 1958 } 1959 1960 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1961 BUS_DMASYNC_PREWRITE); 1962 1963 for (i = 0; i < map->dm_nsegs; i++) { 1964 sc->sc_txdescs[frag].cd_addr = 1965 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1966 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1967 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1968 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1969 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1970 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1971 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1972 BUS_DMASYNC_PREWRITE); 1973 cur = frag; 1974 if (++frag == CAS_NTXDESC) 1975 frag = 0; 1976 } 1977 1978 sc->sc_tx_cnt += map->dm_nsegs; 1979 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1980 sc->sc_txd[cur].sd_map = map; 1981 sc->sc_txd[cur].sd_mbuf = mhead; 1982 1983 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1984 1985 *bixp = frag; 1986 1987 /* sync descriptors */ 1988 1989 return (0); 1990 } 1991 1992 /* 1993 * Transmit interrupt. 1994 */ 1995 int 1996 cas_tint(struct cas_softc *sc, u_int32_t status) 1997 { 1998 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1999 struct cas_sxd *sd; 2000 u_int32_t cons, comp; 2001 2002 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2003 cons = sc->sc_tx_cons; 2004 while (cons != comp) { 2005 sd = &sc->sc_txd[cons]; 2006 if (sd->sd_mbuf != NULL) { 2007 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2008 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2009 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2010 m_freem(sd->sd_mbuf); 2011 sd->sd_mbuf = NULL; 2012 ifp->if_opackets++; 2013 } 2014 sc->sc_tx_cnt--; 2015 if (++cons == CAS_NTXDESC) 2016 cons = 0; 2017 } 2018 sc->sc_tx_cons = cons; 2019 2020 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2021 ifp->if_flags &= ~IFF_OACTIVE; 2022 if (sc->sc_tx_cnt == 0) 2023 ifp->if_timer = 0; 2024 2025 cas_start(ifp); 2026 2027 return (1); 2028 } 2029 2030 void 2031 cas_start(struct ifnet *ifp) 2032 { 2033 struct cas_softc *sc = ifp->if_softc; 2034 struct mbuf *m; 2035 u_int32_t bix; 2036 2037 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2038 return; 2039 2040 bix = sc->sc_tx_prod; 2041 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2042 IFQ_POLL(&ifp->if_snd, m); 2043 if (m == NULL) 2044 break; 2045 2046 /* 2047 * If BPF is listening on this interface, let it see the 2048 * packet before we commit it to the wire. 2049 */ 2050 bpf_mtap(ifp, m); 2051 2052 /* 2053 * Encapsulate this packet and start it going... 2054 * or fail... 2055 */ 2056 if (cas_encap(sc, m, &bix)) { 2057 ifp->if_flags |= IFF_OACTIVE; 2058 break; 2059 } 2060 2061 IFQ_DEQUEUE(&ifp->if_snd, m); 2062 ifp->if_timer = 5; 2063 } 2064 2065 sc->sc_tx_prod = bix; 2066 } 2067