1 /* $NetBSD: if_cas.c,v 1.43 2020/07/02 09:02:04 msaitoh Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.43 2020/07/02 09:02:04 msaitoh Exp $"); 48 49 #ifndef _MODULE 50 #include "opt_inet.h" 51 #endif 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/syslog.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/module.h> 65 66 #include <machine/endian.h> 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/tcp.h> 79 #include <netinet/udp.h> 80 #endif 81 82 #include <net/bpf.h> 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 #include <sys/rndsource.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 #include <dev/mii/mii_bitbang.h> 91 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcidevs.h> 95 #include <prop/proplib.h> 96 97 #include <dev/pci/if_casreg.h> 98 #include <dev/pci/if_casvar.h> 99 100 #define TRIES 10000 101 102 static bool cas_estintr(struct cas_softc *sc, int); 103 bool cas_shutdown(device_t, int); 104 static bool cas_suspend(device_t, const pmf_qual_t *); 105 static bool cas_resume(device_t, const pmf_qual_t *); 106 static int cas_detach(device_t, int); 107 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 108 109 int cas_match(device_t, cfdata_t, void *); 110 void cas_attach(device_t, device_t, void *); 111 112 113 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 114 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 115 DVF_DETACH_SHUTDOWN); 116 117 int cas_pci_readvpd(struct cas_softc *, struct pci_attach_args *, uint8_t *); 118 119 void cas_config(struct cas_softc *, const uint8_t *); 120 void cas_start(struct ifnet *); 121 void cas_stop(struct ifnet *, int); 122 int cas_ioctl(struct ifnet *, u_long, void *); 123 void cas_tick(void *); 124 void cas_watchdog(struct ifnet *); 125 int cas_init(struct ifnet *); 126 void cas_init_regs(struct cas_softc *); 127 int cas_ringsize(int); 128 int cas_cringsize(int); 129 int cas_meminit(struct cas_softc *); 130 void cas_mifinit(struct cas_softc *); 131 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 132 uint32_t, uint32_t); 133 void cas_reset(struct cas_softc *); 134 int cas_reset_rx(struct cas_softc *); 135 int cas_reset_tx(struct cas_softc *); 136 int cas_disable_rx(struct cas_softc *); 137 int cas_disable_tx(struct cas_softc *); 138 void cas_rxdrain(struct cas_softc *); 139 int cas_add_rxbuf(struct cas_softc *, int); 140 void cas_iff(struct cas_softc *); 141 int cas_encap(struct cas_softc *, struct mbuf *, uint32_t *); 142 143 /* MII methods & callbacks */ 144 int cas_mii_readreg(device_t, int, int, uint16_t*); 145 int cas_mii_writereg(device_t, int, int, uint16_t); 146 void cas_mii_statchg(struct ifnet *); 147 int cas_pcs_readreg(device_t, int, int, uint16_t *); 148 int cas_pcs_writereg(device_t, int, int, uint16_t); 149 150 int cas_mediachange(struct ifnet *); 151 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 152 153 int cas_eint(struct cas_softc *, u_int); 154 int cas_rint(struct cas_softc *); 155 int cas_tint(struct cas_softc *, uint32_t); 156 int cas_pint(struct cas_softc *); 157 int cas_intr(void *); 158 159 #ifdef CAS_DEBUG 160 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 161 printf x 162 #else 163 #define DPRINTF(sc, x) /* nothing */ 164 #endif 165 166 static const struct cas_pci_dev { 167 uint16_t cpd_vendor; 168 uint16_t cpd_device; 169 int cpd_variant; 170 } cas_pci_devlist[] = { 171 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_CASSINI, CAS_CAS }, 172 { PCI_VENDOR_NS, PCI_PRODUCT_NS_SATURN, CAS_SATURN }, 173 { 0, 0, 0 } 174 }; 175 176 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 177 #define CAS_PHY_INTERFACE "phy-interface" 178 #define CAS_PHY_TYPE "phy-type" 179 #define CAS_PHY_TYPE_PCS "pcs" 180 181 int 182 cas_match(device_t parent, cfdata_t cf, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 int i; 186 187 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 188 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 189 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) 190 return 1; 191 } 192 193 return 0; 194 } 195 196 #define PROMHDR_PTR_DATA 0x18 197 #define PROMDATA_PTR_VPD 0x08 198 #define PROMDATA_DATA2 0x0a 199 200 static const uint8_t cas_promhdr[] = { 0x55, 0xaa }; 201 static const uint8_t cas_promdat[] = { 202 'P', 'C', 'I', 'R', 203 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 204 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 205 }; 206 static const uint8_t cas_promdat_ns[] = { 207 'P', 'C', 'I', 'R', 208 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 209 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 210 }; 211 212 static const uint8_t cas_promdat2[] = { 213 0x18, 0x00, /* structure length */ 214 0x00, /* structure revision */ 215 0x00, /* interface revision */ 216 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 217 PCI_CLASS_NETWORK /* class code */ 218 }; 219 220 #define CAS_LMA_MAXNUM 4 221 int 222 cas_pci_readvpd(struct cas_softc *sc, struct pci_attach_args *pa, 223 uint8_t *enaddr) 224 { 225 struct pci_vpd_largeres *res; 226 struct pci_vpd *vpd; 227 bus_space_handle_t romh; 228 bus_space_tag_t romt; 229 bus_size_t romsize = 0; 230 uint8_t enaddrs[CAS_LMA_MAXNUM][ETHER_ADDR_LEN]; 231 bool pcs[4] = {false, false, false, false}; 232 uint8_t buf[32], *desc; 233 pcireg_t address; 234 int dataoff, vpdoff, len, lma = 0, phy = 0; 235 int i, rv = -1; 236 237 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 238 &romt, &romh, NULL, &romsize)) 239 return (-1); 240 241 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 242 address |= PCI_MAPREG_ROM_ENABLE; 243 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 244 245 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 246 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 247 goto fail; 248 249 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 250 if (dataoff < 0x1c) 251 goto fail; 252 253 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 254 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 255 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 256 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 257 goto fail; 258 259 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 260 if (vpdoff < 0x1c) 261 goto fail; 262 263 next: 264 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 265 if (!PCI_VPDRES_ISLARGE(buf[0])) 266 goto fail; 267 268 res = (struct pci_vpd_largeres *)buf; 269 vpdoff += sizeof(*res); 270 271 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 272 switch (PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 273 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 274 /* Skip identifier string. */ 275 vpdoff += len; 276 goto next; 277 278 case PCI_VPDRES_TYPE_VPD: 279 #ifdef CAS_DEBUG 280 printf("\n"); 281 for (i = 0; i < len; i++) { 282 uint8_t byte; 283 if (i % 16 == 0) 284 printf("%04x :", i); 285 byte = bus_space_read_1(romt, romh, vpdoff + i); 286 printf(" %02x", byte); 287 if (i % 16 == 15) 288 printf("\n"); 289 } 290 printf("\n"); 291 #endif 292 293 while (len > 0) { 294 bus_space_read_region_1(romt, romh, vpdoff, 295 buf, sizeof(buf)); 296 297 vpd = (struct pci_vpd *)buf; 298 vpdoff += sizeof(*vpd) + vpd->vpd_len; 299 len -= sizeof(*vpd) + vpd->vpd_len; 300 301 /* 302 * We're looking for an "Enhanced" VPD... 303 */ 304 if (vpd->vpd_key0 != 'Z') 305 continue; 306 307 desc = buf + sizeof(*vpd); 308 309 /* 310 * ...which is an instance property... 311 */ 312 if (desc[0] != 'I') 313 continue; 314 desc += 3; 315 316 if (desc[0] == 'B' || desc[1] == ETHER_ADDR_LEN) { 317 /* 318 * ...that's a byte array with the proper 319 * length for a MAC address... 320 */ 321 desc += 2; 322 323 /* 324 * ...named "local-mac-address". 325 */ 326 if (strcmp(desc, CAS_LOCAL_MAC_ADDRESS) != 0) 327 continue; 328 desc += sizeof(CAS_LOCAL_MAC_ADDRESS); 329 330 if (lma == CAS_LMA_MAXNUM) 331 continue; 332 333 memcpy(enaddrs[lma], desc, ETHER_ADDR_LEN); 334 lma++; 335 rv = 0; 336 continue; 337 } else if (desc[0] == 'S') { 338 size_t k; 339 340 /* String */ 341 desc += 2; 342 #ifdef CAS_DEBUG 343 /* ...named "pcs". */ 344 printf("STR: \"%s\"\n", desc); 345 if (strcmp(desc, CAS_PHY_TYPE_PCS) != 0) 346 continue; 347 desc += sizeof(CAS_PHY_TYPE_PCS); 348 printf("STR: \"%s\"\n", desc); 349 #endif 350 /* ...named "phy-interface" or "phy-type". */ 351 if (strcmp(desc, CAS_PHY_INTERFACE) == 0) 352 k = sizeof(CAS_PHY_INTERFACE); 353 else if (strcmp(desc, CAS_PHY_TYPE) == 0) 354 k = sizeof(CAS_PHY_TYPE); 355 else 356 continue; 357 358 desc += k; 359 #ifdef CAS_DEBUG 360 printf("STR: \"%s\"\n", desc); 361 #endif 362 if (strcmp(desc, CAS_PHY_TYPE_PCS) == 0) 363 pcs[phy] = true; 364 phy++; 365 continue; 366 } 367 } 368 break; 369 370 default: 371 goto fail; 372 } 373 374 /* 375 * Multi port card has bridge chip. The device number is fixed: 376 * e.g. 377 * p0: 005:00:0 378 * p1: 005:01:0 379 * p2: 006:02:0 380 * p3: 006:03:0 381 */ 382 if (enaddr != 0) { 383 i = 0; 384 if ((lma > 1) && (pa->pa_device < CAS_LMA_MAXNUM) 385 && (pa->pa_device < lma)) 386 i = pa->pa_device; 387 memcpy(enaddr, enaddrs[i], ETHER_ADDR_LEN); 388 } 389 if (pcs[pa->pa_device]) 390 sc->sc_flags |= CAS_SERDES; 391 fail: 392 if (romsize != 0) 393 bus_space_unmap(romt, romh, romsize); 394 395 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 396 address &= ~PCI_MAPREG_ROM_ENABLE; 397 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 398 399 return (rv); 400 } 401 402 void 403 cas_attach(device_t parent, device_t self, void *aux) 404 { 405 struct pci_attach_args *pa = aux; 406 struct cas_softc *sc = device_private(self); 407 int i; 408 prop_data_t data; 409 uint8_t enaddr[ETHER_ADDR_LEN]; 410 411 sc->sc_dev = self; 412 pci_aprint_devinfo(pa, NULL); 413 sc->sc_rev = PCI_REVISION(pa->pa_class); 414 415 if (pci_dma64_available(pa)) 416 sc->sc_dmatag = pa->pa_dmat64; 417 else 418 sc->sc_dmatag = pa->pa_dmat; 419 420 sc->sc_variant = CAS_UNKNOWN; 421 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 422 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 423 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) { 424 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 425 break; 426 } 427 } 428 aprint_debug_dev(sc->sc_dev, "variant = %d\n", sc->sc_variant); 429 if (sc->sc_variant == CAS_UNKNOWN) { 430 aprint_error_dev(sc->sc_dev, "unknown adaptor\n"); 431 return; 432 } 433 434 #define PCI_CAS_BASEADDR 0x10 435 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 436 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 437 aprint_error_dev(sc->sc_dev, 438 "unable to map device registers\n"); 439 return; 440 } 441 442 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 443 "mac-address")) != NULL) 444 memcpy(enaddr, prop_data_value(data), ETHER_ADDR_LEN); 445 if (cas_pci_readvpd(sc, pa, (data == NULL) ? enaddr : 0) != 0) { 446 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 447 memset(enaddr, 0, sizeof(enaddr)); 448 } 449 450 sc->sc_burst = 16; /* XXX */ 451 452 sc->sc_att_stage = CAS_ATT_BACKEND_0; 453 454 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 455 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 456 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 457 return; 458 } 459 sc->sc_pc = pa->pa_pc; 460 if (!cas_estintr(sc, CAS_INTR_PCI)) { 461 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 462 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 463 return; 464 } 465 466 sc->sc_att_stage = CAS_ATT_BACKEND_1; 467 468 /* 469 * call the main configure 470 */ 471 cas_config(sc, enaddr); 472 473 if (pmf_device_register1(sc->sc_dev, 474 cas_suspend, cas_resume, cas_shutdown)) 475 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 476 else 477 aprint_error_dev(sc->sc_dev, 478 "could not establish power handlers\n"); 479 480 sc->sc_att_stage = CAS_ATT_FINISHED; 481 /*FALLTHROUGH*/ 482 } 483 484 /* 485 * cas_config: 486 * 487 * Attach a Cassini interface to the system. 488 */ 489 void 490 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 491 { 492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 493 struct mii_data *mii = &sc->sc_mii; 494 struct mii_softc *child; 495 uint32_t reg; 496 int i, error; 497 498 /* Make sure the chip is stopped. */ 499 ifp->if_softc = sc; 500 cas_reset(sc); 501 502 /* 503 * Allocate the control data structures, and create and load the 504 * DMA map for it. 505 */ 506 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 507 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 508 1, &sc->sc_cdnseg, 0)) != 0) { 509 aprint_error_dev(sc->sc_dev, 510 "unable to allocate control data, error = %d\n", 511 error); 512 cas_partial_detach(sc, CAS_ATT_0); 513 } 514 515 /* XXX should map this in with correct endianness */ 516 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, 517 sc->sc_cdnseg, sizeof(struct cas_control_data), 518 (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) { 519 aprint_error_dev(sc->sc_dev, 520 "unable to map control data, error = %d\n", error); 521 cas_partial_detach(sc, CAS_ATT_1); 522 } 523 524 if ((error = bus_dmamap_create(sc->sc_dmatag, 525 sizeof(struct cas_control_data), 1, 526 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 527 aprint_error_dev(sc->sc_dev, 528 "unable to create control data DMA map, error = %d\n", 529 error); 530 cas_partial_detach(sc, CAS_ATT_2); 531 } 532 533 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 534 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 535 0)) != 0) { 536 aprint_error_dev(sc->sc_dev, 537 "unable to load control data DMA map, error = %d\n", 538 error); 539 cas_partial_detach(sc, CAS_ATT_3); 540 } 541 542 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 543 544 /* 545 * Create the receive buffer DMA maps. 546 */ 547 for (i = 0; i < CAS_NRXDESC; i++) { 548 bus_dma_segment_t seg; 549 char *kva; 550 int rseg; 551 552 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 553 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 554 aprint_error_dev(sc->sc_dev, 555 "unable to alloc rx DMA mem %d, error = %d\n", 556 i, error); 557 cas_partial_detach(sc, CAS_ATT_5); 558 } 559 sc->sc_rxsoft[i].rxs_dmaseg = seg; 560 561 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 562 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 563 aprint_error_dev(sc->sc_dev, 564 "unable to alloc rx DMA mem %d, error = %d\n", 565 i, error); 566 cas_partial_detach(sc, CAS_ATT_5); 567 } 568 sc->sc_rxsoft[i].rxs_kva = kva; 569 570 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 571 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 572 aprint_error_dev(sc->sc_dev, 573 "unable to create rx DMA map %d, error = %d\n", 574 i, error); 575 cas_partial_detach(sc, CAS_ATT_5); 576 } 577 578 if ((error = bus_dmamap_load(sc->sc_dmatag, 579 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 580 BUS_DMA_NOWAIT)) != 0) { 581 aprint_error_dev(sc->sc_dev, 582 "unable to load rx DMA map %d, error = %d\n", 583 i, error); 584 cas_partial_detach(sc, CAS_ATT_5); 585 } 586 } 587 588 /* 589 * Create the transmit buffer DMA maps. 590 */ 591 for (i = 0; i < CAS_NTXDESC; i++) { 592 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 593 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 594 &sc->sc_txd[i].sd_map)) != 0) { 595 aprint_error_dev(sc->sc_dev, 596 "unable to create tx DMA map %d, error = %d\n", 597 i, error); 598 cas_partial_detach(sc, CAS_ATT_6); 599 } 600 sc->sc_txd[i].sd_mbuf = NULL; 601 } 602 603 /* 604 * From this point forward, the attachment cannot fail. A failure 605 * before this point releases all resources that may have been 606 * allocated. 607 */ 608 609 /* Announce ourselves. */ 610 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 611 ether_sprintf(enaddr)); 612 aprint_naive(": Ethernet controller\n"); 613 614 /* Get RX FIFO size */ 615 sc->sc_rxfifosize = 16 * 1024; 616 617 /* Initialize ifnet structure. */ 618 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 619 ifp->if_softc = sc; 620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 621 ifp->if_start = cas_start; 622 ifp->if_ioctl = cas_ioctl; 623 ifp->if_watchdog = cas_watchdog; 624 ifp->if_stop = cas_stop; 625 ifp->if_init = cas_init; 626 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 627 IFQ_SET_READY(&ifp->if_snd); 628 629 /* Initialize ifmedia structures and MII info */ 630 mii->mii_ifp = ifp; 631 mii->mii_readreg = cas_mii_readreg; 632 mii->mii_writereg = cas_mii_writereg; 633 mii->mii_statchg = cas_mii_statchg; 634 635 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 636 sc->sc_ethercom.ec_mii = mii; 637 638 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 639 640 cas_mifinit(sc); 641 642 if (sc->sc_mif_config & (CAS_MIF_CONFIG_MDI1 | CAS_MIF_CONFIG_MDI0)) { 643 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 644 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 645 bus_space_write_4(sc->sc_memt, sc->sc_memh, 646 CAS_MIF_CONFIG, sc->sc_mif_config); 647 } 648 /* Enable/unfreeze the GMII pins of Saturn. */ 649 if (sc->sc_variant == CAS_SATURN) { 650 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 651 CAS_SATURN_PCFG) & ~CAS_SATURN_PCFG_FSI; 652 if ((sc->sc_mif_config & CAS_MIF_CONFIG_MDI0) != 0) 653 reg |= CAS_SATURN_PCFG_FSI; 654 bus_space_write_4(sc->sc_memt, sc->sc_memh, 655 CAS_SATURN_PCFG, reg); 656 /* Read to flush */ 657 bus_space_read_4(sc->sc_memt, sc->sc_memh, 658 CAS_SATURN_PCFG); 659 DELAY(10000); 660 } 661 } 662 663 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 664 MII_OFFSET_ANY, 0); 665 666 child = LIST_FIRST(&mii->mii_phys); 667 if (child == NULL && 668 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0 | CAS_MIF_CONFIG_MDI1)) { 669 /* 670 * Try the external PCS SERDES if we didn't find any 671 * MII devices. 672 */ 673 bus_space_write_4(sc->sc_memt, sc->sc_memh, 674 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 675 676 bus_space_write_4(sc->sc_memt, sc->sc_memh, 677 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 678 679 mii->mii_readreg = cas_pcs_readreg; 680 mii->mii_writereg = cas_pcs_writereg; 681 682 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 683 MII_OFFSET_ANY, MIIF_NOISOLATE); 684 } 685 686 child = LIST_FIRST(&mii->mii_phys); 687 if (child == NULL) { 688 /* No PHY attached */ 689 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 690 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 691 } else { 692 /* 693 * Walk along the list of attached MII devices and 694 * establish an `MII instance' to `phy number' 695 * mapping. We'll use this mapping in media change 696 * requests to determine which phy to use to program 697 * the MIF configuration register. 698 */ 699 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 700 /* 701 * Note: we support just two PHYs: the built-in 702 * internal device and an external on the MII 703 * connector. 704 */ 705 if (child->mii_phy > 1 || child->mii_inst > 1) { 706 aprint_error_dev(sc->sc_dev, 707 "cannot accommodate MII device %s" 708 " at phy %d, instance %d\n", 709 device_xname(child->mii_dev), 710 child->mii_phy, child->mii_inst); 711 continue; 712 } 713 714 sc->sc_phys[child->mii_inst] = child->mii_phy; 715 } 716 717 /* 718 * XXX - we can really do the following ONLY if the 719 * phy indeed has the auto negotiation capability!! 720 */ 721 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 722 } 723 724 /* claim 802.1q capability */ 725 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 726 727 /* Attach the interface. */ 728 if_attach(ifp); 729 if_deferred_start_init(ifp, NULL); 730 ether_ifattach(ifp, enaddr); 731 732 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 733 RND_TYPE_NET, RND_FLAG_DEFAULT); 734 735 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 736 NULL, device_xname(sc->sc_dev), "interrupts"); 737 738 callout_init(&sc->sc_tick_ch, 0); 739 callout_setfunc(&sc->sc_tick_ch, cas_tick, sc); 740 741 return; 742 } 743 744 int 745 cas_detach(device_t self, int flags) 746 { 747 int i; 748 struct cas_softc *sc = device_private(self); 749 bus_space_tag_t t = sc->sc_memt; 750 bus_space_handle_t h = sc->sc_memh; 751 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 752 753 /* 754 * Free any resources we've allocated during the failed attach 755 * attempt. Do this in reverse order and fall through. 756 */ 757 switch (sc->sc_att_stage) { 758 case CAS_ATT_FINISHED: 759 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 760 pmf_device_deregister(self); 761 cas_stop(&sc->sc_ethercom.ec_if, 1); 762 evcnt_detach(&sc->sc_ev_intr); 763 764 rnd_detach_source(&sc->rnd_source); 765 766 ether_ifdetach(ifp); 767 if_detach(ifp); 768 ifmedia_fini(&sc->sc_mii.mii_media); 769 770 callout_destroy(&sc->sc_tick_ch); 771 772 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 773 774 /*FALLTHROUGH*/ 775 case CAS_ATT_MII: 776 case CAS_ATT_7: 777 case CAS_ATT_6: 778 for (i = 0; i < CAS_NTXDESC; i++) { 779 if (sc->sc_txd[i].sd_map != NULL) 780 bus_dmamap_destroy(sc->sc_dmatag, 781 sc->sc_txd[i].sd_map); 782 } 783 /*FALLTHROUGH*/ 784 case CAS_ATT_5: 785 for (i = 0; i < CAS_NRXDESC; i++) { 786 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 787 bus_dmamap_unload(sc->sc_dmatag, 788 sc->sc_rxsoft[i].rxs_dmamap); 789 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 790 bus_dmamap_destroy(sc->sc_dmatag, 791 sc->sc_rxsoft[i].rxs_dmamap); 792 if (sc->sc_rxsoft[i].rxs_kva != NULL) 793 bus_dmamem_unmap(sc->sc_dmatag, 794 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 795 /* XXX need to check that bus_dmamem_alloc suceeded 796 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 797 */ 798 bus_dmamem_free(sc->sc_dmatag, 799 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 800 } 801 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 802 /*FALLTHROUGH*/ 803 case CAS_ATT_4: 804 case CAS_ATT_3: 805 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 806 /*FALLTHROUGH*/ 807 case CAS_ATT_2: 808 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 809 sizeof(struct cas_control_data)); 810 /*FALLTHROUGH*/ 811 case CAS_ATT_1: 812 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 813 /*FALLTHROUGH*/ 814 case CAS_ATT_0: 815 sc->sc_att_stage = CAS_ATT_0; 816 /*FALLTHROUGH*/ 817 case CAS_ATT_BACKEND_2: 818 case CAS_ATT_BACKEND_1: 819 if (sc->sc_ih != NULL) { 820 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 821 sc->sc_ih = NULL; 822 } 823 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 824 /*FALLTHROUGH*/ 825 case CAS_ATT_BACKEND_0: 826 break; 827 } 828 return 0; 829 } 830 831 static void 832 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 833 { 834 cfattach_t ca = device_cfattach(sc->sc_dev); 835 836 sc->sc_att_stage = stage; 837 (*ca->ca_detach)(sc->sc_dev, 0); 838 } 839 840 void 841 cas_tick(void *arg) 842 { 843 struct cas_softc *sc = arg; 844 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 845 bus_space_tag_t t = sc->sc_memt; 846 bus_space_handle_t mac = sc->sc_memh; 847 int s; 848 uint32_t v; 849 850 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 851 852 /* unload collisions counters */ 853 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 854 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 855 if_statadd_ref(nsr, if_collisions, v + 856 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 857 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT)); 858 if_statadd_ref(nsr, if_oerrors, v); 859 860 /* read error counters */ 861 if_statadd_ref(nsr, if_ierrors, 862 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 863 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 864 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 865 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL)); 866 867 IF_STAT_PUTREF(ifp); 868 869 /* clear the hardware counters */ 870 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 871 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 872 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 873 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 874 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 875 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 876 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 877 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 878 879 s = splnet(); 880 mii_tick(&sc->sc_mii); 881 splx(s); 882 883 callout_schedule(&sc->sc_tick_ch, hz); 884 } 885 886 int 887 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 888 uint32_t clr, uint32_t set) 889 { 890 int i; 891 uint32_t reg; 892 893 for (i = TRIES; i--; DELAY(100)) { 894 reg = bus_space_read_4(sc->sc_memt, h, r); 895 if ((reg & clr) == 0 && (reg & set) == set) 896 return (1); 897 } 898 899 return (0); 900 } 901 902 void 903 cas_reset(struct cas_softc *sc) 904 { 905 bus_space_tag_t t = sc->sc_memt; 906 bus_space_handle_t h = sc->sc_memh; 907 int s; 908 909 s = splnet(); 910 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 911 cas_reset_rx(sc); 912 cas_reset_tx(sc); 913 914 /* Disable interrupts */ 915 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 916 917 /* Do a full reset */ 918 bus_space_write_4(t, h, CAS_RESET, 919 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 920 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 921 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 922 splx(s); 923 } 924 925 926 /* 927 * cas_rxdrain: 928 * 929 * Drain the receive queue. 930 */ 931 void 932 cas_rxdrain(struct cas_softc *sc) 933 { 934 /* Nothing to do yet. */ 935 } 936 937 /* 938 * Reset the whole thing. 939 */ 940 void 941 cas_stop(struct ifnet *ifp, int disable) 942 { 943 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 944 struct cas_sxd *sd; 945 uint32_t i; 946 947 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 948 949 callout_stop(&sc->sc_tick_ch); 950 951 /* 952 * Mark the interface down and cancel the watchdog timer. 953 */ 954 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 955 ifp->if_timer = 0; 956 957 mii_down(&sc->sc_mii); 958 959 cas_reset_rx(sc); 960 cas_reset_tx(sc); 961 962 /* 963 * Release any queued transmit buffers. 964 */ 965 for (i = 0; i < CAS_NTXDESC; i++) { 966 sd = &sc->sc_txd[i]; 967 if (sd->sd_mbuf != NULL) { 968 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 969 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 970 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 971 m_freem(sd->sd_mbuf); 972 sd->sd_mbuf = NULL; 973 } 974 } 975 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 976 977 if (disable) 978 cas_rxdrain(sc); 979 } 980 981 982 /* 983 * Reset the receiver 984 */ 985 int 986 cas_reset_rx(struct cas_softc *sc) 987 { 988 bus_space_tag_t t = sc->sc_memt; 989 bus_space_handle_t h = sc->sc_memh; 990 991 /* 992 * Resetting while DMA is in progress can cause a bus hang, so we 993 * disable DMA first. 994 */ 995 cas_disable_rx(sc); 996 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 997 /* Wait till it finishes */ 998 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 999 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 1000 /* Wait 5ms extra. */ 1001 delay(5000); 1002 1003 /* Finally, reset the ERX */ 1004 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 1005 /* Wait till it finishes */ 1006 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 1007 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 1008 return (1); 1009 } 1010 return (0); 1011 } 1012 1013 1014 /* 1015 * Reset the transmitter 1016 */ 1017 int 1018 cas_reset_tx(struct cas_softc *sc) 1019 { 1020 bus_space_tag_t t = sc->sc_memt; 1021 bus_space_handle_t h = sc->sc_memh; 1022 1023 /* 1024 * Resetting while DMA is in progress can cause a bus hang, so we 1025 * disable DMA first. 1026 */ 1027 cas_disable_tx(sc); 1028 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 1029 /* Wait till it finishes */ 1030 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 1031 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 1032 /* Wait 5ms extra. */ 1033 delay(5000); 1034 1035 /* Finally, reset the ETX */ 1036 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 1037 /* Wait till it finishes */ 1038 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 1039 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 1040 return (1); 1041 } 1042 return (0); 1043 } 1044 1045 /* 1046 * Disable receiver. 1047 */ 1048 int 1049 cas_disable_rx(struct cas_softc *sc) 1050 { 1051 bus_space_tag_t t = sc->sc_memt; 1052 bus_space_handle_t h = sc->sc_memh; 1053 uint32_t cfg; 1054 1055 /* Flip the enable bit */ 1056 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1057 cfg &= ~CAS_MAC_RX_ENABLE; 1058 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 1059 1060 /* Wait for it to finish */ 1061 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 1062 } 1063 1064 /* 1065 * Disable transmitter. 1066 */ 1067 int 1068 cas_disable_tx(struct cas_softc *sc) 1069 { 1070 bus_space_tag_t t = sc->sc_memt; 1071 bus_space_handle_t h = sc->sc_memh; 1072 uint32_t cfg; 1073 1074 /* Flip the enable bit */ 1075 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 1076 cfg &= ~CAS_MAC_TX_ENABLE; 1077 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 1078 1079 /* Wait for it to finish */ 1080 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 1081 } 1082 1083 /* 1084 * Initialize interface. 1085 */ 1086 int 1087 cas_meminit(struct cas_softc *sc) 1088 { 1089 int i; 1090 1091 /* 1092 * Initialize the transmit descriptor ring. 1093 */ 1094 for (i = 0; i < CAS_NTXDESC; i++) { 1095 sc->sc_txdescs[i].cd_flags = 0; 1096 sc->sc_txdescs[i].cd_addr = 0; 1097 } 1098 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 1099 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1100 1101 /* 1102 * Initialize the receive descriptor and receive job 1103 * descriptor rings. 1104 */ 1105 for (i = 0; i < CAS_NRXDESC; i++) 1106 CAS_INIT_RXDESC(sc, i, i); 1107 sc->sc_rxdptr = 0; 1108 sc->sc_rxptr = 0; 1109 1110 /* 1111 * Initialize the receive completion ring. 1112 */ 1113 for (i = 0; i < CAS_NRXCOMP; i++) { 1114 sc->sc_rxcomps[i].cc_word[0] = 0; 1115 sc->sc_rxcomps[i].cc_word[1] = 0; 1116 sc->sc_rxcomps[i].cc_word[2] = 0; 1117 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1118 CAS_CDRXCSYNC(sc, i, 1119 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1120 } 1121 1122 return (0); 1123 } 1124 1125 int 1126 cas_ringsize(int sz) 1127 { 1128 switch (sz) { 1129 case 32: 1130 return CAS_RING_SZ_32; 1131 case 64: 1132 return CAS_RING_SZ_64; 1133 case 128: 1134 return CAS_RING_SZ_128; 1135 case 256: 1136 return CAS_RING_SZ_256; 1137 case 512: 1138 return CAS_RING_SZ_512; 1139 case 1024: 1140 return CAS_RING_SZ_1024; 1141 case 2048: 1142 return CAS_RING_SZ_2048; 1143 case 4096: 1144 return CAS_RING_SZ_4096; 1145 case 8192: 1146 return CAS_RING_SZ_8192; 1147 default: 1148 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1149 sz); 1150 return CAS_RING_SZ_32; 1151 } 1152 } 1153 1154 int 1155 cas_cringsize(int sz) 1156 { 1157 int i; 1158 1159 for (i = 0; i < 9; i++) 1160 if (sz == (128 << i)) 1161 return i; 1162 1163 aprint_error("cas: invalid completion ring size %d\n", sz); 1164 return 128; 1165 } 1166 1167 /* 1168 * Initialization of interface; set up initialization block 1169 * and transmit/receive descriptor rings. 1170 */ 1171 int 1172 cas_init(struct ifnet *ifp) 1173 { 1174 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1175 bus_space_tag_t t = sc->sc_memt; 1176 bus_space_handle_t h = sc->sc_memh; 1177 int s; 1178 u_int max_frame_size; 1179 uint32_t v; 1180 1181 s = splnet(); 1182 1183 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1184 /* 1185 * Initialization sequence. The numbered steps below correspond 1186 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1187 * Channel Engine manual (part of the PCIO manual). 1188 * See also the STP2002-STQ document from Sun Microsystems. 1189 */ 1190 1191 /* step 1 & 2. Reset the Ethernet Channel */ 1192 cas_stop(ifp, 0); 1193 cas_reset(sc); 1194 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1195 1196 /* Re-initialize the MIF */ 1197 cas_mifinit(sc); 1198 1199 /* step 3. Setup data structures in host memory */ 1200 cas_meminit(sc); 1201 1202 /* step 4. TX MAC registers & counters */ 1203 cas_init_regs(sc); 1204 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1205 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1206 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1207 1208 /* step 5. RX MAC registers & counters */ 1209 cas_iff(sc); 1210 1211 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1212 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1213 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1214 BUS_ADDR_HI32(CAS_CDTXADDR(sc, 0))); 1215 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, 1216 BUS_ADDR_LO32(CAS_CDTXADDR(sc, 0))); 1217 1218 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1219 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1220 BUS_ADDR_HI32(CAS_CDRXADDR(sc, 0))); 1221 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, 1222 BUS_ADDR_LO32(CAS_CDRXADDR(sc, 0))); 1223 1224 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1225 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1226 BUS_ADDR_HI32(CAS_CDRXCADDR(sc, 0))); 1227 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, 1228 BUS_ADDR_LO32(CAS_CDRXCADDR(sc, 0))); 1229 1230 if (CAS_PLUS(sc)) { 1231 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1232 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1233 BUS_ADDR_HI32(CAS_CDRXADDR2(sc, 0))); 1234 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1235 BUS_ADDR_LO32(CAS_CDRXADDR2(sc, 0))); 1236 } 1237 1238 /* step 8. Global Configuration & Interrupt Mask */ 1239 cas_estintr(sc, CAS_INTR_REG); 1240 1241 /* step 9. ETX Configuration: use mostly default values */ 1242 1243 /* Enable DMA */ 1244 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1245 bus_space_write_4(t, h, CAS_TX_CONFIG, 1246 v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29)); 1247 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1248 1249 /* step 10. ERX Configuration */ 1250 1251 /* Encode Receive Descriptor ring size */ 1252 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1253 if (CAS_PLUS(sc)) 1254 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1255 1256 /* Encode Receive Completion ring size */ 1257 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1258 1259 /* Enable DMA */ 1260 bus_space_write_4(t, h, CAS_RX_CONFIG, 1261 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT) | CAS_RX_CONFIG_RXDMA_EN); 1262 1263 /* 1264 * The following value is for an OFF Threshold of about 3/4 full 1265 * and an ON Threshold of 1/4 full. 1266 */ 1267 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1268 (3 * sc->sc_rxfifosize / 256) | 1269 ((sc->sc_rxfifosize / 256) << 12)); 1270 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1271 1272 /* step 11. Configure Media */ 1273 mii_ifmedia_change(&sc->sc_mii); 1274 1275 /* step 12. RX_MAC Configuration Register */ 1276 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1277 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1278 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1279 1280 /* step 14. Issue Transmit Pending command */ 1281 1282 /* step 15. Give the receiver a swift kick */ 1283 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1284 if (CAS_PLUS(sc)) 1285 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1286 1287 /* Start the one second timer. */ 1288 callout_schedule(&sc->sc_tick_ch, hz); 1289 1290 ifp->if_flags |= IFF_RUNNING; 1291 ifp->if_flags &= ~IFF_OACTIVE; 1292 ifp->if_timer = 0; 1293 splx(s); 1294 1295 return (0); 1296 } 1297 1298 void 1299 cas_init_regs(struct cas_softc *sc) 1300 { 1301 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1302 bus_space_tag_t t = sc->sc_memt; 1303 bus_space_handle_t h = sc->sc_memh; 1304 const u_char *laddr = CLLADDR(ifp->if_sadl); 1305 uint32_t v, r; 1306 1307 /* These regs are not cleared on reset */ 1308 sc->sc_inited = 0; 1309 if (!sc->sc_inited) { 1310 /* Load recommended values */ 1311 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1312 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1313 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1314 1315 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1316 /* Max frame and max burst size */ 1317 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1318 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1319 1320 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1321 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1322 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1323 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1324 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1325 ((laddr[5]<<8)|laddr[4])&0x3ff); 1326 1327 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1328 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1329 bus_space_write_4(t, h, r, 0); 1330 1331 /* MAC control addr set to 0:1:c2:0:1:80 */ 1332 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1333 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1334 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1335 1336 /* MAC filter addr set to 0:0:0:0:0:0 */ 1337 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1338 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1339 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1340 1341 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1342 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1343 1344 /* Hash table initialized to 0 */ 1345 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1346 bus_space_write_4(t, h, r, 0); 1347 1348 sc->sc_inited = 1; 1349 } 1350 1351 /* Counters need to be zeroed */ 1352 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1353 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1354 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1355 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1356 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1357 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1358 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1359 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1360 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1361 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1362 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1363 1364 /* Un-pause stuff */ 1365 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1366 1367 /* 1368 * Set the station address. 1369 */ 1370 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1371 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1372 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1373 } 1374 1375 /* 1376 * Receive interrupt. 1377 */ 1378 int 1379 cas_rint(struct cas_softc *sc) 1380 { 1381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1382 bus_space_tag_t t = sc->sc_memt; 1383 bus_space_handle_t h = sc->sc_memh; 1384 struct cas_rxsoft *rxs; 1385 struct mbuf *m; 1386 uint64_t word[4]; 1387 int len, off, idx; 1388 int i, skip; 1389 void *cp; 1390 1391 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1392 CAS_CDRXCSYNC(sc, i, 1393 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1394 1395 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1396 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1397 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1398 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1399 1400 /* Stop if the hardware still owns the descriptor. */ 1401 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1402 break; 1403 1404 len = CAS_RC1_HDR_LEN(word[1]); 1405 if (len > 0) { 1406 off = CAS_RC1_HDR_OFF(word[1]); 1407 idx = CAS_RC1_HDR_IDX(word[1]); 1408 rxs = &sc->sc_rxsoft[idx]; 1409 1410 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1411 idx, off, len)); 1412 1413 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1414 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1415 1416 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1417 m = m_devget(cp, len, 0, ifp); 1418 1419 if (word[0] & CAS_RC0_RELEASE_HDR) 1420 cas_add_rxbuf(sc, idx); 1421 1422 if (m != NULL) { 1423 1424 /* 1425 * Pass this up to any BPF listeners, but only 1426 * pass it up the stack if its for us. 1427 */ 1428 m->m_pkthdr.csum_flags = 0; 1429 if_percpuq_enqueue(ifp->if_percpuq, m); 1430 } else 1431 if_statinc(ifp, if_ierrors); 1432 } 1433 1434 len = CAS_RC0_DATA_LEN(word[0]); 1435 if (len > 0) { 1436 off = CAS_RC0_DATA_OFF(word[0]); 1437 idx = CAS_RC0_DATA_IDX(word[0]); 1438 rxs = &sc->sc_rxsoft[idx]; 1439 1440 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1441 idx, off, len)); 1442 1443 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1444 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1445 1446 /* XXX We should not be copying the packet here. */ 1447 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1448 m = m_devget(cp, len, 0, ifp); 1449 1450 if (word[0] & CAS_RC0_RELEASE_DATA) 1451 cas_add_rxbuf(sc, idx); 1452 1453 if (m != NULL) { 1454 /* 1455 * Pass this up to any BPF listeners, but only 1456 * pass it up the stack if its for us. 1457 */ 1458 m->m_pkthdr.csum_flags = 0; 1459 if_percpuq_enqueue(ifp->if_percpuq, m); 1460 } else 1461 if_statinc(ifp, if_ierrors); 1462 } 1463 1464 if (word[0] & CAS_RC0_SPLIT) 1465 aprint_error_dev(sc->sc_dev, "split packet\n"); 1466 1467 skip = CAS_RC0_SKIP(word[0]); 1468 } 1469 1470 while (sc->sc_rxptr != i) { 1471 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1472 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1473 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1474 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1475 CAS_DMA_WRITE(CAS_RC3_OWN); 1476 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1477 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1478 1479 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1480 } 1481 1482 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1483 1484 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1485 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1486 1487 return (1); 1488 } 1489 1490 /* 1491 * cas_add_rxbuf: 1492 * 1493 * Add a receive buffer to the indicated descriptor. 1494 */ 1495 int 1496 cas_add_rxbuf(struct cas_softc *sc, int idx) 1497 { 1498 bus_space_tag_t t = sc->sc_memt; 1499 bus_space_handle_t h = sc->sc_memh; 1500 1501 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1502 1503 if ((sc->sc_rxdptr % 4) == 0) 1504 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1505 1506 if (++sc->sc_rxdptr == CAS_NRXDESC) 1507 sc->sc_rxdptr = 0; 1508 1509 return (0); 1510 } 1511 1512 int 1513 cas_eint(struct cas_softc *sc, u_int status) 1514 { 1515 char bits[128]; 1516 if ((status & CAS_INTR_MIF) != 0) { 1517 DPRINTF(sc, ("%s: link status changed\n", 1518 device_xname(sc->sc_dev))); 1519 return (1); 1520 } 1521 1522 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1523 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1524 return (1); 1525 } 1526 1527 int 1528 cas_pint(struct cas_softc *sc) 1529 { 1530 bus_space_tag_t t = sc->sc_memt; 1531 bus_space_handle_t seb = sc->sc_memh; 1532 uint32_t status; 1533 1534 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1535 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1536 #ifdef CAS_DEBUG 1537 if (status) 1538 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1539 #endif 1540 return (1); 1541 } 1542 1543 int 1544 cas_intr(void *v) 1545 { 1546 struct cas_softc *sc = (struct cas_softc *)v; 1547 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1548 bus_space_tag_t t = sc->sc_memt; 1549 bus_space_handle_t seb = sc->sc_memh; 1550 uint32_t status; 1551 int r = 0; 1552 #ifdef CAS_DEBUG 1553 char bits[128]; 1554 #endif 1555 1556 sc->sc_ev_intr.ev_count++; 1557 1558 status = bus_space_read_4(t, seb, CAS_STATUS); 1559 #ifdef CAS_DEBUG 1560 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1561 #endif 1562 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1563 device_xname(sc->sc_dev), (status>>19), bits)); 1564 1565 if ((status & CAS_INTR_PCS) != 0) 1566 r |= cas_pint(sc); 1567 1568 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1569 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1570 r |= cas_eint(sc, status); 1571 1572 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1573 r |= cas_tint(sc, status); 1574 1575 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1576 r |= cas_rint(sc); 1577 1578 /* We should eventually do more than just print out error stats. */ 1579 if (status & CAS_INTR_TX_MAC) { 1580 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1581 #ifdef CAS_DEBUG 1582 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1583 printf("%s: MAC tx fault, status %x\n", 1584 device_xname(sc->sc_dev), txstat); 1585 #endif 1586 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1587 cas_init(ifp); 1588 } 1589 if (status & CAS_INTR_RX_MAC) { 1590 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1591 #ifdef CAS_DEBUG 1592 if (rxstat & ~CAS_MAC_RX_DONE) 1593 printf("%s: MAC rx fault, status %x\n", 1594 device_xname(sc->sc_dev), rxstat); 1595 #endif 1596 /* 1597 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1598 * due to a silicon bug so handle them silently. 1599 */ 1600 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1601 if_statinc(ifp, if_ierrors); 1602 cas_init(ifp); 1603 } 1604 #ifdef CAS_DEBUG 1605 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1606 printf("%s: MAC rx fault, status %x\n", 1607 device_xname(sc->sc_dev), rxstat); 1608 #endif 1609 } 1610 rnd_add_uint32(&sc->rnd_source, status); 1611 return (r); 1612 } 1613 1614 1615 void 1616 cas_watchdog(struct ifnet *ifp) 1617 { 1618 struct cas_softc *sc = ifp->if_softc; 1619 1620 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1621 "CAS_MAC_RX_CONFIG %x\n", 1622 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1623 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1624 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1625 1626 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1627 if_statinc(ifp, if_oerrors); 1628 1629 /* Try to get more packets going. */ 1630 cas_init(ifp); 1631 } 1632 1633 /* 1634 * Initialize the MII Management Interface 1635 */ 1636 void 1637 cas_mifinit(struct cas_softc *sc) 1638 { 1639 bus_space_tag_t t = sc->sc_memt; 1640 bus_space_handle_t mif = sc->sc_memh; 1641 1642 /* Configure the MIF in frame mode */ 1643 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1644 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1645 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1646 } 1647 1648 /* 1649 * MII interface 1650 * 1651 * The Cassini MII interface supports at least three different operating modes: 1652 * 1653 * Bitbang mode is implemented using data, clock and output enable registers. 1654 * 1655 * Frame mode is implemented by loading a complete frame into the frame 1656 * register and polling the valid bit for completion. 1657 * 1658 * Polling mode uses the frame register but completion is indicated by 1659 * an interrupt. 1660 * 1661 */ 1662 int 1663 cas_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1664 { 1665 struct cas_softc *sc = device_private(self); 1666 bus_space_tag_t t = sc->sc_memt; 1667 bus_space_handle_t mif = sc->sc_memh; 1668 int n; 1669 uint32_t v; 1670 1671 #ifdef CAS_DEBUG 1672 if (sc->sc_debug) 1673 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1674 #endif 1675 1676 /* Construct the frame command */ 1677 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1678 CAS_MIF_FRAME_READ; 1679 1680 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1681 for (n = 0; n < 100; n++) { 1682 DELAY(1); 1683 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1684 if (v & CAS_MIF_FRAME_TA0) { 1685 *val = v & CAS_MIF_FRAME_DATA; 1686 return 0; 1687 } 1688 } 1689 1690 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1691 return ETIMEDOUT; 1692 } 1693 1694 int 1695 cas_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1696 { 1697 struct cas_softc *sc = device_private(self); 1698 bus_space_tag_t t = sc->sc_memt; 1699 bus_space_handle_t mif = sc->sc_memh; 1700 int n; 1701 uint32_t v; 1702 1703 #ifdef CAS_DEBUG 1704 if (sc->sc_debug) 1705 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1706 phy, reg, val); 1707 #endif 1708 1709 /* Construct the frame command */ 1710 v = CAS_MIF_FRAME_WRITE | 1711 (phy << CAS_MIF_PHY_SHIFT) | 1712 (reg << CAS_MIF_REG_SHIFT) | 1713 (val & CAS_MIF_FRAME_DATA); 1714 1715 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1716 for (n = 0; n < 100; n++) { 1717 DELAY(1); 1718 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1719 if (v & CAS_MIF_FRAME_TA0) 1720 return 0; 1721 } 1722 1723 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1724 return ETIMEDOUT; 1725 } 1726 1727 void 1728 cas_mii_statchg(struct ifnet *ifp) 1729 { 1730 struct cas_softc *sc = ifp->if_softc; 1731 #ifdef CAS_DEBUG 1732 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1733 #endif 1734 bus_space_tag_t t = sc->sc_memt; 1735 bus_space_handle_t mac = sc->sc_memh; 1736 uint32_t v; 1737 1738 #ifdef CAS_DEBUG 1739 if (sc->sc_debug) 1740 printf("cas_mii_statchg: status change: phy = %d\n", 1741 sc->sc_phys[instance]); 1742 #endif 1743 1744 /* Set tx full duplex options */ 1745 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1746 delay(10000); /* reg must be cleared and delay before changing. */ 1747 v = CAS_MAC_TX_ENA_IPG0 | CAS_MAC_TX_NGU | CAS_MAC_TX_NGU_LIMIT | 1748 CAS_MAC_TX_ENABLE; 1749 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1750 v |= CAS_MAC_TX_IGN_CARRIER | CAS_MAC_TX_IGN_COLLIS; 1751 } 1752 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1753 1754 /* XIF Configuration */ 1755 v = CAS_MAC_XIF_TX_MII_ENA; 1756 v |= CAS_MAC_XIF_LINK_LED; 1757 1758 /* MII needs echo disable if half duplex. */ 1759 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1760 /* turn on full duplex LED */ 1761 v |= CAS_MAC_XIF_FDPLX_LED; 1762 else 1763 /* half duplex -- disable echo */ 1764 v |= CAS_MAC_XIF_ECHO_DISABL; 1765 1766 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1767 case IFM_1000_T: /* Gigabit using GMII interface */ 1768 case IFM_1000_SX: 1769 v |= CAS_MAC_XIF_GMII_MODE; 1770 break; 1771 default: 1772 v &= ~CAS_MAC_XIF_GMII_MODE; 1773 } 1774 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1775 } 1776 1777 int 1778 cas_pcs_readreg(device_t self, int phy, int reg, uint16_t *val) 1779 { 1780 struct cas_softc *sc = device_private(self); 1781 bus_space_tag_t t = sc->sc_memt; 1782 bus_space_handle_t pcs = sc->sc_memh; 1783 1784 #ifdef CAS_DEBUG 1785 if (sc->sc_debug) 1786 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1787 #endif 1788 1789 if (phy != CAS_PHYAD_EXTERNAL) 1790 return -1; 1791 1792 switch (reg) { 1793 case MII_BMCR: 1794 reg = CAS_MII_CONTROL; 1795 break; 1796 case MII_BMSR: 1797 reg = CAS_MII_STATUS; 1798 break; 1799 case MII_ANAR: 1800 reg = CAS_MII_ANAR; 1801 break; 1802 case MII_ANLPAR: 1803 reg = CAS_MII_ANLPAR; 1804 break; 1805 case MII_EXTSR: 1806 *val = EXTSR_1000XFDX | EXTSR_1000XHDX; 1807 return 0; 1808 default: 1809 return (0); 1810 } 1811 1812 *val = bus_space_read_4(t, pcs, reg) & 0xffff; 1813 return 0; 1814 } 1815 1816 int 1817 cas_pcs_writereg(device_t self, int phy, int reg, uint16_t val) 1818 { 1819 struct cas_softc *sc = device_private(self); 1820 bus_space_tag_t t = sc->sc_memt; 1821 bus_space_handle_t pcs = sc->sc_memh; 1822 int reset = 0; 1823 1824 #ifdef CAS_DEBUG 1825 if (sc->sc_debug) 1826 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1827 phy, reg, val); 1828 #endif 1829 1830 if (phy != CAS_PHYAD_EXTERNAL) 1831 return -1; 1832 1833 if (reg == MII_ANAR) 1834 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1835 1836 switch (reg) { 1837 case MII_BMCR: 1838 reset = (val & CAS_MII_CONTROL_RESET); 1839 reg = CAS_MII_CONTROL; 1840 break; 1841 case MII_BMSR: 1842 reg = CAS_MII_STATUS; 1843 break; 1844 case MII_ANAR: 1845 reg = CAS_MII_ANAR; 1846 break; 1847 case MII_ANLPAR: 1848 reg = CAS_MII_ANLPAR; 1849 break; 1850 default: 1851 return 0; 1852 } 1853 1854 bus_space_write_4(t, pcs, reg, val); 1855 1856 if (reset) 1857 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1858 1859 if (reg == CAS_MII_ANAR || reset) 1860 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1861 CAS_MII_CONFIG_ENABLE); 1862 1863 return 0; 1864 } 1865 1866 int 1867 cas_mediachange(struct ifnet *ifp) 1868 { 1869 struct cas_softc *sc = ifp->if_softc; 1870 struct mii_data *mii = &sc->sc_mii; 1871 1872 if (mii->mii_instance) { 1873 struct mii_softc *miisc; 1874 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1875 mii_phy_reset(miisc); 1876 } 1877 1878 return (mii_mediachg(&sc->sc_mii)); 1879 } 1880 1881 void 1882 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1883 { 1884 struct cas_softc *sc = ifp->if_softc; 1885 1886 mii_pollstat(&sc->sc_mii); 1887 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1888 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1889 } 1890 1891 /* 1892 * Process an ioctl request. 1893 */ 1894 int 1895 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1896 { 1897 struct cas_softc *sc = ifp->if_softc; 1898 int s, error = 0; 1899 1900 s = splnet(); 1901 1902 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1903 error = 0; 1904 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1905 ; 1906 else if (ifp->if_flags & IFF_RUNNING) { 1907 /* 1908 * Multicast list has changed; set the hardware filter 1909 * accordingly. 1910 */ 1911 cas_iff(sc); 1912 } 1913 } 1914 1915 splx(s); 1916 return (error); 1917 } 1918 1919 static bool 1920 cas_suspend(device_t self, const pmf_qual_t *qual) 1921 { 1922 struct cas_softc *sc = device_private(self); 1923 bus_space_tag_t t = sc->sc_memt; 1924 bus_space_handle_t h = sc->sc_memh; 1925 1926 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1927 if (sc->sc_ih != NULL) { 1928 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1929 sc->sc_ih = NULL; 1930 } 1931 1932 return true; 1933 } 1934 1935 static bool 1936 cas_resume(device_t self, const pmf_qual_t *qual) 1937 { 1938 struct cas_softc *sc = device_private(self); 1939 1940 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1941 } 1942 1943 static bool 1944 cas_estintr(struct cas_softc *sc, int what) 1945 { 1946 bus_space_tag_t t = sc->sc_memt; 1947 bus_space_handle_t h = sc->sc_memh; 1948 const char *intrstr = NULL; 1949 char intrbuf[PCI_INTRSTR_LEN]; 1950 1951 /* PCI interrupts */ 1952 if (what & CAS_INTR_PCI) { 1953 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle, intrbuf, 1954 sizeof(intrbuf)); 1955 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_handle, 1956 IPL_NET, cas_intr, sc, device_xname(sc->sc_dev)); 1957 if (sc->sc_ih == NULL) { 1958 aprint_error_dev(sc->sc_dev, 1959 "unable to establish interrupt"); 1960 if (intrstr != NULL) 1961 aprint_error(" at %s", intrstr); 1962 aprint_error("\n"); 1963 return false; 1964 } 1965 1966 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1967 } 1968 1969 /* Interrupt register */ 1970 if (what & CAS_INTR_REG) { 1971 bus_space_write_4(t, h, CAS_INTMASK, 1972 ~(CAS_INTR_TX_INTME | CAS_INTR_TX_EMPTY | 1973 CAS_INTR_TX_TAG_ERR | 1974 CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF | 1975 CAS_INTR_RX_TAG_ERR | 1976 CAS_INTR_RX_COMP_FULL | CAS_INTR_PCS | 1977 CAS_INTR_MAC_CONTROL | CAS_INTR_MIF | 1978 CAS_INTR_BERR)); 1979 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1980 CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT); 1981 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1982 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1983 } 1984 return true; 1985 } 1986 1987 bool 1988 cas_shutdown(device_t self, int howto) 1989 { 1990 struct cas_softc *sc = device_private(self); 1991 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1992 1993 cas_stop(ifp, 1); 1994 1995 return true; 1996 } 1997 1998 void 1999 cas_iff(struct cas_softc *sc) 2000 { 2001 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2002 struct ethercom *ec = &sc->sc_ethercom; 2003 struct ether_multi *enm; 2004 struct ether_multistep step; 2005 bus_space_tag_t t = sc->sc_memt; 2006 bus_space_handle_t h = sc->sc_memh; 2007 uint32_t crc, hash[16], rxcfg; 2008 int i; 2009 2010 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 2011 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 2012 CAS_MAC_RX_PROMISC_GRP); 2013 ifp->if_flags &= ~IFF_ALLMULTI; 2014 2015 if ((ifp->if_flags & IFF_PROMISC) != 0) 2016 goto update; 2017 2018 /* 2019 * Set up multicast address filter by passing all multicast 2020 * addresses through a crc generator, and then using the 2021 * high order 8 bits as an index into the 256 bit logical 2022 * address filter. The high order 4 bits selects the word, 2023 * while the other 4 bits select the bit within the word 2024 * (where bit 0 is the MSB). 2025 */ 2026 2027 /* Clear hash table */ 2028 for (i = 0; i < 16; i++) 2029 hash[i] = 0; 2030 2031 ETHER_LOCK(ec); 2032 ETHER_FIRST_MULTI(step, ec, enm); 2033 while (enm != NULL) { 2034 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2035 /* XXX Use ETHER_F_ALLMULTI in future. */ 2036 ifp->if_flags |= IFF_ALLMULTI; 2037 ETHER_UNLOCK(ec); 2038 goto update; 2039 } 2040 2041 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2042 2043 /* Just want the 8 most significant bits. */ 2044 crc >>= 24; 2045 2046 /* Set the corresponding bit in the filter. */ 2047 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2048 2049 ETHER_NEXT_MULTI(step, enm); 2050 } 2051 ETHER_UNLOCK(ec); 2052 2053 rxcfg |= CAS_MAC_RX_HASH_FILTER; 2054 2055 /* Now load the hash table into the chip (if we are using it) */ 2056 for (i = 0; i < 16; i++) { 2057 bus_space_write_4(t, h, 2058 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2059 hash[i]); 2060 } 2061 2062 update: 2063 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2064 if (ifp->if_flags & IFF_PROMISC) { 2065 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 2066 /* XXX Use ETHER_F_ALLMULTI in future. */ 2067 ifp->if_flags |= IFF_ALLMULTI; 2068 } else 2069 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 2070 } 2071 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 2072 } 2073 2074 int 2075 cas_encap(struct cas_softc *sc, struct mbuf *mhead, uint32_t *bixp) 2076 { 2077 uint64_t flags; 2078 uint32_t cur, frag, i; 2079 bus_dmamap_t map; 2080 2081 cur = frag = *bixp; 2082 map = sc->sc_txd[cur].sd_map; 2083 2084 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 2085 BUS_DMA_NOWAIT) != 0) { 2086 return (ENOBUFS); 2087 } 2088 2089 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 2090 bus_dmamap_unload(sc->sc_dmatag, map); 2091 return (ENOBUFS); 2092 } 2093 2094 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 2095 BUS_DMASYNC_PREWRITE); 2096 2097 for (i = 0; i < map->dm_nsegs; i++) { 2098 sc->sc_txdescs[frag].cd_addr = 2099 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 2100 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 2101 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 2102 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 2103 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 2104 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 2105 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 2106 BUS_DMASYNC_PREWRITE); 2107 cur = frag; 2108 if (++frag == CAS_NTXDESC) 2109 frag = 0; 2110 } 2111 2112 sc->sc_tx_cnt += map->dm_nsegs; 2113 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 2114 sc->sc_txd[cur].sd_map = map; 2115 sc->sc_txd[cur].sd_mbuf = mhead; 2116 2117 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 2118 2119 *bixp = frag; 2120 2121 /* sync descriptors */ 2122 2123 return (0); 2124 } 2125 2126 /* 2127 * Transmit interrupt. 2128 */ 2129 int 2130 cas_tint(struct cas_softc *sc, uint32_t status) 2131 { 2132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2133 struct cas_sxd *sd; 2134 uint32_t cons, comp; 2135 2136 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2137 cons = sc->sc_tx_cons; 2138 while (cons != comp) { 2139 sd = &sc->sc_txd[cons]; 2140 if (sd->sd_mbuf != NULL) { 2141 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2142 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2143 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2144 m_freem(sd->sd_mbuf); 2145 sd->sd_mbuf = NULL; 2146 if_statinc(ifp, if_opackets); 2147 } 2148 sc->sc_tx_cnt--; 2149 if (++cons == CAS_NTXDESC) 2150 cons = 0; 2151 } 2152 sc->sc_tx_cons = cons; 2153 2154 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2155 ifp->if_flags &= ~IFF_OACTIVE; 2156 if (sc->sc_tx_cnt == 0) 2157 ifp->if_timer = 0; 2158 2159 if_schedule_deferred_start(ifp); 2160 2161 return (1); 2162 } 2163 2164 void 2165 cas_start(struct ifnet *ifp) 2166 { 2167 struct cas_softc *sc = ifp->if_softc; 2168 struct mbuf *m; 2169 uint32_t bix; 2170 2171 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2172 return; 2173 2174 bix = sc->sc_tx_prod; 2175 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2176 IFQ_POLL(&ifp->if_snd, m); 2177 if (m == NULL) 2178 break; 2179 2180 /* 2181 * If BPF is listening on this interface, let it see the 2182 * packet before we commit it to the wire. 2183 */ 2184 bpf_mtap(ifp, m, BPF_D_OUT); 2185 2186 /* 2187 * Encapsulate this packet and start it going... 2188 * or fail... 2189 */ 2190 if (cas_encap(sc, m, &bix)) { 2191 ifp->if_flags |= IFF_OACTIVE; 2192 break; 2193 } 2194 2195 IFQ_DEQUEUE(&ifp->if_snd, m); 2196 ifp->if_timer = 5; 2197 } 2198 2199 sc->sc_tx_prod = bix; 2200 } 2201 2202 MODULE(MODULE_CLASS_DRIVER, if_cas, "pci"); 2203 2204 #ifdef _MODULE 2205 #include "ioconf.c" 2206 #endif 2207 2208 static int 2209 if_cas_modcmd(modcmd_t cmd, void *opaque) 2210 { 2211 int error = 0; 2212 2213 switch (cmd) { 2214 case MODULE_CMD_INIT: 2215 #ifdef _MODULE 2216 error = config_init_component(cfdriver_ioconf_cas, 2217 cfattach_ioconf_cas, cfdata_ioconf_cas); 2218 #endif 2219 return error; 2220 case MODULE_CMD_FINI: 2221 #ifdef _MODULE 2222 error = config_fini_component(cfdriver_ioconf_cas, 2223 cfattach_ioconf_cas, cfdata_ioconf_cas); 2224 #endif 2225 return error; 2226 default: 2227 return ENOTTY; 2228 } 2229 } 2230