1 /* $NetBSD: if_cas.c,v 1.7 2010/03/11 04:00:36 mrg Exp $ */ 2 /* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.7 2010/03/11 04:00:36 mrg Exp $"); 48 49 #include "opt_inet.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/syslog.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/socket.h> 59 #include <sys/ioctl.h> 60 #include <sys/errno.h> 61 #include <sys/device.h> 62 63 #include <machine/endian.h> 64 65 #include <uvm/uvm_extern.h> 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/in_systm.h> 75 #include <netinet/in_var.h> 76 #include <netinet/ip.h> 77 #include <netinet/tcp.h> 78 #include <netinet/udp.h> 79 #endif 80 81 #include <net/bpf.h> 82 83 #include <sys/bus.h> 84 #include <sys/intr.h> 85 86 #include <dev/mii/mii.h> 87 #include <dev/mii/miivar.h> 88 #include <dev/mii/mii_bitbang.h> 89 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcidevs.h> 93 #include <prop/proplib.h> 94 95 #include <dev/pci/if_casreg.h> 96 #include <dev/pci/if_casvar.h> 97 98 #define TRIES 10000 99 100 static bool cas_estintr(struct cas_softc *sc, int); 101 bool cas_shutdown(device_t, int); 102 static bool cas_suspend(device_t, const pmf_qual_t *); 103 static bool cas_resume(device_t, const pmf_qual_t *); 104 static int cas_detach(device_t, int); 105 static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 106 107 int cas_match(device_t, cfdata_t, void *); 108 void cas_attach(device_t, device_t, void *); 109 110 111 CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 112 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 113 DVF_DETACH_SHUTDOWN); 114 115 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 116 117 void cas_config(struct cas_softc *, const uint8_t *); 118 void cas_start(struct ifnet *); 119 void cas_stop(struct ifnet *, int); 120 int cas_ioctl(struct ifnet *, u_long, void *); 121 void cas_tick(void *); 122 void cas_watchdog(struct ifnet *); 123 int cas_init(struct ifnet *); 124 void cas_init_regs(struct cas_softc *); 125 int cas_ringsize(int); 126 int cas_cringsize(int); 127 int cas_meminit(struct cas_softc *); 128 void cas_mifinit(struct cas_softc *); 129 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 130 u_int32_t, u_int32_t); 131 void cas_reset(struct cas_softc *); 132 int cas_reset_rx(struct cas_softc *); 133 int cas_reset_tx(struct cas_softc *); 134 int cas_disable_rx(struct cas_softc *); 135 int cas_disable_tx(struct cas_softc *); 136 void cas_rxdrain(struct cas_softc *); 137 int cas_add_rxbuf(struct cas_softc *, int idx); 138 void cas_iff(struct cas_softc *); 139 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 140 141 /* MII methods & callbacks */ 142 int cas_mii_readreg(device_t, int, int); 143 void cas_mii_writereg(device_t, int, int, int); 144 void cas_mii_statchg(device_t); 145 int cas_pcs_readreg(device_t, int, int); 146 void cas_pcs_writereg(device_t, int, int, int); 147 148 int cas_mediachange(struct ifnet *); 149 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 150 151 int cas_eint(struct cas_softc *, u_int); 152 int cas_rint(struct cas_softc *); 153 int cas_tint(struct cas_softc *, u_int32_t); 154 int cas_pint(struct cas_softc *); 155 int cas_intr(void *); 156 157 #ifdef CAS_DEBUG 158 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 159 printf x 160 #else 161 #define DPRINTF(sc, x) /* nothing */ 162 #endif 163 164 int 165 cas_match(device_t parent, cfdata_t cf, void *aux) 166 { 167 struct pci_attach_args *pa = aux; 168 169 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 170 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 171 return 1; 172 173 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 174 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 175 return 1; 176 177 return 0; 178 } 179 180 #define PROMHDR_PTR_DATA 0x18 181 #define PROMDATA_PTR_VPD 0x08 182 #define PROMDATA_DATA2 0x0a 183 184 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 185 static const u_int8_t cas_promdat[] = { 186 'P', 'C', 'I', 'R', 187 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 188 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 189 }; 190 191 static const u_int8_t cas_promdat2[] = { 192 0x18, 0x00, /* structure length */ 193 0x00, /* structure revision */ 194 0x00, /* interface revision */ 195 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 196 PCI_CLASS_NETWORK /* class code */ 197 }; 198 199 int 200 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 201 uint8_t *enaddr) 202 { 203 struct pci_vpd_largeres *res; 204 struct pci_vpd *vpd; 205 bus_space_handle_t romh; 206 bus_space_tag_t romt; 207 bus_size_t romsize = 0; 208 u_int8_t buf[32], *desc; 209 pcireg_t address; 210 int dataoff, vpdoff, len; 211 int rv = -1; 212 213 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 214 &romt, &romh, NULL, &romsize)) 215 return (-1); 216 217 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 218 address |= PCI_MAPREG_ROM_ENABLE; 219 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 220 221 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 222 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 223 goto fail; 224 225 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 226 if (dataoff < 0x1c) 227 goto fail; 228 229 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 230 if (bcmp(buf, cas_promdat, sizeof(cas_promdat)) || 231 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 232 goto fail; 233 234 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 235 if (vpdoff < 0x1c) 236 goto fail; 237 238 next: 239 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 240 if (!PCI_VPDRES_ISLARGE(buf[0])) 241 goto fail; 242 243 res = (struct pci_vpd_largeres *)buf; 244 vpdoff += sizeof(*res); 245 246 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 247 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 248 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 249 /* Skip identifier string. */ 250 vpdoff += len; 251 goto next; 252 253 case PCI_VPDRES_TYPE_VPD: 254 while (len > 0) { 255 bus_space_read_region_1(romt, romh, vpdoff, 256 buf, sizeof(buf)); 257 258 vpd = (struct pci_vpd *)buf; 259 vpdoff += sizeof(*vpd) + vpd->vpd_len; 260 len -= sizeof(*vpd) + vpd->vpd_len; 261 262 /* 263 * We're looking for an "Enhanced" VPD... 264 */ 265 if (vpd->vpd_key0 != 'Z') 266 continue; 267 268 desc = buf + sizeof(*vpd); 269 270 /* 271 * ...which is an instance property... 272 */ 273 if (desc[0] != 'I') 274 continue; 275 desc += 3; 276 277 /* 278 * ...that's a byte array with the proper 279 * length for a MAC address... 280 */ 281 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 282 continue; 283 desc += 2; 284 285 /* 286 * ...named "local-mac-address". 287 */ 288 if (strcmp(desc, "local-mac-address") != 0) 289 continue; 290 desc += strlen("local-mac-address") + 1; 291 292 memcpy(enaddr, desc, ETHER_ADDR_LEN); 293 rv = 0; 294 } 295 break; 296 297 default: 298 goto fail; 299 } 300 301 fail: 302 if (romsize != 0) 303 bus_space_unmap(romt, romh, romsize); 304 305 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 306 address &= ~PCI_MAPREG_ROM_ENABLE; 307 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 308 309 return (rv); 310 } 311 312 void 313 cas_attach(device_t parent, device_t self, void *aux) 314 { 315 struct pci_attach_args *pa = aux; 316 struct cas_softc *sc = device_private(self); 317 char devinfo[256]; 318 prop_data_t data; 319 uint8_t enaddr[ETHER_ADDR_LEN]; 320 321 sc->sc_dev = self; 322 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 323 sc->sc_rev = PCI_REVISION(pa->pa_class); 324 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, sc->sc_rev); 325 sc->sc_dmatag = pa->pa_dmat; 326 327 #define PCI_CAS_BASEADDR 0x10 328 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 329 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 330 aprint_error_dev(sc->sc_dev, 331 "unable to map device registers\n"); 332 return; 333 } 334 335 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 336 "mac-address")) != NULL) 337 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 338 else if (cas_pci_enaddr(sc, pa, enaddr) != 0) 339 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 340 341 sc->sc_burst = 16; /* XXX */ 342 343 sc->sc_att_stage = CAS_ATT_BACKEND_0; 344 345 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 346 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 347 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 348 return; 349 } 350 sc->sc_pc = pa->pa_pc; 351 if (!cas_estintr(sc, CAS_INTR_PCI)) { 352 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 353 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 354 return; 355 } 356 357 sc->sc_att_stage = CAS_ATT_BACKEND_1; 358 359 /* 360 * call the main configure 361 */ 362 cas_config(sc, enaddr); 363 364 if (pmf_device_register1(sc->sc_dev, 365 cas_suspend, cas_resume, cas_shutdown)) 366 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 367 else 368 aprint_error_dev(sc->sc_dev, 369 "could not establish power handlers\n"); 370 371 sc->sc_att_stage = CAS_ATT_FINISHED; 372 /*FALLTHROUGH*/ 373 } 374 375 /* 376 * cas_config: 377 * 378 * Attach a Cassini interface to the system. 379 */ 380 void 381 cas_config(struct cas_softc *sc, const uint8_t *enaddr) 382 { 383 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 384 struct mii_data *mii = &sc->sc_mii; 385 struct mii_softc *child; 386 int i, error; 387 388 /* Make sure the chip is stopped. */ 389 ifp->if_softc = sc; 390 cas_reset(sc); 391 392 /* 393 * Allocate the control data structures, and create and load the 394 * DMA map for it. 395 */ 396 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 397 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 398 1, &sc->sc_cdnseg, 0)) != 0) { 399 aprint_error_dev(sc->sc_dev, 400 "unable to allocate control data, error = %d\n", 401 error); 402 cas_partial_detach(sc, CAS_ATT_0); 403 } 404 405 /* XXX should map this in with correct endianness */ 406 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 407 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 408 BUS_DMA_COHERENT)) != 0) { 409 aprint_error_dev(sc->sc_dev, 410 "unable to map control data, error = %d\n", error); 411 cas_partial_detach(sc, CAS_ATT_1); 412 } 413 414 if ((error = bus_dmamap_create(sc->sc_dmatag, 415 sizeof(struct cas_control_data), 1, 416 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 417 aprint_error_dev(sc->sc_dev, 418 "unable to create control data DMA map, error = %d\n", error); 419 cas_partial_detach(sc, CAS_ATT_2); 420 } 421 422 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 423 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 424 0)) != 0) { 425 aprint_error_dev(sc->sc_dev, 426 "unable to load control data DMA map, error = %d\n", 427 error); 428 cas_partial_detach(sc, CAS_ATT_3); 429 } 430 431 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 432 433 /* 434 * Create the receive buffer DMA maps. 435 */ 436 for (i = 0; i < CAS_NRXDESC; i++) { 437 bus_dma_segment_t seg; 438 char *kva; 439 int rseg; 440 441 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 442 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 443 aprint_error_dev(sc->sc_dev, 444 "unable to alloc rx DMA mem %d, error = %d\n", 445 i, error); 446 cas_partial_detach(sc, CAS_ATT_5); 447 } 448 sc->sc_rxsoft[i].rxs_dmaseg = seg; 449 450 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 451 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 452 aprint_error_dev(sc->sc_dev, 453 "unable to alloc rx DMA mem %d, error = %d\n", 454 i, error); 455 cas_partial_detach(sc, CAS_ATT_5); 456 } 457 sc->sc_rxsoft[i].rxs_kva = kva; 458 459 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 460 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 461 aprint_error_dev(sc->sc_dev, 462 "unable to create rx DMA map %d, error = %d\n", 463 i, error); 464 cas_partial_detach(sc, CAS_ATT_5); 465 } 466 467 if ((error = bus_dmamap_load(sc->sc_dmatag, 468 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 469 BUS_DMA_NOWAIT)) != 0) { 470 aprint_error_dev(sc->sc_dev, 471 "unable to load rx DMA map %d, error = %d\n", 472 i, error); 473 cas_partial_detach(sc, CAS_ATT_5); 474 } 475 } 476 477 /* 478 * Create the transmit buffer DMA maps. 479 */ 480 for (i = 0; i < CAS_NTXDESC; i++) { 481 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 482 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 483 &sc->sc_txd[i].sd_map)) != 0) { 484 aprint_error_dev(sc->sc_dev, 485 "unable to create tx DMA map %d, error = %d\n", 486 i, error); 487 cas_partial_detach(sc, CAS_ATT_6); 488 } 489 sc->sc_txd[i].sd_mbuf = NULL; 490 } 491 492 /* 493 * From this point forward, the attachment cannot fail. A failure 494 * before this point releases all resources that may have been 495 * allocated. 496 */ 497 498 /* Announce ourselves. */ 499 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 500 ether_sprintf(enaddr)); 501 aprint_naive(": Ethernet controller\n"); 502 503 /* Get RX FIFO size */ 504 sc->sc_rxfifosize = 16 * 1024; 505 506 /* Initialize ifnet structure. */ 507 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 508 ifp->if_softc = sc; 509 ifp->if_flags = 510 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 511 ifp->if_start = cas_start; 512 ifp->if_ioctl = cas_ioctl; 513 ifp->if_watchdog = cas_watchdog; 514 ifp->if_stop = cas_stop; 515 ifp->if_init = cas_init; 516 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 517 IFQ_SET_READY(&ifp->if_snd); 518 519 /* Initialize ifmedia structures and MII info */ 520 mii->mii_ifp = ifp; 521 mii->mii_readreg = cas_mii_readreg; 522 mii->mii_writereg = cas_mii_writereg; 523 mii->mii_statchg = cas_mii_statchg; 524 525 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 526 sc->sc_ethercom.ec_mii = mii; 527 528 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 529 530 cas_mifinit(sc); 531 532 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 533 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 534 bus_space_write_4(sc->sc_memt, sc->sc_memh, 535 CAS_MIF_CONFIG, sc->sc_mif_config); 536 } 537 538 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 539 MII_OFFSET_ANY, 0); 540 541 child = LIST_FIRST(&mii->mii_phys); 542 if (child == NULL && 543 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 544 /* 545 * Try the external PCS SERDES if we didn't find any 546 * MII devices. 547 */ 548 bus_space_write_4(sc->sc_memt, sc->sc_memh, 549 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 550 551 bus_space_write_4(sc->sc_memt, sc->sc_memh, 552 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 553 554 mii->mii_readreg = cas_pcs_readreg; 555 mii->mii_writereg = cas_pcs_writereg; 556 557 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 558 MII_OFFSET_ANY, MIIF_NOISOLATE); 559 } 560 561 child = LIST_FIRST(&mii->mii_phys); 562 if (child == NULL) { 563 /* No PHY attached */ 564 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 565 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 566 } else { 567 /* 568 * Walk along the list of attached MII devices and 569 * establish an `MII instance' to `phy number' 570 * mapping. We'll use this mapping in media change 571 * requests to determine which phy to use to program 572 * the MIF configuration register. 573 */ 574 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 575 /* 576 * Note: we support just two PHYs: the built-in 577 * internal device and an external on the MII 578 * connector. 579 */ 580 if (child->mii_phy > 1 || child->mii_inst > 1) { 581 aprint_error_dev(sc->sc_dev, 582 "cannot accommodate MII device %s" 583 " at phy %d, instance %d\n", 584 device_xname(child->mii_dev), 585 child->mii_phy, child->mii_inst); 586 continue; 587 } 588 589 sc->sc_phys[child->mii_inst] = child->mii_phy; 590 } 591 592 /* 593 * XXX - we can really do the following ONLY if the 594 * phy indeed has the auto negotiation capability!! 595 */ 596 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 597 } 598 599 /* claim 802.1q capability */ 600 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 601 602 /* Attach the interface. */ 603 if_attach(ifp); 604 ether_ifattach(ifp, enaddr); 605 606 #if NRND > 0 607 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 608 RND_TYPE_NET, 0); 609 #endif 610 611 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 612 NULL, device_xname(sc->sc_dev), "interrupts"); 613 614 callout_init(&sc->sc_tick_ch, 0); 615 616 return; 617 } 618 619 int 620 cas_detach(device_t self, int flags) 621 { 622 int i; 623 struct cas_softc *sc = device_private(self); 624 bus_space_tag_t t = sc->sc_memt; 625 bus_space_handle_t h = sc->sc_memh; 626 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 627 628 /* 629 * Free any resources we've allocated during the failed attach 630 * attempt. Do this in reverse order and fall through. 631 */ 632 switch (sc->sc_att_stage) { 633 case CAS_ATT_FINISHED: 634 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 635 pmf_device_deregister(self); 636 cas_stop(&sc->sc_ethercom.ec_if, 1); 637 evcnt_detach(&sc->sc_ev_intr); 638 639 #if NRND > 0 640 rnd_detach_source(&sc->rnd_source); 641 #endif 642 643 ether_ifdetach(ifp); 644 if_detach(ifp); 645 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 646 647 callout_destroy(&sc->sc_tick_ch); 648 649 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 650 651 /*FALLTHROUGH*/ 652 case CAS_ATT_MII: 653 case CAS_ATT_7: 654 case CAS_ATT_6: 655 for (i = 0; i < CAS_NTXDESC; i++) { 656 if (sc->sc_txd[i].sd_map != NULL) 657 bus_dmamap_destroy(sc->sc_dmatag, 658 sc->sc_txd[i].sd_map); 659 } 660 /*FALLTHROUGH*/ 661 case CAS_ATT_5: 662 for (i = 0; i < CAS_NRXDESC; i++) { 663 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 664 bus_dmamap_unload(sc->sc_dmatag, 665 sc->sc_rxsoft[i].rxs_dmamap); 666 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 667 bus_dmamap_destroy(sc->sc_dmatag, 668 sc->sc_rxsoft[i].rxs_dmamap); 669 if (sc->sc_rxsoft[i].rxs_kva != NULL) 670 bus_dmamem_unmap(sc->sc_dmatag, 671 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 672 /* XXX need to check that bus_dmamem_alloc suceeded 673 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 674 */ 675 bus_dmamem_free(sc->sc_dmatag, 676 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 677 } 678 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 679 /*FALLTHROUGH*/ 680 case CAS_ATT_4: 681 case CAS_ATT_3: 682 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 683 /*FALLTHROUGH*/ 684 case CAS_ATT_2: 685 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 686 sizeof(struct cas_control_data)); 687 /*FALLTHROUGH*/ 688 case CAS_ATT_1: 689 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 690 /*FALLTHROUGH*/ 691 case CAS_ATT_0: 692 sc->sc_att_stage = CAS_ATT_0; 693 /*FALLTHROUGH*/ 694 case CAS_ATT_BACKEND_2: 695 case CAS_ATT_BACKEND_1: 696 if (sc->sc_ih != NULL) { 697 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 698 sc->sc_ih = NULL; 699 } 700 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 701 /*FALLTHROUGH*/ 702 case CAS_ATT_BACKEND_0: 703 break; 704 } 705 return 0; 706 } 707 708 static void 709 cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 710 { 711 cfattach_t ca = device_cfattach(sc->sc_dev); 712 713 sc->sc_att_stage = stage; 714 (*ca->ca_detach)(sc->sc_dev, 0); 715 } 716 717 void 718 cas_tick(void *arg) 719 { 720 struct cas_softc *sc = arg; 721 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 722 bus_space_tag_t t = sc->sc_memt; 723 bus_space_handle_t mac = sc->sc_memh; 724 int s; 725 u_int32_t v; 726 727 /* unload collisions counters */ 728 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 729 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 730 ifp->if_collisions += v + 731 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 732 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 733 ifp->if_oerrors += v; 734 735 /* read error counters */ 736 ifp->if_ierrors += 737 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 738 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 739 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 740 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 741 742 /* clear the hardware counters */ 743 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 744 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 745 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 746 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 747 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 748 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 749 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 750 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 751 752 s = splnet(); 753 mii_tick(&sc->sc_mii); 754 splx(s); 755 756 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 757 } 758 759 int 760 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 761 u_int32_t clr, u_int32_t set) 762 { 763 int i; 764 u_int32_t reg; 765 766 for (i = TRIES; i--; DELAY(100)) { 767 reg = bus_space_read_4(sc->sc_memt, h, r); 768 if ((reg & clr) == 0 && (reg & set) == set) 769 return (1); 770 } 771 772 return (0); 773 } 774 775 void 776 cas_reset(struct cas_softc *sc) 777 { 778 bus_space_tag_t t = sc->sc_memt; 779 bus_space_handle_t h = sc->sc_memh; 780 int s; 781 782 s = splnet(); 783 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 784 cas_reset_rx(sc); 785 cas_reset_tx(sc); 786 787 /* Do a full reset */ 788 bus_space_write_4(t, h, CAS_RESET, 789 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 790 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 791 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 792 splx(s); 793 } 794 795 796 /* 797 * cas_rxdrain: 798 * 799 * Drain the receive queue. 800 */ 801 void 802 cas_rxdrain(struct cas_softc *sc) 803 { 804 /* Nothing to do yet. */ 805 } 806 807 /* 808 * Reset the whole thing. 809 */ 810 void 811 cas_stop(struct ifnet *ifp, int disable) 812 { 813 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 814 struct cas_sxd *sd; 815 u_int32_t i; 816 817 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 818 819 callout_stop(&sc->sc_tick_ch); 820 821 /* 822 * Mark the interface down and cancel the watchdog timer. 823 */ 824 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 825 ifp->if_timer = 0; 826 827 mii_down(&sc->sc_mii); 828 829 cas_reset_rx(sc); 830 cas_reset_tx(sc); 831 832 /* 833 * Release any queued transmit buffers. 834 */ 835 for (i = 0; i < CAS_NTXDESC; i++) { 836 sd = &sc->sc_txd[i]; 837 if (sd->sd_mbuf != NULL) { 838 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 839 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 840 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 841 m_freem(sd->sd_mbuf); 842 sd->sd_mbuf = NULL; 843 } 844 } 845 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 846 847 if (disable) 848 cas_rxdrain(sc); 849 } 850 851 852 /* 853 * Reset the receiver 854 */ 855 int 856 cas_reset_rx(struct cas_softc *sc) 857 { 858 bus_space_tag_t t = sc->sc_memt; 859 bus_space_handle_t h = sc->sc_memh; 860 861 /* 862 * Resetting while DMA is in progress can cause a bus hang, so we 863 * disable DMA first. 864 */ 865 cas_disable_rx(sc); 866 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 867 /* Wait till it finishes */ 868 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 869 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 870 /* Wait 5ms extra. */ 871 delay(5000); 872 873 /* Finally, reset the ERX */ 874 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 875 /* Wait till it finishes */ 876 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 877 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 878 return (1); 879 } 880 return (0); 881 } 882 883 884 /* 885 * Reset the transmitter 886 */ 887 int 888 cas_reset_tx(struct cas_softc *sc) 889 { 890 bus_space_tag_t t = sc->sc_memt; 891 bus_space_handle_t h = sc->sc_memh; 892 893 /* 894 * Resetting while DMA is in progress can cause a bus hang, so we 895 * disable DMA first. 896 */ 897 cas_disable_tx(sc); 898 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 899 /* Wait till it finishes */ 900 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 901 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 902 /* Wait 5ms extra. */ 903 delay(5000); 904 905 /* Finally, reset the ETX */ 906 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 907 /* Wait till it finishes */ 908 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 909 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 910 return (1); 911 } 912 return (0); 913 } 914 915 /* 916 * Disable receiver. 917 */ 918 int 919 cas_disable_rx(struct cas_softc *sc) 920 { 921 bus_space_tag_t t = sc->sc_memt; 922 bus_space_handle_t h = sc->sc_memh; 923 u_int32_t cfg; 924 925 /* Flip the enable bit */ 926 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 927 cfg &= ~CAS_MAC_RX_ENABLE; 928 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 929 930 /* Wait for it to finish */ 931 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 932 } 933 934 /* 935 * Disable transmitter. 936 */ 937 int 938 cas_disable_tx(struct cas_softc *sc) 939 { 940 bus_space_tag_t t = sc->sc_memt; 941 bus_space_handle_t h = sc->sc_memh; 942 u_int32_t cfg; 943 944 /* Flip the enable bit */ 945 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 946 cfg &= ~CAS_MAC_TX_ENABLE; 947 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 948 949 /* Wait for it to finish */ 950 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 951 } 952 953 /* 954 * Initialize interface. 955 */ 956 int 957 cas_meminit(struct cas_softc *sc) 958 { 959 struct cas_rxsoft *rxs; 960 int i, error; 961 962 rxs = (void *)&error; 963 964 /* 965 * Initialize the transmit descriptor ring. 966 */ 967 for (i = 0; i < CAS_NTXDESC; i++) { 968 sc->sc_txdescs[i].cd_flags = 0; 969 sc->sc_txdescs[i].cd_addr = 0; 970 } 971 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 972 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 973 974 /* 975 * Initialize the receive descriptor and receive job 976 * descriptor rings. 977 */ 978 for (i = 0; i < CAS_NRXDESC; i++) 979 CAS_INIT_RXDESC(sc, i, i); 980 sc->sc_rxdptr = 0; 981 sc->sc_rxptr = 0; 982 983 /* 984 * Initialize the receive completion ring. 985 */ 986 for (i = 0; i < CAS_NRXCOMP; i++) { 987 sc->sc_rxcomps[i].cc_word[0] = 0; 988 sc->sc_rxcomps[i].cc_word[1] = 0; 989 sc->sc_rxcomps[i].cc_word[2] = 0; 990 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 991 CAS_CDRXCSYNC(sc, i, 992 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 993 } 994 995 return (0); 996 } 997 998 int 999 cas_ringsize(int sz) 1000 { 1001 switch (sz) { 1002 case 32: 1003 return CAS_RING_SZ_32; 1004 case 64: 1005 return CAS_RING_SZ_64; 1006 case 128: 1007 return CAS_RING_SZ_128; 1008 case 256: 1009 return CAS_RING_SZ_256; 1010 case 512: 1011 return CAS_RING_SZ_512; 1012 case 1024: 1013 return CAS_RING_SZ_1024; 1014 case 2048: 1015 return CAS_RING_SZ_2048; 1016 case 4096: 1017 return CAS_RING_SZ_4096; 1018 case 8192: 1019 return CAS_RING_SZ_8192; 1020 default: 1021 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1022 sz); 1023 return CAS_RING_SZ_32; 1024 } 1025 } 1026 1027 int 1028 cas_cringsize(int sz) 1029 { 1030 int i; 1031 1032 for (i = 0; i < 9; i++) 1033 if (sz == (128 << i)) 1034 return i; 1035 1036 aprint_error("cas: invalid completion ring size %d\n", sz); 1037 return 128; 1038 } 1039 1040 /* 1041 * Initialization of interface; set up initialization block 1042 * and transmit/receive descriptor rings. 1043 */ 1044 int 1045 cas_init(struct ifnet *ifp) 1046 { 1047 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1048 bus_space_tag_t t = sc->sc_memt; 1049 bus_space_handle_t h = sc->sc_memh; 1050 int s; 1051 u_int max_frame_size; 1052 u_int32_t v; 1053 1054 s = splnet(); 1055 1056 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1057 /* 1058 * Initialization sequence. The numbered steps below correspond 1059 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1060 * Channel Engine manual (part of the PCIO manual). 1061 * See also the STP2002-STQ document from Sun Microsystems. 1062 */ 1063 1064 /* step 1 & 2. Reset the Ethernet Channel */ 1065 cas_stop(ifp, 0); 1066 cas_reset(sc); 1067 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1068 1069 /* Re-initialize the MIF */ 1070 cas_mifinit(sc); 1071 1072 /* step 3. Setup data structures in host memory */ 1073 cas_meminit(sc); 1074 1075 /* step 4. TX MAC registers & counters */ 1076 cas_init_regs(sc); 1077 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1078 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1079 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1080 1081 /* step 5. RX MAC registers & counters */ 1082 cas_iff(sc); 1083 1084 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1085 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1086 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1087 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1088 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1089 1090 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1091 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1092 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1093 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1094 1095 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1096 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1097 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1098 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1099 1100 if (CAS_PLUS(sc)) { 1101 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1102 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1103 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1104 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1105 CAS_CDRXADDR2(sc, 0)); 1106 } 1107 1108 /* step 8. Global Configuration & Interrupt Mask */ 1109 cas_estintr(sc, CAS_INTR_REG); 1110 1111 /* step 9. ETX Configuration: use mostly default values */ 1112 1113 /* Enable DMA */ 1114 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1115 bus_space_write_4(t, h, CAS_TX_CONFIG, 1116 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1117 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1118 1119 /* step 10. ERX Configuration */ 1120 1121 /* Encode Receive Descriptor ring size */ 1122 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1123 if (CAS_PLUS(sc)) 1124 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1125 1126 /* Encode Receive Completion ring size */ 1127 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1128 1129 /* Enable DMA */ 1130 bus_space_write_4(t, h, CAS_RX_CONFIG, 1131 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1132 1133 /* 1134 * The following value is for an OFF Threshold of about 3/4 full 1135 * and an ON Threshold of 1/4 full. 1136 */ 1137 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1138 (3 * sc->sc_rxfifosize / 256) | 1139 ((sc->sc_rxfifosize / 256) << 12)); 1140 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1141 1142 /* step 11. Configure Media */ 1143 mii_ifmedia_change(&sc->sc_mii); 1144 1145 /* step 12. RX_MAC Configuration Register */ 1146 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1147 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1148 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1149 1150 /* step 14. Issue Transmit Pending command */ 1151 1152 /* step 15. Give the receiver a swift kick */ 1153 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1154 if (CAS_PLUS(sc)) 1155 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1156 1157 /* Start the one second timer. */ 1158 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1159 1160 ifp->if_flags |= IFF_RUNNING; 1161 ifp->if_flags &= ~IFF_OACTIVE; 1162 ifp->if_timer = 0; 1163 splx(s); 1164 1165 return (0); 1166 } 1167 1168 void 1169 cas_init_regs(struct cas_softc *sc) 1170 { 1171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1172 bus_space_tag_t t = sc->sc_memt; 1173 bus_space_handle_t h = sc->sc_memh; 1174 const u_char *laddr = CLLADDR(ifp->if_sadl); 1175 u_int32_t v, r; 1176 1177 /* These regs are not cleared on reset */ 1178 sc->sc_inited = 0; 1179 if (!sc->sc_inited) { 1180 /* Load recommended values */ 1181 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1182 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1183 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1184 1185 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1186 /* Max frame and max burst size */ 1187 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1188 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1189 1190 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1191 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1192 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1193 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1194 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1195 ((laddr[5]<<8)|laddr[4])&0x3ff); 1196 1197 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1198 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1199 bus_space_write_4(t, h, r, 0); 1200 1201 /* MAC control addr set to 0:1:c2:0:1:80 */ 1202 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1203 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1204 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1205 1206 /* MAC filter addr set to 0:0:0:0:0:0 */ 1207 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1208 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1209 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1210 1211 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1212 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1213 1214 /* Hash table initialized to 0 */ 1215 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1216 bus_space_write_4(t, h, r, 0); 1217 1218 sc->sc_inited = 1; 1219 } 1220 1221 /* Counters need to be zeroed */ 1222 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1223 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1224 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1225 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1226 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1227 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1228 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1229 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1230 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1231 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1232 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1233 1234 /* Un-pause stuff */ 1235 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1236 1237 /* 1238 * Set the station address. 1239 */ 1240 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1241 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1242 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1243 } 1244 1245 /* 1246 * Receive interrupt. 1247 */ 1248 int 1249 cas_rint(struct cas_softc *sc) 1250 { 1251 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1252 bus_space_tag_t t = sc->sc_memt; 1253 bus_space_handle_t h = sc->sc_memh; 1254 struct cas_rxsoft *rxs; 1255 struct mbuf *m; 1256 u_int64_t word[4]; 1257 int len, off, idx; 1258 int i, skip; 1259 void *cp; 1260 1261 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1262 CAS_CDRXCSYNC(sc, i, 1263 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1264 1265 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1266 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1267 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1268 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1269 1270 /* Stop if the hardware still owns the descriptor. */ 1271 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1272 break; 1273 1274 len = CAS_RC1_HDR_LEN(word[1]); 1275 if (len > 0) { 1276 off = CAS_RC1_HDR_OFF(word[1]); 1277 idx = CAS_RC1_HDR_IDX(word[1]); 1278 rxs = &sc->sc_rxsoft[idx]; 1279 1280 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1281 idx, off, len)); 1282 1283 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1284 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1285 1286 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1287 m = m_devget(cp, len, 0, ifp, NULL); 1288 1289 if (word[0] & CAS_RC0_RELEASE_HDR) 1290 cas_add_rxbuf(sc, idx); 1291 1292 if (m != NULL) { 1293 1294 /* 1295 * Pass this up to any BPF listeners, but only 1296 * pass it up the stack if its for us. 1297 */ 1298 if (ifp->if_bpf) 1299 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1300 1301 ifp->if_ipackets++; 1302 m->m_pkthdr.csum_flags = 0; 1303 (*ifp->if_input)(ifp, m); 1304 } else 1305 ifp->if_ierrors++; 1306 } 1307 1308 len = CAS_RC0_DATA_LEN(word[0]); 1309 if (len > 0) { 1310 off = CAS_RC0_DATA_OFF(word[0]); 1311 idx = CAS_RC0_DATA_IDX(word[0]); 1312 rxs = &sc->sc_rxsoft[idx]; 1313 1314 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1315 idx, off, len)); 1316 1317 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1318 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1319 1320 /* XXX We should not be copying the packet here. */ 1321 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1322 m = m_devget(cp, len, 0, ifp, NULL); 1323 1324 if (word[0] & CAS_RC0_RELEASE_DATA) 1325 cas_add_rxbuf(sc, idx); 1326 1327 if (m != NULL) { 1328 /* 1329 * Pass this up to any BPF listeners, but only 1330 * pass it up the stack if its for us. 1331 */ 1332 if (ifp->if_bpf) 1333 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1334 1335 ifp->if_ipackets++; 1336 m->m_pkthdr.csum_flags = 0; 1337 (*ifp->if_input)(ifp, m); 1338 } else 1339 ifp->if_ierrors++; 1340 } 1341 1342 if (word[0] & CAS_RC0_SPLIT) 1343 aprint_error_dev(sc->sc_dev, "split packet\n"); 1344 1345 skip = CAS_RC0_SKIP(word[0]); 1346 } 1347 1348 while (sc->sc_rxptr != i) { 1349 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1350 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1351 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1352 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1353 CAS_DMA_WRITE(CAS_RC3_OWN); 1354 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1355 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1356 1357 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1358 } 1359 1360 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1361 1362 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1363 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1364 1365 return (1); 1366 } 1367 1368 /* 1369 * cas_add_rxbuf: 1370 * 1371 * Add a receive buffer to the indicated descriptor. 1372 */ 1373 int 1374 cas_add_rxbuf(struct cas_softc *sc, int idx) 1375 { 1376 bus_space_tag_t t = sc->sc_memt; 1377 bus_space_handle_t h = sc->sc_memh; 1378 1379 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1380 1381 if ((sc->sc_rxdptr % 4) == 0) 1382 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1383 1384 if (++sc->sc_rxdptr == CAS_NRXDESC) 1385 sc->sc_rxdptr = 0; 1386 1387 return (0); 1388 } 1389 1390 int 1391 cas_eint(struct cas_softc *sc, u_int status) 1392 { 1393 char bits[128]; 1394 if ((status & CAS_INTR_MIF) != 0) { 1395 DPRINTF(sc, ("%s: link status changed\n", 1396 device_xname(sc->sc_dev))); 1397 return (1); 1398 } 1399 1400 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1401 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1402 return (1); 1403 } 1404 1405 int 1406 cas_pint(struct cas_softc *sc) 1407 { 1408 bus_space_tag_t t = sc->sc_memt; 1409 bus_space_handle_t seb = sc->sc_memh; 1410 u_int32_t status; 1411 1412 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1413 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1414 #ifdef CAS_DEBUG 1415 if (status) 1416 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1417 #endif 1418 return (1); 1419 } 1420 1421 int 1422 cas_intr(void *v) 1423 { 1424 struct cas_softc *sc = (struct cas_softc *)v; 1425 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1426 bus_space_tag_t t = sc->sc_memt; 1427 bus_space_handle_t seb = sc->sc_memh; 1428 u_int32_t status; 1429 int r = 0; 1430 #ifdef CAS_DEBUG 1431 char bits[128]; 1432 #endif 1433 1434 sc->sc_ev_intr.ev_count++; 1435 1436 status = bus_space_read_4(t, seb, CAS_STATUS); 1437 #ifdef CAS_DEBUG 1438 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1439 #endif 1440 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1441 device_xname(sc->sc_dev), (status>>19), bits)); 1442 1443 if ((status & CAS_INTR_PCS) != 0) 1444 r |= cas_pint(sc); 1445 1446 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1447 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1448 r |= cas_eint(sc, status); 1449 1450 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1451 r |= cas_tint(sc, status); 1452 1453 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1454 r |= cas_rint(sc); 1455 1456 /* We should eventually do more than just print out error stats. */ 1457 if (status & CAS_INTR_TX_MAC) { 1458 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1459 #ifdef CAS_DEBUG 1460 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1461 printf("%s: MAC tx fault, status %x\n", 1462 device_xname(sc->sc_dev), txstat); 1463 #endif 1464 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1465 cas_init(ifp); 1466 } 1467 if (status & CAS_INTR_RX_MAC) { 1468 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1469 #ifdef CAS_DEBUG 1470 if (rxstat & ~CAS_MAC_RX_DONE) 1471 printf("%s: MAC rx fault, status %x\n", 1472 device_xname(sc->sc_dev), rxstat); 1473 #endif 1474 /* 1475 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1476 * due to a silicon bug so handle them silently. 1477 */ 1478 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1479 ifp->if_ierrors++; 1480 cas_init(ifp); 1481 } 1482 #ifdef CAS_DEBUG 1483 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1484 printf("%s: MAC rx fault, status %x\n", 1485 device_xname(sc->sc_dev), rxstat); 1486 #endif 1487 } 1488 #if NRND > 0 1489 rnd_add_uint32(&sc->rnd_source, status); 1490 #endif 1491 return (r); 1492 } 1493 1494 1495 void 1496 cas_watchdog(struct ifnet *ifp) 1497 { 1498 struct cas_softc *sc = ifp->if_softc; 1499 1500 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1501 "CAS_MAC_RX_CONFIG %x\n", 1502 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1503 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1504 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1505 1506 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1507 ++ifp->if_oerrors; 1508 1509 /* Try to get more packets going. */ 1510 cas_init(ifp); 1511 } 1512 1513 /* 1514 * Initialize the MII Management Interface 1515 */ 1516 void 1517 cas_mifinit(struct cas_softc *sc) 1518 { 1519 bus_space_tag_t t = sc->sc_memt; 1520 bus_space_handle_t mif = sc->sc_memh; 1521 1522 /* Configure the MIF in frame mode */ 1523 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1524 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1525 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1526 } 1527 1528 /* 1529 * MII interface 1530 * 1531 * The Cassini MII interface supports at least three different operating modes: 1532 * 1533 * Bitbang mode is implemented using data, clock and output enable registers. 1534 * 1535 * Frame mode is implemented by loading a complete frame into the frame 1536 * register and polling the valid bit for completion. 1537 * 1538 * Polling mode uses the frame register but completion is indicated by 1539 * an interrupt. 1540 * 1541 */ 1542 int 1543 cas_mii_readreg(device_t self, int phy, int reg) 1544 { 1545 struct cas_softc *sc = device_private(self); 1546 bus_space_tag_t t = sc->sc_memt; 1547 bus_space_handle_t mif = sc->sc_memh; 1548 int n; 1549 u_int32_t v; 1550 1551 #ifdef CAS_DEBUG 1552 if (sc->sc_debug) 1553 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1554 #endif 1555 1556 /* Construct the frame command */ 1557 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1558 CAS_MIF_FRAME_READ; 1559 1560 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1561 for (n = 0; n < 100; n++) { 1562 DELAY(1); 1563 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1564 if (v & CAS_MIF_FRAME_TA0) 1565 return (v & CAS_MIF_FRAME_DATA); 1566 } 1567 1568 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1569 return (0); 1570 } 1571 1572 void 1573 cas_mii_writereg(device_t self, int phy, int reg, int val) 1574 { 1575 struct cas_softc *sc = device_private(self); 1576 bus_space_tag_t t = sc->sc_memt; 1577 bus_space_handle_t mif = sc->sc_memh; 1578 int n; 1579 u_int32_t v; 1580 1581 #ifdef CAS_DEBUG 1582 if (sc->sc_debug) 1583 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1584 phy, reg, val); 1585 #endif 1586 1587 /* Construct the frame command */ 1588 v = CAS_MIF_FRAME_WRITE | 1589 (phy << CAS_MIF_PHY_SHIFT) | 1590 (reg << CAS_MIF_REG_SHIFT) | 1591 (val & CAS_MIF_FRAME_DATA); 1592 1593 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1594 for (n = 0; n < 100; n++) { 1595 DELAY(1); 1596 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1597 if (v & CAS_MIF_FRAME_TA0) 1598 return; 1599 } 1600 1601 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1602 } 1603 1604 void 1605 cas_mii_statchg(device_t self) 1606 { 1607 struct cas_softc *sc = device_private(self); 1608 #ifdef CAS_DEBUG 1609 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1610 #endif 1611 bus_space_tag_t t = sc->sc_memt; 1612 bus_space_handle_t mac = sc->sc_memh; 1613 u_int32_t v; 1614 1615 #ifdef CAS_DEBUG 1616 if (sc->sc_debug) 1617 printf("cas_mii_statchg: status change: phy = %d\n", 1618 sc->sc_phys[instance]); 1619 #endif 1620 1621 /* Set tx full duplex options */ 1622 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1623 delay(10000); /* reg must be cleared and delay before changing. */ 1624 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1625 CAS_MAC_TX_ENABLE; 1626 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1627 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1628 } 1629 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1630 1631 /* XIF Configuration */ 1632 v = CAS_MAC_XIF_TX_MII_ENA; 1633 v |= CAS_MAC_XIF_LINK_LED; 1634 1635 /* MII needs echo disable if half duplex. */ 1636 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1637 /* turn on full duplex LED */ 1638 v |= CAS_MAC_XIF_FDPLX_LED; 1639 else 1640 /* half duplex -- disable echo */ 1641 v |= CAS_MAC_XIF_ECHO_DISABL; 1642 1643 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1644 case IFM_1000_T: /* Gigabit using GMII interface */ 1645 case IFM_1000_SX: 1646 v |= CAS_MAC_XIF_GMII_MODE; 1647 break; 1648 default: 1649 v &= ~CAS_MAC_XIF_GMII_MODE; 1650 } 1651 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1652 } 1653 1654 int 1655 cas_pcs_readreg(device_t self, int phy, int reg) 1656 { 1657 struct cas_softc *sc = device_private(self); 1658 bus_space_tag_t t = sc->sc_memt; 1659 bus_space_handle_t pcs = sc->sc_memh; 1660 1661 #ifdef CAS_DEBUG 1662 if (sc->sc_debug) 1663 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1664 #endif 1665 1666 if (phy != CAS_PHYAD_EXTERNAL) 1667 return (0); 1668 1669 switch (reg) { 1670 case MII_BMCR: 1671 reg = CAS_MII_CONTROL; 1672 break; 1673 case MII_BMSR: 1674 reg = CAS_MII_STATUS; 1675 break; 1676 case MII_ANAR: 1677 reg = CAS_MII_ANAR; 1678 break; 1679 case MII_ANLPAR: 1680 reg = CAS_MII_ANLPAR; 1681 break; 1682 case MII_EXTSR: 1683 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1684 default: 1685 return (0); 1686 } 1687 1688 return bus_space_read_4(t, pcs, reg); 1689 } 1690 1691 void 1692 cas_pcs_writereg(device_t self, int phy, int reg, int val) 1693 { 1694 struct cas_softc *sc = device_private(self); 1695 bus_space_tag_t t = sc->sc_memt; 1696 bus_space_handle_t pcs = sc->sc_memh; 1697 int reset = 0; 1698 1699 #ifdef CAS_DEBUG 1700 if (sc->sc_debug) 1701 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1702 phy, reg, val); 1703 #endif 1704 1705 if (phy != CAS_PHYAD_EXTERNAL) 1706 return; 1707 1708 if (reg == MII_ANAR) 1709 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1710 1711 switch (reg) { 1712 case MII_BMCR: 1713 reset = (val & CAS_MII_CONTROL_RESET); 1714 reg = CAS_MII_CONTROL; 1715 break; 1716 case MII_BMSR: 1717 reg = CAS_MII_STATUS; 1718 break; 1719 case MII_ANAR: 1720 reg = CAS_MII_ANAR; 1721 break; 1722 case MII_ANLPAR: 1723 reg = CAS_MII_ANLPAR; 1724 break; 1725 default: 1726 return; 1727 } 1728 1729 bus_space_write_4(t, pcs, reg, val); 1730 1731 if (reset) 1732 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1733 1734 if (reg == CAS_MII_ANAR || reset) 1735 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1736 CAS_MII_CONFIG_ENABLE); 1737 } 1738 1739 int 1740 cas_mediachange(struct ifnet *ifp) 1741 { 1742 struct cas_softc *sc = ifp->if_softc; 1743 struct mii_data *mii = &sc->sc_mii; 1744 1745 if (mii->mii_instance) { 1746 struct mii_softc *miisc; 1747 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1748 mii_phy_reset(miisc); 1749 } 1750 1751 return (mii_mediachg(&sc->sc_mii)); 1752 } 1753 1754 void 1755 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1756 { 1757 struct cas_softc *sc = ifp->if_softc; 1758 1759 mii_pollstat(&sc->sc_mii); 1760 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1761 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1762 } 1763 1764 /* 1765 * Process an ioctl request. 1766 */ 1767 int 1768 cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1769 { 1770 struct cas_softc *sc = ifp->if_softc; 1771 int s, error = 0; 1772 1773 s = splnet(); 1774 1775 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1776 error = 0; 1777 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1778 ; 1779 else if (ifp->if_flags & IFF_RUNNING) { 1780 /* 1781 * Multicast list has changed; set the hardware filter 1782 * accordingly. 1783 */ 1784 cas_iff(sc); 1785 } 1786 } 1787 1788 splx(s); 1789 return (error); 1790 } 1791 1792 static bool 1793 cas_suspend(device_t self, const pmf_qual_t *qual) 1794 { 1795 struct cas_softc *sc = device_private(self); 1796 bus_space_tag_t t = sc->sc_memt; 1797 bus_space_handle_t h = sc->sc_memh; 1798 1799 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1800 if (sc->sc_ih != NULL) { 1801 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1802 sc->sc_ih = NULL; 1803 } 1804 1805 return true; 1806 } 1807 1808 static bool 1809 cas_resume(device_t self, const pmf_qual_t *qual) 1810 { 1811 struct cas_softc *sc = device_private(self); 1812 1813 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1814 } 1815 1816 static bool 1817 cas_estintr(struct cas_softc *sc, int what) 1818 { 1819 bus_space_tag_t t = sc->sc_memt; 1820 bus_space_handle_t h = sc->sc_memh; 1821 const char *intrstr = NULL; 1822 1823 /* PCI interrupts */ 1824 if (what & CAS_INTR_PCI) { 1825 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle); 1826 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1827 IPL_NET, cas_intr, sc); 1828 if (sc->sc_ih == NULL) { 1829 aprint_error_dev(sc->sc_dev, 1830 "unable to establish interrupt"); 1831 if (intrstr != NULL) 1832 aprint_error(" at %s", intrstr); 1833 aprint_error("\n"); 1834 return false; 1835 } 1836 1837 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1838 } 1839 1840 /* Interrupt register */ 1841 if (what & CAS_INTR_REG) { 1842 bus_space_write_4(t, h, CAS_INTMASK, 1843 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1844 CAS_INTR_TX_TAG_ERR| 1845 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1846 CAS_INTR_RX_TAG_ERR| 1847 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1848 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1849 CAS_INTR_BERR)); 1850 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1851 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1852 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1853 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1854 } 1855 return true; 1856 } 1857 1858 bool 1859 cas_shutdown(device_t self, int howto) 1860 { 1861 struct cas_softc *sc = device_private(self); 1862 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1863 1864 cas_stop(ifp, 1); 1865 1866 return true; 1867 } 1868 1869 void 1870 cas_iff(struct cas_softc *sc) 1871 { 1872 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1873 struct ethercom *ec = &sc->sc_ethercom; 1874 struct ether_multi *enm; 1875 struct ether_multistep step; 1876 bus_space_tag_t t = sc->sc_memt; 1877 bus_space_handle_t h = sc->sc_memh; 1878 u_int32_t crc, hash[16], rxcfg; 1879 int i; 1880 1881 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1882 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1883 CAS_MAC_RX_PROMISC_GRP); 1884 ifp->if_flags &= ~IFF_ALLMULTI; 1885 1886 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1887 ifp->if_flags |= IFF_ALLMULTI; 1888 if (ifp->if_flags & IFF_PROMISC) 1889 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1890 else 1891 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1892 } else { 1893 /* 1894 * Set up multicast address filter by passing all multicast 1895 * addresses through a crc generator, and then using the 1896 * high order 8 bits as an index into the 256 bit logical 1897 * address filter. The high order 4 bits selects the word, 1898 * while the other 4 bits select the bit within the word 1899 * (where bit 0 is the MSB). 1900 */ 1901 1902 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1903 1904 /* Clear hash table */ 1905 for (i = 0; i < 16; i++) 1906 hash[i] = 0; 1907 1908 ETHER_FIRST_MULTI(step, ec, enm); 1909 while (enm != NULL) { 1910 crc = ether_crc32_le(enm->enm_addrlo, 1911 ETHER_ADDR_LEN); 1912 1913 /* Just want the 8 most significant bits. */ 1914 crc >>= 24; 1915 1916 /* Set the corresponding bit in the filter. */ 1917 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1918 1919 ETHER_NEXT_MULTI(step, enm); 1920 } 1921 1922 /* Now load the hash table into the chip (if we are using it) */ 1923 for (i = 0; i < 16; i++) { 1924 bus_space_write_4(t, h, 1925 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1926 hash[i]); 1927 } 1928 } 1929 1930 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1931 } 1932 1933 int 1934 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1935 { 1936 u_int64_t flags; 1937 u_int32_t cur, frag, i; 1938 bus_dmamap_t map; 1939 1940 cur = frag = *bixp; 1941 map = sc->sc_txd[cur].sd_map; 1942 1943 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1944 BUS_DMA_NOWAIT) != 0) { 1945 return (ENOBUFS); 1946 } 1947 1948 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1949 bus_dmamap_unload(sc->sc_dmatag, map); 1950 return (ENOBUFS); 1951 } 1952 1953 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1954 BUS_DMASYNC_PREWRITE); 1955 1956 for (i = 0; i < map->dm_nsegs; i++) { 1957 sc->sc_txdescs[frag].cd_addr = 1958 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1959 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1960 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1961 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1962 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1963 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1964 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1965 BUS_DMASYNC_PREWRITE); 1966 cur = frag; 1967 if (++frag == CAS_NTXDESC) 1968 frag = 0; 1969 } 1970 1971 sc->sc_tx_cnt += map->dm_nsegs; 1972 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1973 sc->sc_txd[cur].sd_map = map; 1974 sc->sc_txd[cur].sd_mbuf = mhead; 1975 1976 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1977 1978 *bixp = frag; 1979 1980 /* sync descriptors */ 1981 1982 return (0); 1983 } 1984 1985 /* 1986 * Transmit interrupt. 1987 */ 1988 int 1989 cas_tint(struct cas_softc *sc, u_int32_t status) 1990 { 1991 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1992 struct cas_sxd *sd; 1993 u_int32_t cons, comp; 1994 1995 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 1996 cons = sc->sc_tx_cons; 1997 while (cons != comp) { 1998 sd = &sc->sc_txd[cons]; 1999 if (sd->sd_mbuf != NULL) { 2000 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2001 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2002 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2003 m_freem(sd->sd_mbuf); 2004 sd->sd_mbuf = NULL; 2005 ifp->if_opackets++; 2006 } 2007 sc->sc_tx_cnt--; 2008 if (++cons == CAS_NTXDESC) 2009 cons = 0; 2010 } 2011 sc->sc_tx_cons = cons; 2012 2013 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2014 ifp->if_flags &= ~IFF_OACTIVE; 2015 if (sc->sc_tx_cnt == 0) 2016 ifp->if_timer = 0; 2017 2018 cas_start(ifp); 2019 2020 return (1); 2021 } 2022 2023 void 2024 cas_start(struct ifnet *ifp) 2025 { 2026 struct cas_softc *sc = ifp->if_softc; 2027 struct mbuf *m; 2028 u_int32_t bix; 2029 2030 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2031 return; 2032 2033 bix = sc->sc_tx_prod; 2034 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2035 IFQ_POLL(&ifp->if_snd, m); 2036 if (m == NULL) 2037 break; 2038 2039 /* 2040 * If BPF is listening on this interface, let it see the 2041 * packet before we commit it to the wire. 2042 */ 2043 if (ifp->if_bpf) 2044 bpf_ops->bpf_mtap(ifp->if_bpf, m); 2045 2046 /* 2047 * Encapsulate this packet and start it going... 2048 * or fail... 2049 */ 2050 if (cas_encap(sc, m, &bix)) { 2051 ifp->if_flags |= IFF_OACTIVE; 2052 break; 2053 } 2054 2055 IFQ_DEQUEUE(&ifp->if_snd, m); 2056 ifp->if_timer = 5; 2057 } 2058 2059 sc->sc_tx_prod = bix; 2060 } 2061