1 /* $NetBSD */ 2 /*- 3 * Copyright (c) 2010 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jean-Yves Migeon <jym@NetBSD.org> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ 31 */ 32 33 #ifndef _DEV_PCI_IF_BNXVAR_H_ 34 #define _DEV_PCI_IF_BNXVAR_H_ 35 36 #ifdef _KERNEL_OPT 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 //#include <sys/workqueue.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #include <net/if_vlanvar.h> 65 66 #include <net/bpf.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 #include <dev/mii/miidevs.h> 75 #include <dev/mii/brgphyreg.h> 76 77 /* 78 * PCI registers defined in the PCI 2.2 spec. 79 */ 80 #define BNX_PCI_BAR0 0x10 81 #define BNX_PCI_PCIX_CMD 0x40 82 83 /****************************************************************************/ 84 /* Convenience definitions. */ 85 /****************************************************************************/ 86 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 87 #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) 88 #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 89 #define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) 90 #define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) 91 #define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) 92 #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 93 #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 94 #define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 95 #define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 96 97 /****************************************************************************/ 98 /* BNX Device State Data Structure */ 99 /****************************************************************************/ 100 101 #define BNX_STATUS_BLK_SZ sizeof(struct status_block) 102 #define BNX_STATS_BLK_SZ sizeof(struct statistics_block) 103 #define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 104 #define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 105 106 struct bnx_pkt { 107 TAILQ_ENTRY(bnx_pkt) pkt_entry; 108 bus_dmamap_t pkt_dmamap; 109 struct mbuf *pkt_mbuf; 110 u_int16_t pkt_end_desc; 111 }; 112 113 TAILQ_HEAD(bnx_pkt_list, bnx_pkt); 114 115 struct bnx_softc 116 { 117 device_t bnx_dev; 118 struct ethercom bnx_ec; 119 struct pci_attach_args bnx_pa; 120 121 struct ifmedia bnx_ifmedia; /* TBI media info */ 122 123 bus_space_tag_t bnx_btag; /* Device bus tag */ 124 bus_space_handle_t bnx_bhandle; /* Device bus handle */ 125 bus_size_t bnx_size; 126 127 void *bnx_intrhand; /* Interrupt handler */ 128 129 /* ASIC Chip ID. */ 130 u_int32_t bnx_chipid; 131 132 /* General controller flags. */ 133 u_int32_t bnx_flags; 134 135 /* PHY specific flags. */ 136 u_int32_t bnx_phy_flags; 137 138 /* Values that need to be shared with the PHY driver. */ 139 u_int32_t bnx_shared_hw_cfg; 140 u_int32_t bnx_port_hw_cfg; 141 142 u_int16_t bus_speed_mhz; /* PCI bus speed */ 143 struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ 144 u_int32_t bnx_flash_size; /* Flash NVRAM size */ 145 u_int32_t bnx_shmem_base; /* Shared Memory base address */ 146 char * bnx_name; /* Name string */ 147 148 /* Tracks the version of bootcode firmware. */ 149 u_int32_t bnx_fw_ver; 150 151 /* Tracks the state of the firmware. 0 = Running while any */ 152 /* other value indicates that the firmware is not responding. */ 153 u_int16_t bnx_fw_timed_out; 154 155 /* An incrementing sequence used to coordinate messages passed */ 156 /* from the driver to the firmware. */ 157 u_int16_t bnx_fw_wr_seq; 158 159 /* An incrementing sequence used to let the firmware know that */ 160 /* the driver is still operating. Without the pulse, management */ 161 /* firmware such as IPMI or UMP will operate in OS absent state. */ 162 u_int16_t bnx_fw_drv_pulse_wr_seq; 163 164 /* Ethernet MAC address. */ 165 u_char eaddr[6]; 166 167 /* These setting are used by the host coalescing (HC) block to */ 168 /* to control how often the status block, statistics block and */ 169 /* interrupts are generated. */ 170 u_int16_t bnx_tx_quick_cons_trip_int; 171 u_int16_t bnx_tx_quick_cons_trip; 172 u_int16_t bnx_rx_quick_cons_trip_int; 173 u_int16_t bnx_rx_quick_cons_trip; 174 u_int16_t bnx_comp_prod_trip_int; 175 u_int16_t bnx_comp_prod_trip; 176 u_int16_t bnx_tx_ticks_int; 177 u_int16_t bnx_tx_ticks; 178 u_int16_t bnx_rx_ticks_int; 179 u_int16_t bnx_rx_ticks; 180 u_int16_t bnx_com_ticks_int; 181 u_int16_t bnx_com_ticks; 182 u_int16_t bnx_cmd_ticks_int; 183 u_int16_t bnx_cmd_ticks; 184 u_int32_t bnx_stats_ticks; 185 186 /* The address of the integrated PHY on the MII bus. */ 187 int bnx_phy_addr; 188 189 /* The device handle for the MII bus child device. */ 190 struct mii_data bnx_mii; 191 192 /* Driver maintained TX chain pointers and byte counter. */ 193 u_int16_t rx_prod; 194 u_int16_t rx_cons; 195 u_int32_t rx_prod_bseq; /* Counts the bytes used. */ 196 u_int16_t tx_prod; 197 u_int16_t tx_cons; 198 u_int32_t tx_prod_bseq; /* Counts the bytes used. */ 199 200 struct callout bnx_timeout; 201 202 /* Frame size and mbuf allocation size for RX frames. */ 203 u_int32_t max_frame_size; 204 int mbuf_alloc_size; 205 206 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 207 u_int32_t rx_mode; 208 209 /* Bus tag for the bnx controller. */ 210 bus_dma_tag_t bnx_dmatag; 211 212 /* H/W maintained TX buffer descriptor chain structure. */ 213 bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; 214 int tx_bd_chain_rseg[TX_PAGES]; 215 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 216 struct tx_bd *tx_bd_chain[TX_PAGES]; 217 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 218 219 /* H/W maintained RX buffer descriptor chain structure. */ 220 bus_dma_segment_t rx_bd_chain_seg[TX_PAGES]; 221 int rx_bd_chain_rseg[TX_PAGES]; 222 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 223 struct rx_bd *rx_bd_chain[RX_PAGES]; 224 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 225 226 /* H/W maintained status block. */ 227 bus_dma_segment_t status_seg; 228 int status_rseg; 229 bus_dmamap_t status_map; 230 struct status_block *status_block; /* virtual address */ 231 bus_addr_t status_block_paddr; /* Physical address */ 232 233 /* H/W maintained context block */ 234 int ctx_pages; 235 bus_dma_segment_t ctx_segs[4]; 236 int ctx_rsegs[4]; 237 bus_dmamap_t ctx_map[4]; 238 void *ctx_block[4]; 239 240 /* Driver maintained status block values. */ 241 u_int16_t last_status_idx; 242 u_int16_t hw_rx_cons; 243 u_int16_t hw_tx_cons; 244 245 /* H/W maintained statistics block. */ 246 bus_dma_segment_t stats_seg; 247 int stats_rseg; 248 bus_dmamap_t stats_map; 249 struct statistics_block *stats_block; /* Virtual address */ 250 bus_addr_t stats_block_paddr; /* Physical address */ 251 252 /* Bus tag for RX/TX mbufs. */ 253 bus_dma_segment_t rx_mbuf_seg; 254 int rx_mbuf_rseg; 255 bus_dma_segment_t tx_mbuf_seg; 256 int tx_mbuf_rseg; 257 258 /* S/W maintained mbuf TX chain structure. */ 259 kmutex_t tx_pkt_mtx; 260 u_int tx_pkt_count; 261 struct bnx_pkt_list tx_free_pkts; 262 struct bnx_pkt_list tx_used_pkts; 263 264 /* S/W maintained mbuf RX chain structure. */ 265 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 266 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 267 268 /* Track the number of rx_bd and tx_bd's in use. */ 269 u_int16_t free_rx_bd; 270 u_int16_t max_rx_bd; 271 u_int16_t used_tx_bd; 272 u_int16_t max_tx_bd; 273 274 /* Provides access to hardware statistics through sysctl. */ 275 u_int64_t stat_IfHCInOctets; 276 u_int64_t stat_IfHCInBadOctets; 277 u_int64_t stat_IfHCOutOctets; 278 u_int64_t stat_IfHCOutBadOctets; 279 u_int64_t stat_IfHCInUcastPkts; 280 u_int64_t stat_IfHCInMulticastPkts; 281 u_int64_t stat_IfHCInBroadcastPkts; 282 u_int64_t stat_IfHCOutUcastPkts; 283 u_int64_t stat_IfHCOutMulticastPkts; 284 u_int64_t stat_IfHCOutBroadcastPkts; 285 286 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 287 u_int32_t stat_Dot3StatsCarrierSenseErrors; 288 u_int32_t stat_Dot3StatsFCSErrors; 289 u_int32_t stat_Dot3StatsAlignmentErrors; 290 u_int32_t stat_Dot3StatsSingleCollisionFrames; 291 u_int32_t stat_Dot3StatsMultipleCollisionFrames; 292 u_int32_t stat_Dot3StatsDeferredTransmissions; 293 u_int32_t stat_Dot3StatsExcessiveCollisions; 294 u_int32_t stat_Dot3StatsLateCollisions; 295 u_int32_t stat_EtherStatsCollisions; 296 u_int32_t stat_EtherStatsFragments; 297 u_int32_t stat_EtherStatsJabbers; 298 u_int32_t stat_EtherStatsUndersizePkts; 299 u_int32_t stat_EtherStatsOverrsizePkts; 300 u_int32_t stat_EtherStatsPktsRx64Octets; 301 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; 302 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; 303 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; 304 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 305 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 306 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 307 u_int32_t stat_EtherStatsPktsTx64Octets; 308 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; 309 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; 310 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; 311 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 312 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 313 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 314 u_int32_t stat_XonPauseFramesReceived; 315 u_int32_t stat_XoffPauseFramesReceived; 316 u_int32_t stat_OutXonSent; 317 u_int32_t stat_OutXoffSent; 318 u_int32_t stat_FlowControlDone; 319 u_int32_t stat_MacControlFramesReceived; 320 u_int32_t stat_XoffStateEntered; 321 u_int32_t stat_IfInFramesL2FilterDiscards; 322 u_int32_t stat_IfInRuleCheckerDiscards; 323 u_int32_t stat_IfInFTQDiscards; 324 u_int32_t stat_IfInMBUFDiscards; 325 u_int32_t stat_IfInRuleCheckerP4Hit; 326 u_int32_t stat_CatchupInRuleCheckerDiscards; 327 u_int32_t stat_CatchupInFTQDiscards; 328 u_int32_t stat_CatchupInMBUFDiscards; 329 u_int32_t stat_CatchupInRuleCheckerP4Hit; 330 331 /* Mbuf allocation failure counter. */ 332 u_int32_t mbuf_alloc_failed; 333 334 /* TX DMA mapping failure counter. */ 335 u_int32_t tx_dma_map_failures; 336 337 #ifdef BNX_DEBUG 338 /* Track the number of enqueued mbufs. */ 339 int tx_mbuf_alloc; 340 int rx_mbuf_alloc; 341 342 /* Track the distribution buffer segments. */ 343 u_int32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1]; 344 345 /* Track how many and what type of interrupts are generated. */ 346 u_int32_t interrupts_generated; 347 u_int32_t interrupts_handled; 348 u_int32_t rx_interrupts; 349 u_int32_t tx_interrupts; 350 351 u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ 352 u_int32_t rx_empty_count; /* Number of times the RX chain was empty. */ 353 u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ 354 u_int32_t tx_full_count; /* Number of times the TX chain was full. */ 355 u_int32_t mbuf_sim_alloc_failed;/* Mbuf simulated allocation failure counter. */ 356 u_int32_t l2fhdr_status_errors; 357 u_int32_t unexpected_attentions; 358 u_int32_t lost_status_block_updates; 359 #endif 360 }; 361 362 struct bnx_firmware_header { 363 int bnx_COM_FwReleaseMajor; 364 int bnx_COM_FwReleaseMinor; 365 int bnx_COM_FwReleaseFix; 366 u_int32_t bnx_COM_FwStartAddr; 367 u_int32_t bnx_COM_FwTextAddr; 368 int bnx_COM_FwTextLen; 369 u_int32_t bnx_COM_FwDataAddr; 370 int bnx_COM_FwDataLen; 371 u_int32_t bnx_COM_FwRodataAddr; 372 int bnx_COM_FwRodataLen; 373 u_int32_t bnx_COM_FwBssAddr; 374 int bnx_COM_FwBssLen; 375 u_int32_t bnx_COM_FwSbssAddr; 376 int bnx_COM_FwSbssLen; 377 378 int bnx_RXP_FwReleaseMajor; 379 int bnx_RXP_FwReleaseMinor; 380 int bnx_RXP_FwReleaseFix; 381 u_int32_t bnx_RXP_FwStartAddr; 382 u_int32_t bnx_RXP_FwTextAddr; 383 int bnx_RXP_FwTextLen; 384 u_int32_t bnx_RXP_FwDataAddr; 385 int bnx_RXP_FwDataLen; 386 u_int32_t bnx_RXP_FwRodataAddr; 387 int bnx_RXP_FwRodataLen; 388 u_int32_t bnx_RXP_FwBssAddr; 389 int bnx_RXP_FwBssLen; 390 u_int32_t bnx_RXP_FwSbssAddr; 391 int bnx_RXP_FwSbssLen; 392 393 int bnx_TPAT_FwReleaseMajor; 394 int bnx_TPAT_FwReleaseMinor; 395 int bnx_TPAT_FwReleaseFix; 396 u_int32_t bnx_TPAT_FwStartAddr; 397 u_int32_t bnx_TPAT_FwTextAddr; 398 int bnx_TPAT_FwTextLen; 399 u_int32_t bnx_TPAT_FwDataAddr; 400 int bnx_TPAT_FwDataLen; 401 u_int32_t bnx_TPAT_FwRodataAddr; 402 int bnx_TPAT_FwRodataLen; 403 u_int32_t bnx_TPAT_FwBssAddr; 404 int bnx_TPAT_FwBssLen; 405 u_int32_t bnx_TPAT_FwSbssAddr; 406 int bnx_TPAT_FwSbssLen; 407 408 int bnx_TXP_FwReleaseMajor; 409 int bnx_TXP_FwReleaseMinor; 410 int bnx_TXP_FwReleaseFix; 411 u_int32_t bnx_TXP_FwStartAddr; 412 u_int32_t bnx_TXP_FwTextAddr; 413 int bnx_TXP_FwTextLen; 414 u_int32_t bnx_TXP_FwDataAddr; 415 int bnx_TXP_FwDataLen; 416 u_int32_t bnx_TXP_FwRodataAddr; 417 int bnx_TXP_FwRodataLen; 418 u_int32_t bnx_TXP_FwBssAddr; 419 int bnx_TXP_FwBssLen; 420 u_int32_t bnx_TXP_FwSbssAddr; 421 int bnx_TXP_FwSbssLen; 422 423 /* Followed by blocks of data, each sized according to 424 * the (rather obvious) block length stated above. 425 * 426 * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata, 427 * bnx_COM_FwBss, bnx_COM_FwSbss, 428 * 429 * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata, 430 * bnx_RXP_FwBss, bnx_RXP_FwSbss, 431 * 432 * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata, 433 * bnx_TPAT_FwBss, bnx_TPAT_FwSbss, 434 * 435 * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata, 436 * bnx_TXP_FwBss, bnx_TXP_FwSbss, 437 */ 438 }; 439 440 #endif /* _DEV_PCI_IF_BNXVAR_H_ */ 441