1 /* $NetBSD: if_bgevar.h,v 1.17 2013/10/31 04:26:40 msaitoh Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $ 35 */ 36 37 /* 38 * BCM570x memory map. The internal memory layout varies somewhat 39 * depending on whether or not we have external SSRAM attached. 40 * The BCM5700 can have up to 16MB of external memory. The BCM5701 41 * is apparently not designed to use external SSRAM. The mappings 42 * up to the first 4 send rings are the same for both internal and 43 * external memory configurations. Note that mini RX ring space is 44 * only available with external SSRAM configurations, which means 45 * the mini RX ring is not supported on the BCM5701. 46 * 47 * The NIC's memory can be accessed by the host in one of 3 ways: 48 * 49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 50 * registers in PCI config space can be used to read any 32-bit 51 * address within the NIC's memory. 52 * 53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 54 * space can be used in conjunction with the memory window in the 55 * device register space at offset 0x8000 to read any 32K chunk 56 * of NIC memory. 57 * 58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 59 * set, the device I/O mapping consumes 32MB of host address space, 60 * allowing all of the registers and internal NIC memory to be 61 * accessed directly. NIC memory addresses are offset by 0x01000000. 62 * Flat mode consumes so much host address space that it is not 63 * recommended. 64 */ 65 66 #ifndef _DEV_PCI_IF_BGEVAR_H_ 67 #define _DEV_PCI_IF_BGEVAR_H_ 68 69 #include <sys/bus.h> 70 #include <net/if_ether.h> 71 #include <dev/pci/pcivar.h> 72 73 #define BGE_HOSTADDR(x, y) \ 74 do { \ 75 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 76 if (sizeof (bus_addr_t) == 8) \ 77 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 78 else \ 79 (x).bge_addr_hi = 0; \ 80 } while(0) 81 82 #define RCB_WRITE_4(sc, rcb, offset, val) \ 83 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 84 rcb + offsetof(struct bge_rcb, offset), val) 85 86 /* 87 * Other utility macros. 88 */ 89 #define BGE_INC(x, y) (x) = (x + 1) % y 90 91 /* 92 * Register access macros. The Tigon always uses memory mapped register 93 * accesses and all registers must be accessed with 32 bit operations. 94 */ 95 96 #define CSR_WRITE_4(sc, reg, val) \ 97 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 98 99 #define CSR_READ_4(sc, reg) \ 100 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 101 102 #define CSR_WRITE_4_FLUSH(sc, reg, val) \ 103 do { \ 104 CSR_WRITE_4(sc, reg, val); \ 105 CSR_READ_4(sc, reg); \ 106 } while(0) 107 108 #define BGE_SETBIT(sc, reg, x) \ 109 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 110 #define BGE_SETBIT_FLUSH(sc, reg, x) \ 111 do { \ 112 BGE_SETBIT(sc, reg, x); \ 113 CSR_READ_4(sc, reg); \ 114 } while(0) 115 #define BGE_CLRBIT(sc, reg, x) \ 116 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 117 #define BGE_CLRBIT_FLUSH(sc, reg, x) \ 118 do { \ 119 BGE_CLRBIT(sc, reg, x); \ 120 CSR_READ_4(sc, reg); \ 121 } while(0) 122 123 /* BAR2 APE register access macros. */ 124 #define APE_WRITE_4(sc, reg, val) \ 125 bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val) 126 127 #define APE_READ_4(sc, reg) \ 128 bus_space_read_4(sc->bge_apetag, sc->bge_apehandle, reg) 129 130 #define APE_WRITE_4_FLUSH(sc, reg, val) \ 131 do { \ 132 APE_WRITE_4(sc, reg, val); \ 133 APE_READ_4(sc, reg); \ 134 } while(0) 135 136 #define APE_SETBIT(sc, reg, x) \ 137 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) 138 #define APE_CLRBIT(sc, reg, x) \ 139 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 140 141 #define PCI_SETBIT(pc, tag, reg, x) \ 142 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 143 #define PCI_CLRBIT(pc, tag, reg, x) \ 144 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 145 146 /* 147 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 148 * values are tuneable. They control the actual amount of buffers 149 * allocated for the standard, mini and jumbo receive rings. 150 */ 151 152 #define BGE_SSLOTS 256 153 #define BGE_MSLOTS 256 154 #define BGE_JSLOTS 384 155 156 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 157 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 158 (BGE_JRAWLEN % sizeof(uint64_t)))) 159 #define BGE_JPAGESZ PAGE_SIZE 160 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 161 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 162 163 /* 164 * Ring structures. Most of these reside in host memory and we tell 165 * the NIC where they are via the ring control blocks. The exceptions 166 * are the tx and command rings, which live in NIC memory and which 167 * we access via the shared memory window. 168 */ 169 struct bge_ring_data { 170 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 171 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 172 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 173 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 174 struct bge_status_block bge_status_block; 175 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 176 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 177 struct bge_gib bge_info; 178 }; 179 180 #define BGE_RING_DMA_ADDR(sc, offset) \ 181 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 182 offsetof(struct bge_ring_data, offset)) 183 184 /* 185 * Number of DMA segments in a TxCB. Note that this is carefully 186 * chosen to make the total struct size an even power of two. It's 187 * critical that no TxCB be split across a page boundary since 188 * no attempt is made to allocate physically contiguous memory. 189 * 190 */ 191 #if 0 /* pre-TSO values */ 192 #define BGE_TXDMA_MAX ETHER_MAX_LEN_JUMBO 193 #ifdef _LP64 194 #define BGE_NTXSEG 30 195 #else 196 #define BGE_NTXSEG 31 197 #endif 198 #else /* TSO values */ 199 #define BGE_TXDMA_MAX (round_page(IP_MAXPACKET)) /* for TSO */ 200 #ifdef _LP64 201 #define BGE_NTXSEG 120 /* XXX just a guess */ 202 #else 203 #define BGE_NTXSEG 124 /* XXX just a guess */ 204 #endif 205 #endif /* TSO values */ 206 207 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 208 209 /* 210 * Mbuf pointers. We need these to keep track of the virtual addresses 211 * of our mbuf chains since we can only convert from physical to virtual, 212 * not the other way around. 213 */ 214 struct bge_chain_data { 215 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 216 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 217 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 218 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 219 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 220 bus_dmamap_t bge_rx_jumbo_map; 221 /* Stick the jumbo mem management stuff here too. */ 222 void * bge_jslots[BGE_JSLOTS]; 223 void * bge_jumbo_buf; 224 }; 225 226 #define BGE_JUMBO_DMA_ADDR(sc, m) \ 227 ((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \ 228 (mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf)) 229 230 struct bge_type { 231 uint16_t bge_vid; 232 uint16_t bge_did; 233 char *bge_name; 234 }; 235 236 #define BGE_TIMEOUT 100000 237 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 238 239 struct bge_jpool_entry { 240 int slot; 241 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 242 }; 243 244 struct bge_bcom_hack { 245 int reg; 246 int val; 247 }; 248 249 struct txdmamap_pool_entry { 250 bus_dmamap_t dmamap; 251 SLIST_ENTRY(txdmamap_pool_entry) link; 252 }; 253 254 #define ASF_ENABLE 1 255 #define ASF_NEW_HANDSHAKE 2 256 #define ASF_STACKUP 4 257 258 struct bge_softc { 259 device_t bge_dev; 260 struct ethercom ethercom; /* interface info */ 261 bus_space_handle_t bge_bhandle; 262 bus_space_tag_t bge_btag; 263 bus_size_t bge_bsize; 264 bus_space_handle_t bge_apehandle; 265 bus_space_tag_t bge_apetag; 266 bus_size_t bge_apesize; 267 void *bge_intrhand; 268 pci_chipset_tag_t sc_pc; 269 pcitag_t sc_pcitag; 270 271 struct pci_attach_args bge_pa; 272 struct mii_data bge_mii; 273 struct ifmedia bge_ifmedia; /* media info */ 274 uint32_t bge_return_ring_cnt; 275 uint32_t bge_tx_prodidx; 276 bus_dma_tag_t bge_dmatag; 277 uint32_t bge_pcixcap; 278 uint32_t bge_pciecap; 279 uint16_t bge_mps; 280 int bge_expmrq; 281 u_int32_t bge_mfw_flags; /* Management F/W flags */ 282 #define BGE_MFW_ON_RXCPU 0x00000001 283 #define BGE_MFW_ON_APE 0x00000002 284 #define BGE_MFW_TYPE_NCSI 0x00000004 285 #define BGE_MFW_TYPE_DASH 0x00000008 286 int bge_phy_ape_lock; 287 int bge_phy_addr; 288 uint32_t bge_chipid; 289 uint8_t bge_asf_mode; 290 uint8_t bge_asf_count; 291 struct bge_ring_data *bge_rdata; /* rings */ 292 struct bge_chain_data bge_cdata; /* mbufs */ 293 bus_dmamap_t bge_ring_map; 294 bus_dma_segment_t bge_ring_seg; 295 int bge_ring_rseg; 296 uint16_t bge_tx_saved_considx; 297 uint16_t bge_rx_saved_considx; 298 uint16_t bge_ev_saved_considx; 299 uint16_t bge_std; /* current std ring head */ 300 uint16_t bge_jumbo; /* current jumo ring head */ 301 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 302 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 303 uint32_t bge_stat_ticks; 304 uint32_t bge_rx_coal_ticks; 305 uint32_t bge_tx_coal_ticks; 306 uint32_t bge_rx_max_coal_bds; 307 uint32_t bge_tx_max_coal_bds; 308 uint32_t bge_tx_buf_ratio; 309 uint32_t bge_sts; 310 #define BGE_STS_LINK 0x00000001 /* MAC link status */ 311 #define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 312 #define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 313 #define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 314 #define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 315 #define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 316 int bge_if_flags; 317 uint32_t bge_flags; 318 uint32_t bge_phy_flags; 319 int bge_flowflags; 320 #ifdef BGE_EVENT_COUNTERS 321 /* 322 * Event counters. 323 */ 324 struct evcnt bge_ev_intr; /* interrupts */ 325 struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */ 326 struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */ 327 struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */ 328 struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */ 329 struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */ 330 struct evcnt bge_ev_xoffentered;/* XOFF state entered */ 331 #endif /* BGE_EVENT_COUNTERS */ 332 int bge_txcnt; 333 struct callout bge_timeout; 334 int bge_pending_rxintr_change; 335 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 336 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 337 338 struct sysctllog *bge_log; 339 340 krndsource_t rnd_source; /* random source */ 341 }; 342 343 #endif /* _DEV_PCI_IF_BGEVAR_H_ */ 344