1 /* $NetBSD: if_bge.c,v 1.199 2011/11/02 16:26:30 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl@wasabisystems.com> 44 * Jason Thorpe <thorpej@wasabisystems.com> 45 * Jonathan Stone <jonathan@dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul@windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.199 2011/11/02 16:26:30 yamt Exp $"); 83 84 #include "vlan.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NRND > 0 104 #include <sys/rnd.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 /* Headers for TCP Segmentation Offload (TSO) */ 115 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 116 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 117 #include <netinet/ip.h> /* for struct ip */ 118 #include <netinet/tcp.h> /* for struct tcphdr */ 119 120 121 #include <net/bpf.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #include <dev/mii/miidevs.h> 130 #include <dev/mii/brgphyreg.h> 131 132 #include <dev/pci/if_bgereg.h> 133 #include <dev/pci/if_bgevar.h> 134 135 #include <prop/proplib.h> 136 137 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 138 139 140 /* 141 * Tunable thresholds for rx-side bge interrupt mitigation. 142 */ 143 144 /* 145 * The pairs of values below were obtained from empirical measurement 146 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 147 * interrupt for every N packets received, where N is, approximately, 148 * the second value (rx_max_bds) in each pair. The values are chosen 149 * such that moving from one pair to the succeeding pair was observed 150 * to roughly halve interrupt rate under sustained input packet load. 151 * The values were empirically chosen to avoid overflowing internal 152 * limits on the bcm5700: increasing rx_ticks much beyond 600 153 * results in internal wrapping and higher interrupt rates. 154 * The limit of 46 frames was chosen to match NFS workloads. 155 * 156 * These values also work well on bcm5701, bcm5704C, and (less 157 * tested) bcm5703. On other chipsets, (including the Altima chip 158 * family), the larger values may overflow internal chip limits, 159 * leading to increasing interrupt rates rather than lower interrupt 160 * rates. 161 * 162 * Applications using heavy interrupt mitigation (interrupting every 163 * 32 or 46 frames) in both directions may need to increase the TCP 164 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 165 * full link bandwidth, due to ACKs and window updates lingering 166 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 167 */ 168 static const struct bge_load_rx_thresh { 169 int rx_ticks; 170 int rx_max_bds; } 171 bge_rx_threshes[] = { 172 { 16, 1 }, /* rx_max_bds = 1 disables interrupt mitigation */ 173 { 32, 2 }, 174 { 50, 4 }, 175 { 100, 8 }, 176 { 192, 16 }, 177 { 416, 32 }, 178 { 598, 46 } 179 }; 180 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 181 182 /* XXX patchable; should be sysctl'able */ 183 static int bge_auto_thresh = 1; 184 static int bge_rx_thresh_lvl; 185 186 static int bge_rxthresh_nodenum; 187 188 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 189 190 static int bge_probe(device_t, cfdata_t, void *); 191 static void bge_attach(device_t, device_t, void *); 192 static void bge_release_resources(struct bge_softc *); 193 194 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 198 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 199 200 static void bge_txeof(struct bge_softc *); 201 static void bge_rxeof(struct bge_softc *); 202 203 static void bge_asf_driver_up (struct bge_softc *); 204 static void bge_tick(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static void bge_stats_update_regs(struct bge_softc *); 207 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 208 209 static int bge_intr(void *); 210 static void bge_start(struct ifnet *); 211 static int bge_ifflags_cb(struct ethercom *); 212 static int bge_ioctl(struct ifnet *, u_long, void *); 213 static int bge_init(struct ifnet *); 214 static void bge_stop(struct ifnet *, int); 215 static void bge_watchdog(struct ifnet *); 216 static int bge_ifmedia_upd(struct ifnet *); 217 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 218 219 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 220 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 221 222 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 223 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 224 static void bge_setmulti(struct bge_softc *); 225 226 static void bge_handle_events(struct bge_softc *); 227 static int bge_alloc_jumbo_mem(struct bge_softc *); 228 #if 0 /* XXX */ 229 static void bge_free_jumbo_mem(struct bge_softc *); 230 #endif 231 static void *bge_jalloc(struct bge_softc *); 232 static void bge_jfree(struct mbuf *, void *, size_t, void *); 233 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 234 bus_dmamap_t); 235 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 236 static int bge_init_rx_ring_std(struct bge_softc *); 237 static void bge_free_rx_ring_std(struct bge_softc *); 238 static int bge_init_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_rx_ring_jumbo(struct bge_softc *); 240 static void bge_free_tx_ring(struct bge_softc *); 241 static int bge_init_tx_ring(struct bge_softc *); 242 243 static int bge_chipinit(struct bge_softc *); 244 static int bge_blockinit(struct bge_softc *); 245 static int bge_setpowerstate(struct bge_softc *, int); 246 static uint32_t bge_readmem_ind(struct bge_softc *, int); 247 static void bge_writemem_ind(struct bge_softc *, int, int); 248 static void bge_writembx(struct bge_softc *, int, int); 249 static void bge_writemem_direct(struct bge_softc *, int, int); 250 static void bge_writereg_ind(struct bge_softc *, int, int); 251 static void bge_set_max_readrq(struct bge_softc *); 252 253 static int bge_miibus_readreg(device_t, int, int); 254 static void bge_miibus_writereg(device_t, int, int, int); 255 static void bge_miibus_statchg(device_t); 256 257 #define BGE_RESET_START 1 258 #define BGE_RESET_STOP 2 259 static void bge_sig_post_reset(struct bge_softc *, int); 260 static void bge_sig_legacy(struct bge_softc *, int); 261 static void bge_sig_pre_reset(struct bge_softc *, int); 262 static void bge_stop_fw(struct bge_softc *); 263 static int bge_reset(struct bge_softc *); 264 static void bge_link_upd(struct bge_softc *); 265 static void sysctl_bge_init(struct bge_softc *); 266 static int sysctl_bge_verify(SYSCTLFN_PROTO); 267 268 #ifdef BGE_DEBUG 269 #define DPRINTF(x) if (bgedebug) printf x 270 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 271 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 272 int bgedebug = 0; 273 int bge_tso_debug = 0; 274 void bge_debug_info(struct bge_softc *); 275 #else 276 #define DPRINTF(x) 277 #define DPRINTFN(n,x) 278 #define BGE_TSO_PRINTF(x) 279 #endif 280 281 #ifdef BGE_EVENT_COUNTERS 282 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 283 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 284 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 285 #else 286 #define BGE_EVCNT_INCR(ev) /* nothing */ 287 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 288 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 289 #endif 290 291 static const struct bge_product { 292 pci_vendor_id_t bp_vendor; 293 pci_product_id_t bp_product; 294 const char *bp_name; 295 } bge_products[] = { 296 /* 297 * The BCM5700 documentation seems to indicate that the hardware 298 * still has the Alteon vendor ID burned into it, though it 299 * should always be overridden by the value in the EEPROM. We'll 300 * check for it anyway. 301 */ 302 { PCI_VENDOR_ALTEON, 303 PCI_PRODUCT_ALTEON_BCM5700, 304 "Broadcom BCM5700 Gigabit Ethernet", 305 }, 306 { PCI_VENDOR_ALTEON, 307 PCI_PRODUCT_ALTEON_BCM5701, 308 "Broadcom BCM5701 Gigabit Ethernet", 309 }, 310 { PCI_VENDOR_ALTIMA, 311 PCI_PRODUCT_ALTIMA_AC1000, 312 "Altima AC1000 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_ALTIMA, 315 PCI_PRODUCT_ALTIMA_AC1001, 316 "Altima AC1001 Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_ALTIMA, 319 PCI_PRODUCT_ALTIMA_AC9100, 320 "Altima AC9100 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_BROADCOM, 323 PCI_PRODUCT_BROADCOM_BCM5700, 324 "Broadcom BCM5700 Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_BROADCOM, 327 PCI_PRODUCT_BROADCOM_BCM5701, 328 "Broadcom BCM5701 Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_BROADCOM, 331 PCI_PRODUCT_BROADCOM_BCM5702, 332 "Broadcom BCM5702 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_BROADCOM, 335 PCI_PRODUCT_BROADCOM_BCM5702X, 336 "Broadcom BCM5702X Gigabit Ethernet" }, 337 { PCI_VENDOR_BROADCOM, 338 PCI_PRODUCT_BROADCOM_BCM5703, 339 "Broadcom BCM5703 Gigabit Ethernet", 340 }, 341 { PCI_VENDOR_BROADCOM, 342 PCI_PRODUCT_BROADCOM_BCM5703X, 343 "Broadcom BCM5703X Gigabit Ethernet", 344 }, 345 { PCI_VENDOR_BROADCOM, 346 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 347 "Broadcom BCM5703 Gigabit Ethernet", 348 }, 349 { PCI_VENDOR_BROADCOM, 350 PCI_PRODUCT_BROADCOM_BCM5704C, 351 "Broadcom BCM5704C Dual Gigabit Ethernet", 352 }, 353 { PCI_VENDOR_BROADCOM, 354 PCI_PRODUCT_BROADCOM_BCM5704S, 355 "Broadcom BCM5704S Dual Gigabit Ethernet", 356 }, 357 { PCI_VENDOR_BROADCOM, 358 PCI_PRODUCT_BROADCOM_BCM5705, 359 "Broadcom BCM5705 Gigabit Ethernet", 360 }, 361 { PCI_VENDOR_BROADCOM, 362 PCI_PRODUCT_BROADCOM_BCM5705F, 363 "Broadcom BCM5705F Gigabit Ethernet", 364 }, 365 { PCI_VENDOR_BROADCOM, 366 PCI_PRODUCT_BROADCOM_BCM5705K, 367 "Broadcom BCM5705K Gigabit Ethernet", 368 }, 369 { PCI_VENDOR_BROADCOM, 370 PCI_PRODUCT_BROADCOM_BCM5705M, 371 "Broadcom BCM5705M Gigabit Ethernet", 372 }, 373 { PCI_VENDOR_BROADCOM, 374 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 375 "Broadcom BCM5705M Gigabit Ethernet", 376 }, 377 { PCI_VENDOR_BROADCOM, 378 PCI_PRODUCT_BROADCOM_BCM5714, 379 "Broadcom BCM5714 Gigabit Ethernet", 380 }, 381 { PCI_VENDOR_BROADCOM, 382 PCI_PRODUCT_BROADCOM_BCM5714S, 383 "Broadcom BCM5714S Gigabit Ethernet", 384 }, 385 { PCI_VENDOR_BROADCOM, 386 PCI_PRODUCT_BROADCOM_BCM5715, 387 "Broadcom BCM5715 Gigabit Ethernet", 388 }, 389 { PCI_VENDOR_BROADCOM, 390 PCI_PRODUCT_BROADCOM_BCM5715S, 391 "Broadcom BCM5715S Gigabit Ethernet", 392 }, 393 { PCI_VENDOR_BROADCOM, 394 PCI_PRODUCT_BROADCOM_BCM5717, 395 "Broadcom BCM5717 Gigabit Ethernet", 396 }, 397 { PCI_VENDOR_BROADCOM, 398 PCI_PRODUCT_BROADCOM_BCM5718, 399 "Broadcom BCM5718 Gigabit Ethernet", 400 }, 401 { PCI_VENDOR_BROADCOM, 402 PCI_PRODUCT_BROADCOM_BCM5720, 403 "Broadcom BCM5720 Gigabit Ethernet", 404 }, 405 { PCI_VENDOR_BROADCOM, 406 PCI_PRODUCT_BROADCOM_BCM5721, 407 "Broadcom BCM5721 Gigabit Ethernet", 408 }, 409 { PCI_VENDOR_BROADCOM, 410 PCI_PRODUCT_BROADCOM_BCM5722, 411 "Broadcom BCM5722 Gigabit Ethernet", 412 }, 413 { PCI_VENDOR_BROADCOM, 414 PCI_PRODUCT_BROADCOM_BCM5723, 415 "Broadcom BCM5723 Gigabit Ethernet", 416 }, 417 { PCI_VENDOR_BROADCOM, 418 PCI_PRODUCT_BROADCOM_BCM5724, 419 "Broadcom BCM5724 Gigabit Ethernet", 420 }, 421 { PCI_VENDOR_BROADCOM, 422 PCI_PRODUCT_BROADCOM_BCM5750, 423 "Broadcom BCM5750 Gigabit Ethernet", 424 }, 425 { PCI_VENDOR_BROADCOM, 426 PCI_PRODUCT_BROADCOM_BCM5750M, 427 "Broadcom BCM5750M Gigabit Ethernet", 428 }, 429 { PCI_VENDOR_BROADCOM, 430 PCI_PRODUCT_BROADCOM_BCM5751, 431 "Broadcom BCM5751 Gigabit Ethernet", 432 }, 433 { PCI_VENDOR_BROADCOM, 434 PCI_PRODUCT_BROADCOM_BCM5751F, 435 "Broadcom BCM5751F Gigabit Ethernet", 436 }, 437 { PCI_VENDOR_BROADCOM, 438 PCI_PRODUCT_BROADCOM_BCM5751M, 439 "Broadcom BCM5751M Gigabit Ethernet", 440 }, 441 { PCI_VENDOR_BROADCOM, 442 PCI_PRODUCT_BROADCOM_BCM5752, 443 "Broadcom BCM5752 Gigabit Ethernet", 444 }, 445 { PCI_VENDOR_BROADCOM, 446 PCI_PRODUCT_BROADCOM_BCM5752M, 447 "Broadcom BCM5752M Gigabit Ethernet", 448 }, 449 { PCI_VENDOR_BROADCOM, 450 PCI_PRODUCT_BROADCOM_BCM5753, 451 "Broadcom BCM5753 Gigabit Ethernet", 452 }, 453 { PCI_VENDOR_BROADCOM, 454 PCI_PRODUCT_BROADCOM_BCM5753F, 455 "Broadcom BCM5753F Gigabit Ethernet", 456 }, 457 { PCI_VENDOR_BROADCOM, 458 PCI_PRODUCT_BROADCOM_BCM5753M, 459 "Broadcom BCM5753M Gigabit Ethernet", 460 }, 461 { PCI_VENDOR_BROADCOM, 462 PCI_PRODUCT_BROADCOM_BCM5754, 463 "Broadcom BCM5754 Gigabit Ethernet", 464 }, 465 { PCI_VENDOR_BROADCOM, 466 PCI_PRODUCT_BROADCOM_BCM5754M, 467 "Broadcom BCM5754M Gigabit Ethernet", 468 }, 469 { PCI_VENDOR_BROADCOM, 470 PCI_PRODUCT_BROADCOM_BCM5755, 471 "Broadcom BCM5755 Gigabit Ethernet", 472 }, 473 { PCI_VENDOR_BROADCOM, 474 PCI_PRODUCT_BROADCOM_BCM5755M, 475 "Broadcom BCM5755M Gigabit Ethernet", 476 }, 477 { PCI_VENDOR_BROADCOM, 478 PCI_PRODUCT_BROADCOM_BCM5756, 479 "Broadcom BCM5756 Gigabit Ethernet", 480 }, 481 { PCI_VENDOR_BROADCOM, 482 PCI_PRODUCT_BROADCOM_BCM5761, 483 "Broadcom BCM5761 Gigabit Ethernet", 484 }, 485 { PCI_VENDOR_BROADCOM, 486 PCI_PRODUCT_BROADCOM_BCM5761E, 487 "Broadcom BCM5761E Gigabit Ethernet", 488 }, 489 { PCI_VENDOR_BROADCOM, 490 PCI_PRODUCT_BROADCOM_BCM5761S, 491 "Broadcom BCM5761S Gigabit Ethernet", 492 }, 493 { PCI_VENDOR_BROADCOM, 494 PCI_PRODUCT_BROADCOM_BCM5761SE, 495 "Broadcom BCM5761SE Gigabit Ethernet", 496 }, 497 { PCI_VENDOR_BROADCOM, 498 PCI_PRODUCT_BROADCOM_BCM5764, 499 "Broadcom BCM5764 Gigabit Ethernet", 500 }, 501 { PCI_VENDOR_BROADCOM, 502 PCI_PRODUCT_BROADCOM_BCM5780, 503 "Broadcom BCM5780 Gigabit Ethernet", 504 }, 505 { PCI_VENDOR_BROADCOM, 506 PCI_PRODUCT_BROADCOM_BCM5780S, 507 "Broadcom BCM5780S Gigabit Ethernet", 508 }, 509 { PCI_VENDOR_BROADCOM, 510 PCI_PRODUCT_BROADCOM_BCM5781, 511 "Broadcom BCM5781 Gigabit Ethernet", 512 }, 513 { PCI_VENDOR_BROADCOM, 514 PCI_PRODUCT_BROADCOM_BCM5782, 515 "Broadcom BCM5782 Gigabit Ethernet", 516 }, 517 { PCI_VENDOR_BROADCOM, 518 PCI_PRODUCT_BROADCOM_BCM5784M, 519 "BCM5784M NetLink 1000baseT Ethernet", 520 }, 521 { PCI_VENDOR_BROADCOM, 522 PCI_PRODUCT_BROADCOM_BCM5786, 523 "Broadcom BCM5786 Gigabit Ethernet", 524 }, 525 { PCI_VENDOR_BROADCOM, 526 PCI_PRODUCT_BROADCOM_BCM5787, 527 "Broadcom BCM5787 Gigabit Ethernet", 528 }, 529 { PCI_VENDOR_BROADCOM, 530 PCI_PRODUCT_BROADCOM_BCM5787M, 531 "Broadcom BCM5787M Gigabit Ethernet", 532 }, 533 { PCI_VENDOR_BROADCOM, 534 PCI_PRODUCT_BROADCOM_BCM5788, 535 "Broadcom BCM5788 Gigabit Ethernet", 536 }, 537 { PCI_VENDOR_BROADCOM, 538 PCI_PRODUCT_BROADCOM_BCM5789, 539 "Broadcom BCM5789 Gigabit Ethernet", 540 }, 541 { PCI_VENDOR_BROADCOM, 542 PCI_PRODUCT_BROADCOM_BCM5901, 543 "Broadcom BCM5901 Fast Ethernet", 544 }, 545 { PCI_VENDOR_BROADCOM, 546 PCI_PRODUCT_BROADCOM_BCM5901A2, 547 "Broadcom BCM5901A2 Fast Ethernet", 548 }, 549 { PCI_VENDOR_BROADCOM, 550 PCI_PRODUCT_BROADCOM_BCM5903M, 551 "Broadcom BCM5903M Fast Ethernet", 552 }, 553 { PCI_VENDOR_BROADCOM, 554 PCI_PRODUCT_BROADCOM_BCM5906, 555 "Broadcom BCM5906 Fast Ethernet", 556 }, 557 { PCI_VENDOR_BROADCOM, 558 PCI_PRODUCT_BROADCOM_BCM5906M, 559 "Broadcom BCM5906M Fast Ethernet", 560 }, 561 { PCI_VENDOR_BROADCOM, 562 PCI_PRODUCT_BROADCOM_BCM57760, 563 "Broadcom BCM57760 Fast Ethernet", 564 }, 565 { PCI_VENDOR_BROADCOM, 566 PCI_PRODUCT_BROADCOM_BCM57761, 567 "Broadcom BCM57761 Fast Ethernet", 568 }, 569 { PCI_VENDOR_BROADCOM, 570 PCI_PRODUCT_BROADCOM_BCM57765, 571 "Broadcom BCM57765 Fast Ethernet", 572 }, 573 { PCI_VENDOR_BROADCOM, 574 PCI_PRODUCT_BROADCOM_BCM57780, 575 "Broadcom BCM57780 Fast Ethernet", 576 }, 577 { PCI_VENDOR_BROADCOM, 578 PCI_PRODUCT_BROADCOM_BCM57781, 579 "Broadcom BCM57781 Fast Ethernet", 580 }, 581 { PCI_VENDOR_BROADCOM, 582 PCI_PRODUCT_BROADCOM_BCM57785, 583 "Broadcom BCM57785 Fast Ethernet", 584 }, 585 { PCI_VENDOR_BROADCOM, 586 PCI_PRODUCT_BROADCOM_BCM57788, 587 "Broadcom BCM57788 Fast Ethernet", 588 }, 589 { PCI_VENDOR_BROADCOM, 590 PCI_PRODUCT_BROADCOM_BCM57790, 591 "Broadcom BCM57790 Fast Ethernet", 592 }, 593 { PCI_VENDOR_BROADCOM, 594 PCI_PRODUCT_BROADCOM_BCM57791, 595 "Broadcom BCM57791 Fast Ethernet", 596 }, 597 { PCI_VENDOR_BROADCOM, 598 PCI_PRODUCT_BROADCOM_BCM57795, 599 "Broadcom BCM57795 Fast Ethernet", 600 }, 601 { PCI_VENDOR_SCHNEIDERKOCH, 602 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 603 "SysKonnect SK-9Dx1 Gigabit Ethernet", 604 }, 605 { PCI_VENDOR_3COM, 606 PCI_PRODUCT_3COM_3C996, 607 "3Com 3c996 Gigabit Ethernet", 608 }, 609 { PCI_VENDOR_FUJITSU4, 610 PCI_PRODUCT_FUJITSU4_PW008GE4, 611 "Fujitsu PW008GE4 Gigabit Ethernet", 612 }, 613 { PCI_VENDOR_FUJITSU4, 614 PCI_PRODUCT_FUJITSU4_PW008GE5, 615 "Fujitsu PW008GE5 Gigabit Ethernet", 616 }, 617 { PCI_VENDOR_FUJITSU4, 618 PCI_PRODUCT_FUJITSU4_PP250_450_LAN, 619 "Fujitsu Primepower 250/450 Gigabit Ethernet", 620 }, 621 { 0, 622 0, 623 NULL }, 624 }; 625 626 /* 627 * XXX: how to handle variants based on 5750 and derivatives: 628 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 629 * in general behave like a 5705, except with additional quirks. 630 * This driver's current handling of the 5721 is wrong; 631 * how we map ASIC revision to "quirks" needs more thought. 632 * (defined here until the thought is done). 633 */ 634 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 635 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 636 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 637 #define BGE_IS_5750_OR_BEYOND(sc) ((sc)->bge_flags & BGE_5750_PLUS) 638 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 639 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 640 641 static const struct bge_revision { 642 uint32_t br_chipid; 643 const char *br_name; 644 } bge_revisions[] = { 645 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 646 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 647 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 648 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 649 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 650 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 651 /* This is treated like a BCM5700 Bx */ 652 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 653 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 654 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 655 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 656 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 657 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 658 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 659 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 660 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 661 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 662 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 663 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 664 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 665 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 666 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 667 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 668 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 669 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 670 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 671 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 672 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 673 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 674 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 675 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 676 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 677 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 678 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 679 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 680 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 681 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 682 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 683 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 684 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 685 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 686 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 687 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 688 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 689 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 690 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 691 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 692 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 693 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 694 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 695 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 696 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 697 /* 5754 and 5787 share the same ASIC ID */ 698 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 699 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 700 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 701 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 702 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 703 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 704 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 705 706 { 0, NULL } 707 }; 708 709 /* 710 * Some defaults for major revisions, so that newer steppings 711 * that we don't know about have a shot at working. 712 */ 713 static const struct bge_revision bge_majorrevs[] = { 714 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 715 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 716 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 717 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 718 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 719 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 720 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 721 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 722 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 723 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 724 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 725 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 726 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 727 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 728 /* 5754 and 5787 share the same ASIC ID */ 729 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 730 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 731 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 732 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 733 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 734 735 { 0, NULL } 736 }; 737 738 static int bge_allow_asf = 1; 739 740 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 741 bge_probe, bge_attach, NULL, NULL); 742 743 static uint32_t 744 bge_readmem_ind(struct bge_softc *sc, int off) 745 { 746 pcireg_t val; 747 748 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 749 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 750 return val; 751 } 752 753 static void 754 bge_writemem_ind(struct bge_softc *sc, int off, int val) 755 { 756 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 757 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 758 } 759 760 /* 761 * PCI Express only 762 */ 763 static void 764 bge_set_max_readrq(struct bge_softc *sc) 765 { 766 pcireg_t val; 767 768 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 769 + PCI_PCIE_DCSR); 770 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 771 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 772 aprint_verbose_dev(sc->bge_dev, 773 "adjust device control 0x%04x ", val); 774 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 775 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 776 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 777 + PCI_PCIE_DCSR, val); 778 aprint_verbose("-> 0x%04x\n", val); 779 } 780 } 781 782 #ifdef notdef 783 static uint32_t 784 bge_readreg_ind(struct bge_softc *sc, int off) 785 { 786 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 787 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 788 } 789 #endif 790 791 static void 792 bge_writereg_ind(struct bge_softc *sc, int off, int val) 793 { 794 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 795 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 796 } 797 798 static void 799 bge_writemem_direct(struct bge_softc *sc, int off, int val) 800 { 801 CSR_WRITE_4(sc, off, val); 802 } 803 804 static void 805 bge_writembx(struct bge_softc *sc, int off, int val) 806 { 807 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 808 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 809 810 CSR_WRITE_4(sc, off, val); 811 } 812 813 static uint8_t 814 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 815 { 816 uint32_t access, byte = 0; 817 int i; 818 819 /* Lock. */ 820 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 821 for (i = 0; i < 8000; i++) { 822 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 823 break; 824 DELAY(20); 825 } 826 if (i == 8000) 827 return 1; 828 829 /* Enable access. */ 830 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 831 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 832 833 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 834 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 835 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 836 DELAY(10); 837 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 838 DELAY(10); 839 break; 840 } 841 } 842 843 if (i == BGE_TIMEOUT * 10) { 844 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 845 return 1; 846 } 847 848 /* Get result. */ 849 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 850 851 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 852 853 /* Disable access. */ 854 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 855 856 /* Unlock. */ 857 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 858 CSR_READ_4(sc, BGE_NVRAM_SWARB); 859 860 return 0; 861 } 862 863 /* 864 * Read a sequence of bytes from NVRAM. 865 */ 866 static int 867 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 868 { 869 int err = 0, i; 870 uint8_t byte = 0; 871 872 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 873 return 1; 874 875 for (i = 0; i < cnt; i++) { 876 err = bge_nvram_getbyte(sc, off + i, &byte); 877 if (err) 878 break; 879 *(dest + i) = byte; 880 } 881 882 return (err ? 1 : 0); 883 } 884 885 /* 886 * Read a byte of data stored in the EEPROM at address 'addr.' The 887 * BCM570x supports both the traditional bitbang interface and an 888 * auto access interface for reading the EEPROM. We use the auto 889 * access method. 890 */ 891 static uint8_t 892 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 893 { 894 int i; 895 uint32_t byte = 0; 896 897 /* 898 * Enable use of auto EEPROM access so we can avoid 899 * having to use the bitbang method. 900 */ 901 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 902 903 /* Reset the EEPROM, load the clock period. */ 904 CSR_WRITE_4(sc, BGE_EE_ADDR, 905 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 906 DELAY(20); 907 908 /* Issue the read EEPROM command. */ 909 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 910 911 /* Wait for completion */ 912 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 913 DELAY(10); 914 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 915 break; 916 } 917 918 if (i == BGE_TIMEOUT * 10) { 919 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 920 return 1; 921 } 922 923 /* Get result. */ 924 byte = CSR_READ_4(sc, BGE_EE_DATA); 925 926 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 927 928 return 0; 929 } 930 931 /* 932 * Read a sequence of bytes from the EEPROM. 933 */ 934 static int 935 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 936 { 937 int err = 0, i; 938 uint8_t byte = 0; 939 char *dest = destv; 940 941 for (i = 0; i < cnt; i++) { 942 err = bge_eeprom_getbyte(sc, off + i, &byte); 943 if (err) 944 break; 945 *(dest + i) = byte; 946 } 947 948 return (err ? 1 : 0); 949 } 950 951 static int 952 bge_miibus_readreg(device_t dev, int phy, int reg) 953 { 954 struct bge_softc *sc = device_private(dev); 955 uint32_t val; 956 uint32_t autopoll; 957 int i; 958 959 /* 960 * Broadcom's own driver always assumes the internal 961 * PHY is at GMII address 1. On some chips, the PHY responds 962 * to accesses at all addresses, which could cause us to 963 * bogusly attach the PHY 32 times at probe type. Always 964 * restricting the lookup to address 1 is simpler than 965 * trying to figure out which chips revisions should be 966 * special-cased. 967 */ 968 if (phy != 1) 969 return 0; 970 971 /* Reading with autopolling on may trigger PCI errors */ 972 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 973 if (autopoll & BGE_MIMODE_AUTOPOLL) { 974 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 975 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 976 DELAY(40); 977 } 978 979 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 980 BGE_MIPHY(phy) | BGE_MIREG(reg)); 981 982 for (i = 0; i < BGE_TIMEOUT; i++) { 983 val = CSR_READ_4(sc, BGE_MI_COMM); 984 if (!(val & BGE_MICOMM_BUSY)) 985 break; 986 delay(10); 987 } 988 989 if (i == BGE_TIMEOUT) { 990 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 991 val = 0; 992 goto done; 993 } 994 995 val = CSR_READ_4(sc, BGE_MI_COMM); 996 997 done: 998 if (autopoll & BGE_MIMODE_AUTOPOLL) { 999 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1000 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1001 DELAY(40); 1002 } 1003 1004 if (val & BGE_MICOMM_READFAIL) 1005 return 0; 1006 1007 return (val & 0xFFFF); 1008 } 1009 1010 static void 1011 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1012 { 1013 struct bge_softc *sc = device_private(dev); 1014 uint32_t autopoll; 1015 int i; 1016 1017 if (phy!=1) { 1018 return; 1019 } 1020 1021 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1022 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 1023 return; 1024 } 1025 1026 /* Reading with autopolling on may trigger PCI errors */ 1027 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1028 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1029 delay(40); 1030 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1031 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1032 delay(10); /* 40 usec is supposed to be adequate */ 1033 } 1034 1035 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1036 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1037 1038 for (i = 0; i < BGE_TIMEOUT; i++) { 1039 delay(10); 1040 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1041 delay(5); 1042 CSR_READ_4(sc, BGE_MI_COMM); 1043 break; 1044 } 1045 } 1046 1047 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1048 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1049 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1050 delay(40); 1051 } 1052 1053 if (i == BGE_TIMEOUT) 1054 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1055 } 1056 1057 static void 1058 bge_miibus_statchg(device_t dev) 1059 { 1060 struct bge_softc *sc = device_private(dev); 1061 struct mii_data *mii = &sc->bge_mii; 1062 1063 /* 1064 * Get flow control negotiation result. 1065 */ 1066 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1067 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1068 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1069 mii->mii_media_active &= ~IFM_ETH_FMASK; 1070 } 1071 1072 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1073 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1074 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1075 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1076 else 1077 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1078 1079 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1080 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1081 else 1082 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1083 1084 /* 1085 * 802.3x flow control 1086 */ 1087 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1088 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1089 else 1090 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1091 1092 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1093 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1094 else 1095 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1096 } 1097 1098 /* 1099 * Update rx threshold levels to values in a particular slot 1100 * of the interrupt-mitigation table bge_rx_threshes. 1101 */ 1102 static void 1103 bge_set_thresh(struct ifnet *ifp, int lvl) 1104 { 1105 struct bge_softc *sc = ifp->if_softc; 1106 int s; 1107 1108 /* For now, just save the new Rx-intr thresholds and record 1109 * that a threshold update is pending. Updating the hardware 1110 * registers here (even at splhigh()) is observed to 1111 * occasionaly cause glitches where Rx-interrupts are not 1112 * honoured for up to 10 seconds. jonathan@NetBSD.org, 2003-04-05 1113 */ 1114 s = splnet(); 1115 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1116 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1117 sc->bge_pending_rxintr_change = 1; 1118 splx(s); 1119 1120 return; 1121 } 1122 1123 1124 /* 1125 * Update Rx thresholds of all bge devices 1126 */ 1127 static void 1128 bge_update_all_threshes(int lvl) 1129 { 1130 struct ifnet *ifp; 1131 const char * const namebuf = "bge"; 1132 int namelen; 1133 1134 if (lvl < 0) 1135 lvl = 0; 1136 else if (lvl >= NBGE_RX_THRESH) 1137 lvl = NBGE_RX_THRESH - 1; 1138 1139 namelen = strlen(namebuf); 1140 /* 1141 * Now search all the interfaces for this name/number 1142 */ 1143 IFNET_FOREACH(ifp) { 1144 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1145 continue; 1146 /* We got a match: update if doing auto-threshold-tuning */ 1147 if (bge_auto_thresh) 1148 bge_set_thresh(ifp, lvl); 1149 } 1150 } 1151 1152 /* 1153 * Handle events that have triggered interrupts. 1154 */ 1155 static void 1156 bge_handle_events(struct bge_softc *sc) 1157 { 1158 1159 return; 1160 } 1161 1162 /* 1163 * Memory management for jumbo frames. 1164 */ 1165 1166 static int 1167 bge_alloc_jumbo_mem(struct bge_softc *sc) 1168 { 1169 char *ptr, *kva; 1170 bus_dma_segment_t seg; 1171 int i, rseg, state, error; 1172 struct bge_jpool_entry *entry; 1173 1174 state = error = 0; 1175 1176 /* Grab a big chunk o' storage. */ 1177 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1178 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1179 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1180 return ENOBUFS; 1181 } 1182 1183 state = 1; 1184 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1185 BUS_DMA_NOWAIT)) { 1186 aprint_error_dev(sc->bge_dev, 1187 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1188 error = ENOBUFS; 1189 goto out; 1190 } 1191 1192 state = 2; 1193 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1194 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1195 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1196 error = ENOBUFS; 1197 goto out; 1198 } 1199 1200 state = 3; 1201 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1202 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1203 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1204 error = ENOBUFS; 1205 goto out; 1206 } 1207 1208 state = 4; 1209 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1210 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1211 1212 SLIST_INIT(&sc->bge_jfree_listhead); 1213 SLIST_INIT(&sc->bge_jinuse_listhead); 1214 1215 /* 1216 * Now divide it up into 9K pieces and save the addresses 1217 * in an array. 1218 */ 1219 ptr = sc->bge_cdata.bge_jumbo_buf; 1220 for (i = 0; i < BGE_JSLOTS; i++) { 1221 sc->bge_cdata.bge_jslots[i] = ptr; 1222 ptr += BGE_JLEN; 1223 entry = malloc(sizeof(struct bge_jpool_entry), 1224 M_DEVBUF, M_NOWAIT); 1225 if (entry == NULL) { 1226 aprint_error_dev(sc->bge_dev, 1227 "no memory for jumbo buffer queue!\n"); 1228 error = ENOBUFS; 1229 goto out; 1230 } 1231 entry->slot = i; 1232 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1233 entry, jpool_entries); 1234 } 1235 out: 1236 if (error != 0) { 1237 switch (state) { 1238 case 4: 1239 bus_dmamap_unload(sc->bge_dmatag, 1240 sc->bge_cdata.bge_rx_jumbo_map); 1241 case 3: 1242 bus_dmamap_destroy(sc->bge_dmatag, 1243 sc->bge_cdata.bge_rx_jumbo_map); 1244 case 2: 1245 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1246 case 1: 1247 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1248 break; 1249 default: 1250 break; 1251 } 1252 } 1253 1254 return error; 1255 } 1256 1257 /* 1258 * Allocate a jumbo buffer. 1259 */ 1260 static void * 1261 bge_jalloc(struct bge_softc *sc) 1262 { 1263 struct bge_jpool_entry *entry; 1264 1265 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1266 1267 if (entry == NULL) { 1268 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1269 return NULL; 1270 } 1271 1272 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1273 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1274 return (sc->bge_cdata.bge_jslots[entry->slot]); 1275 } 1276 1277 /* 1278 * Release a jumbo buffer. 1279 */ 1280 static void 1281 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1282 { 1283 struct bge_jpool_entry *entry; 1284 struct bge_softc *sc; 1285 int i, s; 1286 1287 /* Extract the softc struct pointer. */ 1288 sc = (struct bge_softc *)arg; 1289 1290 if (sc == NULL) 1291 panic("bge_jfree: can't find softc pointer!"); 1292 1293 /* calculate the slot this buffer belongs to */ 1294 1295 i = ((char *)buf 1296 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1297 1298 if ((i < 0) || (i >= BGE_JSLOTS)) 1299 panic("bge_jfree: asked to free buffer that we don't manage!"); 1300 1301 s = splvm(); 1302 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1303 if (entry == NULL) 1304 panic("bge_jfree: buffer not in use!"); 1305 entry->slot = i; 1306 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1307 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1308 1309 if (__predict_true(m != NULL)) 1310 pool_cache_put(mb_cache, m); 1311 splx(s); 1312 } 1313 1314 1315 /* 1316 * Initialize a standard receive ring descriptor. 1317 */ 1318 static int 1319 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1320 bus_dmamap_t dmamap) 1321 { 1322 struct mbuf *m_new = NULL; 1323 struct bge_rx_bd *r; 1324 int error; 1325 1326 if (dmamap == NULL) { 1327 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1328 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1329 if (error != 0) 1330 return error; 1331 } 1332 1333 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1334 1335 if (m == NULL) { 1336 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1337 if (m_new == NULL) 1338 return ENOBUFS; 1339 1340 MCLGET(m_new, M_DONTWAIT); 1341 if (!(m_new->m_flags & M_EXT)) { 1342 m_freem(m_new); 1343 return ENOBUFS; 1344 } 1345 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1346 1347 } else { 1348 m_new = m; 1349 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1350 m_new->m_data = m_new->m_ext.ext_buf; 1351 } 1352 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1353 m_adj(m_new, ETHER_ALIGN); 1354 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1355 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1356 return ENOBUFS; 1357 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1358 BUS_DMASYNC_PREREAD); 1359 1360 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1361 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1362 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1363 r->bge_flags = BGE_RXBDFLAG_END; 1364 r->bge_len = m_new->m_len; 1365 r->bge_idx = i; 1366 1367 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1368 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1369 i * sizeof (struct bge_rx_bd), 1370 sizeof (struct bge_rx_bd), 1371 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1372 1373 return 0; 1374 } 1375 1376 /* 1377 * Initialize a jumbo receive ring descriptor. This allocates 1378 * a jumbo buffer from the pool managed internally by the driver. 1379 */ 1380 static int 1381 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1382 { 1383 struct mbuf *m_new = NULL; 1384 struct bge_rx_bd *r; 1385 void *buf = NULL; 1386 1387 if (m == NULL) { 1388 1389 /* Allocate the mbuf. */ 1390 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1391 if (m_new == NULL) 1392 return ENOBUFS; 1393 1394 /* Allocate the jumbo buffer */ 1395 buf = bge_jalloc(sc); 1396 if (buf == NULL) { 1397 m_freem(m_new); 1398 aprint_error_dev(sc->bge_dev, 1399 "jumbo allocation failed -- packet dropped!\n"); 1400 return ENOBUFS; 1401 } 1402 1403 /* Attach the buffer to the mbuf. */ 1404 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1405 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1406 bge_jfree, sc); 1407 m_new->m_flags |= M_EXT_RW; 1408 } else { 1409 m_new = m; 1410 buf = m_new->m_data = m_new->m_ext.ext_buf; 1411 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1412 } 1413 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1414 m_adj(m_new, ETHER_ALIGN); 1415 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1416 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1417 BUS_DMASYNC_PREREAD); 1418 /* Set up the descriptor. */ 1419 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1420 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1421 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1422 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1423 r->bge_len = m_new->m_len; 1424 r->bge_idx = i; 1425 1426 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1427 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1428 i * sizeof (struct bge_rx_bd), 1429 sizeof (struct bge_rx_bd), 1430 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1431 1432 return 0; 1433 } 1434 1435 /* 1436 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1437 * that's 1MB or memory, which is a lot. For now, we fill only the first 1438 * 256 ring entries and hope that our CPU is fast enough to keep up with 1439 * the NIC. 1440 */ 1441 static int 1442 bge_init_rx_ring_std(struct bge_softc *sc) 1443 { 1444 int i; 1445 1446 if (sc->bge_flags & BGE_RXRING_VALID) 1447 return 0; 1448 1449 for (i = 0; i < BGE_SSLOTS; i++) { 1450 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1451 return ENOBUFS; 1452 } 1453 1454 sc->bge_std = i - 1; 1455 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1456 1457 sc->bge_flags |= BGE_RXRING_VALID; 1458 1459 return 0; 1460 } 1461 1462 static void 1463 bge_free_rx_ring_std(struct bge_softc *sc) 1464 { 1465 int i; 1466 1467 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1468 return; 1469 1470 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1471 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1472 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1473 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1474 bus_dmamap_destroy(sc->bge_dmatag, 1475 sc->bge_cdata.bge_rx_std_map[i]); 1476 } 1477 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1478 sizeof(struct bge_rx_bd)); 1479 } 1480 1481 sc->bge_flags &= ~BGE_RXRING_VALID; 1482 } 1483 1484 static int 1485 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1486 { 1487 int i; 1488 volatile struct bge_rcb *rcb; 1489 1490 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1491 return 0; 1492 1493 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1494 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1495 return ENOBUFS; 1496 }; 1497 1498 sc->bge_jumbo = i - 1; 1499 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1500 1501 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1502 rcb->bge_maxlen_flags = 0; 1503 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1504 1505 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1506 1507 return 0; 1508 } 1509 1510 static void 1511 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1512 { 1513 int i; 1514 1515 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1516 return; 1517 1518 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1519 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1520 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1521 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1522 } 1523 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1524 sizeof(struct bge_rx_bd)); 1525 } 1526 1527 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1528 } 1529 1530 static void 1531 bge_free_tx_ring(struct bge_softc *sc) 1532 { 1533 int i, freed; 1534 struct txdmamap_pool_entry *dma; 1535 1536 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1537 return; 1538 1539 freed = 0; 1540 1541 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1542 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1543 freed++; 1544 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1545 sc->bge_cdata.bge_tx_chain[i] = NULL; 1546 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1547 link); 1548 sc->txdma[i] = 0; 1549 } 1550 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1551 sizeof(struct bge_tx_bd)); 1552 } 1553 1554 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1555 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1556 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1557 free(dma, M_DEVBUF); 1558 } 1559 1560 sc->bge_flags &= ~BGE_TXRING_VALID; 1561 } 1562 1563 static int 1564 bge_init_tx_ring(struct bge_softc *sc) 1565 { 1566 int i; 1567 bus_dmamap_t dmamap; 1568 struct txdmamap_pool_entry *dma; 1569 1570 if (sc->bge_flags & BGE_TXRING_VALID) 1571 return 0; 1572 1573 sc->bge_txcnt = 0; 1574 sc->bge_tx_saved_considx = 0; 1575 1576 /* Initialize transmit producer index for host-memory send ring. */ 1577 sc->bge_tx_prodidx = 0; 1578 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1579 /* 5700 b2 errata */ 1580 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1581 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1582 1583 /* NIC-memory send ring not used; initialize to zero. */ 1584 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1585 /* 5700 b2 errata */ 1586 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1587 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1588 1589 SLIST_INIT(&sc->txdma_list); 1590 for (i = 0; i < BGE_RSLOTS; i++) { 1591 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1592 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1593 &dmamap)) 1594 return ENOBUFS; 1595 if (dmamap == NULL) 1596 panic("dmamap NULL in bge_init_tx_ring"); 1597 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1598 if (dma == NULL) { 1599 aprint_error_dev(sc->bge_dev, 1600 "can't alloc txdmamap_pool_entry\n"); 1601 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1602 return ENOMEM; 1603 } 1604 dma->dmamap = dmamap; 1605 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1606 } 1607 1608 sc->bge_flags |= BGE_TXRING_VALID; 1609 1610 return 0; 1611 } 1612 1613 static void 1614 bge_setmulti(struct bge_softc *sc) 1615 { 1616 struct ethercom *ac = &sc->ethercom; 1617 struct ifnet *ifp = &ac->ec_if; 1618 struct ether_multi *enm; 1619 struct ether_multistep step; 1620 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1621 uint32_t h; 1622 int i; 1623 1624 if (ifp->if_flags & IFF_PROMISC) 1625 goto allmulti; 1626 1627 /* Now program new ones. */ 1628 ETHER_FIRST_MULTI(step, ac, enm); 1629 while (enm != NULL) { 1630 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1631 /* 1632 * We must listen to a range of multicast addresses. 1633 * For now, just accept all multicasts, rather than 1634 * trying to set only those filter bits needed to match 1635 * the range. (At this time, the only use of address 1636 * ranges is for IP multicast routing, for which the 1637 * range is big enough to require all bits set.) 1638 */ 1639 goto allmulti; 1640 } 1641 1642 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1643 1644 /* Just want the 7 least-significant bits. */ 1645 h &= 0x7f; 1646 1647 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1648 ETHER_NEXT_MULTI(step, enm); 1649 } 1650 1651 ifp->if_flags &= ~IFF_ALLMULTI; 1652 goto setit; 1653 1654 allmulti: 1655 ifp->if_flags |= IFF_ALLMULTI; 1656 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1657 1658 setit: 1659 for (i = 0; i < 4; i++) 1660 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1661 } 1662 1663 static void 1664 bge_sig_pre_reset(struct bge_softc *sc, int type) 1665 { 1666 /* 1667 * Some chips don't like this so only do this if ASF is enabled 1668 */ 1669 if (sc->bge_asf_mode) 1670 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1671 1672 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1673 switch (type) { 1674 case BGE_RESET_START: 1675 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1676 break; 1677 case BGE_RESET_STOP: 1678 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1679 break; 1680 } 1681 } 1682 } 1683 1684 static void 1685 bge_sig_post_reset(struct bge_softc *sc, int type) 1686 { 1687 1688 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1689 switch (type) { 1690 case BGE_RESET_START: 1691 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1692 /* START DONE */ 1693 break; 1694 case BGE_RESET_STOP: 1695 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1696 break; 1697 } 1698 } 1699 } 1700 1701 static void 1702 bge_sig_legacy(struct bge_softc *sc, int type) 1703 { 1704 1705 if (sc->bge_asf_mode) { 1706 switch (type) { 1707 case BGE_RESET_START: 1708 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1709 break; 1710 case BGE_RESET_STOP: 1711 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1712 break; 1713 } 1714 } 1715 } 1716 1717 static void 1718 bge_stop_fw(struct bge_softc *sc) 1719 { 1720 int i; 1721 1722 if (sc->bge_asf_mode) { 1723 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1724 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1725 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1726 1727 for (i = 0; i < 100; i++) { 1728 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1729 break; 1730 DELAY(10); 1731 } 1732 } 1733 } 1734 1735 static int 1736 bge_poll_fw(struct bge_softc *sc) 1737 { 1738 uint32_t val; 1739 int i; 1740 1741 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1742 for (i = 0; i < BGE_TIMEOUT; i++) { 1743 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1744 if (val & BGE_VCPU_STATUS_INIT_DONE) 1745 break; 1746 DELAY(100); 1747 } 1748 if (i >= BGE_TIMEOUT) { 1749 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1750 return -1; 1751 } 1752 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 1753 /* 1754 * Poll the value location we just wrote until 1755 * we see the 1's complement of the magic number. 1756 * This indicates that the firmware initialization 1757 * is complete. 1758 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1759 */ 1760 for (i = 0; i < BGE_TIMEOUT; i++) { 1761 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1762 if (val == ~BGE_MAGIC_NUMBER) 1763 break; 1764 DELAY(10); 1765 } 1766 1767 if (i >= BGE_TIMEOUT) { 1768 aprint_error_dev(sc->bge_dev, 1769 "firmware handshake timed out, val = %x\n", val); 1770 return -1; 1771 } 1772 } 1773 1774 return 0; 1775 } 1776 1777 /* 1778 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1779 * self-test results. 1780 */ 1781 static int 1782 bge_chipinit(struct bge_softc *sc) 1783 { 1784 int i; 1785 uint32_t dma_rw_ctl; 1786 1787 /* Set endianness before we access any non-PCI registers. */ 1788 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1789 BGE_INIT); 1790 1791 /* Set power state to D0. */ 1792 bge_setpowerstate(sc, 0); 1793 1794 /* Clear the MAC control register */ 1795 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1796 1797 /* 1798 * Clear the MAC statistics block in the NIC's 1799 * internal memory. 1800 */ 1801 for (i = BGE_STATS_BLOCK; 1802 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1803 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1804 1805 for (i = BGE_STATUS_BLOCK; 1806 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1807 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1808 1809 /* Set up the PCI DMA control register. */ 1810 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1811 if (sc->bge_flags & BGE_PCIE) { 1812 /* Read watermark not used, 128 bytes for write. */ 1813 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1814 device_xname(sc->bge_dev))); 1815 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1816 } else if (sc->bge_flags & BGE_PCIX) { 1817 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1818 device_xname(sc->bge_dev))); 1819 /* PCI-X bus */ 1820 if (BGE_IS_5714_FAMILY(sc)) { 1821 /* 256 bytes for read and write. */ 1822 dma_rw_ctl |= (0x02 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1823 (0x02 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1824 1825 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1826 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1827 else 1828 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1829 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1830 /* 1536 bytes for read, 384 bytes for write. */ 1831 dma_rw_ctl |= 1832 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1833 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1834 } else { 1835 /* 384 bytes for read and write. */ 1836 dma_rw_ctl |= (0x03 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1837 (0x03 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1838 (0x0F); 1839 } 1840 1841 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1842 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1843 uint32_t tmp; 1844 1845 /* Set ONEDMA_ATONCE for hardware workaround. */ 1846 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1847 if (tmp == 6 || tmp == 7) 1848 dma_rw_ctl |= 1849 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1850 1851 /* Set PCI-X DMA write workaround. */ 1852 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1853 } 1854 } else { 1855 /* Conventional PCI bus: 256 bytes for read and write. */ 1856 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1857 device_xname(sc->bge_dev))); 1858 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1859 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1860 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1861 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1862 dma_rw_ctl |= 0x0F; 1863 } 1864 1865 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1866 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1867 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1868 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1869 1870 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1871 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1872 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1873 1874 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1875 dma_rw_ctl); 1876 1877 /* 1878 * Set up general mode register. 1879 */ 1880 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1881 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1882 BGE_MODECTL_TX_NO_PHDR_CSUM); 1883 1884 /* 1885 * BCM5701 B5 have a bug causing data corruption when using 1886 * 64-bit DMA reads, which can be terminated early and then 1887 * completed later as 32-bit accesses, in combination with 1888 * certain bridges. 1889 */ 1890 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1891 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1892 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1893 1894 /* 1895 * Tell the firmware the driver is running 1896 */ 1897 if (sc->bge_asf_mode & ASF_STACKUP) 1898 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1899 1900 /* 1901 * Disable memory write invalidate. Apparently it is not supported 1902 * properly by these devices. 1903 */ 1904 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1905 PCI_COMMAND_INVALIDATE_ENABLE); 1906 1907 #ifdef __brokenalpha__ 1908 /* 1909 * Must insure that we do not cross an 8K (bytes) boundary 1910 * for DMA reads. Our highest limit is 1K bytes. This is a 1911 * restriction on some ALPHA platforms with early revision 1912 * 21174 PCI chipsets, such as the AlphaPC 164lx 1913 */ 1914 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1915 #endif 1916 1917 /* Set the timer prescaler (always 66MHz) */ 1918 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1919 1920 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1921 DELAY(40); /* XXX */ 1922 1923 /* Put PHY into ready state */ 1924 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1925 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1926 DELAY(40); 1927 } 1928 1929 return 0; 1930 } 1931 1932 static int 1933 bge_blockinit(struct bge_softc *sc) 1934 { 1935 volatile struct bge_rcb *rcb; 1936 bus_size_t rcb_addr; 1937 int i; 1938 struct ifnet *ifp = &sc->ethercom.ec_if; 1939 bge_hostaddr taddr; 1940 uint32_t val; 1941 1942 /* 1943 * Initialize the memory window pointer register so that 1944 * we can access the first 32K of internal NIC RAM. This will 1945 * allow us to set up the TX send ring RCBs and the RX return 1946 * ring RCBs, plus other things which live in NIC memory. 1947 */ 1948 1949 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1950 1951 /* Step 33: Configure mbuf memory pool */ 1952 if (BGE_IS_5700_FAMILY(sc)) { 1953 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1954 BGE_BUFFPOOL_1); 1955 1956 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1957 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1958 else 1959 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1960 1961 /* Configure DMA resource pool */ 1962 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1963 BGE_DMA_DESCRIPTORS); 1964 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1965 } 1966 1967 /* Step 35: Configure mbuf pool watermarks */ 1968 #ifdef ORIG_WPAUL_VALUES 1969 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1970 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1972 #else 1973 1974 /* new broadcom docs strongly recommend these: */ 1975 if (!BGE_IS_5705_PLUS(sc)) { 1976 if (ifp->if_mtu > ETHER_MAX_LEN) { 1977 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1978 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1979 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1980 } else { 1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1982 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1983 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1984 } 1985 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1986 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1987 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1989 } else { 1990 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1991 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1992 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1993 } 1994 #endif 1995 1996 /* Step 36: Configure DMA resource watermarks */ 1997 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1998 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1999 2000 /* Step 38: Enable buffer manager */ 2001 CSR_WRITE_4(sc, BGE_BMAN_MODE, 2002 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 2003 2004 /* Step 39: Poll for buffer manager start indication */ 2005 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2006 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2007 break; 2008 DELAY(10); 2009 } 2010 2011 if (i == BGE_TIMEOUT * 2) { 2012 aprint_error_dev(sc->bge_dev, 2013 "buffer manager failed to start\n"); 2014 return ENXIO; 2015 } 2016 2017 /* Step 40: Enable flow-through queues */ 2018 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2019 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2020 2021 /* Wait until queue initialization is complete */ 2022 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2023 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2024 break; 2025 DELAY(10); 2026 } 2027 2028 if (i == BGE_TIMEOUT * 2) { 2029 aprint_error_dev(sc->bge_dev, 2030 "flow-through queue init failed\n"); 2031 return ENXIO; 2032 } 2033 2034 /* Step 41: Initialize the standard RX ring control block */ 2035 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2036 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2037 if (BGE_IS_5705_PLUS(sc)) 2038 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2039 else 2040 rcb->bge_maxlen_flags = 2041 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2042 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2043 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2044 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2045 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2046 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2047 2048 /* 2049 * Step 42: Initialize the jumbo RX ring control block 2050 * We set the 'ring disabled' bit in the flags 2051 * field until we're actually ready to start 2052 * using this ring (i.e. once we set the MTU 2053 * high enough to require it). 2054 */ 2055 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2056 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2057 BGE_HOSTADDR(rcb->bge_hostaddr, 2058 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2059 rcb->bge_maxlen_flags = 2060 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2061 BGE_RCB_FLAG_RING_DISABLED); 2062 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2063 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2064 rcb->bge_hostaddr.bge_addr_hi); 2065 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2066 rcb->bge_hostaddr.bge_addr_lo); 2067 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2068 rcb->bge_maxlen_flags); 2069 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2070 2071 /* Set up dummy disabled mini ring RCB */ 2072 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2073 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2074 BGE_RCB_FLAG_RING_DISABLED); 2075 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2076 rcb->bge_maxlen_flags); 2077 2078 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2079 offsetof(struct bge_ring_data, bge_info), 2080 sizeof (struct bge_gib), 2081 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2082 } 2083 2084 /* 2085 * Set the BD ring replenish thresholds. The recommended 2086 * values are 1/8th the number of descriptors allocated to 2087 * each ring. 2088 */ 2089 i = BGE_STD_RX_RING_CNT / 8; 2090 2091 /* 2092 * Use a value of 8 for the following chips to workaround HW errata. 2093 * Some of these chips have been added based on empirical 2094 * evidence (they don't work unless this is done). 2095 */ 2096 if (BGE_IS_5705_PLUS(sc)) 2097 i = 8; 2098 2099 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2100 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2101 2102 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2103 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 2104 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2105 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2106 } 2107 2108 /* 2109 * Disable all unused send rings by setting the 'ring disabled' 2110 * bit in the flags field of all the TX send ring control blocks. 2111 * These are located in NIC memory. 2112 */ 2113 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2114 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2115 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2116 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2117 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2118 rcb_addr += sizeof(struct bge_rcb); 2119 } 2120 2121 /* Configure TX RCB 0 (we use only the first ring) */ 2122 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2123 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2124 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2125 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2126 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2127 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2128 if (BGE_IS_5700_FAMILY(sc)) 2129 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2130 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2131 2132 /* Disable all unused RX return rings */ 2133 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2134 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2135 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2136 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2137 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2138 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2139 BGE_RCB_FLAG_RING_DISABLED)); 2140 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2141 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2142 (i * (sizeof(uint64_t))), 0); 2143 rcb_addr += sizeof(struct bge_rcb); 2144 } 2145 2146 /* Initialize RX ring indexes */ 2147 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2148 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2149 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2150 2151 /* 2152 * Set up RX return ring 0 2153 * Note that the NIC address for RX return rings is 0x00000000. 2154 * The return rings live entirely within the host, so the 2155 * nicaddr field in the RCB isn't used. 2156 */ 2157 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2158 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2159 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2160 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2161 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2162 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2163 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2164 2165 /* Set random backoff seed for TX */ 2166 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2167 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2168 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2169 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2170 BGE_TX_BACKOFF_SEED_MASK); 2171 2172 /* Set inter-packet gap */ 2173 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2174 2175 /* 2176 * Specify which ring to use for packets that don't match 2177 * any RX rules. 2178 */ 2179 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2180 2181 /* 2182 * Configure number of RX lists. One interrupt distribution 2183 * list, sixteen active lists, one bad frames class. 2184 */ 2185 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2186 2187 /* Inialize RX list placement stats mask. */ 2188 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2189 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2190 2191 /* Disable host coalescing until we get it set up */ 2192 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2193 2194 /* Poll to make sure it's shut down. */ 2195 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2196 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2197 break; 2198 DELAY(10); 2199 } 2200 2201 if (i == BGE_TIMEOUT * 2) { 2202 aprint_error_dev(sc->bge_dev, 2203 "host coalescing engine failed to idle\n"); 2204 return ENXIO; 2205 } 2206 2207 /* Set up host coalescing defaults */ 2208 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2209 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2210 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2211 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2212 if (BGE_IS_5700_FAMILY(sc)) { 2213 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2214 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2215 } 2216 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2217 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2218 2219 /* Set up address of statistics block */ 2220 if (BGE_IS_5700_FAMILY(sc)) { 2221 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2222 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2223 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2224 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2225 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2226 } 2227 2228 /* Set up address of status block */ 2229 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2230 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2231 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2232 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2233 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2234 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2235 2236 /* Turn on host coalescing state machine */ 2237 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2238 2239 /* Turn on RX BD completion state machine and enable attentions */ 2240 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2241 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2242 2243 /* Turn on RX list placement state machine */ 2244 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2245 2246 /* Turn on RX list selector state machine. */ 2247 if (BGE_IS_5700_FAMILY(sc)) 2248 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2249 2250 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2251 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2252 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2253 BGE_MACMODE_FRMHDR_DMA_ENB; 2254 2255 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2256 val |= BGE_PORTMODE_TBI; 2257 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2258 val |= BGE_PORTMODE_GMII; 2259 else 2260 val |= BGE_PORTMODE_MII; 2261 2262 /* Turn on DMA, clear stats */ 2263 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2264 2265 /* Set misc. local control, enable interrupts on attentions */ 2266 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2267 2268 #ifdef notdef 2269 /* Assert GPIO pins for PHY reset */ 2270 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2271 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2272 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2273 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2274 #endif 2275 2276 #if defined(not_quite_yet) 2277 /* Linux driver enables enable gpio pin #1 on 5700s */ 2278 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2279 sc->bge_local_ctrl_reg |= 2280 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2281 } 2282 #endif 2283 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2284 2285 /* Turn on DMA completion state machine */ 2286 if (BGE_IS_5700_FAMILY(sc)) 2287 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2288 2289 /* Turn on write DMA state machine */ 2290 { 2291 uint32_t bge_wdma_mode = 2292 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2293 2294 /* Enable host coalescing bug fix; see Linux tg3.c */ 2295 if (BGE_IS_5755_PLUS(sc)) 2296 bge_wdma_mode |= BGE_WDMAMODE_STATUS_TAG_FIX; 2297 2298 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2299 } 2300 2301 /* Turn on read DMA state machine */ 2302 { 2303 uint32_t dma_read_modebits; 2304 2305 dma_read_modebits = 2306 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2307 2308 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2309 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2310 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2311 dma_read_modebits |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2312 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2313 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2314 2315 if (sc->bge_flags & BGE_PCIE) 2316 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2317 if (sc->bge_flags & BGE_TSO) 2318 dma_read_modebits |= BGE_RDMAMODE_TSO4_ENABLE; 2319 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2320 delay(40); 2321 } 2322 2323 /* Turn on RX data completion state machine */ 2324 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2325 2326 /* Turn on RX BD initiator state machine */ 2327 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2328 2329 /* Turn on RX data and RX BD initiator state machine */ 2330 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2331 2332 /* Turn on Mbuf cluster free state machine */ 2333 if (BGE_IS_5700_FAMILY(sc)) 2334 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2335 2336 /* Turn on send BD completion state machine */ 2337 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2338 2339 /* Turn on send data completion state machine */ 2340 val = BGE_SDCMODE_ENABLE; 2341 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2342 val |= BGE_SDCMODE_CDELAY; 2343 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2344 2345 /* Turn on send data initiator state machine */ 2346 if (sc->bge_flags & BGE_TSO) { 2347 /* XXX: magic value from Linux driver */ 2348 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2349 } else 2350 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2351 2352 /* Turn on send BD initiator state machine */ 2353 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2354 2355 /* Turn on send BD selector state machine */ 2356 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2357 2358 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2359 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2360 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2361 2362 /* ack/clear link change events */ 2363 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2364 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2365 BGE_MACSTAT_LINK_CHANGED); 2366 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2367 2368 /* Enable PHY auto polling (for MII/GMII only) */ 2369 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2370 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2371 } else { 2372 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2373 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2374 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2375 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2376 BGE_EVTENB_MI_INTERRUPT); 2377 } 2378 2379 /* 2380 * Clear any pending link state attention. 2381 * Otherwise some link state change events may be lost until attention 2382 * is cleared by bge_intr() -> bge_link_upd() sequence. 2383 * It's not necessary on newer BCM chips - perhaps enabling link 2384 * state change attentions implies clearing pending attention. 2385 */ 2386 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2387 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2388 BGE_MACSTAT_LINK_CHANGED); 2389 2390 /* Enable link state change attentions. */ 2391 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2392 2393 return 0; 2394 } 2395 2396 static const struct bge_revision * 2397 bge_lookup_rev(uint32_t chipid) 2398 { 2399 const struct bge_revision *br; 2400 2401 for (br = bge_revisions; br->br_name != NULL; br++) { 2402 if (br->br_chipid == chipid) 2403 return br; 2404 } 2405 2406 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2407 if (br->br_chipid == BGE_ASICREV(chipid)) 2408 return br; 2409 } 2410 2411 return NULL; 2412 } 2413 2414 static const struct bge_product * 2415 bge_lookup(const struct pci_attach_args *pa) 2416 { 2417 const struct bge_product *bp; 2418 2419 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2420 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2421 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2422 return bp; 2423 } 2424 2425 return NULL; 2426 } 2427 2428 static int 2429 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2430 { 2431 #ifdef NOTYET 2432 uint32_t pm_ctl = 0; 2433 2434 /* XXX FIXME: make sure indirect accesses enabled? */ 2435 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2436 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2437 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2438 2439 /* clear the PME_assert bit and power state bits, enable PME */ 2440 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2441 pm_ctl &= ~PCIM_PSTAT_DMASK; 2442 pm_ctl |= (1 << 8); 2443 2444 if (powerlevel == 0) { 2445 pm_ctl |= PCIM_PSTAT_D0; 2446 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2447 pm_ctl, 2); 2448 DELAY(10000); 2449 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2450 DELAY(10000); 2451 2452 #ifdef NOTYET 2453 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2454 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2455 #endif 2456 DELAY(40); DELAY(40); DELAY(40); 2457 DELAY(10000); /* above not quite adequate on 5700 */ 2458 return 0; 2459 } 2460 2461 2462 /* 2463 * Entering ACPI power states D1-D3 is achieved by wiggling 2464 * GMII gpio pins. Example code assumes all hardware vendors 2465 * followed Broadcom's sample pcb layout. Until we verify that 2466 * for all supported OEM cards, states D1-D3 are unsupported. 2467 */ 2468 aprint_error_dev(sc->bge_dev, 2469 "power state %d unimplemented; check GPIO pins\n", 2470 powerlevel); 2471 #endif 2472 return EOPNOTSUPP; 2473 } 2474 2475 2476 /* 2477 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2478 * against our list and return its name if we find a match. Note 2479 * that since the Broadcom controller contains VPD support, we 2480 * can get the device name string from the controller itself instead 2481 * of the compiled-in string. This is a little slow, but it guarantees 2482 * we'll always announce the right product name. 2483 */ 2484 static int 2485 bge_probe(device_t parent, cfdata_t match, void *aux) 2486 { 2487 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2488 2489 if (bge_lookup(pa) != NULL) 2490 return 1; 2491 2492 return 0; 2493 } 2494 2495 static void 2496 bge_attach(device_t parent, device_t self, void *aux) 2497 { 2498 struct bge_softc *sc = device_private(self); 2499 struct pci_attach_args *pa = aux; 2500 prop_dictionary_t dict; 2501 const struct bge_product *bp; 2502 const struct bge_revision *br; 2503 pci_chipset_tag_t pc; 2504 pci_intr_handle_t ih; 2505 const char *intrstr = NULL; 2506 bus_dma_segment_t seg; 2507 int rseg; 2508 uint32_t hwcfg = 0; 2509 uint32_t command; 2510 struct ifnet *ifp; 2511 uint32_t misccfg; 2512 void * kva; 2513 u_char eaddr[ETHER_ADDR_LEN]; 2514 pcireg_t memtype, subid; 2515 bus_addr_t memaddr; 2516 bus_size_t memsize; 2517 uint32_t pm_ctl; 2518 bool no_seeprom; 2519 2520 bp = bge_lookup(pa); 2521 KASSERT(bp != NULL); 2522 2523 sc->sc_pc = pa->pa_pc; 2524 sc->sc_pcitag = pa->pa_tag; 2525 sc->bge_dev = self; 2526 2527 pc = sc->sc_pc; 2528 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2529 2530 aprint_naive(": Ethernet controller\n"); 2531 aprint_normal(": %s\n", bp->bp_name); 2532 2533 /* 2534 * Map control/status registers. 2535 */ 2536 DPRINTFN(5, ("Map control/status regs\n")); 2537 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2538 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2539 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2540 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2541 2542 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2543 aprint_error_dev(sc->bge_dev, 2544 "failed to enable memory mapping!\n"); 2545 return; 2546 } 2547 2548 DPRINTFN(5, ("pci_mem_find\n")); 2549 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2550 switch (memtype) { 2551 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2552 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2553 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2554 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2555 &memaddr, &memsize) == 0) 2556 break; 2557 default: 2558 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2559 return; 2560 } 2561 2562 DPRINTFN(5, ("pci_intr_map\n")); 2563 if (pci_intr_map(pa, &ih)) { 2564 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2565 return; 2566 } 2567 2568 DPRINTFN(5, ("pci_intr_string\n")); 2569 intrstr = pci_intr_string(pc, ih); 2570 2571 DPRINTFN(5, ("pci_intr_establish\n")); 2572 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2573 2574 if (sc->bge_intrhand == NULL) { 2575 aprint_error_dev(sc->bge_dev, 2576 "couldn't establish interrupt%s%s\n", 2577 intrstr ? " at " : "", intrstr ? intrstr : ""); 2578 return; 2579 } 2580 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2581 2582 /* 2583 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2584 * can clobber the chip's PCI config-space power control registers, 2585 * leaving the card in D3 powersave state. 2586 * We do not have memory-mapped registers in this state, 2587 * so force device into D0 state before starting initialization. 2588 */ 2589 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2590 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2591 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2592 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2593 DELAY(1000); /* 27 usec is allegedly sufficent */ 2594 2595 /* 2596 * Save ASIC rev. 2597 */ 2598 sc->bge_chipid = 2599 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2600 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2601 2602 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2603 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5717 || 2604 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 || 2605 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5724) 2606 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2607 BGE_PCI_GEN2_PRODID_ASICREV); 2608 else if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57761 || 2609 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57765 || 2610 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57781 || 2611 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57785 || 2612 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 2613 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795) 2614 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2615 BGE_PCI_GEN15_PRODID_ASICREV); 2616 else 2617 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2618 BGE_PCI_PRODID_ASICREV); 2619 } 2620 2621 if ((pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2622 &sc->bge_pciecap, NULL) != 0) 2623 || (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) { 2624 /* PCIe */ 2625 sc->bge_flags |= BGE_PCIE; 2626 bge_set_max_readrq(sc); 2627 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2628 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2629 /* PCI-X */ 2630 sc->bge_flags |= BGE_PCIX; 2631 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 2632 &sc->bge_pcixcap, NULL) == 0) 2633 aprint_error_dev(sc->bge_dev, 2634 "unable to find PCIX capability\n"); 2635 } 2636 2637 /* chipid */ 2638 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2639 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2640 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2641 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2642 sc->bge_flags |= BGE_5700_FAMILY; 2643 2644 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2646 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2647 sc->bge_flags |= BGE_5714_FAMILY; 2648 2649 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2650 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2651 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2652 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2653 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2654 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2655 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2656 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2657 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2658 sc->bge_flags |= BGE_5755_PLUS; 2659 2660 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2661 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2662 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2663 BGE_IS_5755_PLUS(sc) || 2664 BGE_IS_5714_FAMILY(sc)) 2665 sc->bge_flags |= BGE_5750_PLUS; 2666 2667 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2668 BGE_IS_5750_OR_BEYOND(sc)) 2669 sc->bge_flags |= BGE_5705_PLUS; 2670 2671 /* 2672 * When using the BCM5701 in PCI-X mode, data corruption has 2673 * been observed in the first few bytes of some received packets. 2674 * Aligning the packet buffer in memory eliminates the corruption. 2675 * Unfortunately, this misaligns the packet payloads. On platforms 2676 * which do not support unaligned accesses, we will realign the 2677 * payloads by copying the received packets. 2678 */ 2679 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2680 sc->bge_flags & BGE_PCIX) 2681 sc->bge_flags |= BGE_RX_ALIGNBUG; 2682 2683 if (BGE_IS_5700_FAMILY(sc)) 2684 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2685 2686 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2687 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2688 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2689 sc->bge_flags |= BGE_NO_3LED; 2690 2691 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2692 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2693 2694 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2695 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2696 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2697 sc->bge_flags |= BGE_IS_5788; 2698 2699 /* 2700 * Some controllers seem to require a special firmware to use 2701 * TSO. But the firmware is not available to FreeBSD and Linux 2702 * claims that the TSO performed by the firmware is slower than 2703 * hardware based TSO. Moreover the firmware based TSO has one 2704 * known bug which can't handle TSO if ethernet header + IP/TCP 2705 * header is greater than 80 bytes. The workaround for the TSO 2706 * bug exist but it seems it's too expensive than not using 2707 * TSO at all. Some hardwares also have the TSO bug so limit 2708 * the TSO to the controllers that are not affected TSO issues 2709 * (e.g. 5755 or higher). 2710 */ 2711 if (BGE_IS_5755_PLUS(sc)) { 2712 /* 2713 * BCM5754 and BCM5787 shares the same ASIC id so 2714 * explicit device id check is required. 2715 */ 2716 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2717 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2718 sc->bge_flags |= BGE_TSO; 2719 } 2720 2721 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2722 (misccfg == 0x4000 || misccfg == 0x8000)) || 2723 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2724 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2725 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2726 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2727 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2728 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2729 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2730 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2731 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2732 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2733 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2734 sc->bge_flags |= BGE_10_100_ONLY; 2735 2736 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2737 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2738 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2739 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2740 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2741 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2742 2743 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2744 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2745 sc->bge_flags |= BGE_PHY_CRC_BUG; 2746 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2747 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2748 sc->bge_flags |= BGE_PHY_ADC_BUG; 2749 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2750 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2751 2752 if (BGE_IS_5705_PLUS(sc) && 2753 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2754 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2755 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2756 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2757 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2758 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2759 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2760 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2761 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2762 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2763 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2764 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2765 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2766 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2767 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2768 sc->bge_flags |= BGE_PHY_BER_BUG; 2769 } 2770 2771 /* 2772 * SEEPROM check. 2773 * First check if firmware knows we do not have SEEPROM. 2774 */ 2775 if (prop_dictionary_get_bool(device_properties(self), 2776 "without-seeprom", &no_seeprom) && no_seeprom) 2777 sc->bge_flags |= BGE_NO_EEPROM; 2778 2779 /* Now check the 'ROM failed' bit on the RX CPU */ 2780 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2781 sc->bge_flags |= BGE_NO_EEPROM; 2782 2783 /* Try to reset the chip. */ 2784 DPRINTFN(5, ("bge_reset\n")); 2785 bge_reset(sc); 2786 2787 sc->bge_asf_mode = 0; 2788 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2789 == BGE_MAGIC_NUMBER)) { 2790 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2791 & BGE_HWCFG_ASF) { 2792 sc->bge_asf_mode |= ASF_ENABLE; 2793 sc->bge_asf_mode |= ASF_STACKUP; 2794 if (BGE_IS_5750_OR_BEYOND(sc)) { 2795 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2796 } 2797 } 2798 } 2799 2800 /* Try to reset the chip again the nice way. */ 2801 bge_stop_fw(sc); 2802 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2803 if (bge_reset(sc)) 2804 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2805 2806 bge_sig_legacy(sc, BGE_RESET_STOP); 2807 bge_sig_post_reset(sc, BGE_RESET_STOP); 2808 2809 if (bge_chipinit(sc)) { 2810 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2811 bge_release_resources(sc); 2812 return; 2813 } 2814 2815 /* 2816 * Get station address from the EEPROM 2817 */ 2818 if (bge_get_eaddr(sc, eaddr)) { 2819 aprint_error_dev(sc->bge_dev, 2820 "failed to read station address\n"); 2821 bge_release_resources(sc); 2822 return; 2823 } 2824 2825 br = bge_lookup_rev(sc->bge_chipid); 2826 2827 if (br == NULL) { 2828 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2829 sc->bge_chipid); 2830 } else { 2831 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2832 br->br_name, sc->bge_chipid); 2833 } 2834 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2835 2836 /* Allocate the general information block and ring buffers. */ 2837 if (pci_dma64_available(pa)) 2838 sc->bge_dmatag = pa->pa_dmat64; 2839 else 2840 sc->bge_dmatag = pa->pa_dmat; 2841 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2842 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2843 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2844 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2845 return; 2846 } 2847 DPRINTFN(5, ("bus_dmamem_map\n")); 2848 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2849 sizeof(struct bge_ring_data), &kva, 2850 BUS_DMA_NOWAIT)) { 2851 aprint_error_dev(sc->bge_dev, 2852 "can't map DMA buffers (%zu bytes)\n", 2853 sizeof(struct bge_ring_data)); 2854 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2855 return; 2856 } 2857 DPRINTFN(5, ("bus_dmamem_create\n")); 2858 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2859 sizeof(struct bge_ring_data), 0, 2860 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2861 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2862 bus_dmamem_unmap(sc->bge_dmatag, kva, 2863 sizeof(struct bge_ring_data)); 2864 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2865 return; 2866 } 2867 DPRINTFN(5, ("bus_dmamem_load\n")); 2868 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2869 sizeof(struct bge_ring_data), NULL, 2870 BUS_DMA_NOWAIT)) { 2871 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2872 bus_dmamem_unmap(sc->bge_dmatag, kva, 2873 sizeof(struct bge_ring_data)); 2874 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2875 return; 2876 } 2877 2878 DPRINTFN(5, ("bzero\n")); 2879 sc->bge_rdata = (struct bge_ring_data *)kva; 2880 2881 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2882 2883 /* Try to allocate memory for jumbo buffers. */ 2884 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2885 if (bge_alloc_jumbo_mem(sc)) { 2886 aprint_error_dev(sc->bge_dev, 2887 "jumbo buffer allocation failed\n"); 2888 } else 2889 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2890 } 2891 2892 /* Set default tuneable values. */ 2893 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2894 sc->bge_rx_coal_ticks = 150; 2895 sc->bge_rx_max_coal_bds = 64; 2896 #ifdef ORIG_WPAUL_VALUES 2897 sc->bge_tx_coal_ticks = 150; 2898 sc->bge_tx_max_coal_bds = 128; 2899 #else 2900 sc->bge_tx_coal_ticks = 300; 2901 sc->bge_tx_max_coal_bds = 400; 2902 #endif 2903 if (BGE_IS_5705_PLUS(sc)) { 2904 sc->bge_tx_coal_ticks = (12 * 5); 2905 sc->bge_tx_max_coal_bds = (12 * 5); 2906 aprint_verbose_dev(sc->bge_dev, 2907 "setting short Tx thresholds\n"); 2908 } 2909 2910 if (BGE_IS_5705_PLUS(sc)) 2911 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2912 else 2913 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2914 2915 /* Set up ifnet structure */ 2916 ifp = &sc->ethercom.ec_if; 2917 ifp->if_softc = sc; 2918 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2919 ifp->if_ioctl = bge_ioctl; 2920 ifp->if_stop = bge_stop; 2921 ifp->if_start = bge_start; 2922 ifp->if_init = bge_init; 2923 ifp->if_watchdog = bge_watchdog; 2924 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2925 IFQ_SET_READY(&ifp->if_snd); 2926 DPRINTFN(5, ("strcpy if_xname\n")); 2927 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2928 2929 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2930 sc->ethercom.ec_if.if_capabilities |= 2931 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2932 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2933 sc->ethercom.ec_if.if_capabilities |= 2934 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2935 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2936 #endif 2937 sc->ethercom.ec_capabilities |= 2938 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2939 2940 if (sc->bge_flags & BGE_TSO) 2941 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2942 2943 /* 2944 * Do MII setup. 2945 */ 2946 DPRINTFN(5, ("mii setup\n")); 2947 sc->bge_mii.mii_ifp = ifp; 2948 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2949 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2950 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2951 2952 /* 2953 * Figure out what sort of media we have by checking the 2954 * hardware config word in the first 32k of NIC internal memory, 2955 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2956 * cards, this value appears to be unset. If that's the 2957 * case, we have to rely on identifying the NIC by its PCI 2958 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2959 */ 2960 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2961 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2962 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2963 bge_read_eeprom(sc, (void *)&hwcfg, 2964 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2965 hwcfg = be32toh(hwcfg); 2966 } 2967 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2968 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2969 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2970 if (BGE_IS_5714_FAMILY(sc)) 2971 sc->bge_flags |= BGE_PHY_FIBER_MII; 2972 else 2973 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2974 } 2975 2976 /* set phyflags and chipid before mii_attach() */ 2977 dict = device_properties(self); 2978 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2979 prop_dictionary_set_uint32(dict, "chipid", sc->bge_chipid); 2980 2981 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2982 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2983 bge_ifmedia_sts); 2984 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 2985 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 2986 0, NULL); 2987 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2988 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2989 /* Pretend the user requested this setting */ 2990 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2991 } else { 2992 /* 2993 * Do transceiver setup and tell the firmware the 2994 * driver is down so we can try to get access the 2995 * probe if ASF is running. Retry a couple of times 2996 * if we get a conflict with the ASF firmware accessing 2997 * the PHY. 2998 */ 2999 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3000 bge_asf_driver_up(sc); 3001 3002 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3003 bge_ifmedia_sts); 3004 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 3005 MII_PHY_ANY, MII_OFFSET_ANY, 3006 MIIF_FORCEANEG|MIIF_DOPAUSE); 3007 3008 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 3009 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 3010 ifmedia_add(&sc->bge_mii.mii_media, 3011 IFM_ETHER|IFM_MANUAL, 0, NULL); 3012 ifmedia_set(&sc->bge_mii.mii_media, 3013 IFM_ETHER|IFM_MANUAL); 3014 } else 3015 ifmedia_set(&sc->bge_mii.mii_media, 3016 IFM_ETHER|IFM_AUTO); 3017 3018 /* 3019 * Now tell the firmware we are going up after probing the PHY 3020 */ 3021 if (sc->bge_asf_mode & ASF_STACKUP) 3022 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3023 } 3024 3025 /* 3026 * Call MI attach routine. 3027 */ 3028 DPRINTFN(5, ("if_attach\n")); 3029 if_attach(ifp); 3030 DPRINTFN(5, ("ether_ifattach\n")); 3031 ether_ifattach(ifp, eaddr); 3032 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3033 #if NRND > 0 3034 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3035 RND_TYPE_NET, 0); 3036 #endif 3037 #ifdef BGE_EVENT_COUNTERS 3038 /* 3039 * Attach event counters. 3040 */ 3041 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3042 NULL, device_xname(sc->bge_dev), "intr"); 3043 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3044 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3045 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3046 NULL, device_xname(sc->bge_dev), "tx_xon"); 3047 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3048 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3049 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3050 NULL, device_xname(sc->bge_dev), "rx_xon"); 3051 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3052 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3053 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3054 NULL, device_xname(sc->bge_dev), "xoffentered"); 3055 #endif /* BGE_EVENT_COUNTERS */ 3056 DPRINTFN(5, ("callout_init\n")); 3057 callout_init(&sc->bge_timeout, 0); 3058 3059 if (pmf_device_register(self, NULL, NULL)) 3060 pmf_class_network_register(self, ifp); 3061 else 3062 aprint_error_dev(self, "couldn't establish power handler\n"); 3063 3064 sysctl_bge_init(sc); 3065 3066 #ifdef BGE_DEBUG 3067 bge_debug_info(sc); 3068 #endif 3069 } 3070 3071 static void 3072 bge_release_resources(struct bge_softc *sc) 3073 { 3074 if (sc->bge_vpd_prodname != NULL) 3075 free(sc->bge_vpd_prodname, M_DEVBUF); 3076 3077 if (sc->bge_vpd_readonly != NULL) 3078 free(sc->bge_vpd_readonly, M_DEVBUF); 3079 } 3080 3081 static int 3082 bge_reset(struct bge_softc *sc) 3083 { 3084 uint32_t cachesize, command, pcistate, marbmode; 3085 #if 0 3086 uint32_t new_pcistate; 3087 #endif 3088 pcireg_t devctl, reg; 3089 int i, val; 3090 void (*write_op)(struct bge_softc *, int, int); 3091 3092 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) 3093 && (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3094 if (sc->bge_flags & BGE_PCIE) 3095 write_op = bge_writemem_direct; 3096 else 3097 write_op = bge_writemem_ind; 3098 } else 3099 write_op = bge_writereg_ind; 3100 3101 /* Save some important PCI state. */ 3102 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3103 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3104 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3105 3106 /* Step 5a: Enable memory arbiter. */ 3107 marbmode = 0; 3108 if (BGE_IS_5714_FAMILY(sc)) 3109 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3110 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3111 3112 /* Step 5b-5d: */ 3113 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3114 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3115 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3116 3117 /* XXX ???: Disable fastboot on controllers that support it. */ 3118 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3119 BGE_IS_5755_PLUS(sc)) 3120 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3121 3122 /* 3123 * Step 6: Write the magic number to SRAM at offset 0xB50. 3124 * When firmware finishes its initialization it will 3125 * write ~BGE_MAGIC_NUMBER to the same location. 3126 */ 3127 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3128 3129 /* Step 7: */ 3130 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3131 /* 3132 * XXX: from FreeBSD/Linux; no documentation 3133 */ 3134 if (sc->bge_flags & BGE_PCIE) { 3135 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 3136 /* PCI Express 1.0 system */ 3137 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 3138 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3139 /* 3140 * Prevent PCI Express link training 3141 * during global reset. 3142 */ 3143 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3144 val |= (1<<29); 3145 } 3146 } 3147 3148 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3149 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3150 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3151 i | BGE_VCPU_STATUS_DRV_RESET); 3152 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3153 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3154 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3155 } 3156 3157 /* 3158 * Set GPHY Power Down Override to leave GPHY 3159 * powered up in D0 uninitialized. 3160 */ 3161 if (BGE_IS_5705_PLUS(sc)) 3162 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3163 3164 /* XXX 5721, 5751 and 5752 */ 3165 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3166 val |= BGE_MISCCFG_GRC_RESET_DISABLE; 3167 3168 /* Issue global reset */ 3169 write_op(sc, BGE_MISC_CFG, val); 3170 3171 /* Step 8: wait for complete */ 3172 if (sc->bge_flags & BGE_PCIE) 3173 delay(100*1000); /* too big */ 3174 else 3175 delay(100); 3176 3177 /* From Linux: dummy read to flush PCI posted writes */ 3178 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3179 3180 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3181 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3182 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3183 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW 3184 | BGE_PCIMISCCTL_CLOCKCTL_RW); 3185 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3186 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3187 3188 /* Step 11: disable PCI-X Relaxed Ordering. */ 3189 if (sc->bge_flags & BGE_PCIX) { 3190 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3191 + PCI_PCIX_CMD); 3192 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3193 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3194 } 3195 3196 if (sc->bge_flags & BGE_PCIE) { 3197 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3198 DELAY(500000); 3199 /* XXX: Magic Numbers */ 3200 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3201 BGE_PCI_UNKNOWN0); 3202 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3203 BGE_PCI_UNKNOWN0, 3204 reg | (1 << 15)); 3205 } 3206 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3207 sc->bge_pciecap + PCI_PCIE_DCSR); 3208 /* Clear enable no snoop and disable relaxed ordering. */ 3209 devctl &= ~(0x0010 | PCI_PCIE_DCSR_ENA_NO_SNOOP); 3210 /* Set PCIE max payload size to 128. */ 3211 devctl &= ~(0x00e0); 3212 /* Clear device status register. Write 1b to clear */ 3213 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3214 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3215 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3216 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3217 } 3218 3219 /* Step 12: Enable memory arbiter. */ 3220 marbmode = 0; 3221 if (BGE_IS_5714_FAMILY(sc)) 3222 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3223 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3224 3225 /* Step 17: Poll until the firmware initialization is complete */ 3226 bge_poll_fw(sc); 3227 3228 /* XXX 5721, 5751 and 5752 */ 3229 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3230 /* Step 19: */ 3231 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3232 /* Step 20: */ 3233 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3234 } 3235 3236 /* 3237 * Step 18: wirte mac mode 3238 * XXX Write 0x0c for 5703S and 5704S 3239 */ 3240 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3241 3242 3243 /* Step 21: 5822 B0 errata */ 3244 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3245 pcireg_t msidata; 3246 3247 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3248 BGE_PCI_MSI_DATA); 3249 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3250 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3251 msidata); 3252 } 3253 3254 /* Step 23: restore cache line size */ 3255 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3256 3257 #if 0 3258 /* 3259 * XXX Wait for the value of the PCISTATE register to 3260 * return to its original pre-reset state. This is a 3261 * fairly good indicator of reset completion. If we don't 3262 * wait for the reset to fully complete, trying to read 3263 * from the device's non-PCI registers may yield garbage 3264 * results. 3265 */ 3266 for (i = 0; i < BGE_TIMEOUT; i++) { 3267 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3268 BGE_PCI_PCISTATE); 3269 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3270 (pcistate & ~BGE_PCISTATE_RESERVED)) 3271 break; 3272 DELAY(10); 3273 } 3274 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3275 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3276 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3277 } 3278 #endif 3279 3280 /* Step 28: Fix up byte swapping */ 3281 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3282 3283 /* Tell the ASF firmware we are up */ 3284 if (sc->bge_asf_mode & ASF_STACKUP) 3285 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3286 3287 /* 3288 * The 5704 in TBI mode apparently needs some special 3289 * adjustment to insure the SERDES drive level is set 3290 * to 1.2V. 3291 */ 3292 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3293 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3294 uint32_t serdescfg; 3295 3296 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3297 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3298 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3299 } 3300 3301 if (sc->bge_flags & BGE_PCIE && 3302 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3303 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3304 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3305 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) { 3306 uint32_t v; 3307 3308 /* Enable PCI Express bug fix */ 3309 v = CSR_READ_4(sc, 0x7c00); 3310 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3311 } 3312 DELAY(10000); 3313 3314 return 0; 3315 } 3316 3317 /* 3318 * Frame reception handling. This is called if there's a frame 3319 * on the receive return list. 3320 * 3321 * Note: we have to be able to handle two possibilities here: 3322 * 1) the frame is from the jumbo receive ring 3323 * 2) the frame is from the standard receive ring 3324 */ 3325 3326 static void 3327 bge_rxeof(struct bge_softc *sc) 3328 { 3329 struct ifnet *ifp; 3330 uint16_t rx_prod, rx_cons; 3331 int stdcnt = 0, jumbocnt = 0; 3332 bus_dmamap_t dmamap; 3333 bus_addr_t offset, toff; 3334 bus_size_t tlen; 3335 int tosync; 3336 3337 rx_cons = sc->bge_rx_saved_considx; 3338 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3339 3340 /* Nothing to do */ 3341 if (rx_cons == rx_prod) 3342 return; 3343 3344 ifp = &sc->ethercom.ec_if; 3345 3346 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3347 offsetof(struct bge_ring_data, bge_status_block), 3348 sizeof (struct bge_status_block), 3349 BUS_DMASYNC_POSTREAD); 3350 3351 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3352 tosync = rx_prod - rx_cons; 3353 3354 #if NRND > 0 3355 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3356 rnd_add_uint32(&sc->rnd_source, tosync); 3357 #endif 3358 3359 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3360 3361 if (tosync < 0) { 3362 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3363 sizeof (struct bge_rx_bd); 3364 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3365 toff, tlen, BUS_DMASYNC_POSTREAD); 3366 tosync = -tosync; 3367 } 3368 3369 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3370 offset, tosync * sizeof (struct bge_rx_bd), 3371 BUS_DMASYNC_POSTREAD); 3372 3373 while (rx_cons != rx_prod) { 3374 struct bge_rx_bd *cur_rx; 3375 uint32_t rxidx; 3376 struct mbuf *m = NULL; 3377 3378 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3379 3380 rxidx = cur_rx->bge_idx; 3381 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3382 3383 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3384 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3385 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3386 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3387 jumbocnt++; 3388 bus_dmamap_sync(sc->bge_dmatag, 3389 sc->bge_cdata.bge_rx_jumbo_map, 3390 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3391 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3392 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3393 ifp->if_ierrors++; 3394 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3395 continue; 3396 } 3397 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3398 NULL)== ENOBUFS) { 3399 ifp->if_ierrors++; 3400 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3401 continue; 3402 } 3403 } else { 3404 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3405 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3406 3407 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3408 stdcnt++; 3409 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3410 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3411 if (dmamap == NULL) { 3412 ifp->if_ierrors++; 3413 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3414 continue; 3415 } 3416 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3417 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3418 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3419 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3420 ifp->if_ierrors++; 3421 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3422 continue; 3423 } 3424 if (bge_newbuf_std(sc, sc->bge_std, 3425 NULL, dmamap) == ENOBUFS) { 3426 ifp->if_ierrors++; 3427 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3428 continue; 3429 } 3430 } 3431 3432 ifp->if_ipackets++; 3433 #ifndef __NO_STRICT_ALIGNMENT 3434 /* 3435 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3436 * the Rx buffer has the layer-2 header unaligned. 3437 * If our CPU requires alignment, re-align by copying. 3438 */ 3439 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3440 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3441 cur_rx->bge_len); 3442 m->m_data += ETHER_ALIGN; 3443 } 3444 #endif 3445 3446 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3447 m->m_pkthdr.rcvif = ifp; 3448 3449 /* 3450 * Handle BPF listeners. Let the BPF user see the packet. 3451 */ 3452 bpf_mtap(ifp, m); 3453 3454 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3455 3456 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3457 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3458 /* 3459 * Rx transport checksum-offload may also 3460 * have bugs with packets which, when transmitted, 3461 * were `runts' requiring padding. 3462 */ 3463 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3464 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3465 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3466 m->m_pkthdr.csum_data = 3467 cur_rx->bge_tcp_udp_csum; 3468 m->m_pkthdr.csum_flags |= 3469 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3470 M_CSUM_DATA); 3471 } 3472 3473 /* 3474 * If we received a packet with a vlan tag, pass it 3475 * to vlan_input() instead of ether_input(). 3476 */ 3477 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3478 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3479 } 3480 3481 (*ifp->if_input)(ifp, m); 3482 } 3483 3484 sc->bge_rx_saved_considx = rx_cons; 3485 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3486 if (stdcnt) 3487 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3488 if (jumbocnt) 3489 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3490 } 3491 3492 static void 3493 bge_txeof(struct bge_softc *sc) 3494 { 3495 struct bge_tx_bd *cur_tx = NULL; 3496 struct ifnet *ifp; 3497 struct txdmamap_pool_entry *dma; 3498 bus_addr_t offset, toff; 3499 bus_size_t tlen; 3500 int tosync; 3501 struct mbuf *m; 3502 3503 ifp = &sc->ethercom.ec_if; 3504 3505 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3506 offsetof(struct bge_ring_data, bge_status_block), 3507 sizeof (struct bge_status_block), 3508 BUS_DMASYNC_POSTREAD); 3509 3510 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3511 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3512 sc->bge_tx_saved_considx; 3513 3514 #if NRND > 0 3515 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3516 rnd_add_uint32(&sc->rnd_source, tosync); 3517 #endif 3518 3519 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3520 3521 if (tosync < 0) { 3522 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3523 sizeof (struct bge_tx_bd); 3524 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3525 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3526 tosync = -tosync; 3527 } 3528 3529 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3530 offset, tosync * sizeof (struct bge_tx_bd), 3531 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3532 3533 /* 3534 * Go through our tx ring and free mbufs for those 3535 * frames that have been sent. 3536 */ 3537 while (sc->bge_tx_saved_considx != 3538 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3539 uint32_t idx = 0; 3540 3541 idx = sc->bge_tx_saved_considx; 3542 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3543 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3544 ifp->if_opackets++; 3545 m = sc->bge_cdata.bge_tx_chain[idx]; 3546 if (m != NULL) { 3547 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3548 dma = sc->txdma[idx]; 3549 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3550 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3551 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3552 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3553 sc->txdma[idx] = NULL; 3554 3555 m_freem(m); 3556 } 3557 sc->bge_txcnt--; 3558 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3559 ifp->if_timer = 0; 3560 } 3561 3562 if (cur_tx != NULL) 3563 ifp->if_flags &= ~IFF_OACTIVE; 3564 } 3565 3566 static int 3567 bge_intr(void *xsc) 3568 { 3569 struct bge_softc *sc; 3570 struct ifnet *ifp; 3571 uint32_t statusword; 3572 3573 sc = xsc; 3574 ifp = &sc->ethercom.ec_if; 3575 3576 /* It is possible for the interrupt to arrive before 3577 * the status block is updated prior to the interrupt. 3578 * Reading the PCI State register will confirm whether the 3579 * interrupt is ours and will flush the status block. 3580 */ 3581 3582 /* read status word from status block */ 3583 statusword = sc->bge_rdata->bge_status_block.bge_status; 3584 3585 if ((statusword & BGE_STATFLAG_UPDATED) || 3586 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3587 /* Ack interrupt and stop others from occuring. */ 3588 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3589 3590 BGE_EVCNT_INCR(sc->bge_ev_intr); 3591 3592 /* clear status word */ 3593 sc->bge_rdata->bge_status_block.bge_status = 0; 3594 3595 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3596 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3597 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3598 bge_link_upd(sc); 3599 3600 if (ifp->if_flags & IFF_RUNNING) { 3601 /* Check RX return ring producer/consumer */ 3602 bge_rxeof(sc); 3603 3604 /* Check TX ring producer/consumer */ 3605 bge_txeof(sc); 3606 } 3607 3608 if (sc->bge_pending_rxintr_change) { 3609 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3610 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3611 uint32_t junk; 3612 3613 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3614 DELAY(10); 3615 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3616 3617 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3618 DELAY(10); 3619 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3620 3621 sc->bge_pending_rxintr_change = 0; 3622 } 3623 bge_handle_events(sc); 3624 3625 /* Re-enable interrupts. */ 3626 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3627 3628 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3629 bge_start(ifp); 3630 3631 return 1; 3632 } else 3633 return 0; 3634 } 3635 3636 static void 3637 bge_asf_driver_up(struct bge_softc *sc) 3638 { 3639 if (sc->bge_asf_mode & ASF_STACKUP) { 3640 /* Send ASF heartbeat aprox. every 2s */ 3641 if (sc->bge_asf_count) 3642 sc->bge_asf_count --; 3643 else { 3644 sc->bge_asf_count = 2; 3645 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3646 BGE_FW_DRV_ALIVE); 3647 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3648 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3649 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3650 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3651 } 3652 } 3653 } 3654 3655 static void 3656 bge_tick(void *xsc) 3657 { 3658 struct bge_softc *sc = xsc; 3659 struct mii_data *mii = &sc->bge_mii; 3660 int s; 3661 3662 s = splnet(); 3663 3664 if (BGE_IS_5705_PLUS(sc)) 3665 bge_stats_update_regs(sc); 3666 else 3667 bge_stats_update(sc); 3668 3669 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3670 /* 3671 * Since in TBI mode auto-polling can't be used we should poll 3672 * link status manually. Here we register pending link event 3673 * and trigger interrupt. 3674 */ 3675 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3676 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3677 } else { 3678 /* 3679 * Do not touch PHY if we have link up. This could break 3680 * IPMI/ASF mode or produce extra input errors. 3681 * (extra input errors was reported for bcm5701 & bcm5704). 3682 */ 3683 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3684 mii_tick(mii); 3685 } 3686 3687 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3688 3689 splx(s); 3690 } 3691 3692 static void 3693 bge_stats_update_regs(struct bge_softc *sc) 3694 { 3695 struct ifnet *ifp = &sc->ethercom.ec_if; 3696 3697 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3698 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3699 3700 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3701 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3702 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3703 } 3704 3705 static void 3706 bge_stats_update(struct bge_softc *sc) 3707 { 3708 struct ifnet *ifp = &sc->ethercom.ec_if; 3709 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3710 3711 #define READ_STAT(sc, stats, stat) \ 3712 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3713 3714 ifp->if_collisions += 3715 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3716 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3717 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3718 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3719 ifp->if_collisions; 3720 3721 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3722 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3723 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3724 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3725 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3726 READ_STAT(sc, stats, 3727 xoffPauseFramesReceived.bge_addr_lo)); 3728 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3729 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3730 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3731 READ_STAT(sc, stats, 3732 macControlFramesReceived.bge_addr_lo)); 3733 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3734 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3735 3736 #undef READ_STAT 3737 3738 #ifdef notdef 3739 ifp->if_collisions += 3740 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3741 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3742 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3743 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3744 ifp->if_collisions; 3745 #endif 3746 } 3747 3748 /* 3749 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3750 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3751 * but when such padded frames employ the bge IP/TCP checksum offload, 3752 * the hardware checksum assist gives incorrect results (possibly 3753 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3754 * If we pad such runts with zeros, the onboard checksum comes out correct. 3755 */ 3756 static inline int 3757 bge_cksum_pad(struct mbuf *pkt) 3758 { 3759 struct mbuf *last = NULL; 3760 int padlen; 3761 3762 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3763 3764 /* if there's only the packet-header and we can pad there, use it. */ 3765 if (pkt->m_pkthdr.len == pkt->m_len && 3766 M_TRAILINGSPACE(pkt) >= padlen) { 3767 last = pkt; 3768 } else { 3769 /* 3770 * Walk packet chain to find last mbuf. We will either 3771 * pad there, or append a new mbuf and pad it 3772 * (thus perhaps avoiding the bcm5700 dma-min bug). 3773 */ 3774 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3775 continue; /* do nothing */ 3776 } 3777 3778 /* `last' now points to last in chain. */ 3779 if (M_TRAILINGSPACE(last) < padlen) { 3780 /* Allocate new empty mbuf, pad it. Compact later. */ 3781 struct mbuf *n; 3782 MGET(n, M_DONTWAIT, MT_DATA); 3783 if (n == NULL) 3784 return ENOBUFS; 3785 n->m_len = 0; 3786 last->m_next = n; 3787 last = n; 3788 } 3789 } 3790 3791 KDASSERT(!M_READONLY(last)); 3792 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3793 3794 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3795 memset(mtod(last, char *) + last->m_len, 0, padlen); 3796 last->m_len += padlen; 3797 pkt->m_pkthdr.len += padlen; 3798 return 0; 3799 } 3800 3801 /* 3802 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3803 */ 3804 static inline int 3805 bge_compact_dma_runt(struct mbuf *pkt) 3806 { 3807 struct mbuf *m, *prev; 3808 int totlen, prevlen; 3809 3810 prev = NULL; 3811 totlen = 0; 3812 prevlen = -1; 3813 3814 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3815 int mlen = m->m_len; 3816 int shortfall = 8 - mlen ; 3817 3818 totlen += mlen; 3819 if (mlen == 0) { 3820 continue; 3821 } 3822 if (mlen >= 8) 3823 continue; 3824 3825 /* If we get here, mbuf data is too small for DMA engine. 3826 * Try to fix by shuffling data to prev or next in chain. 3827 * If that fails, do a compacting deep-copy of the whole chain. 3828 */ 3829 3830 /* Internal frag. If fits in prev, copy it there. */ 3831 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3832 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3833 prev->m_len += mlen; 3834 m->m_len = 0; 3835 /* XXX stitch chain */ 3836 prev->m_next = m_free(m); 3837 m = prev; 3838 continue; 3839 } 3840 else if (m->m_next != NULL && 3841 M_TRAILINGSPACE(m) >= shortfall && 3842 m->m_next->m_len >= (8 + shortfall)) { 3843 /* m is writable and have enough data in next, pull up. */ 3844 3845 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3846 shortfall); 3847 m->m_len += shortfall; 3848 m->m_next->m_len -= shortfall; 3849 m->m_next->m_data += shortfall; 3850 } 3851 else if (m->m_next == NULL || 1) { 3852 /* Got a runt at the very end of the packet. 3853 * borrow data from the tail of the preceding mbuf and 3854 * update its length in-place. (The original data is still 3855 * valid, so we can do this even if prev is not writable.) 3856 */ 3857 3858 /* if we'd make prev a runt, just move all of its data. */ 3859 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3860 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3861 3862 if ((prev->m_len - shortfall) < 8) 3863 shortfall = prev->m_len; 3864 3865 #ifdef notyet /* just do the safe slow thing for now */ 3866 if (!M_READONLY(m)) { 3867 if (M_LEADINGSPACE(m) < shorfall) { 3868 void *m_dat; 3869 m_dat = (m->m_flags & M_PKTHDR) ? 3870 m->m_pktdat : m->dat; 3871 memmove(m_dat, mtod(m, void*), m->m_len); 3872 m->m_data = m_dat; 3873 } 3874 } else 3875 #endif /* just do the safe slow thing */ 3876 { 3877 struct mbuf * n = NULL; 3878 int newprevlen = prev->m_len - shortfall; 3879 3880 MGET(n, M_NOWAIT, MT_DATA); 3881 if (n == NULL) 3882 return ENOBUFS; 3883 KASSERT(m->m_len + shortfall < MLEN 3884 /*, 3885 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3886 3887 /* first copy the data we're stealing from prev */ 3888 memcpy(n->m_data, prev->m_data + newprevlen, 3889 shortfall); 3890 3891 /* update prev->m_len accordingly */ 3892 prev->m_len -= shortfall; 3893 3894 /* copy data from runt m */ 3895 memcpy(n->m_data + shortfall, m->m_data, 3896 m->m_len); 3897 3898 /* n holds what we stole from prev, plus m */ 3899 n->m_len = shortfall + m->m_len; 3900 3901 /* stitch n into chain and free m */ 3902 n->m_next = m->m_next; 3903 prev->m_next = n; 3904 /* KASSERT(m->m_next == NULL); */ 3905 m->m_next = NULL; 3906 m_free(m); 3907 m = n; /* for continuing loop */ 3908 } 3909 } 3910 prevlen = m->m_len; 3911 } 3912 return 0; 3913 } 3914 3915 /* 3916 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3917 * pointers to descriptors. 3918 */ 3919 static int 3920 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3921 { 3922 struct bge_tx_bd *f = NULL; 3923 uint32_t frag, cur; 3924 uint16_t csum_flags = 0; 3925 uint16_t txbd_tso_flags = 0; 3926 struct txdmamap_pool_entry *dma; 3927 bus_dmamap_t dmamap; 3928 int i = 0; 3929 struct m_tag *mtag; 3930 int use_tso, maxsegsize, error; 3931 3932 cur = frag = *txidx; 3933 3934 if (m_head->m_pkthdr.csum_flags) { 3935 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3936 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3937 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3938 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3939 } 3940 3941 /* 3942 * If we were asked to do an outboard checksum, and the NIC 3943 * has the bug where it sometimes adds in the Ethernet padding, 3944 * explicitly pad with zeros so the cksum will be correct either way. 3945 * (For now, do this for all chip versions, until newer 3946 * are confirmed to not require the workaround.) 3947 */ 3948 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3949 #ifdef notyet 3950 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3951 #endif 3952 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3953 goto check_dma_bug; 3954 3955 if (bge_cksum_pad(m_head) != 0) 3956 return ENOBUFS; 3957 3958 check_dma_bug: 3959 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3960 goto doit; 3961 3962 /* 3963 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3964 * less than eight bytes. If we encounter a teeny mbuf 3965 * at the end of a chain, we can pad. Otherwise, copy. 3966 */ 3967 if (bge_compact_dma_runt(m_head) != 0) 3968 return ENOBUFS; 3969 3970 doit: 3971 dma = SLIST_FIRST(&sc->txdma_list); 3972 if (dma == NULL) 3973 return ENOBUFS; 3974 dmamap = dma->dmamap; 3975 3976 /* 3977 * Set up any necessary TSO state before we start packing... 3978 */ 3979 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3980 if (!use_tso) { 3981 maxsegsize = 0; 3982 } else { /* TSO setup */ 3983 unsigned mss; 3984 struct ether_header *eh; 3985 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3986 struct mbuf * m0 = m_head; 3987 struct ip *ip; 3988 struct tcphdr *th; 3989 int iphl, hlen; 3990 3991 /* 3992 * XXX It would be nice if the mbuf pkthdr had offset 3993 * fields for the protocol headers. 3994 */ 3995 3996 eh = mtod(m0, struct ether_header *); 3997 switch (htons(eh->ether_type)) { 3998 case ETHERTYPE_IP: 3999 offset = ETHER_HDR_LEN; 4000 break; 4001 4002 case ETHERTYPE_VLAN: 4003 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4004 break; 4005 4006 default: 4007 /* 4008 * Don't support this protocol or encapsulation. 4009 */ 4010 return ENOBUFS; 4011 } 4012 4013 /* 4014 * TCP/IP headers are in the first mbuf; we can do 4015 * this the easy way. 4016 */ 4017 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 4018 hlen = iphl + offset; 4019 if (__predict_false(m0->m_len < 4020 (hlen + sizeof(struct tcphdr)))) { 4021 4022 aprint_debug_dev(sc->bge_dev, 4023 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 4024 "not handled yet\n", 4025 m0->m_len, hlen+ sizeof(struct tcphdr)); 4026 #ifdef NOTYET 4027 /* 4028 * XXX jonathan@NetBSD.org: untested. 4029 * how to force this branch to be taken? 4030 */ 4031 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4032 4033 m_copydata(m0, offset, sizeof(ip), &ip); 4034 m_copydata(m0, hlen, sizeof(th), &th); 4035 4036 ip.ip_len = 0; 4037 4038 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4039 sizeof(ip.ip_len), &ip.ip_len); 4040 4041 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4042 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4043 4044 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4045 sizeof(th.th_sum), &th.th_sum); 4046 4047 hlen += th.th_off << 2; 4048 iptcp_opt_words = hlen; 4049 #else 4050 /* 4051 * if_wm "hard" case not yet supported, can we not 4052 * mandate it out of existence? 4053 */ 4054 (void) ip; (void)th; (void) ip_tcp_hlen; 4055 4056 return ENOBUFS; 4057 #endif 4058 } else { 4059 ip = (struct ip *) (mtod(m0, char *) + offset); 4060 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4061 ip_tcp_hlen = iphl + (th->th_off << 2); 4062 4063 /* Total IP/TCP options, in 32-bit words */ 4064 iptcp_opt_words = (ip_tcp_hlen 4065 - sizeof(struct tcphdr) 4066 - sizeof(struct ip)) >> 2; 4067 } 4068 if (BGE_IS_5750_OR_BEYOND(sc)) { 4069 th->th_sum = 0; 4070 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4071 } else { 4072 /* 4073 * XXX jonathan@NetBSD.org: 5705 untested. 4074 * Requires TSO firmware patch for 5701/5703/5704. 4075 */ 4076 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4077 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4078 } 4079 4080 mss = m_head->m_pkthdr.segsz; 4081 txbd_tso_flags |= 4082 BGE_TXBDFLAG_CPU_PRE_DMA | 4083 BGE_TXBDFLAG_CPU_POST_DMA; 4084 4085 /* 4086 * Our NIC TSO-assist assumes TSO has standard, optionless 4087 * IPv4 and TCP headers, which total 40 bytes. By default, 4088 * the NIC copies 40 bytes of IP/TCP header from the 4089 * supplied header into the IP/TCP header portion of 4090 * each post-TSO-segment. If the supplied packet has IP or 4091 * TCP options, we need to tell the NIC to copy those extra 4092 * bytes into each post-TSO header, in addition to the normal 4093 * 40-byte IP/TCP header (and to leave space accordingly). 4094 * Unfortunately, the driver encoding of option length 4095 * varies across different ASIC families. 4096 */ 4097 tcp_seg_flags = 0; 4098 if (iptcp_opt_words) { 4099 if (BGE_IS_5705_PLUS(sc)) { 4100 tcp_seg_flags = 4101 iptcp_opt_words << 11; 4102 } else { 4103 txbd_tso_flags |= 4104 iptcp_opt_words << 12; 4105 } 4106 } 4107 maxsegsize = mss | tcp_seg_flags; 4108 ip->ip_len = htons(mss + ip_tcp_hlen); 4109 4110 } /* TSO setup */ 4111 4112 /* 4113 * Start packing the mbufs in this chain into 4114 * the fragment pointers. Stop when we run out 4115 * of fragments or hit the end of the mbuf chain. 4116 */ 4117 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4118 BUS_DMA_NOWAIT); 4119 if (error) 4120 return ENOBUFS; 4121 /* 4122 * Sanity check: avoid coming within 16 descriptors 4123 * of the end of the ring. 4124 */ 4125 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4126 BGE_TSO_PRINTF(("%s: " 4127 " dmamap_load_mbuf too close to ring wrap\n", 4128 device_xname(sc->bge_dev))); 4129 goto fail_unload; 4130 } 4131 4132 mtag = sc->ethercom.ec_nvlans ? 4133 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4134 4135 4136 /* Iterate over dmap-map fragments. */ 4137 for (i = 0; i < dmamap->dm_nsegs; i++) { 4138 f = &sc->bge_rdata->bge_tx_ring[frag]; 4139 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4140 break; 4141 4142 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4143 f->bge_len = dmamap->dm_segs[i].ds_len; 4144 4145 /* 4146 * For 5751 and follow-ons, for TSO we must turn 4147 * off checksum-assist flag in the tx-descr, and 4148 * supply the ASIC-revision-specific encoding 4149 * of TSO flags and segsize. 4150 */ 4151 if (use_tso) { 4152 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 4153 f->bge_rsvd = maxsegsize; 4154 f->bge_flags = csum_flags | txbd_tso_flags; 4155 } else { 4156 f->bge_rsvd = 0; 4157 f->bge_flags = 4158 (csum_flags | txbd_tso_flags) & 0x0fff; 4159 } 4160 } else { 4161 f->bge_rsvd = 0; 4162 f->bge_flags = csum_flags; 4163 } 4164 4165 if (mtag != NULL) { 4166 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4167 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4168 } else { 4169 f->bge_vlan_tag = 0; 4170 } 4171 cur = frag; 4172 BGE_INC(frag, BGE_TX_RING_CNT); 4173 } 4174 4175 if (i < dmamap->dm_nsegs) { 4176 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4177 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4178 goto fail_unload; 4179 } 4180 4181 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4182 BUS_DMASYNC_PREWRITE); 4183 4184 if (frag == sc->bge_tx_saved_considx) { 4185 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4186 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4187 4188 goto fail_unload; 4189 } 4190 4191 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4192 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4193 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4194 sc->txdma[cur] = dma; 4195 sc->bge_txcnt += dmamap->dm_nsegs; 4196 4197 *txidx = frag; 4198 4199 return 0; 4200 4201 fail_unload: 4202 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4203 4204 return ENOBUFS; 4205 } 4206 4207 /* 4208 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4209 * to the mbuf data regions directly in the transmit descriptors. 4210 */ 4211 static void 4212 bge_start(struct ifnet *ifp) 4213 { 4214 struct bge_softc *sc; 4215 struct mbuf *m_head = NULL; 4216 uint32_t prodidx; 4217 int pkts = 0; 4218 4219 sc = ifp->if_softc; 4220 4221 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4222 return; 4223 4224 prodidx = sc->bge_tx_prodidx; 4225 4226 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4227 IFQ_POLL(&ifp->if_snd, m_head); 4228 if (m_head == NULL) 4229 break; 4230 4231 #if 0 4232 /* 4233 * XXX 4234 * safety overkill. If this is a fragmented packet chain 4235 * with delayed TCP/UDP checksums, then only encapsulate 4236 * it if we have enough descriptors to handle the entire 4237 * chain at once. 4238 * (paranoia -- may not actually be needed) 4239 */ 4240 if (m_head->m_flags & M_FIRSTFRAG && 4241 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4242 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4243 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4244 ifp->if_flags |= IFF_OACTIVE; 4245 break; 4246 } 4247 } 4248 #endif 4249 4250 /* 4251 * Pack the data into the transmit ring. If we 4252 * don't have room, set the OACTIVE flag and wait 4253 * for the NIC to drain the ring. 4254 */ 4255 if (bge_encap(sc, m_head, &prodidx)) { 4256 ifp->if_flags |= IFF_OACTIVE; 4257 break; 4258 } 4259 4260 /* now we are committed to transmit the packet */ 4261 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4262 pkts++; 4263 4264 /* 4265 * If there's a BPF listener, bounce a copy of this frame 4266 * to him. 4267 */ 4268 bpf_mtap(ifp, m_head); 4269 } 4270 if (pkts == 0) 4271 return; 4272 4273 /* Transmit */ 4274 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4275 /* 5700 b2 errata */ 4276 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4277 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4278 4279 sc->bge_tx_prodidx = prodidx; 4280 4281 /* 4282 * Set a timeout in case the chip goes out to lunch. 4283 */ 4284 ifp->if_timer = 5; 4285 } 4286 4287 static int 4288 bge_init(struct ifnet *ifp) 4289 { 4290 struct bge_softc *sc = ifp->if_softc; 4291 const uint16_t *m; 4292 int s, error = 0; 4293 4294 s = splnet(); 4295 4296 ifp = &sc->ethercom.ec_if; 4297 4298 /* Cancel pending I/O and flush buffers. */ 4299 bge_stop(ifp, 0); 4300 4301 bge_stop_fw(sc); 4302 bge_sig_pre_reset(sc, BGE_RESET_START); 4303 bge_reset(sc); 4304 bge_sig_legacy(sc, BGE_RESET_START); 4305 bge_sig_post_reset(sc, BGE_RESET_START); 4306 4307 bge_chipinit(sc); 4308 4309 /* 4310 * Init the various state machines, ring 4311 * control blocks and firmware. 4312 */ 4313 error = bge_blockinit(sc); 4314 if (error != 0) { 4315 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4316 error); 4317 splx(s); 4318 return error; 4319 } 4320 4321 ifp = &sc->ethercom.ec_if; 4322 4323 /* Specify MTU. */ 4324 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4325 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4326 4327 /* Load our MAC address. */ 4328 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4329 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4330 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4331 4332 /* Enable or disable promiscuous mode as needed. */ 4333 if (ifp->if_flags & IFF_PROMISC) 4334 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4335 else 4336 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4337 4338 /* Program multicast filter. */ 4339 bge_setmulti(sc); 4340 4341 /* Init RX ring. */ 4342 bge_init_rx_ring_std(sc); 4343 4344 /* 4345 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4346 * memory to insure that the chip has in fact read the first 4347 * entry of the ring. 4348 */ 4349 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4350 uint32_t v, i; 4351 for (i = 0; i < 10; i++) { 4352 DELAY(20); 4353 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4354 if (v == (MCLBYTES - ETHER_ALIGN)) 4355 break; 4356 } 4357 if (i == 10) 4358 aprint_error_dev(sc->bge_dev, 4359 "5705 A0 chip failed to load RX ring\n"); 4360 } 4361 4362 /* Init jumbo RX ring. */ 4363 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4364 bge_init_rx_ring_jumbo(sc); 4365 4366 /* Init our RX return ring index */ 4367 sc->bge_rx_saved_considx = 0; 4368 4369 /* Init TX ring. */ 4370 bge_init_tx_ring(sc); 4371 4372 /* Turn on transmitter */ 4373 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4374 4375 /* Turn on receiver */ 4376 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4377 4378 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4379 4380 /* Tell firmware we're alive. */ 4381 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4382 4383 /* Enable host interrupts. */ 4384 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4385 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4386 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4387 4388 if ((error = bge_ifmedia_upd(ifp)) != 0) 4389 goto out; 4390 4391 ifp->if_flags |= IFF_RUNNING; 4392 ifp->if_flags &= ~IFF_OACTIVE; 4393 4394 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4395 4396 out: 4397 sc->bge_if_flags = ifp->if_flags; 4398 splx(s); 4399 4400 return error; 4401 } 4402 4403 /* 4404 * Set media options. 4405 */ 4406 static int 4407 bge_ifmedia_upd(struct ifnet *ifp) 4408 { 4409 struct bge_softc *sc = ifp->if_softc; 4410 struct mii_data *mii = &sc->bge_mii; 4411 struct ifmedia *ifm = &sc->bge_ifmedia; 4412 int rc; 4413 4414 /* If this is a 1000baseX NIC, enable the TBI port. */ 4415 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4416 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4417 return EINVAL; 4418 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4419 case IFM_AUTO: 4420 /* 4421 * The BCM5704 ASIC appears to have a special 4422 * mechanism for programming the autoneg 4423 * advertisement registers in TBI mode. 4424 */ 4425 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4426 uint32_t sgdig; 4427 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4428 if (sgdig & BGE_SGDIGSTS_DONE) { 4429 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4430 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4431 sgdig |= BGE_SGDIGCFG_AUTO | 4432 BGE_SGDIGCFG_PAUSE_CAP | 4433 BGE_SGDIGCFG_ASYM_PAUSE; 4434 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4435 sgdig | BGE_SGDIGCFG_SEND); 4436 DELAY(5); 4437 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4438 } 4439 } 4440 break; 4441 case IFM_1000_SX: 4442 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4443 BGE_CLRBIT(sc, BGE_MAC_MODE, 4444 BGE_MACMODE_HALF_DUPLEX); 4445 } else { 4446 BGE_SETBIT(sc, BGE_MAC_MODE, 4447 BGE_MACMODE_HALF_DUPLEX); 4448 } 4449 break; 4450 default: 4451 return EINVAL; 4452 } 4453 /* XXX 802.3x flow control for 1000BASE-SX */ 4454 return 0; 4455 } 4456 4457 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4458 if ((rc = mii_mediachg(mii)) == ENXIO) 4459 return 0; 4460 4461 /* 4462 * Force an interrupt so that we will call bge_link_upd 4463 * if needed and clear any pending link state attention. 4464 * Without this we are not getting any further interrupts 4465 * for link state changes and thus will not UP the link and 4466 * not be able to send in bge_start. The only way to get 4467 * things working was to receive a packet and get a RX intr. 4468 */ 4469 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4470 sc->bge_flags & BGE_IS_5788) 4471 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4472 else 4473 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4474 4475 return rc; 4476 } 4477 4478 /* 4479 * Report current media status. 4480 */ 4481 static void 4482 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4483 { 4484 struct bge_softc *sc = ifp->if_softc; 4485 struct mii_data *mii = &sc->bge_mii; 4486 4487 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4488 ifmr->ifm_status = IFM_AVALID; 4489 ifmr->ifm_active = IFM_ETHER; 4490 if (CSR_READ_4(sc, BGE_MAC_STS) & 4491 BGE_MACSTAT_TBI_PCS_SYNCHED) 4492 ifmr->ifm_status |= IFM_ACTIVE; 4493 ifmr->ifm_active |= IFM_1000_SX; 4494 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4495 ifmr->ifm_active |= IFM_HDX; 4496 else 4497 ifmr->ifm_active |= IFM_FDX; 4498 return; 4499 } 4500 4501 mii_pollstat(mii); 4502 ifmr->ifm_status = mii->mii_media_status; 4503 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4504 sc->bge_flowflags; 4505 } 4506 4507 static int 4508 bge_ifflags_cb(struct ethercom *ec) 4509 { 4510 struct ifnet *ifp = &ec->ec_if; 4511 struct bge_softc *sc = ifp->if_softc; 4512 int change = ifp->if_flags ^ sc->bge_if_flags; 4513 4514 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 4515 return ENETRESET; 4516 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 4517 return 0; 4518 4519 if ((ifp->if_flags & IFF_PROMISC) == 0) 4520 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4521 else 4522 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4523 4524 bge_setmulti(sc); 4525 4526 sc->bge_if_flags = ifp->if_flags; 4527 return 0; 4528 } 4529 4530 static int 4531 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4532 { 4533 struct bge_softc *sc = ifp->if_softc; 4534 struct ifreq *ifr = (struct ifreq *) data; 4535 int s, error = 0; 4536 struct mii_data *mii; 4537 4538 s = splnet(); 4539 4540 switch (command) { 4541 case SIOCSIFMEDIA: 4542 /* XXX Flow control is not supported for 1000BASE-SX */ 4543 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4544 ifr->ifr_media &= ~IFM_ETH_FMASK; 4545 sc->bge_flowflags = 0; 4546 } 4547 4548 /* Flow control requires full-duplex mode. */ 4549 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4550 (ifr->ifr_media & IFM_FDX) == 0) { 4551 ifr->ifr_media &= ~IFM_ETH_FMASK; 4552 } 4553 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4554 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4555 /* We can do both TXPAUSE and RXPAUSE. */ 4556 ifr->ifr_media |= 4557 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4558 } 4559 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4560 } 4561 /* FALLTHROUGH */ 4562 case SIOCGIFMEDIA: 4563 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4564 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4565 command); 4566 } else { 4567 mii = &sc->bge_mii; 4568 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4569 command); 4570 } 4571 break; 4572 default: 4573 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4574 break; 4575 4576 error = 0; 4577 4578 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4579 ; 4580 else if (ifp->if_flags & IFF_RUNNING) 4581 bge_setmulti(sc); 4582 break; 4583 } 4584 4585 splx(s); 4586 4587 return error; 4588 } 4589 4590 static void 4591 bge_watchdog(struct ifnet *ifp) 4592 { 4593 struct bge_softc *sc; 4594 4595 sc = ifp->if_softc; 4596 4597 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4598 4599 ifp->if_flags &= ~IFF_RUNNING; 4600 bge_init(ifp); 4601 4602 ifp->if_oerrors++; 4603 } 4604 4605 static void 4606 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4607 { 4608 int i; 4609 4610 BGE_CLRBIT(sc, reg, bit); 4611 4612 for (i = 0; i < 1000; i++) { 4613 if ((CSR_READ_4(sc, reg) & bit) == 0) 4614 return; 4615 delay(100); 4616 } 4617 4618 /* 4619 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4620 * on some environment (and once after boot?) 4621 */ 4622 if (reg != BGE_SRS_MODE) 4623 aprint_error_dev(sc->bge_dev, 4624 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4625 (u_long)reg, bit); 4626 } 4627 4628 /* 4629 * Stop the adapter and free any mbufs allocated to the 4630 * RX and TX lists. 4631 */ 4632 static void 4633 bge_stop(struct ifnet *ifp, int disable) 4634 { 4635 struct bge_softc *sc = ifp->if_softc; 4636 4637 callout_stop(&sc->bge_timeout); 4638 4639 /* 4640 * Tell firmware we're shutting down. 4641 */ 4642 bge_stop_fw(sc); 4643 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4644 4645 /* Disable host interrupts. */ 4646 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4647 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4648 4649 /* 4650 * Disable all of the receiver blocks 4651 */ 4652 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4653 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4654 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4655 if (BGE_IS_5700_FAMILY(sc)) 4656 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4657 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4658 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4659 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4660 4661 /* 4662 * Disable all of the transmit blocks 4663 */ 4664 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4665 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4666 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4667 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4668 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4669 if (BGE_IS_5700_FAMILY(sc)) 4670 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4671 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4672 4673 /* 4674 * Shut down all of the memory managers and related 4675 * state machines. 4676 */ 4677 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4678 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4679 if (BGE_IS_5700_FAMILY(sc)) 4680 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4681 4682 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4683 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4684 4685 if (BGE_IS_5700_FAMILY(sc)) { 4686 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4687 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4688 } 4689 4690 bge_reset(sc); 4691 bge_sig_legacy(sc, BGE_RESET_STOP); 4692 bge_sig_post_reset(sc, BGE_RESET_STOP); 4693 4694 /* 4695 * Keep the ASF firmware running if up. 4696 */ 4697 if (sc->bge_asf_mode & ASF_STACKUP) 4698 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4699 else 4700 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4701 4702 /* Free the RX lists. */ 4703 bge_free_rx_ring_std(sc); 4704 4705 /* Free jumbo RX list. */ 4706 if (BGE_IS_JUMBO_CAPABLE(sc)) 4707 bge_free_rx_ring_jumbo(sc); 4708 4709 /* Free TX buffers. */ 4710 bge_free_tx_ring(sc); 4711 4712 /* 4713 * Isolate/power down the PHY. 4714 */ 4715 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4716 mii_down(&sc->bge_mii); 4717 4718 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4719 4720 /* Clear MAC's link state (PHY may still have link UP). */ 4721 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4722 4723 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4724 } 4725 4726 static void 4727 bge_link_upd(struct bge_softc *sc) 4728 { 4729 struct ifnet *ifp = &sc->ethercom.ec_if; 4730 struct mii_data *mii = &sc->bge_mii; 4731 uint32_t status; 4732 int link; 4733 4734 /* Clear 'pending link event' flag */ 4735 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4736 4737 /* 4738 * Process link state changes. 4739 * Grrr. The link status word in the status block does 4740 * not work correctly on the BCM5700 rev AX and BX chips, 4741 * according to all available information. Hence, we have 4742 * to enable MII interrupts in order to properly obtain 4743 * async link changes. Unfortunately, this also means that 4744 * we have to read the MAC status register to detect link 4745 * changes, thereby adding an additional register access to 4746 * the interrupt handler. 4747 */ 4748 4749 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4750 status = CSR_READ_4(sc, BGE_MAC_STS); 4751 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4752 mii_pollstat(mii); 4753 4754 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4755 mii->mii_media_status & IFM_ACTIVE && 4756 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4757 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4758 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4759 (!(mii->mii_media_status & IFM_ACTIVE) || 4760 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4761 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4762 4763 /* Clear the interrupt */ 4764 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4765 BGE_EVTENB_MI_INTERRUPT); 4766 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4767 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4768 BRGPHY_INTRS); 4769 } 4770 return; 4771 } 4772 4773 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4774 status = CSR_READ_4(sc, BGE_MAC_STS); 4775 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4776 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4777 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4778 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4779 BGE_CLRBIT(sc, BGE_MAC_MODE, 4780 BGE_MACMODE_TBI_SEND_CFGS); 4781 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4782 if_link_state_change(ifp, LINK_STATE_UP); 4783 } 4784 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4785 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4786 if_link_state_change(ifp, LINK_STATE_DOWN); 4787 } 4788 /* 4789 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4790 * This should not happen since mii callouts are locked now, but 4791 * we keep this check for debug. 4792 */ 4793 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4794 /* 4795 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4796 * bit in status word always set. Workaround this bug by 4797 * reading PHY link status directly. 4798 */ 4799 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4800 BGE_STS_LINK : 0; 4801 4802 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4803 mii_pollstat(mii); 4804 4805 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4806 mii->mii_media_status & IFM_ACTIVE && 4807 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4808 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4809 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4810 (!(mii->mii_media_status & IFM_ACTIVE) || 4811 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4812 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4813 } 4814 } 4815 4816 /* Clear the attention */ 4817 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4818 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4819 BGE_MACSTAT_LINK_CHANGED); 4820 } 4821 4822 static int 4823 sysctl_bge_verify(SYSCTLFN_ARGS) 4824 { 4825 int error, t; 4826 struct sysctlnode node; 4827 4828 node = *rnode; 4829 t = *(int*)rnode->sysctl_data; 4830 node.sysctl_data = &t; 4831 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4832 if (error || newp == NULL) 4833 return error; 4834 4835 #if 0 4836 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4837 node.sysctl_num, rnode->sysctl_num)); 4838 #endif 4839 4840 if (node.sysctl_num == bge_rxthresh_nodenum) { 4841 if (t < 0 || t >= NBGE_RX_THRESH) 4842 return EINVAL; 4843 bge_update_all_threshes(t); 4844 } else 4845 return EINVAL; 4846 4847 *(int*)rnode->sysctl_data = t; 4848 4849 return 0; 4850 } 4851 4852 /* 4853 * Set up sysctl(3) MIB, hw.bge.*. 4854 */ 4855 static void 4856 sysctl_bge_init(struct bge_softc *sc) 4857 { 4858 int rc, bge_root_num; 4859 const struct sysctlnode *node; 4860 4861 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, NULL, 4862 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4863 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4864 goto err; 4865 } 4866 4867 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4868 0, CTLTYPE_NODE, "bge", 4869 SYSCTL_DESCR("BGE interface controls"), 4870 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4871 goto err; 4872 } 4873 4874 bge_root_num = node->sysctl_num; 4875 4876 /* BGE Rx interrupt mitigation level */ 4877 if ((rc = sysctl_createv(&sc->bge_log, 0, NULL, &node, 4878 CTLFLAG_READWRITE, 4879 CTLTYPE_INT, "rx_lvl", 4880 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4881 sysctl_bge_verify, 0, 4882 &bge_rx_thresh_lvl, 4883 0, CTL_HW, bge_root_num, CTL_CREATE, 4884 CTL_EOL)) != 0) { 4885 goto err; 4886 } 4887 4888 bge_rxthresh_nodenum = node->sysctl_num; 4889 4890 return; 4891 4892 err: 4893 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4894 } 4895 4896 #ifdef BGE_DEBUG 4897 void 4898 bge_debug_info(struct bge_softc *sc) 4899 { 4900 4901 printf("Hardware Flags:\n"); 4902 if (BGE_IS_5755_PLUS(sc)) 4903 printf(" - 5755 Plus\n"); 4904 if (BGE_IS_5750_OR_BEYOND(sc)) 4905 printf(" - 5750 Plus\n"); 4906 if (BGE_IS_5705_PLUS(sc)) 4907 printf(" - 5705 Plus\n"); 4908 if (BGE_IS_5714_FAMILY(sc)) 4909 printf(" - 5714 Family\n"); 4910 if (BGE_IS_5700_FAMILY(sc)) 4911 printf(" - 5700 Family\n"); 4912 if (sc->bge_flags & BGE_IS_5788) 4913 printf(" - 5788\n"); 4914 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4915 printf(" - Supports Jumbo Frames\n"); 4916 if (sc->bge_flags & BGE_NO_EEPROM) 4917 printf(" - No EEPROM\n"); 4918 if (sc->bge_flags & BGE_PCIX) 4919 printf(" - PCI-X Bus\n"); 4920 if (sc->bge_flags & BGE_PCIE) 4921 printf(" - PCI Express Bus\n"); 4922 if (sc->bge_flags & BGE_NO_3LED) 4923 printf(" - No 3 LEDs\n"); 4924 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4925 printf(" - RX Alignment Bug\n"); 4926 if (sc->bge_flags & BGE_TSO) 4927 printf(" - TSO\n"); 4928 } 4929 #endif /* BGE_DEBUG */ 4930 4931 static int 4932 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4933 { 4934 prop_dictionary_t dict; 4935 prop_data_t ea; 4936 4937 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4938 return 1; 4939 4940 dict = device_properties(sc->bge_dev); 4941 ea = prop_dictionary_get(dict, "mac-address"); 4942 if (ea != NULL) { 4943 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4944 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4945 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4946 return 0; 4947 } 4948 4949 return 1; 4950 } 4951 4952 static int 4953 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4954 { 4955 uint32_t mac_addr; 4956 4957 mac_addr = bge_readmem_ind(sc, 0x0c14); 4958 if ((mac_addr >> 16) == 0x484b) { 4959 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4960 ether_addr[1] = (uint8_t)mac_addr; 4961 mac_addr = bge_readmem_ind(sc, 0x0c18); 4962 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4963 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4964 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4965 ether_addr[5] = (uint8_t)mac_addr; 4966 return 0; 4967 } 4968 return 1; 4969 } 4970 4971 static int 4972 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4973 { 4974 int mac_offset = BGE_EE_MAC_OFFSET; 4975 4976 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4977 mac_offset = BGE_EE_MAC_OFFSET_5906; 4978 4979 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4980 ETHER_ADDR_LEN)); 4981 } 4982 4983 static int 4984 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4985 { 4986 4987 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4988 return 1; 4989 4990 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4991 ETHER_ADDR_LEN)); 4992 } 4993 4994 static int 4995 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4996 { 4997 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4998 /* NOTE: Order is critical */ 4999 bge_get_eaddr_fw, 5000 bge_get_eaddr_mem, 5001 bge_get_eaddr_nvram, 5002 bge_get_eaddr_eeprom, 5003 NULL 5004 }; 5005 const bge_eaddr_fcn_t *func; 5006 5007 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5008 if ((*func)(sc, eaddr) == 0) 5009 break; 5010 } 5011 return (*func == NULL ? ENXIO : 0); 5012 } 5013