1 /* $NetBSD: if_bge.c,v 1.90 2005/06/20 02:49:18 atatat Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl@wasabisystems.com> 44 * Jason Thorpe <thorpej@wasabisystems.com> 45 * Jonathan Stone <jonathan@dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul@windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.90 2005/06/20 02:49:18 atatat Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/in_systm.h> 106 #include <netinet/in_var.h> 107 #include <netinet/ip.h> 108 #endif 109 110 #if NBPFILTER > 0 111 #include <net/bpf.h> 112 #endif 113 114 #include <dev/pci/pcireg.h> 115 #include <dev/pci/pcivar.h> 116 #include <dev/pci/pcidevs.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 #include <dev/mii/miidevs.h> 121 #include <dev/mii/brgphyreg.h> 122 123 #include <dev/pci/if_bgereg.h> 124 125 #include <uvm/uvm_extern.h> 126 127 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 128 129 130 /* 131 * Tunable thresholds for rx-side bge interrupt mitigation. 132 */ 133 134 /* 135 * The pairs of values below were obtained from empirical measurement 136 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 137 * interrupt for every N packets received, where N is, approximately, 138 * the second value (rx_max_bds) in each pair. The values are chosen 139 * such that moving from one pair to the succeeding pair was observed 140 * to roughly halve interrupt rate under sustained input packet load. 141 * The values were empirically chosen to avoid overflowing internal 142 * limits on the bcm5700: inreasing rx_ticks much beyond 600 143 * results in internal wrapping and higher interrupt rates. 144 * The limit of 46 frames was chosen to match NFS workloads. 145 * 146 * These values also work well on bcm5701, bcm5704C, and (less 147 * tested) bcm5703. On other chipsets, (including the Altima chip 148 * family), the larger values may overflow internal chip limits, 149 * leading to increasing interrupt rates rather than lower interrupt 150 * rates. 151 * 152 * Applications using heavy interrupt mitigation (interrupting every 153 * 32 or 46 frames) in both directions may need to increase the TCP 154 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 155 * full link bandwidth, due to ACKs and window updates lingering 156 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 157 */ 158 struct bge_load_rx_thresh { 159 int rx_ticks; 160 int rx_max_bds; } 161 bge_rx_threshes[] = { 162 { 32, 2 }, 163 { 50, 4 }, 164 { 100, 8 }, 165 { 192, 16 }, 166 { 416, 32 }, 167 { 598, 46 } 168 }; 169 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 170 171 /* XXX patchable; should be sysctl'able */ 172 static int bge_auto_thresh = 1; 173 static int bge_rx_thresh_lvl; 174 175 #ifdef __NetBSD__ 176 static int bge_rxthresh_nodenum; 177 #endif /* __NetBSD__ */ 178 179 int bge_probe(struct device *, struct cfdata *, void *); 180 void bge_attach(struct device *, struct device *, void *); 181 void bge_powerhook(int, void *); 182 void bge_release_resources(struct bge_softc *); 183 void bge_txeof(struct bge_softc *); 184 void bge_rxeof(struct bge_softc *); 185 186 void bge_tick(void *); 187 void bge_stats_update(struct bge_softc *); 188 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 189 static __inline int bge_cksum_pad(struct mbuf *pkt); 190 static __inline int bge_compact_dma_runt(struct mbuf *pkt); 191 192 int bge_intr(void *); 193 void bge_start(struct ifnet *); 194 int bge_ioctl(struct ifnet *, u_long, caddr_t); 195 int bge_init(struct ifnet *); 196 void bge_stop(struct bge_softc *); 197 void bge_watchdog(struct ifnet *); 198 void bge_shutdown(void *); 199 int bge_ifmedia_upd(struct ifnet *); 200 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 201 202 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 203 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 204 205 void bge_setmulti(struct bge_softc *); 206 207 void bge_handle_events(struct bge_softc *); 208 int bge_alloc_jumbo_mem(struct bge_softc *); 209 void bge_free_jumbo_mem(struct bge_softc *); 210 void *bge_jalloc(struct bge_softc *); 211 void bge_jfree(struct mbuf *, caddr_t, size_t, void *); 212 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t); 213 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 214 int bge_init_rx_ring_std(struct bge_softc *); 215 void bge_free_rx_ring_std(struct bge_softc *); 216 int bge_init_rx_ring_jumbo(struct bge_softc *); 217 void bge_free_rx_ring_jumbo(struct bge_softc *); 218 void bge_free_tx_ring(struct bge_softc *); 219 int bge_init_tx_ring(struct bge_softc *); 220 221 int bge_chipinit(struct bge_softc *); 222 int bge_blockinit(struct bge_softc *); 223 int bge_setpowerstate(struct bge_softc *, int); 224 225 #ifdef notdef 226 u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 227 void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, int); 228 void bge_vpd_read(struct bge_softc *); 229 #endif 230 231 u_int32_t bge_readmem_ind(struct bge_softc *, int); 232 void bge_writemem_ind(struct bge_softc *, int, int); 233 #ifdef notdef 234 u_int32_t bge_readreg_ind(struct bge_softc *, int); 235 #endif 236 void bge_writereg_ind(struct bge_softc *, int, int); 237 238 int bge_miibus_readreg(struct device *, int, int); 239 void bge_miibus_writereg(struct device *, int, int, int); 240 void bge_miibus_statchg(struct device *); 241 242 void bge_reset(struct bge_softc *); 243 244 void bge_set_thresh(struct ifnet * /*ifp*/, int /*lvl*/); 245 void bge_update_all_threshes(int /*lvl*/); 246 247 void bge_dump_status(struct bge_softc *); 248 void bge_dump_rxbd(struct bge_rx_bd *); 249 250 #define BGE_DEBUG 251 #ifdef BGE_DEBUG 252 #define DPRINTF(x) if (bgedebug) printf x 253 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 254 int bgedebug = 0; 255 #else 256 #define DPRINTF(x) 257 #define DPRINTFN(n,x) 258 #endif 259 260 #ifdef BGE_EVENT_COUNTERS 261 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 262 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 263 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 264 #else 265 #define BGE_EVCNT_INCR(ev) /* nothing */ 266 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 267 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 268 #endif 269 270 /* Various chip quirks. */ 271 #define BGE_QUIRK_LINK_STATE_BROKEN 0x00000001 272 #define BGE_QUIRK_CSUM_BROKEN 0x00000002 273 #define BGE_QUIRK_ONLY_PHY_1 0x00000004 274 #define BGE_QUIRK_5700_SMALLDMA 0x00000008 275 #define BGE_QUIRK_5700_PCIX_REG_BUG 0x00000010 276 #define BGE_QUIRK_PRODUCER_BUG 0x00000020 277 #define BGE_QUIRK_PCIX_DMA_ALIGN_BUG 0x00000040 278 #define BGE_QUIRK_5705_CORE 0x00000080 279 #define BGE_QUIRK_FEWER_MBUFS 0x00000100 280 281 /* following bugs are common to bcm5700 rev B, all flavours */ 282 #define BGE_QUIRK_5700_COMMON \ 283 (BGE_QUIRK_5700_SMALLDMA|BGE_QUIRK_PRODUCER_BUG) 284 285 CFATTACH_DECL(bge, sizeof(struct bge_softc), 286 bge_probe, bge_attach, NULL, NULL); 287 288 u_int32_t 289 bge_readmem_ind(sc, off) 290 struct bge_softc *sc; 291 int off; 292 { 293 struct pci_attach_args *pa = &(sc->bge_pa); 294 pcireg_t val; 295 296 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 297 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 298 return val; 299 } 300 301 void 302 bge_writemem_ind(sc, off, val) 303 struct bge_softc *sc; 304 int off, val; 305 { 306 struct pci_attach_args *pa = &(sc->bge_pa); 307 308 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 309 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 310 } 311 312 #ifdef notdef 313 u_int32_t 314 bge_readreg_ind(sc, off) 315 struct bge_softc *sc; 316 int off; 317 { 318 struct pci_attach_args *pa = &(sc->bge_pa); 319 320 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 321 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 322 } 323 #endif 324 325 void 326 bge_writereg_ind(sc, off, val) 327 struct bge_softc *sc; 328 int off, val; 329 { 330 struct pci_attach_args *pa = &(sc->bge_pa); 331 332 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 333 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 334 } 335 336 #ifdef notdef 337 u_int8_t 338 bge_vpd_readbyte(sc, addr) 339 struct bge_softc *sc; 340 int addr; 341 { 342 int i; 343 u_int32_t val; 344 struct pci_attach_args *pa = &(sc->bge_pa); 345 346 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 347 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 348 DELAY(10); 349 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 350 BGE_VPD_FLAG) 351 break; 352 } 353 354 if (i == BGE_TIMEOUT) { 355 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 356 return(0); 357 } 358 359 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 360 361 return((val >> ((addr % 4) * 8)) & 0xFF); 362 } 363 364 void 365 bge_vpd_read_res(sc, res, addr) 366 struct bge_softc *sc; 367 struct vpd_res *res; 368 int addr; 369 { 370 int i; 371 u_int8_t *ptr; 372 373 ptr = (u_int8_t *)res; 374 for (i = 0; i < sizeof(struct vpd_res); i++) 375 ptr[i] = bge_vpd_readbyte(sc, i + addr); 376 } 377 378 void 379 bge_vpd_read(sc) 380 struct bge_softc *sc; 381 { 382 int pos = 0, i; 383 struct vpd_res res; 384 385 if (sc->bge_vpd_prodname != NULL) 386 free(sc->bge_vpd_prodname, M_DEVBUF); 387 if (sc->bge_vpd_readonly != NULL) 388 free(sc->bge_vpd_readonly, M_DEVBUF); 389 sc->bge_vpd_prodname = NULL; 390 sc->bge_vpd_readonly = NULL; 391 392 bge_vpd_read_res(sc, &res, pos); 393 394 if (res.vr_id != VPD_RES_ID) { 395 printf("%s: bad VPD resource id: expected %x got %x\n", 396 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 402 if (sc->bge_vpd_prodname == NULL) 403 panic("bge_vpd_read"); 404 for (i = 0; i < res.vr_len; i++) 405 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 406 sc->bge_vpd_prodname[i] = '\0'; 407 pos += i; 408 409 bge_vpd_read_res(sc, &res, pos); 410 411 if (res.vr_id != VPD_RES_READ) { 412 printf("%s: bad VPD resource id: expected %x got %x\n", 413 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 414 return; 415 } 416 417 pos += sizeof(res); 418 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 419 if (sc->bge_vpd_readonly == NULL) 420 panic("bge_vpd_read"); 421 for (i = 0; i < res.vr_len + 1; i++) 422 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 423 } 424 #endif 425 426 /* 427 * Read a byte of data stored in the EEPROM at address 'addr.' The 428 * BCM570x supports both the traditional bitbang interface and an 429 * auto access interface for reading the EEPROM. We use the auto 430 * access method. 431 */ 432 u_int8_t 433 bge_eeprom_getbyte(sc, addr, dest) 434 struct bge_softc *sc; 435 int addr; 436 u_int8_t *dest; 437 { 438 int i; 439 u_int32_t byte = 0; 440 441 /* 442 * Enable use of auto EEPROM access so we can avoid 443 * having to use the bitbang method. 444 */ 445 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 446 447 /* Reset the EEPROM, load the clock period. */ 448 CSR_WRITE_4(sc, BGE_EE_ADDR, 449 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 450 DELAY(20); 451 452 /* Issue the read EEPROM command. */ 453 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 454 455 /* Wait for completion */ 456 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 457 DELAY(10); 458 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 459 break; 460 } 461 462 if (i == BGE_TIMEOUT) { 463 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 464 return(0); 465 } 466 467 /* Get result. */ 468 byte = CSR_READ_4(sc, BGE_EE_DATA); 469 470 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 471 472 return(0); 473 } 474 475 /* 476 * Read a sequence of bytes from the EEPROM. 477 */ 478 int 479 bge_read_eeprom(sc, dest, off, cnt) 480 struct bge_softc *sc; 481 caddr_t dest; 482 int off; 483 int cnt; 484 { 485 int err = 0, i; 486 u_int8_t byte = 0; 487 488 for (i = 0; i < cnt; i++) { 489 err = bge_eeprom_getbyte(sc, off + i, &byte); 490 if (err) 491 break; 492 *(dest + i) = byte; 493 } 494 495 return(err ? 1 : 0); 496 } 497 498 int 499 bge_miibus_readreg(dev, phy, reg) 500 struct device *dev; 501 int phy, reg; 502 { 503 struct bge_softc *sc = (struct bge_softc *)dev; 504 u_int32_t val; 505 u_int32_t saved_autopoll; 506 int i; 507 508 /* 509 * Several chips with builtin PHYs will incorrectly answer to 510 * other PHY instances than the builtin PHY at id 1. 511 */ 512 if (phy != 1 && (sc->bge_quirks & BGE_QUIRK_ONLY_PHY_1)) 513 return(0); 514 515 /* Reading with autopolling on may trigger PCI errors */ 516 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 517 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 518 CSR_WRITE_4(sc, BGE_MI_MODE, 519 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 520 DELAY(40); 521 } 522 523 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 524 BGE_MIPHY(phy)|BGE_MIREG(reg)); 525 526 for (i = 0; i < BGE_TIMEOUT; i++) { 527 val = CSR_READ_4(sc, BGE_MI_COMM); 528 if (!(val & BGE_MICOMM_BUSY)) 529 break; 530 delay(10); 531 } 532 533 if (i == BGE_TIMEOUT) { 534 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 535 val = 0; 536 goto done; 537 } 538 539 val = CSR_READ_4(sc, BGE_MI_COMM); 540 541 done: 542 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 543 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 544 DELAY(40); 545 } 546 547 if (val & BGE_MICOMM_READFAIL) 548 return(0); 549 550 return(val & 0xFFFF); 551 } 552 553 void 554 bge_miibus_writereg(dev, phy, reg, val) 555 struct device *dev; 556 int phy, reg, val; 557 { 558 struct bge_softc *sc = (struct bge_softc *)dev; 559 u_int32_t saved_autopoll; 560 int i; 561 562 /* Touching the PHY while autopolling is on may trigger PCI errors */ 563 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 564 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 565 delay(40); 566 CSR_WRITE_4(sc, BGE_MI_MODE, 567 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 568 delay(10); /* 40 usec is supposed to be adequate */ 569 } 570 571 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 572 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 573 574 for (i = 0; i < BGE_TIMEOUT; i++) { 575 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 576 break; 577 delay(10); 578 } 579 580 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 581 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 582 delay(40); 583 } 584 585 if (i == BGE_TIMEOUT) { 586 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 587 } 588 } 589 590 void 591 bge_miibus_statchg(dev) 592 struct device *dev; 593 { 594 struct bge_softc *sc = (struct bge_softc *)dev; 595 struct mii_data *mii = &sc->bge_mii; 596 597 /* 598 * Get flow control negotiation result. 599 */ 600 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 601 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 602 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 603 mii->mii_media_active &= ~IFM_ETH_FMASK; 604 } 605 606 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 607 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 608 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 609 } else { 610 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 611 } 612 613 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 614 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 615 } else { 616 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 617 } 618 619 /* 620 * 802.3x flow control 621 */ 622 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) { 623 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 624 } else { 625 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 626 } 627 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) { 628 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 629 } else { 630 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 631 } 632 } 633 634 /* 635 * Update rx threshold levels to values in a particular slot 636 * of the interrupt-mitigation table bge_rx_threshes. 637 */ 638 void 639 bge_set_thresh(struct ifnet *ifp, int lvl) 640 { 641 struct bge_softc *sc = ifp->if_softc; 642 int s; 643 644 /* For now, just save the new Rx-intr thresholds and record 645 * that a threshold update is pending. Updating the hardware 646 * registers here (even at splhigh()) is observed to 647 * occasionaly cause glitches where Rx-interrupts are not 648 * honoured for up to 10 seconds. jonathan@NetBSD.org, 2003-04-05 649 */ 650 s = splnet(); 651 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 652 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 653 sc->bge_pending_rxintr_change = 1; 654 splx(s); 655 656 return; 657 } 658 659 660 /* 661 * Update Rx thresholds of all bge devices 662 */ 663 void 664 bge_update_all_threshes(int lvl) 665 { 666 struct ifnet *ifp; 667 const char * const namebuf = "bge"; 668 int namelen; 669 670 if (lvl < 0) 671 lvl = 0; 672 else if( lvl >= NBGE_RX_THRESH) 673 lvl = NBGE_RX_THRESH - 1; 674 675 namelen = strlen(namebuf); 676 /* 677 * Now search all the interfaces for this name/number 678 */ 679 IFNET_FOREACH(ifp) { 680 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 681 continue; 682 /* We got a match: update if doing auto-threshold-tuning */ 683 if (bge_auto_thresh) 684 bge_set_thresh(ifp, lvl); 685 } 686 } 687 688 /* 689 * Handle events that have triggered interrupts. 690 */ 691 void 692 bge_handle_events(sc) 693 struct bge_softc *sc; 694 { 695 696 return; 697 } 698 699 /* 700 * Memory management for jumbo frames. 701 */ 702 703 int 704 bge_alloc_jumbo_mem(sc) 705 struct bge_softc *sc; 706 { 707 caddr_t ptr, kva; 708 bus_dma_segment_t seg; 709 int i, rseg, state, error; 710 struct bge_jpool_entry *entry; 711 712 state = error = 0; 713 714 /* Grab a big chunk o' storage. */ 715 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 716 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 717 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 718 return ENOBUFS; 719 } 720 721 state = 1; 722 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 723 BUS_DMA_NOWAIT)) { 724 printf("%s: can't map DMA buffers (%d bytes)\n", 725 sc->bge_dev.dv_xname, (int)BGE_JMEM); 726 error = ENOBUFS; 727 goto out; 728 } 729 730 state = 2; 731 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 732 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 733 printf("%s: can't create DMA map\n", sc->bge_dev.dv_xname); 734 error = ENOBUFS; 735 goto out; 736 } 737 738 state = 3; 739 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 740 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 741 printf("%s: can't load DMA map\n", sc->bge_dev.dv_xname); 742 error = ENOBUFS; 743 goto out; 744 } 745 746 state = 4; 747 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 748 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 749 750 SLIST_INIT(&sc->bge_jfree_listhead); 751 SLIST_INIT(&sc->bge_jinuse_listhead); 752 753 /* 754 * Now divide it up into 9K pieces and save the addresses 755 * in an array. 756 */ 757 ptr = sc->bge_cdata.bge_jumbo_buf; 758 for (i = 0; i < BGE_JSLOTS; i++) { 759 sc->bge_cdata.bge_jslots[i] = ptr; 760 ptr += BGE_JLEN; 761 entry = malloc(sizeof(struct bge_jpool_entry), 762 M_DEVBUF, M_NOWAIT); 763 if (entry == NULL) { 764 printf("%s: no memory for jumbo buffer queue!\n", 765 sc->bge_dev.dv_xname); 766 error = ENOBUFS; 767 goto out; 768 } 769 entry->slot = i; 770 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 771 entry, jpool_entries); 772 } 773 out: 774 if (error != 0) { 775 switch (state) { 776 case 4: 777 bus_dmamap_unload(sc->bge_dmatag, 778 sc->bge_cdata.bge_rx_jumbo_map); 779 case 3: 780 bus_dmamap_destroy(sc->bge_dmatag, 781 sc->bge_cdata.bge_rx_jumbo_map); 782 case 2: 783 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 784 case 1: 785 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 786 break; 787 default: 788 break; 789 } 790 } 791 792 return error; 793 } 794 795 /* 796 * Allocate a jumbo buffer. 797 */ 798 void * 799 bge_jalloc(sc) 800 struct bge_softc *sc; 801 { 802 struct bge_jpool_entry *entry; 803 804 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 805 806 if (entry == NULL) { 807 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 808 return(NULL); 809 } 810 811 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 812 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 813 return(sc->bge_cdata.bge_jslots[entry->slot]); 814 } 815 816 /* 817 * Release a jumbo buffer. 818 */ 819 void 820 bge_jfree(m, buf, size, arg) 821 struct mbuf *m; 822 caddr_t buf; 823 size_t size; 824 void *arg; 825 { 826 struct bge_jpool_entry *entry; 827 struct bge_softc *sc; 828 int i, s; 829 830 /* Extract the softc struct pointer. */ 831 sc = (struct bge_softc *)arg; 832 833 if (sc == NULL) 834 panic("bge_jfree: can't find softc pointer!"); 835 836 /* calculate the slot this buffer belongs to */ 837 838 i = ((caddr_t)buf 839 - (caddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 840 841 if ((i < 0) || (i >= BGE_JSLOTS)) 842 panic("bge_jfree: asked to free buffer that we don't manage!"); 843 844 s = splvm(); 845 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 846 if (entry == NULL) 847 panic("bge_jfree: buffer not in use!"); 848 entry->slot = i; 849 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 850 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 851 852 if (__predict_true(m != NULL)) 853 pool_cache_put(&mbpool_cache, m); 854 splx(s); 855 } 856 857 858 /* 859 * Intialize a standard receive ring descriptor. 860 */ 861 int 862 bge_newbuf_std(sc, i, m, dmamap) 863 struct bge_softc *sc; 864 int i; 865 struct mbuf *m; 866 bus_dmamap_t dmamap; 867 { 868 struct mbuf *m_new = NULL; 869 struct bge_rx_bd *r; 870 int error; 871 872 if (dmamap == NULL) { 873 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 874 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 875 if (error != 0) 876 return error; 877 } 878 879 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 880 881 if (m == NULL) { 882 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 883 if (m_new == NULL) { 884 return(ENOBUFS); 885 } 886 887 MCLGET(m_new, M_DONTWAIT); 888 if (!(m_new->m_flags & M_EXT)) { 889 m_freem(m_new); 890 return(ENOBUFS); 891 } 892 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 893 if (!sc->bge_rx_alignment_bug) 894 m_adj(m_new, ETHER_ALIGN); 895 896 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 897 BUS_DMA_READ|BUS_DMA_NOWAIT)) 898 return(ENOBUFS); 899 } else { 900 m_new = m; 901 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 902 m_new->m_data = m_new->m_ext.ext_buf; 903 if (!sc->bge_rx_alignment_bug) 904 m_adj(m_new, ETHER_ALIGN); 905 } 906 907 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 908 r = &sc->bge_rdata->bge_rx_std_ring[i]; 909 bge_set_hostaddr(&r->bge_addr, 910 dmamap->dm_segs[0].ds_addr); 911 r->bge_flags = BGE_RXBDFLAG_END; 912 r->bge_len = m_new->m_len; 913 r->bge_idx = i; 914 915 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 916 offsetof(struct bge_ring_data, bge_rx_std_ring) + 917 i * sizeof (struct bge_rx_bd), 918 sizeof (struct bge_rx_bd), 919 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 920 921 return(0); 922 } 923 924 /* 925 * Initialize a jumbo receive ring descriptor. This allocates 926 * a jumbo buffer from the pool managed internally by the driver. 927 */ 928 int 929 bge_newbuf_jumbo(sc, i, m) 930 struct bge_softc *sc; 931 int i; 932 struct mbuf *m; 933 { 934 struct mbuf *m_new = NULL; 935 struct bge_rx_bd *r; 936 937 if (m == NULL) { 938 caddr_t buf = NULL; 939 940 /* Allocate the mbuf. */ 941 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 942 if (m_new == NULL) { 943 return(ENOBUFS); 944 } 945 946 /* Allocate the jumbo buffer */ 947 buf = bge_jalloc(sc); 948 if (buf == NULL) { 949 m_freem(m_new); 950 printf("%s: jumbo allocation failed " 951 "-- packet dropped!\n", sc->bge_dev.dv_xname); 952 return(ENOBUFS); 953 } 954 955 /* Attach the buffer to the mbuf. */ 956 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 957 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 958 bge_jfree, sc); 959 m_new->m_flags |= M_EXT_RW; 960 } else { 961 m_new = m; 962 m_new->m_data = m_new->m_ext.ext_buf; 963 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 964 } 965 966 if (!sc->bge_rx_alignment_bug) 967 m_adj(m_new, ETHER_ALIGN); 968 /* Set up the descriptor. */ 969 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 970 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 971 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 972 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 973 r->bge_len = m_new->m_len; 974 r->bge_idx = i; 975 976 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 977 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 978 i * sizeof (struct bge_rx_bd), 979 sizeof (struct bge_rx_bd), 980 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 981 982 return(0); 983 } 984 985 /* 986 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 987 * that's 1MB or memory, which is a lot. For now, we fill only the first 988 * 256 ring entries and hope that our CPU is fast enough to keep up with 989 * the NIC. 990 */ 991 int 992 bge_init_rx_ring_std(sc) 993 struct bge_softc *sc; 994 { 995 int i; 996 997 if (sc->bge_flags & BGE_RXRING_VALID) 998 return 0; 999 1000 for (i = 0; i < BGE_SSLOTS; i++) { 1001 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1002 return(ENOBUFS); 1003 } 1004 1005 sc->bge_std = i - 1; 1006 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1007 1008 sc->bge_flags |= BGE_RXRING_VALID; 1009 1010 return(0); 1011 } 1012 1013 void 1014 bge_free_rx_ring_std(sc) 1015 struct bge_softc *sc; 1016 { 1017 int i; 1018 1019 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1020 return; 1021 1022 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1023 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1024 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1025 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1026 bus_dmamap_destroy(sc->bge_dmatag, 1027 sc->bge_cdata.bge_rx_std_map[i]); 1028 } 1029 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1030 sizeof(struct bge_rx_bd)); 1031 } 1032 1033 sc->bge_flags &= ~BGE_RXRING_VALID; 1034 } 1035 1036 int 1037 bge_init_rx_ring_jumbo(sc) 1038 struct bge_softc *sc; 1039 { 1040 int i; 1041 volatile struct bge_rcb *rcb; 1042 1043 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1044 return 0; 1045 1046 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1047 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1048 return(ENOBUFS); 1049 }; 1050 1051 sc->bge_jumbo = i - 1; 1052 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1053 1054 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1055 rcb->bge_maxlen_flags = 0; 1056 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1057 1058 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1059 1060 return(0); 1061 } 1062 1063 void 1064 bge_free_rx_ring_jumbo(sc) 1065 struct bge_softc *sc; 1066 { 1067 int i; 1068 1069 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1070 return; 1071 1072 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1073 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1074 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1075 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1076 } 1077 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1078 sizeof(struct bge_rx_bd)); 1079 } 1080 1081 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1082 } 1083 1084 void 1085 bge_free_tx_ring(sc) 1086 struct bge_softc *sc; 1087 { 1088 int i, freed; 1089 struct txdmamap_pool_entry *dma; 1090 1091 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1092 return; 1093 1094 freed = 0; 1095 1096 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1097 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1098 freed++; 1099 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1100 sc->bge_cdata.bge_tx_chain[i] = NULL; 1101 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1102 link); 1103 sc->txdma[i] = 0; 1104 } 1105 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1106 sizeof(struct bge_tx_bd)); 1107 } 1108 1109 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1110 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1111 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1112 free(dma, M_DEVBUF); 1113 } 1114 1115 sc->bge_flags &= ~BGE_TXRING_VALID; 1116 } 1117 1118 int 1119 bge_init_tx_ring(sc) 1120 struct bge_softc *sc; 1121 { 1122 int i; 1123 bus_dmamap_t dmamap; 1124 struct txdmamap_pool_entry *dma; 1125 1126 if (sc->bge_flags & BGE_TXRING_VALID) 1127 return 0; 1128 1129 sc->bge_txcnt = 0; 1130 sc->bge_tx_saved_considx = 0; 1131 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1132 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1133 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1134 1135 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1136 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 1137 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1138 1139 SLIST_INIT(&sc->txdma_list); 1140 for (i = 0; i < BGE_RSLOTS; i++) { 1141 if (bus_dmamap_create(sc->bge_dmatag, ETHER_MAX_LEN_JUMBO, 1142 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1143 &dmamap)) 1144 return(ENOBUFS); 1145 if (dmamap == NULL) 1146 panic("dmamap NULL in bge_init_tx_ring"); 1147 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1148 if (dma == NULL) { 1149 printf("%s: can't alloc txdmamap_pool_entry\n", 1150 sc->bge_dev.dv_xname); 1151 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1152 return (ENOMEM); 1153 } 1154 dma->dmamap = dmamap; 1155 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1156 } 1157 1158 sc->bge_flags |= BGE_TXRING_VALID; 1159 1160 return(0); 1161 } 1162 1163 void 1164 bge_setmulti(sc) 1165 struct bge_softc *sc; 1166 { 1167 struct ethercom *ac = &sc->ethercom; 1168 struct ifnet *ifp = &ac->ec_if; 1169 struct ether_multi *enm; 1170 struct ether_multistep step; 1171 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1172 u_int32_t h; 1173 int i; 1174 1175 if (ifp->if_flags & IFF_PROMISC) 1176 goto allmulti; 1177 1178 /* Now program new ones. */ 1179 ETHER_FIRST_MULTI(step, ac, enm); 1180 while (enm != NULL) { 1181 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1182 /* 1183 * We must listen to a range of multicast addresses. 1184 * For now, just accept all multicasts, rather than 1185 * trying to set only those filter bits needed to match 1186 * the range. (At this time, the only use of address 1187 * ranges is for IP multicast routing, for which the 1188 * range is big enough to require all bits set.) 1189 */ 1190 goto allmulti; 1191 } 1192 1193 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1194 1195 /* Just want the 7 least-significant bits. */ 1196 h &= 0x7f; 1197 1198 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1199 ETHER_NEXT_MULTI(step, enm); 1200 } 1201 1202 ifp->if_flags &= ~IFF_ALLMULTI; 1203 goto setit; 1204 1205 allmulti: 1206 ifp->if_flags |= IFF_ALLMULTI; 1207 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1208 1209 setit: 1210 for (i = 0; i < 4; i++) 1211 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1212 } 1213 1214 const int bge_swapbits[] = { 1215 0, 1216 BGE_MODECTL_BYTESWAP_DATA, 1217 BGE_MODECTL_WORDSWAP_DATA, 1218 BGE_MODECTL_BYTESWAP_NONFRAME, 1219 BGE_MODECTL_WORDSWAP_NONFRAME, 1220 1221 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1222 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1223 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1224 1225 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1226 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1227 1228 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1229 1230 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1231 BGE_MODECTL_BYTESWAP_NONFRAME, 1232 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1233 BGE_MODECTL_WORDSWAP_NONFRAME, 1234 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1235 BGE_MODECTL_WORDSWAP_NONFRAME, 1236 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1237 BGE_MODECTL_WORDSWAP_NONFRAME, 1238 1239 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1240 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1241 }; 1242 1243 int bge_swapindex = 0; 1244 1245 /* 1246 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1247 * self-test results. 1248 */ 1249 int 1250 bge_chipinit(sc) 1251 struct bge_softc *sc; 1252 { 1253 u_int32_t cachesize; 1254 int i; 1255 u_int32_t dma_rw_ctl; 1256 struct pci_attach_args *pa = &(sc->bge_pa); 1257 1258 1259 /* Set endianness before we access any non-PCI registers. */ 1260 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1261 BGE_INIT); 1262 1263 /* Set power state to D0. */ 1264 bge_setpowerstate(sc, 0); 1265 1266 /* 1267 * Check the 'ROM failed' bit on the RX CPU to see if 1268 * self-tests passed. 1269 */ 1270 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1271 printf("%s: RX CPU self-diagnostics failed!\n", 1272 sc->bge_dev.dv_xname); 1273 return(ENODEV); 1274 } 1275 1276 /* Clear the MAC control register */ 1277 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1278 1279 /* 1280 * Clear the MAC statistics block in the NIC's 1281 * internal memory. 1282 */ 1283 for (i = BGE_STATS_BLOCK; 1284 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1285 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1286 1287 for (i = BGE_STATUS_BLOCK; 1288 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1289 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1290 1291 /* Set up the PCI DMA control register. */ 1292 if (sc->bge_pcie) { 1293 /* From FreeBSD */ 1294 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1295 sc->bge_dev.dv_xname)); 1296 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1297 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1298 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1299 } else if (pci_conf_read(pa->pa_pc, pa->pa_tag,BGE_PCI_PCISTATE) & 1300 BGE_PCISTATE_PCI_BUSMODE) { 1301 /* Conventional PCI bus */ 1302 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", sc->bge_dev.dv_xname)); 1303 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1304 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1305 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1306 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1307 dma_rw_ctl |= 0x0F; 1308 } 1309 } else { 1310 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", sc->bge_dev.dv_xname)); 1311 /* PCI-X bus */ 1312 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1313 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1314 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1315 (0x0F); 1316 /* 1317 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1318 * for hardware bugs, which means we should also clear 1319 * the low-order MINDMA bits. In addition, the 5704 1320 * uses a different encoding of read/write watermarks. 1321 */ 1322 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1323 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1324 /* should be 0x1f0000 */ 1325 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1326 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1327 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1328 } 1329 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1330 dma_rw_ctl &= 0xfffffff0; 1331 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1332 } 1333 } 1334 1335 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1336 1337 /* 1338 * Set up general mode register. 1339 */ 1340 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1341 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1342 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1343 1344 /* Get cache line size. */ 1345 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1346 1347 /* 1348 * Avoid violating PCI spec on certain chip revs. 1349 */ 1350 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 1351 PCIM_CMD_MWIEN) { 1352 switch(cachesize) { 1353 case 1: 1354 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1355 BGE_PCI_WRITE_BNDRY_16BYTES); 1356 break; 1357 case 2: 1358 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1359 BGE_PCI_WRITE_BNDRY_32BYTES); 1360 break; 1361 case 4: 1362 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1363 BGE_PCI_WRITE_BNDRY_64BYTES); 1364 break; 1365 case 8: 1366 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1367 BGE_PCI_WRITE_BNDRY_128BYTES); 1368 break; 1369 case 16: 1370 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1371 BGE_PCI_WRITE_BNDRY_256BYTES); 1372 break; 1373 case 32: 1374 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1375 BGE_PCI_WRITE_BNDRY_512BYTES); 1376 break; 1377 case 64: 1378 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1379 BGE_PCI_WRITE_BNDRY_1024BYTES); 1380 break; 1381 default: 1382 /* Disable PCI memory write and invalidate. */ 1383 #if 0 1384 if (bootverbose) 1385 printf("%s: cache line size %d not " 1386 "supported; disabling PCI MWI\n", 1387 sc->bge_dev.dv_xname, cachesize); 1388 #endif 1389 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1390 PCIM_CMD_MWIEN); 1391 break; 1392 } 1393 } 1394 1395 /* 1396 * Disable memory write invalidate. Apparently it is not supported 1397 * properly by these devices. 1398 */ 1399 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1400 1401 1402 #ifdef __brokenalpha__ 1403 /* 1404 * Must insure that we do not cross an 8K (bytes) boundary 1405 * for DMA reads. Our highest limit is 1K bytes. This is a 1406 * restriction on some ALPHA platforms with early revision 1407 * 21174 PCI chipsets, such as the AlphaPC 164lx 1408 */ 1409 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1410 #endif 1411 1412 /* Set the timer prescaler (always 66MHz) */ 1413 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1414 1415 return(0); 1416 } 1417 1418 int 1419 bge_blockinit(sc) 1420 struct bge_softc *sc; 1421 { 1422 volatile struct bge_rcb *rcb; 1423 bus_size_t rcb_addr; 1424 int i; 1425 struct ifnet *ifp = &sc->ethercom.ec_if; 1426 bge_hostaddr taddr; 1427 1428 /* 1429 * Initialize the memory window pointer register so that 1430 * we can access the first 32K of internal NIC RAM. This will 1431 * allow us to set up the TX send ring RCBs and the RX return 1432 * ring RCBs, plus other things which live in NIC memory. 1433 */ 1434 1435 pci_conf_write(sc->bge_pa.pa_pc, sc->bge_pa.pa_tag, 1436 BGE_PCI_MEMWIN_BASEADDR, 0); 1437 1438 /* Configure mbuf memory pool */ 1439 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1440 if (sc->bge_extram) { 1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1442 BGE_EXT_SSRAM); 1443 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1444 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1445 else 1446 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1447 } else { 1448 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1449 BGE_BUFFPOOL_1); 1450 if ((sc->bge_quirks & BGE_QUIRK_FEWER_MBUFS) != 0) 1451 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1452 else 1453 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1454 } 1455 1456 /* Configure DMA resource pool */ 1457 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1458 BGE_DMA_DESCRIPTORS); 1459 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1460 } 1461 1462 /* Configure mbuf pool watermarks */ 1463 #ifdef ORIG_WPAUL_VALUES 1464 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1465 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1466 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1467 #else 1468 /* new broadcom docs strongly recommend these: */ 1469 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1470 if (ifp->if_mtu > ETHER_MAX_LEN) { 1471 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1472 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1473 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1474 } else { 1475 /* Values from Linux driver... */ 1476 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1477 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1478 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1479 } 1480 } else { 1481 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1482 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1483 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1484 } 1485 #endif 1486 1487 /* Configure DMA resource watermarks */ 1488 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1489 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1490 1491 /* Enable buffer manager */ 1492 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1493 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1494 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1495 1496 /* Poll for buffer manager start indication */ 1497 for (i = 0; i < BGE_TIMEOUT; i++) { 1498 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1499 break; 1500 DELAY(10); 1501 } 1502 1503 if (i == BGE_TIMEOUT) { 1504 printf("%s: buffer manager failed to start\n", 1505 sc->bge_dev.dv_xname); 1506 return(ENXIO); 1507 } 1508 } 1509 1510 /* Enable flow-through queues */ 1511 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1512 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1513 1514 /* Wait until queue initialization is complete */ 1515 for (i = 0; i < BGE_TIMEOUT; i++) { 1516 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1517 break; 1518 DELAY(10); 1519 } 1520 1521 if (i == BGE_TIMEOUT) { 1522 printf("%s: flow-through queue init failed\n", 1523 sc->bge_dev.dv_xname); 1524 return(ENXIO); 1525 } 1526 1527 /* Initialize the standard RX ring control block */ 1528 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1529 bge_set_hostaddr(&rcb->bge_hostaddr, 1530 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1531 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1532 rcb->bge_maxlen_flags = 1533 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1534 } else { 1535 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1536 } 1537 if (sc->bge_extram) 1538 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1539 else 1540 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1541 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1542 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1543 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1544 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1545 1546 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1547 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1548 } else { 1549 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1550 } 1551 1552 /* 1553 * Initialize the jumbo RX ring control block 1554 * We set the 'ring disabled' bit in the flags 1555 * field until we're actually ready to start 1556 * using this ring (i.e. once we set the MTU 1557 * high enough to require it). 1558 */ 1559 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1560 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1561 bge_set_hostaddr(&rcb->bge_hostaddr, 1562 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1563 rcb->bge_maxlen_flags = 1564 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1565 BGE_RCB_FLAG_RING_DISABLED); 1566 if (sc->bge_extram) 1567 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1568 else 1569 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1570 1571 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1572 rcb->bge_hostaddr.bge_addr_hi); 1573 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1574 rcb->bge_hostaddr.bge_addr_lo); 1575 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1576 rcb->bge_maxlen_flags); 1577 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1578 1579 /* Set up dummy disabled mini ring RCB */ 1580 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1581 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1582 BGE_RCB_FLAG_RING_DISABLED); 1583 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1584 rcb->bge_maxlen_flags); 1585 1586 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1587 offsetof(struct bge_ring_data, bge_info), 1588 sizeof (struct bge_gib), 1589 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1590 } 1591 1592 /* 1593 * Set the BD ring replentish thresholds. The recommended 1594 * values are 1/8th the number of descriptors allocated to 1595 * each ring. 1596 */ 1597 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1598 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1599 1600 /* 1601 * Disable all unused send rings by setting the 'ring disabled' 1602 * bit in the flags field of all the TX send ring control blocks. 1603 * These are located in NIC memory. 1604 */ 1605 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1606 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1607 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1608 BGE_RCB_MAXLEN_FLAGS(0,BGE_RCB_FLAG_RING_DISABLED)); 1609 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1610 rcb_addr += sizeof(struct bge_rcb); 1611 } 1612 1613 /* Configure TX RCB 0 (we use only the first ring) */ 1614 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1615 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1616 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1617 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1618 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1619 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1620 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1621 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1622 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1623 } 1624 1625 /* Disable all unused RX return rings */ 1626 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1627 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1628 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1629 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1630 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1631 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1632 BGE_RCB_FLAG_RING_DISABLED)); 1633 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1634 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1635 (i * (sizeof(u_int64_t))), 0); 1636 rcb_addr += sizeof(struct bge_rcb); 1637 } 1638 1639 /* Initialize RX ring indexes */ 1640 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1641 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1642 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1643 1644 /* 1645 * Set up RX return ring 0 1646 * Note that the NIC address for RX return rings is 0x00000000. 1647 * The return rings live entirely within the host, so the 1648 * nicaddr field in the RCB isn't used. 1649 */ 1650 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1651 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1652 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1653 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1654 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1655 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1656 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1657 1658 /* Set random backoff seed for TX */ 1659 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1660 LLADDR(ifp->if_sadl)[0] + LLADDR(ifp->if_sadl)[1] + 1661 LLADDR(ifp->if_sadl)[2] + LLADDR(ifp->if_sadl)[3] + 1662 LLADDR(ifp->if_sadl)[4] + LLADDR(ifp->if_sadl)[5] + 1663 BGE_TX_BACKOFF_SEED_MASK); 1664 1665 /* Set inter-packet gap */ 1666 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1667 1668 /* 1669 * Specify which ring to use for packets that don't match 1670 * any RX rules. 1671 */ 1672 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1673 1674 /* 1675 * Configure number of RX lists. One interrupt distribution 1676 * list, sixteen active lists, one bad frames class. 1677 */ 1678 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1679 1680 /* Inialize RX list placement stats mask. */ 1681 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1682 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1683 1684 /* Disable host coalescing until we get it set up */ 1685 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1686 1687 /* Poll to make sure it's shut down. */ 1688 for (i = 0; i < BGE_TIMEOUT; i++) { 1689 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1690 break; 1691 DELAY(10); 1692 } 1693 1694 if (i == BGE_TIMEOUT) { 1695 printf("%s: host coalescing engine failed to idle\n", 1696 sc->bge_dev.dv_xname); 1697 return(ENXIO); 1698 } 1699 1700 /* Set up host coalescing defaults */ 1701 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1702 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1703 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1704 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1705 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1706 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1707 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1708 } 1709 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1710 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1711 1712 /* Set up address of statistics block */ 1713 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1714 bge_set_hostaddr(&taddr, 1715 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1716 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1717 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1718 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1719 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1720 } 1721 1722 /* Set up address of status block */ 1723 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1724 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1725 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1726 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1727 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1728 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1729 1730 /* Turn on host coalescing state machine */ 1731 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1732 1733 /* Turn on RX BD completion state machine and enable attentions */ 1734 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1735 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1736 1737 /* Turn on RX list placement state machine */ 1738 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1739 1740 /* Turn on RX list selector state machine. */ 1741 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1742 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1743 } 1744 1745 /* Turn on DMA, clear stats */ 1746 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1747 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1748 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1749 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1750 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1751 1752 /* Set misc. local control, enable interrupts on attentions */ 1753 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 1754 1755 #ifdef notdef 1756 /* Assert GPIO pins for PHY reset */ 1757 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1758 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1759 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1760 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1761 #endif 1762 1763 #if defined(not_quite_yet) 1764 /* Linux driver enables enable gpio pin #1 on 5700s */ 1765 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 1766 sc->bge_local_ctrl_reg |= 1767 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 1768 } 1769 #endif 1770 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 1771 1772 /* Turn on DMA completion state machine */ 1773 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1774 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1775 } 1776 1777 /* Turn on write DMA state machine */ 1778 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1779 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1780 1781 /* Turn on read DMA state machine */ 1782 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1783 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1784 1785 /* Turn on RX data completion state machine */ 1786 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1787 1788 /* Turn on RX BD initiator state machine */ 1789 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1790 1791 /* Turn on RX data and RX BD initiator state machine */ 1792 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1793 1794 /* Turn on Mbuf cluster free state machine */ 1795 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 1796 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1797 } 1798 1799 /* Turn on send BD completion state machine */ 1800 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1801 1802 /* Turn on send data completion state machine */ 1803 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1804 1805 /* Turn on send data initiator state machine */ 1806 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1807 1808 /* Turn on send BD initiator state machine */ 1809 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1810 1811 /* Turn on send BD selector state machine */ 1812 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1813 1814 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1815 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1816 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1817 1818 /* ack/clear link change events */ 1819 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1820 BGE_MACSTAT_CFG_CHANGED); 1821 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1822 1823 /* Enable PHY auto polling (for MII/GMII only) */ 1824 if (sc->bge_tbi) { 1825 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1826 } else { 1827 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1828 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) 1829 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1830 BGE_EVTENB_MI_INTERRUPT); 1831 } 1832 1833 /* Enable link state change attentions. */ 1834 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1835 1836 return(0); 1837 } 1838 1839 static const struct bge_revision { 1840 uint32_t br_chipid; 1841 uint32_t br_quirks; 1842 const char *br_name; 1843 } bge_revisions[] = { 1844 { BGE_CHIPID_BCM5700_A0, 1845 BGE_QUIRK_LINK_STATE_BROKEN, 1846 "BCM5700 A0" }, 1847 1848 { BGE_CHIPID_BCM5700_A1, 1849 BGE_QUIRK_LINK_STATE_BROKEN, 1850 "BCM5700 A1" }, 1851 1852 { BGE_CHIPID_BCM5700_B0, 1853 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_CSUM_BROKEN|BGE_QUIRK_5700_COMMON, 1854 "BCM5700 B0" }, 1855 1856 { BGE_CHIPID_BCM5700_B1, 1857 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1858 "BCM5700 B1" }, 1859 1860 { BGE_CHIPID_BCM5700_B2, 1861 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1862 "BCM5700 B2" }, 1863 1864 /* This is treated like a BCM5700 Bx */ 1865 { BGE_CHIPID_BCM5700_ALTIMA, 1866 BGE_QUIRK_LINK_STATE_BROKEN|BGE_QUIRK_5700_COMMON, 1867 "BCM5700 Altima" }, 1868 1869 { BGE_CHIPID_BCM5700_C0, 1870 0, 1871 "BCM5700 C0" }, 1872 1873 { BGE_CHIPID_BCM5701_A0, 1874 0, /*XXX really, just not known */ 1875 "BCM5701 A0" }, 1876 1877 { BGE_CHIPID_BCM5701_B0, 1878 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1879 "BCM5701 B0" }, 1880 1881 { BGE_CHIPID_BCM5701_B2, 1882 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1883 "BCM5701 B2" }, 1884 1885 { BGE_CHIPID_BCM5701_B5, 1886 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1887 "BCM5701 B5" }, 1888 1889 { BGE_CHIPID_BCM5703_A0, 1890 0, 1891 "BCM5703 A0" }, 1892 1893 { BGE_CHIPID_BCM5703_A1, 1894 0, 1895 "BCM5703 A1" }, 1896 1897 { BGE_CHIPID_BCM5703_A2, 1898 BGE_QUIRK_ONLY_PHY_1, 1899 "BCM5703 A2" }, 1900 1901 { BGE_CHIPID_BCM5703_A3, 1902 BGE_QUIRK_ONLY_PHY_1, 1903 "BCM5703 A3" }, 1904 1905 { BGE_CHIPID_BCM5704_A0, 1906 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1907 "BCM5704 A0" }, 1908 1909 { BGE_CHIPID_BCM5704_A1, 1910 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1911 "BCM5704 A1" }, 1912 1913 { BGE_CHIPID_BCM5704_A2, 1914 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1915 "BCM5704 A2" }, 1916 1917 { BGE_CHIPID_BCM5704_A3, 1918 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_FEWER_MBUFS, 1919 "BCM5704 A3" }, 1920 1921 { BGE_CHIPID_BCM5705_A0, 1922 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1923 "BCM5705 A0" }, 1924 1925 { BGE_CHIPID_BCM5705_A1, 1926 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1927 "BCM5705 A1" }, 1928 1929 { BGE_CHIPID_BCM5705_A2, 1930 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1931 "BCM5705 A2" }, 1932 1933 { BGE_CHIPID_BCM5705_A3, 1934 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1935 "BCM5705 A3" }, 1936 1937 { BGE_CHIPID_BCM5750_A0, 1938 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1939 "BCM5750 A1" }, 1940 1941 { BGE_CHIPID_BCM5750_A1, 1942 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1943 "BCM5750 A1" }, 1944 1945 { 0, 0, NULL } 1946 }; 1947 1948 /* 1949 * Some defaults for major revisions, so that newer steppings 1950 * that we don't know about have a shot at working. 1951 */ 1952 static const struct bge_revision bge_majorrevs[] = { 1953 { BGE_ASICREV_BCM5700, 1954 BGE_QUIRK_LINK_STATE_BROKEN, 1955 "unknown BCM5700" }, 1956 1957 { BGE_ASICREV_BCM5701, 1958 BGE_QUIRK_PCIX_DMA_ALIGN_BUG, 1959 "unknown BCM5701" }, 1960 1961 { BGE_ASICREV_BCM5703, 1962 0, 1963 "unknown BCM5703" }, 1964 1965 { BGE_ASICREV_BCM5704, 1966 BGE_QUIRK_ONLY_PHY_1, 1967 "unknown BCM5704" }, 1968 1969 { BGE_ASICREV_BCM5705, 1970 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1971 "unknown BCM5705" }, 1972 1973 { BGE_ASICREV_BCM5750, 1974 BGE_QUIRK_ONLY_PHY_1|BGE_QUIRK_5705_CORE, 1975 "unknown BCM5750" }, 1976 1977 { 0, 1978 0, 1979 NULL } 1980 }; 1981 1982 1983 static const struct bge_revision * 1984 bge_lookup_rev(uint32_t chipid) 1985 { 1986 const struct bge_revision *br; 1987 1988 for (br = bge_revisions; br->br_name != NULL; br++) { 1989 if (br->br_chipid == chipid) 1990 return (br); 1991 } 1992 1993 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1994 if (br->br_chipid == BGE_ASICREV(chipid)) 1995 return (br); 1996 } 1997 1998 return (NULL); 1999 } 2000 2001 static const struct bge_product { 2002 pci_vendor_id_t bp_vendor; 2003 pci_product_id_t bp_product; 2004 const char *bp_name; 2005 } bge_products[] = { 2006 /* 2007 * The BCM5700 documentation seems to indicate that the hardware 2008 * still has the Alteon vendor ID burned into it, though it 2009 * should always be overridden by the value in the EEPROM. We'll 2010 * check for it anyway. 2011 */ 2012 { PCI_VENDOR_ALTEON, 2013 PCI_PRODUCT_ALTEON_BCM5700, 2014 "Broadcom BCM5700 Gigabit Ethernet", 2015 }, 2016 { PCI_VENDOR_ALTEON, 2017 PCI_PRODUCT_ALTEON_BCM5701, 2018 "Broadcom BCM5701 Gigabit Ethernet", 2019 }, 2020 2021 { PCI_VENDOR_ALTIMA, 2022 PCI_PRODUCT_ALTIMA_AC1000, 2023 "Altima AC1000 Gigabit Ethernet", 2024 }, 2025 { PCI_VENDOR_ALTIMA, 2026 PCI_PRODUCT_ALTIMA_AC1001, 2027 "Altima AC1001 Gigabit Ethernet", 2028 }, 2029 { PCI_VENDOR_ALTIMA, 2030 PCI_PRODUCT_ALTIMA_AC9100, 2031 "Altima AC9100 Gigabit Ethernet", 2032 }, 2033 2034 { PCI_VENDOR_BROADCOM, 2035 PCI_PRODUCT_BROADCOM_BCM5700, 2036 "Broadcom BCM5700 Gigabit Ethernet", 2037 }, 2038 { PCI_VENDOR_BROADCOM, 2039 PCI_PRODUCT_BROADCOM_BCM5701, 2040 "Broadcom BCM5701 Gigabit Ethernet", 2041 }, 2042 { PCI_VENDOR_BROADCOM, 2043 PCI_PRODUCT_BROADCOM_BCM5702, 2044 "Broadcom BCM5702 Gigabit Ethernet", 2045 }, 2046 { PCI_VENDOR_BROADCOM, 2047 PCI_PRODUCT_BROADCOM_BCM5702X, 2048 "Broadcom BCM5702X Gigabit Ethernet" }, 2049 2050 { PCI_VENDOR_BROADCOM, 2051 PCI_PRODUCT_BROADCOM_BCM5703, 2052 "Broadcom BCM5703 Gigabit Ethernet", 2053 }, 2054 { PCI_VENDOR_BROADCOM, 2055 PCI_PRODUCT_BROADCOM_BCM5703X, 2056 "Broadcom BCM5703X Gigabit Ethernet", 2057 }, 2058 { PCI_VENDOR_BROADCOM, 2059 PCI_PRODUCT_BROADCOM_BCM5703A3, 2060 "Broadcom BCM5703A3 Gigabit Ethernet", 2061 }, 2062 2063 { PCI_VENDOR_BROADCOM, 2064 PCI_PRODUCT_BROADCOM_BCM5704C, 2065 "Broadcom BCM5704C Dual Gigabit Ethernet", 2066 }, 2067 { PCI_VENDOR_BROADCOM, 2068 PCI_PRODUCT_BROADCOM_BCM5704S, 2069 "Broadcom BCM5704S Dual Gigabit Ethernet", 2070 }, 2071 2072 { PCI_VENDOR_BROADCOM, 2073 PCI_PRODUCT_BROADCOM_BCM5705, 2074 "Broadcom BCM5705 Gigabit Ethernet", 2075 }, 2076 { PCI_VENDOR_BROADCOM, 2077 PCI_PRODUCT_BROADCOM_BCM5705K, 2078 "Broadcom BCM5705K Gigabit Ethernet", 2079 }, 2080 { PCI_VENDOR_BROADCOM, 2081 PCI_PRODUCT_BROADCOM_BCM5705_ALT, 2082 "Broadcom BCM5705 Gigabit Ethernet", 2083 }, 2084 { PCI_VENDOR_BROADCOM, 2085 PCI_PRODUCT_BROADCOM_BCM5705M, 2086 "Broadcom BCM5705M Gigabit Ethernet", 2087 }, 2088 2089 { PCI_VENDOR_BROADCOM, 2090 PCI_PRODUCT_BROADCOM_BCM5721, 2091 "Broadcom BCM5721 Gigabit Ethernet", 2092 }, 2093 2094 { PCI_VENDOR_BROADCOM, 2095 PCI_PRODUCT_BROADCOM_BCM5750, 2096 "Broadcom BCM5750 Gigabit Ethernet", 2097 }, 2098 2099 { PCI_VENDOR_BROADCOM, 2100 PCI_PRODUCT_BROADCOM_BCM5750M, 2101 "Broadcom BCM5750M Gigabit Ethernet", 2102 }, 2103 2104 { PCI_VENDOR_BROADCOM, 2105 PCI_PRODUCT_BROADCOM_BCM5751, 2106 "Broadcom BCM5751 Gigabit Ethernet", 2107 }, 2108 2109 { PCI_VENDOR_BROADCOM, 2110 PCI_PRODUCT_BROADCOM_BCM5782, 2111 "Broadcom BCM5782 Gigabit Ethernet", 2112 }, 2113 { PCI_VENDOR_BROADCOM, 2114 PCI_PRODUCT_BROADCOM_BCM5788, 2115 "Broadcom BCM5788 Gigabit Ethernet", 2116 }, 2117 2118 { PCI_VENDOR_BROADCOM, 2119 PCI_PRODUCT_BROADCOM_BCM5901, 2120 "Broadcom BCM5901 Fast Ethernet", 2121 }, 2122 { PCI_VENDOR_BROADCOM, 2123 PCI_PRODUCT_BROADCOM_BCM5901A2, 2124 "Broadcom BCM5901A2 Fast Ethernet", 2125 }, 2126 2127 { PCI_VENDOR_SCHNEIDERKOCH, 2128 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 2129 "SysKonnect SK-9Dx1 Gigabit Ethernet", 2130 }, 2131 2132 { PCI_VENDOR_3COM, 2133 PCI_PRODUCT_3COM_3C996, 2134 "3Com 3c996 Gigabit Ethernet", 2135 }, 2136 2137 { 0, 2138 0, 2139 NULL }, 2140 }; 2141 2142 static const struct bge_product * 2143 bge_lookup(const struct pci_attach_args *pa) 2144 { 2145 const struct bge_product *bp; 2146 2147 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2148 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2149 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2150 return (bp); 2151 } 2152 2153 return (NULL); 2154 } 2155 2156 int 2157 bge_setpowerstate(sc, powerlevel) 2158 struct bge_softc *sc; 2159 int powerlevel; 2160 { 2161 #ifdef NOTYET 2162 u_int32_t pm_ctl = 0; 2163 2164 /* XXX FIXME: make sure indirect accesses enabled? */ 2165 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2166 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2167 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2168 2169 /* clear the PME_assert bit and power state bits, enable PME */ 2170 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2171 pm_ctl &= ~PCIM_PSTAT_DMASK; 2172 pm_ctl |= (1 << 8); 2173 2174 if (powerlevel == 0) { 2175 pm_ctl |= PCIM_PSTAT_D0; 2176 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2177 pm_ctl, 2); 2178 DELAY(10000); 2179 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2180 DELAY(10000); 2181 2182 #ifdef NOTYET 2183 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2184 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2185 #endif 2186 DELAY(40); DELAY(40); DELAY(40); 2187 DELAY(10000); /* above not quite adequate on 5700 */ 2188 return 0; 2189 } 2190 2191 2192 /* 2193 * Entering ACPI power states D1-D3 is achieved by wiggling 2194 * GMII gpio pins. Example code assumes all hardware vendors 2195 * followed Broadom's sample pcb layout. Until we verify that 2196 * for all supported OEM cards, states D1-D3 are unsupported. 2197 */ 2198 printf("%s: power state %d unimplemented; check GPIO pins\n", 2199 sc->bge_dev.dv_xname, powerlevel); 2200 #endif 2201 return EOPNOTSUPP; 2202 } 2203 2204 2205 /* 2206 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2207 * against our list and return its name if we find a match. Note 2208 * that since the Broadcom controller contains VPD support, we 2209 * can get the device name string from the controller itself instead 2210 * of the compiled-in string. This is a little slow, but it guarantees 2211 * we'll always announce the right product name. 2212 */ 2213 int 2214 bge_probe(parent, match, aux) 2215 struct device *parent; 2216 struct cfdata *match; 2217 void *aux; 2218 { 2219 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2220 2221 if (bge_lookup(pa) != NULL) 2222 return (1); 2223 2224 return (0); 2225 } 2226 2227 void 2228 bge_attach(parent, self, aux) 2229 struct device *parent, *self; 2230 void *aux; 2231 { 2232 struct bge_softc *sc = (struct bge_softc *)self; 2233 struct pci_attach_args *pa = aux; 2234 const struct bge_product *bp; 2235 const struct bge_revision *br; 2236 pci_chipset_tag_t pc = pa->pa_pc; 2237 pci_intr_handle_t ih; 2238 const char *intrstr = NULL; 2239 bus_dma_segment_t seg; 2240 int rseg; 2241 u_int32_t hwcfg = 0; 2242 u_int32_t mac_addr = 0; 2243 u_int32_t command; 2244 struct ifnet *ifp; 2245 caddr_t kva; 2246 u_char eaddr[ETHER_ADDR_LEN]; 2247 pcireg_t memtype; 2248 bus_addr_t memaddr; 2249 bus_size_t memsize; 2250 u_int32_t pm_ctl; 2251 2252 bp = bge_lookup(pa); 2253 KASSERT(bp != NULL); 2254 2255 sc->bge_pa = *pa; 2256 2257 aprint_naive(": Ethernet controller\n"); 2258 aprint_normal(": %s\n", bp->bp_name); 2259 2260 /* 2261 * Map control/status registers. 2262 */ 2263 DPRINTFN(5, ("Map control/status regs\n")); 2264 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2265 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2266 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 2267 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 2268 2269 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2270 aprint_error("%s: failed to enable memory mapping!\n", 2271 sc->bge_dev.dv_xname); 2272 return; 2273 } 2274 2275 DPRINTFN(5, ("pci_mem_find\n")); 2276 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2277 switch (memtype) { 2278 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2279 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2280 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2281 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2282 &memaddr, &memsize) == 0) 2283 break; 2284 default: 2285 aprint_error("%s: can't find mem space\n", 2286 sc->bge_dev.dv_xname); 2287 return; 2288 } 2289 2290 DPRINTFN(5, ("pci_intr_map\n")); 2291 if (pci_intr_map(pa, &ih)) { 2292 aprint_error("%s: couldn't map interrupt\n", 2293 sc->bge_dev.dv_xname); 2294 return; 2295 } 2296 2297 DPRINTFN(5, ("pci_intr_string\n")); 2298 intrstr = pci_intr_string(pc, ih); 2299 2300 DPRINTFN(5, ("pci_intr_establish\n")); 2301 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2302 2303 if (sc->bge_intrhand == NULL) { 2304 aprint_error("%s: couldn't establish interrupt", 2305 sc->bge_dev.dv_xname); 2306 if (intrstr != NULL) 2307 aprint_normal(" at %s", intrstr); 2308 aprint_normal("\n"); 2309 return; 2310 } 2311 aprint_normal("%s: interrupting at %s\n", 2312 sc->bge_dev.dv_xname, intrstr); 2313 2314 /* 2315 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2316 * can clobber the chip's PCI config-space power control registers, 2317 * leaving the card in D3 powersave state. 2318 * We do not have memory-mapped registers in this state, 2319 * so force device into D0 state before starting initialization. 2320 */ 2321 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2322 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2323 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2324 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2325 DELAY(1000); /* 27 usec is allegedly sufficent */ 2326 2327 /* 2328 * Save ASIC rev. Look up any quirks associated with this 2329 * ASIC. 2330 */ 2331 sc->bge_chipid = 2332 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) & 2333 BGE_PCIMISCCTL_ASICREV; 2334 2335 /* 2336 * Detect PCI-Express devices 2337 * XXX: guessed from Linux/FreeBSD; no documentation 2338 */ 2339 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 && 2340 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 2341 NULL, NULL) != 0) 2342 sc->bge_pcie = 1; 2343 else 2344 sc->bge_pcie = 0; 2345 2346 /* Try to reset the chip. */ 2347 DPRINTFN(5, ("bge_reset\n")); 2348 bge_reset(sc); 2349 2350 if (bge_chipinit(sc)) { 2351 aprint_error("%s: chip initialization failed\n", 2352 sc->bge_dev.dv_xname); 2353 bge_release_resources(sc); 2354 return; 2355 } 2356 2357 /* 2358 * Get station address from the EEPROM. 2359 */ 2360 mac_addr = bge_readmem_ind(sc, 0x0c14); 2361 if ((mac_addr >> 16) == 0x484b) { 2362 eaddr[0] = (u_char)(mac_addr >> 8); 2363 eaddr[1] = (u_char)(mac_addr >> 0); 2364 mac_addr = bge_readmem_ind(sc, 0x0c18); 2365 eaddr[2] = (u_char)(mac_addr >> 24); 2366 eaddr[3] = (u_char)(mac_addr >> 16); 2367 eaddr[4] = (u_char)(mac_addr >> 8); 2368 eaddr[5] = (u_char)(mac_addr >> 0); 2369 } else if (bge_read_eeprom(sc, (caddr_t)eaddr, 2370 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2371 aprint_error("%s: failed to read station address\n", 2372 sc->bge_dev.dv_xname); 2373 bge_release_resources(sc); 2374 return; 2375 } 2376 2377 br = bge_lookup_rev(sc->bge_chipid); 2378 aprint_normal("%s: ", sc->bge_dev.dv_xname); 2379 2380 if (br == NULL) { 2381 aprint_normal("unknown ASIC (0x%04x)", sc->bge_chipid >> 16); 2382 sc->bge_quirks = 0; 2383 } else { 2384 aprint_normal("ASIC %s (0x%04x)", 2385 br->br_name, sc->bge_chipid >> 16); 2386 sc->bge_quirks |= br->br_quirks; 2387 } 2388 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2389 2390 /* Allocate the general information block and ring buffers. */ 2391 if (pci_dma64_available(pa)) 2392 sc->bge_dmatag = pa->pa_dmat64; 2393 else 2394 sc->bge_dmatag = pa->pa_dmat; 2395 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2396 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2397 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2398 aprint_error("%s: can't alloc rx buffers\n", 2399 sc->bge_dev.dv_xname); 2400 return; 2401 } 2402 DPRINTFN(5, ("bus_dmamem_map\n")); 2403 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2404 sizeof(struct bge_ring_data), &kva, 2405 BUS_DMA_NOWAIT)) { 2406 aprint_error("%s: can't map DMA buffers (%d bytes)\n", 2407 sc->bge_dev.dv_xname, (int)sizeof(struct bge_ring_data)); 2408 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2409 return; 2410 } 2411 DPRINTFN(5, ("bus_dmamem_create\n")); 2412 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2413 sizeof(struct bge_ring_data), 0, 2414 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2415 aprint_error("%s: can't create DMA map\n", 2416 sc->bge_dev.dv_xname); 2417 bus_dmamem_unmap(sc->bge_dmatag, kva, 2418 sizeof(struct bge_ring_data)); 2419 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2420 return; 2421 } 2422 DPRINTFN(5, ("bus_dmamem_load\n")); 2423 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2424 sizeof(struct bge_ring_data), NULL, 2425 BUS_DMA_NOWAIT)) { 2426 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2427 bus_dmamem_unmap(sc->bge_dmatag, kva, 2428 sizeof(struct bge_ring_data)); 2429 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2430 return; 2431 } 2432 2433 DPRINTFN(5, ("bzero\n")); 2434 sc->bge_rdata = (struct bge_ring_data *)kva; 2435 2436 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2437 2438 /* Try to allocate memory for jumbo buffers. */ 2439 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2440 if (bge_alloc_jumbo_mem(sc)) { 2441 aprint_error("%s: jumbo buffer allocation failed\n", 2442 sc->bge_dev.dv_xname); 2443 } else 2444 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2445 } 2446 2447 /* Set default tuneable values. */ 2448 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2449 sc->bge_rx_coal_ticks = 150; 2450 sc->bge_rx_max_coal_bds = 64; 2451 #ifdef ORIG_WPAUL_VALUES 2452 sc->bge_tx_coal_ticks = 150; 2453 sc->bge_tx_max_coal_bds = 128; 2454 #else 2455 sc->bge_tx_coal_ticks = 300; 2456 sc->bge_tx_max_coal_bds = 400; 2457 #endif 2458 2459 /* Set up ifnet structure */ 2460 ifp = &sc->ethercom.ec_if; 2461 ifp->if_softc = sc; 2462 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2463 ifp->if_ioctl = bge_ioctl; 2464 ifp->if_start = bge_start; 2465 ifp->if_init = bge_init; 2466 ifp->if_watchdog = bge_watchdog; 2467 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2468 IFQ_SET_READY(&ifp->if_snd); 2469 DPRINTFN(5, ("bcopy\n")); 2470 strcpy(ifp->if_xname, sc->bge_dev.dv_xname); 2471 2472 if ((sc->bge_quirks & BGE_QUIRK_CSUM_BROKEN) == 0) 2473 sc->ethercom.ec_if.if_capabilities |= 2474 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2475 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2476 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2477 sc->ethercom.ec_capabilities |= 2478 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2479 2480 /* 2481 * Do MII setup. 2482 */ 2483 DPRINTFN(5, ("mii setup\n")); 2484 sc->bge_mii.mii_ifp = ifp; 2485 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2486 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2487 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2488 2489 /* 2490 * Figure out what sort of media we have by checking the 2491 * hardware config word in the first 32k of NIC internal memory, 2492 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2493 * cards, this value appears to be unset. If that's the 2494 * case, we have to rely on identifying the NIC by its PCI 2495 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2496 */ 2497 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2498 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2499 } else { 2500 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2501 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2502 hwcfg = be32toh(hwcfg); 2503 } 2504 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2505 sc->bge_tbi = 1; 2506 2507 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2508 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 2509 SK_SUBSYSID_9D41) 2510 sc->bge_tbi = 1; 2511 2512 if (sc->bge_tbi) { 2513 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2514 bge_ifmedia_sts); 2515 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2516 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2517 0, NULL); 2518 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2519 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2520 } else { 2521 /* 2522 * Do transceiver setup. 2523 */ 2524 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2525 bge_ifmedia_sts); 2526 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2527 MII_PHY_ANY, MII_OFFSET_ANY, 2528 MIIF_FORCEANEG|MIIF_DOPAUSE); 2529 2530 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2531 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2532 ifmedia_add(&sc->bge_mii.mii_media, 2533 IFM_ETHER|IFM_MANUAL, 0, NULL); 2534 ifmedia_set(&sc->bge_mii.mii_media, 2535 IFM_ETHER|IFM_MANUAL); 2536 } else 2537 ifmedia_set(&sc->bge_mii.mii_media, 2538 IFM_ETHER|IFM_AUTO); 2539 } 2540 2541 /* 2542 * When using the BCM5701 in PCI-X mode, data corruption has 2543 * been observed in the first few bytes of some received packets. 2544 * Aligning the packet buffer in memory eliminates the corruption. 2545 * Unfortunately, this misaligns the packet payloads. On platforms 2546 * which do not support unaligned accesses, we will realign the 2547 * payloads by copying the received packets. 2548 */ 2549 if (sc->bge_quirks & BGE_QUIRK_PCIX_DMA_ALIGN_BUG) { 2550 /* If in PCI-X mode, work around the alignment bug. */ 2551 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2552 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2553 BGE_PCISTATE_PCI_BUSSPEED) 2554 sc->bge_rx_alignment_bug = 1; 2555 } 2556 2557 /* 2558 * Call MI attach routine. 2559 */ 2560 DPRINTFN(5, ("if_attach\n")); 2561 if_attach(ifp); 2562 DPRINTFN(5, ("ether_ifattach\n")); 2563 ether_ifattach(ifp, eaddr); 2564 #ifdef BGE_EVENT_COUNTERS 2565 /* 2566 * Attach event counters. 2567 */ 2568 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2569 NULL, sc->bge_dev.dv_xname, "intr"); 2570 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2571 NULL, sc->bge_dev.dv_xname, "tx_xoff"); 2572 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2573 NULL, sc->bge_dev.dv_xname, "tx_xon"); 2574 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2575 NULL, sc->bge_dev.dv_xname, "rx_xoff"); 2576 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2577 NULL, sc->bge_dev.dv_xname, "rx_xon"); 2578 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2579 NULL, sc->bge_dev.dv_xname, "rx_macctl"); 2580 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2581 NULL, sc->bge_dev.dv_xname, "xoffentered"); 2582 #endif /* BGE_EVENT_COUNTERS */ 2583 DPRINTFN(5, ("callout_init\n")); 2584 callout_init(&sc->bge_timeout); 2585 2586 sc->bge_powerhook = powerhook_establish(bge_powerhook, sc); 2587 if (sc->bge_powerhook == NULL) 2588 printf("%s: WARNING: unable to establish PCI power hook\n", 2589 sc->bge_dev.dv_xname); 2590 } 2591 2592 void 2593 bge_release_resources(sc) 2594 struct bge_softc *sc; 2595 { 2596 if (sc->bge_vpd_prodname != NULL) 2597 free(sc->bge_vpd_prodname, M_DEVBUF); 2598 2599 if (sc->bge_vpd_readonly != NULL) 2600 free(sc->bge_vpd_readonly, M_DEVBUF); 2601 } 2602 2603 void 2604 bge_reset(sc) 2605 struct bge_softc *sc; 2606 { 2607 struct pci_attach_args *pa = &sc->bge_pa; 2608 u_int32_t cachesize, command, pcistate, new_pcistate; 2609 int i, val; 2610 2611 /* Save some important PCI state. */ 2612 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2613 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2614 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2615 2616 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2617 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2618 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2619 2620 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2621 /* 2622 * XXX: from FreeBSD/Linux; no documentation 2623 */ 2624 if (sc->bge_pcie) { 2625 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2626 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2627 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2628 /* No idea what that actually means */ 2629 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2630 val |= (1<<29); 2631 } 2632 } 2633 2634 /* Issue global reset */ 2635 bge_writereg_ind(sc, BGE_MISC_CFG, val); 2636 2637 DELAY(1000); 2638 2639 /* 2640 * XXX: from FreeBSD/Linux; no documentation 2641 */ 2642 if (sc->bge_pcie) { 2643 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2644 pcireg_t reg; 2645 2646 DELAY(500000); 2647 /* XXX: Magic Numbers */ 2648 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0); 2649 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN0, 2650 reg | (1 << 15)); 2651 } 2652 /* XXX: Magic Numbers */ 2653 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_UNKNOWN1, 0xf5000); 2654 } 2655 2656 /* Reset some of the PCI state that got zapped by reset */ 2657 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2658 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2659 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2660 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2661 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2662 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2663 2664 /* Enable memory arbiter. */ 2665 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2666 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2667 } 2668 2669 /* 2670 * Prevent PXE restart: write a magic number to the 2671 * general communications memory at 0xB50. 2672 */ 2673 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2674 2675 /* 2676 * Poll the value location we just wrote until 2677 * we see the 1's complement of the magic number. 2678 * This indicates that the firmware initialization 2679 * is complete. 2680 */ 2681 for (i = 0; i < 750; i++) { 2682 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2683 if (val == ~BGE_MAGIC_NUMBER) 2684 break; 2685 DELAY(1000); 2686 } 2687 2688 if (i == 750) { 2689 printf("%s: firmware handshake timed out, val = %x\n", 2690 sc->bge_dev.dv_xname, val); 2691 return; 2692 } 2693 2694 /* 2695 * XXX Wait for the value of the PCISTATE register to 2696 * return to its original pre-reset state. This is a 2697 * fairly good indicator of reset completion. If we don't 2698 * wait for the reset to fully complete, trying to read 2699 * from the device's non-PCI registers may yield garbage 2700 * results. 2701 */ 2702 for (i = 0; i < BGE_TIMEOUT; i++) { 2703 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2704 BGE_PCI_PCISTATE); 2705 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2706 (pcistate & ~BGE_PCISTATE_RESERVED)) 2707 break; 2708 DELAY(10); 2709 } 2710 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2711 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2712 printf("%s: pcistate failed to revert\n", 2713 sc->bge_dev.dv_xname); 2714 } 2715 2716 /* XXX: from FreeBSD/Linux; no documentation */ 2717 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2718 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2719 2720 /* Enable memory arbiter. */ 2721 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 2722 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2723 } 2724 2725 /* Fix up byte swapping */ 2726 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2727 2728 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2729 2730 DELAY(10000); 2731 } 2732 2733 /* 2734 * Frame reception handling. This is called if there's a frame 2735 * on the receive return list. 2736 * 2737 * Note: we have to be able to handle two possibilities here: 2738 * 1) the frame is from the jumbo recieve ring 2739 * 2) the frame is from the standard receive ring 2740 */ 2741 2742 void 2743 bge_rxeof(sc) 2744 struct bge_softc *sc; 2745 { 2746 struct ifnet *ifp; 2747 int stdcnt = 0, jumbocnt = 0; 2748 bus_dmamap_t dmamap; 2749 bus_addr_t offset, toff; 2750 bus_size_t tlen; 2751 int tosync; 2752 2753 ifp = &sc->ethercom.ec_if; 2754 2755 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2756 offsetof(struct bge_ring_data, bge_status_block), 2757 sizeof (struct bge_status_block), 2758 BUS_DMASYNC_POSTREAD); 2759 2760 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2761 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2762 sc->bge_rx_saved_considx; 2763 2764 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2765 2766 if (tosync < 0) { 2767 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2768 sizeof (struct bge_rx_bd); 2769 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2770 toff, tlen, BUS_DMASYNC_POSTREAD); 2771 tosync = -tosync; 2772 } 2773 2774 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2775 offset, tosync * sizeof (struct bge_rx_bd), 2776 BUS_DMASYNC_POSTREAD); 2777 2778 while(sc->bge_rx_saved_considx != 2779 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2780 struct bge_rx_bd *cur_rx; 2781 u_int32_t rxidx; 2782 struct mbuf *m = NULL; 2783 2784 cur_rx = &sc->bge_rdata-> 2785 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2786 2787 rxidx = cur_rx->bge_idx; 2788 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2789 2790 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2791 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2792 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2793 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2794 jumbocnt++; 2795 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2796 ifp->if_ierrors++; 2797 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2798 continue; 2799 } 2800 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2801 NULL)== ENOBUFS) { 2802 ifp->if_ierrors++; 2803 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2804 continue; 2805 } 2806 } else { 2807 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2808 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2809 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2810 stdcnt++; 2811 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2812 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2813 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2814 ifp->if_ierrors++; 2815 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2816 continue; 2817 } 2818 if (bge_newbuf_std(sc, sc->bge_std, 2819 NULL, dmamap) == ENOBUFS) { 2820 ifp->if_ierrors++; 2821 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2822 continue; 2823 } 2824 } 2825 2826 ifp->if_ipackets++; 2827 #ifndef __NO_STRICT_ALIGNMENT 2828 /* 2829 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2830 * the Rx buffer has the layer-2 header unaligned. 2831 * If our CPU requires alignment, re-align by copying. 2832 */ 2833 if (sc->bge_rx_alignment_bug) { 2834 memmove(mtod(m, caddr_t) + ETHER_ALIGN, m->m_data, 2835 cur_rx->bge_len); 2836 m->m_data += ETHER_ALIGN; 2837 } 2838 #endif 2839 2840 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2841 m->m_pkthdr.rcvif = ifp; 2842 2843 #if NBPFILTER > 0 2844 /* 2845 * Handle BPF listeners. Let the BPF user see the packet. 2846 */ 2847 if (ifp->if_bpf) 2848 bpf_mtap(ifp->if_bpf, m); 2849 #endif 2850 2851 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 2852 2853 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 2854 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2855 /* 2856 * Rx transport checksum-offload may also 2857 * have bugs with packets which, when transmitted, 2858 * were `runts' requiring padding. 2859 */ 2860 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2861 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 2862 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 2863 m->m_pkthdr.csum_data = 2864 cur_rx->bge_tcp_udp_csum; 2865 m->m_pkthdr.csum_flags |= 2866 (M_CSUM_TCPv4|M_CSUM_UDPv4| 2867 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 2868 } 2869 2870 /* 2871 * If we received a packet with a vlan tag, pass it 2872 * to vlan_input() instead of ether_input(). 2873 */ 2874 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) 2875 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 2876 2877 (*ifp->if_input)(ifp, m); 2878 } 2879 2880 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2881 if (stdcnt) 2882 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2883 if (jumbocnt) 2884 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2885 } 2886 2887 void 2888 bge_txeof(sc) 2889 struct bge_softc *sc; 2890 { 2891 struct bge_tx_bd *cur_tx = NULL; 2892 struct ifnet *ifp; 2893 struct txdmamap_pool_entry *dma; 2894 bus_addr_t offset, toff; 2895 bus_size_t tlen; 2896 int tosync; 2897 struct mbuf *m; 2898 2899 ifp = &sc->ethercom.ec_if; 2900 2901 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2902 offsetof(struct bge_ring_data, bge_status_block), 2903 sizeof (struct bge_status_block), 2904 BUS_DMASYNC_POSTREAD); 2905 2906 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2907 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2908 sc->bge_tx_saved_considx; 2909 2910 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2911 2912 if (tosync < 0) { 2913 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2914 sizeof (struct bge_tx_bd); 2915 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2916 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2917 tosync = -tosync; 2918 } 2919 2920 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2921 offset, tosync * sizeof (struct bge_tx_bd), 2922 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2923 2924 /* 2925 * Go through our tx ring and free mbufs for those 2926 * frames that have been sent. 2927 */ 2928 while (sc->bge_tx_saved_considx != 2929 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2930 u_int32_t idx = 0; 2931 2932 idx = sc->bge_tx_saved_considx; 2933 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2934 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2935 ifp->if_opackets++; 2936 m = sc->bge_cdata.bge_tx_chain[idx]; 2937 if (m != NULL) { 2938 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2939 dma = sc->txdma[idx]; 2940 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2941 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2942 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2943 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2944 sc->txdma[idx] = NULL; 2945 2946 m_freem(m); 2947 } 2948 sc->bge_txcnt--; 2949 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2950 ifp->if_timer = 0; 2951 } 2952 2953 if (cur_tx != NULL) 2954 ifp->if_flags &= ~IFF_OACTIVE; 2955 } 2956 2957 int 2958 bge_intr(xsc) 2959 void *xsc; 2960 { 2961 struct bge_softc *sc; 2962 struct ifnet *ifp; 2963 2964 sc = xsc; 2965 ifp = &sc->ethercom.ec_if; 2966 2967 #ifdef notdef 2968 /* Avoid this for now -- checking this register is expensive. */ 2969 /* Make sure this is really our interrupt. */ 2970 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2971 return (0); 2972 #endif 2973 /* Ack interrupt and stop others from occuring. */ 2974 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2975 2976 BGE_EVCNT_INCR(sc->bge_ev_intr); 2977 2978 /* 2979 * Process link state changes. 2980 * Grrr. The link status word in the status block does 2981 * not work correctly on the BCM5700 rev AX and BX chips, 2982 * according to all avaibable information. Hence, we have 2983 * to enable MII interrupts in order to properly obtain 2984 * async link changes. Unfortunately, this also means that 2985 * we have to read the MAC status register to detect link 2986 * changes, thereby adding an additional register access to 2987 * the interrupt handler. 2988 */ 2989 2990 if (sc->bge_quirks & BGE_QUIRK_LINK_STATE_BROKEN) { 2991 u_int32_t status; 2992 2993 status = CSR_READ_4(sc, BGE_MAC_STS); 2994 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2995 sc->bge_link = 0; 2996 callout_stop(&sc->bge_timeout); 2997 bge_tick(sc); 2998 /* Clear the interrupt */ 2999 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3000 BGE_EVTENB_MI_INTERRUPT); 3001 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 3002 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 3003 BRGPHY_INTRS); 3004 } 3005 } else { 3006 if (sc->bge_rdata->bge_status_block.bge_status & 3007 BGE_STATFLAG_LINKSTATE_CHANGED) { 3008 sc->bge_link = 0; 3009 callout_stop(&sc->bge_timeout); 3010 bge_tick(sc); 3011 /* Clear the interrupt */ 3012 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3013 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3014 BGE_MACSTAT_LINK_CHANGED); 3015 } 3016 } 3017 3018 if (ifp->if_flags & IFF_RUNNING) { 3019 /* Check RX return ring producer/consumer */ 3020 bge_rxeof(sc); 3021 3022 /* Check TX ring producer/consumer */ 3023 bge_txeof(sc); 3024 } 3025 3026 if (sc->bge_pending_rxintr_change) { 3027 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3028 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3029 uint32_t junk; 3030 3031 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3032 DELAY(10); 3033 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3034 3035 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3036 DELAY(10); 3037 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3038 3039 sc->bge_pending_rxintr_change = 0; 3040 } 3041 bge_handle_events(sc); 3042 3043 /* Re-enable interrupts. */ 3044 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3045 3046 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3047 bge_start(ifp); 3048 3049 return (1); 3050 } 3051 3052 void 3053 bge_tick(xsc) 3054 void *xsc; 3055 { 3056 struct bge_softc *sc = xsc; 3057 struct mii_data *mii = &sc->bge_mii; 3058 struct ifmedia *ifm = NULL; 3059 struct ifnet *ifp = &sc->ethercom.ec_if; 3060 int s; 3061 3062 s = splnet(); 3063 3064 bge_stats_update(sc); 3065 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3066 if (sc->bge_link) { 3067 splx(s); 3068 return; 3069 } 3070 3071 if (sc->bge_tbi) { 3072 ifm = &sc->bge_ifmedia; 3073 if (CSR_READ_4(sc, BGE_MAC_STS) & 3074 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3075 sc->bge_link++; 3076 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3077 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3078 bge_start(ifp); 3079 } 3080 splx(s); 3081 return; 3082 } 3083 3084 mii_tick(mii); 3085 3086 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 3087 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 3088 sc->bge_link++; 3089 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 3090 bge_start(ifp); 3091 } 3092 3093 splx(s); 3094 } 3095 3096 void 3097 bge_stats_update(sc) 3098 struct bge_softc *sc; 3099 { 3100 struct ifnet *ifp = &sc->ethercom.ec_if; 3101 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3102 bus_size_t rstats = BGE_RX_STATS; 3103 3104 #define READ_RSTAT(sc, stats, stat) \ 3105 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3106 3107 if (sc->bge_quirks & BGE_QUIRK_5705_CORE) { 3108 ifp->if_collisions += 3109 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3110 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3111 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3112 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3113 3114 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3115 READ_RSTAT(sc, rstats, outXoffSent)); 3116 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3117 READ_RSTAT(sc, rstats, outXonSent)); 3118 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3119 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3120 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3121 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3122 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3123 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3124 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3125 READ_RSTAT(sc, rstats, xoffStateEntered)); 3126 return; 3127 } 3128 3129 #undef READ_RSTAT 3130 #define READ_STAT(sc, stats, stat) \ 3131 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3132 3133 ifp->if_collisions += 3134 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3135 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3136 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3137 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3138 ifp->if_collisions; 3139 3140 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3141 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3142 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3143 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3144 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3145 READ_STAT(sc, stats, 3146 xoffPauseFramesReceived.bge_addr_lo)); 3147 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3148 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3149 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3150 READ_STAT(sc, stats, 3151 macControlFramesReceived.bge_addr_lo)); 3152 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3153 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3154 3155 #undef READ_STAT 3156 3157 #ifdef notdef 3158 ifp->if_collisions += 3159 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3160 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3161 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3162 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3163 ifp->if_collisions; 3164 #endif 3165 } 3166 3167 /* 3168 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3169 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3170 * but when such padded frames employ the bge IP/TCP checksum offload, 3171 * the hardware checksum assist gives incorrect results (possibly 3172 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3173 * If we pad such runts with zeros, the onboard checksum comes out correct. 3174 */ 3175 static __inline int 3176 bge_cksum_pad(struct mbuf *pkt) 3177 { 3178 struct mbuf *last = NULL; 3179 int padlen; 3180 3181 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3182 3183 /* if there's only the packet-header and we can pad there, use it. */ 3184 if (pkt->m_pkthdr.len == pkt->m_len && 3185 !M_READONLY(pkt) && M_TRAILINGSPACE(pkt) >= padlen) { 3186 last = pkt; 3187 } else { 3188 /* 3189 * Walk packet chain to find last mbuf. We will either 3190 * pad there, or append a new mbuf and pad it 3191 * (thus perhaps avoiding the bcm5700 dma-min bug). 3192 */ 3193 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3194 (void) 0; /* do nothing*/ 3195 } 3196 3197 /* `last' now points to last in chain. */ 3198 if (!M_READONLY(last) && M_TRAILINGSPACE(last) >= padlen) { 3199 (void) 0; /* we can pad here, in-place. */ 3200 } else { 3201 /* Allocate new empty mbuf, pad it. Compact later. */ 3202 struct mbuf *n; 3203 MGET(n, M_DONTWAIT, MT_DATA); 3204 n->m_len = 0; 3205 last->m_next = n; 3206 last = n; 3207 } 3208 } 3209 3210 #ifdef DEBUG 3211 /*KASSERT(M_WRITABLE(last), ("to-pad mbuf not writeable\n"));*/ 3212 KASSERT(M_TRAILINGSPACE(last) >= padlen /*, ("insufficient space to pad\n")*/ ); 3213 #endif 3214 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3215 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3216 last->m_len += padlen; 3217 pkt->m_pkthdr.len += padlen; 3218 return 0; 3219 } 3220 3221 /* 3222 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3223 */ 3224 static __inline int 3225 bge_compact_dma_runt(struct mbuf *pkt) 3226 { 3227 struct mbuf *m, *prev; 3228 int totlen, prevlen; 3229 3230 prev = NULL; 3231 totlen = 0; 3232 prevlen = -1; 3233 3234 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3235 int mlen = m->m_len; 3236 int shortfall = 8 - mlen ; 3237 3238 totlen += mlen; 3239 if (mlen == 0) { 3240 continue; 3241 } 3242 if (mlen >= 8) 3243 continue; 3244 3245 /* If we get here, mbuf data is too small for DMA engine. 3246 * Try to fix by shuffling data to prev or next in chain. 3247 * If that fails, do a compacting deep-copy of the whole chain. 3248 */ 3249 3250 /* Internal frag. If fits in prev, copy it there. */ 3251 if (prev && !M_READONLY(prev) && 3252 M_TRAILINGSPACE(prev) >= m->m_len) { 3253 bcopy(m->m_data, 3254 prev->m_data+prev->m_len, 3255 mlen); 3256 prev->m_len += mlen; 3257 m->m_len = 0; 3258 /* XXX stitch chain */ 3259 prev->m_next = m_free(m); 3260 m = prev; 3261 continue; 3262 } 3263 else if (m->m_next != NULL && !M_READONLY(m) && 3264 M_TRAILINGSPACE(m) >= shortfall && 3265 m->m_next->m_len >= (8 + shortfall)) { 3266 /* m is writable and have enough data in next, pull up. */ 3267 3268 bcopy(m->m_next->m_data, 3269 m->m_data+m->m_len, 3270 shortfall); 3271 m->m_len += shortfall; 3272 m->m_next->m_len -= shortfall; 3273 m->m_next->m_data += shortfall; 3274 } 3275 else if (m->m_next == NULL || 1) { 3276 /* Got a runt at the very end of the packet. 3277 * borrow data from the tail of the preceding mbuf and 3278 * update its length in-place. (The original data is still 3279 * valid, so we can do this even if prev is not writable.) 3280 */ 3281 3282 /* if we'd make prev a runt, just move all of its data. */ 3283 #ifdef DEBUG 3284 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3285 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3286 #endif 3287 if ((prev->m_len - shortfall) < 8) 3288 shortfall = prev->m_len; 3289 3290 #ifdef notyet /* just do the safe slow thing for now */ 3291 if (!M_READONLY(m)) { 3292 if (M_LEADINGSPACE(m) < shorfall) { 3293 void *m_dat; 3294 m_dat = (m->m_flags & M_PKTHDR) ? 3295 m->m_pktdat : m->dat; 3296 memmove(m_dat, mtod(m, void*), m->m_len); 3297 m->m_data = m_dat; 3298 } 3299 } else 3300 #endif /* just do the safe slow thing */ 3301 { 3302 struct mbuf * n = NULL; 3303 int newprevlen = prev->m_len - shortfall; 3304 3305 MGET(n, M_NOWAIT, MT_DATA); 3306 if (n == NULL) 3307 return ENOBUFS; 3308 KASSERT(m->m_len + shortfall < MLEN 3309 /*, 3310 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3311 3312 /* first copy the data we're stealing from prev */ 3313 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3314 3315 /* update prev->m_len accordingly */ 3316 prev->m_len -= shortfall; 3317 3318 /* copy data from runt m */ 3319 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3320 3321 /* n holds what we stole from prev, plus m */ 3322 n->m_len = shortfall + m->m_len; 3323 3324 /* stitch n into chain and free m */ 3325 n->m_next = m->m_next; 3326 prev->m_next = n; 3327 /* KASSERT(m->m_next == NULL); */ 3328 m->m_next = NULL; 3329 m_free(m); 3330 m = n; /* for continuing loop */ 3331 } 3332 } 3333 prevlen = m->m_len; 3334 } 3335 return 0; 3336 } 3337 3338 /* 3339 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3340 * pointers to descriptors. 3341 */ 3342 int 3343 bge_encap(sc, m_head, txidx) 3344 struct bge_softc *sc; 3345 struct mbuf *m_head; 3346 u_int32_t *txidx; 3347 { 3348 struct bge_tx_bd *f = NULL; 3349 u_int32_t frag, cur, cnt = 0; 3350 u_int16_t csum_flags = 0; 3351 struct txdmamap_pool_entry *dma; 3352 bus_dmamap_t dmamap; 3353 int i = 0; 3354 struct m_tag *mtag; 3355 3356 cur = frag = *txidx; 3357 3358 if (m_head->m_pkthdr.csum_flags) { 3359 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3360 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3361 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3362 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3363 } 3364 3365 /* 3366 * If we were asked to do an outboard checksum, and the NIC 3367 * has the bug where it sometimes adds in the Ethernet padding, 3368 * explicitly pad with zeros so the cksum will be correct either way. 3369 * (For now, do this for all chip versions, until newer 3370 * are confirmed to not require the workaround.) 3371 */ 3372 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3373 #ifdef notyet 3374 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3375 #endif 3376 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3377 goto check_dma_bug; 3378 3379 if (bge_cksum_pad(m_head) != 0) 3380 return ENOBUFS; 3381 3382 check_dma_bug: 3383 if (!(sc->bge_quirks & BGE_QUIRK_5700_SMALLDMA)) 3384 goto doit; 3385 /* 3386 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3387 * less than eight bytes. If we encounter a teeny mbuf 3388 * at the end of a chain, we can pad. Otherwise, copy. 3389 */ 3390 if (bge_compact_dma_runt(m_head) != 0) 3391 return ENOBUFS; 3392 3393 doit: 3394 dma = SLIST_FIRST(&sc->txdma_list); 3395 if (dma == NULL) 3396 return ENOBUFS; 3397 dmamap = dma->dmamap; 3398 3399 /* 3400 * Start packing the mbufs in this chain into 3401 * the fragment pointers. Stop when we run out 3402 * of fragments or hit the end of the mbuf chain. 3403 */ 3404 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3405 BUS_DMA_NOWAIT)) 3406 return(ENOBUFS); 3407 3408 mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head); 3409 3410 for (i = 0; i < dmamap->dm_nsegs; i++) { 3411 f = &sc->bge_rdata->bge_tx_ring[frag]; 3412 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3413 break; 3414 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3415 f->bge_len = dmamap->dm_segs[i].ds_len; 3416 f->bge_flags = csum_flags; 3417 3418 if (mtag != NULL) { 3419 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3420 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3421 } else { 3422 f->bge_vlan_tag = 0; 3423 } 3424 /* 3425 * Sanity check: avoid coming within 16 descriptors 3426 * of the end of the ring. 3427 */ 3428 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 3429 return(ENOBUFS); 3430 cur = frag; 3431 BGE_INC(frag, BGE_TX_RING_CNT); 3432 cnt++; 3433 } 3434 3435 if (i < dmamap->dm_nsegs) 3436 return ENOBUFS; 3437 3438 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3439 BUS_DMASYNC_PREWRITE); 3440 3441 if (frag == sc->bge_tx_saved_considx) 3442 return(ENOBUFS); 3443 3444 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3445 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3446 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3447 sc->txdma[cur] = dma; 3448 sc->bge_txcnt += cnt; 3449 3450 *txidx = frag; 3451 3452 return(0); 3453 } 3454 3455 /* 3456 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3457 * to the mbuf data regions directly in the transmit descriptors. 3458 */ 3459 void 3460 bge_start(ifp) 3461 struct ifnet *ifp; 3462 { 3463 struct bge_softc *sc; 3464 struct mbuf *m_head = NULL; 3465 u_int32_t prodidx = 0; 3466 int pkts = 0; 3467 3468 sc = ifp->if_softc; 3469 3470 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3471 return; 3472 3473 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3474 3475 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3476 IFQ_POLL(&ifp->if_snd, m_head); 3477 if (m_head == NULL) 3478 break; 3479 3480 #if 0 3481 /* 3482 * XXX 3483 * safety overkill. If this is a fragmented packet chain 3484 * with delayed TCP/UDP checksums, then only encapsulate 3485 * it if we have enough descriptors to handle the entire 3486 * chain at once. 3487 * (paranoia -- may not actually be needed) 3488 */ 3489 if (m_head->m_flags & M_FIRSTFRAG && 3490 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3491 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3492 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3493 ifp->if_flags |= IFF_OACTIVE; 3494 break; 3495 } 3496 } 3497 #endif 3498 3499 /* 3500 * Pack the data into the transmit ring. If we 3501 * don't have room, set the OACTIVE flag and wait 3502 * for the NIC to drain the ring. 3503 */ 3504 if (bge_encap(sc, m_head, &prodidx)) { 3505 ifp->if_flags |= IFF_OACTIVE; 3506 break; 3507 } 3508 3509 /* now we are committed to transmit the packet */ 3510 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3511 pkts++; 3512 3513 #if NBPFILTER > 0 3514 /* 3515 * If there's a BPF listener, bounce a copy of this frame 3516 * to him. 3517 */ 3518 if (ifp->if_bpf) 3519 bpf_mtap(ifp->if_bpf, m_head); 3520 #endif 3521 } 3522 if (pkts == 0) 3523 return; 3524 3525 /* Transmit */ 3526 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3527 if (sc->bge_quirks & BGE_QUIRK_PRODUCER_BUG) /* 5700 b2 errata */ 3528 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3529 3530 /* 3531 * Set a timeout in case the chip goes out to lunch. 3532 */ 3533 ifp->if_timer = 5; 3534 } 3535 3536 int 3537 bge_init(ifp) 3538 struct ifnet *ifp; 3539 { 3540 struct bge_softc *sc = ifp->if_softc; 3541 u_int16_t *m; 3542 int s, error; 3543 3544 s = splnet(); 3545 3546 ifp = &sc->ethercom.ec_if; 3547 3548 /* Cancel pending I/O and flush buffers. */ 3549 bge_stop(sc); 3550 bge_reset(sc); 3551 bge_chipinit(sc); 3552 3553 /* 3554 * Init the various state machines, ring 3555 * control blocks and firmware. 3556 */ 3557 error = bge_blockinit(sc); 3558 if (error != 0) { 3559 printf("%s: initialization error %d\n", sc->bge_dev.dv_xname, 3560 error); 3561 splx(s); 3562 return error; 3563 } 3564 3565 ifp = &sc->ethercom.ec_if; 3566 3567 /* Specify MTU. */ 3568 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3569 ETHER_HDR_LEN + ETHER_CRC_LEN); 3570 3571 /* Load our MAC address. */ 3572 m = (u_int16_t *)&(LLADDR(ifp->if_sadl)[0]); 3573 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3574 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3575 3576 /* Enable or disable promiscuous mode as needed. */ 3577 if (ifp->if_flags & IFF_PROMISC) { 3578 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3579 } else { 3580 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3581 } 3582 3583 /* Program multicast filter. */ 3584 bge_setmulti(sc); 3585 3586 /* Init RX ring. */ 3587 bge_init_rx_ring_std(sc); 3588 3589 /* Init jumbo RX ring. */ 3590 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3591 bge_init_rx_ring_jumbo(sc); 3592 3593 /* Init our RX return ring index */ 3594 sc->bge_rx_saved_considx = 0; 3595 3596 /* Init TX ring. */ 3597 bge_init_tx_ring(sc); 3598 3599 /* Turn on transmitter */ 3600 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3601 3602 /* Turn on receiver */ 3603 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3604 3605 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3606 3607 /* Tell firmware we're alive. */ 3608 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3609 3610 /* Enable host interrupts. */ 3611 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3612 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3613 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3614 3615 bge_ifmedia_upd(ifp); 3616 3617 ifp->if_flags |= IFF_RUNNING; 3618 ifp->if_flags &= ~IFF_OACTIVE; 3619 3620 splx(s); 3621 3622 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3623 3624 return 0; 3625 } 3626 3627 /* 3628 * Set media options. 3629 */ 3630 int 3631 bge_ifmedia_upd(ifp) 3632 struct ifnet *ifp; 3633 { 3634 struct bge_softc *sc = ifp->if_softc; 3635 struct mii_data *mii = &sc->bge_mii; 3636 struct ifmedia *ifm = &sc->bge_ifmedia; 3637 3638 /* If this is a 1000baseX NIC, enable the TBI port. */ 3639 if (sc->bge_tbi) { 3640 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3641 return(EINVAL); 3642 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3643 case IFM_AUTO: 3644 break; 3645 case IFM_1000_SX: 3646 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3647 BGE_CLRBIT(sc, BGE_MAC_MODE, 3648 BGE_MACMODE_HALF_DUPLEX); 3649 } else { 3650 BGE_SETBIT(sc, BGE_MAC_MODE, 3651 BGE_MACMODE_HALF_DUPLEX); 3652 } 3653 break; 3654 default: 3655 return(EINVAL); 3656 } 3657 /* XXX 802.3x flow control for 1000BASE-SX */ 3658 return(0); 3659 } 3660 3661 sc->bge_link = 0; 3662 mii_mediachg(mii); 3663 3664 return(0); 3665 } 3666 3667 /* 3668 * Report current media status. 3669 */ 3670 void 3671 bge_ifmedia_sts(ifp, ifmr) 3672 struct ifnet *ifp; 3673 struct ifmediareq *ifmr; 3674 { 3675 struct bge_softc *sc = ifp->if_softc; 3676 struct mii_data *mii = &sc->bge_mii; 3677 3678 if (sc->bge_tbi) { 3679 ifmr->ifm_status = IFM_AVALID; 3680 ifmr->ifm_active = IFM_ETHER; 3681 if (CSR_READ_4(sc, BGE_MAC_STS) & 3682 BGE_MACSTAT_TBI_PCS_SYNCHED) 3683 ifmr->ifm_status |= IFM_ACTIVE; 3684 ifmr->ifm_active |= IFM_1000_SX; 3685 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3686 ifmr->ifm_active |= IFM_HDX; 3687 else 3688 ifmr->ifm_active |= IFM_FDX; 3689 return; 3690 } 3691 3692 mii_pollstat(mii); 3693 ifmr->ifm_status = mii->mii_media_status; 3694 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 3695 sc->bge_flowflags; 3696 } 3697 3698 int 3699 bge_ioctl(ifp, command, data) 3700 struct ifnet *ifp; 3701 u_long command; 3702 caddr_t data; 3703 { 3704 struct bge_softc *sc = ifp->if_softc; 3705 struct ifreq *ifr = (struct ifreq *) data; 3706 int s, error = 0; 3707 struct mii_data *mii; 3708 3709 s = splnet(); 3710 3711 switch(command) { 3712 case SIOCSIFFLAGS: 3713 if (ifp->if_flags & IFF_UP) { 3714 /* 3715 * If only the state of the PROMISC flag changed, 3716 * then just use the 'set promisc mode' command 3717 * instead of reinitializing the entire NIC. Doing 3718 * a full re-init means reloading the firmware and 3719 * waiting for it to start up, which may take a 3720 * second or two. 3721 */ 3722 if (ifp->if_flags & IFF_RUNNING && 3723 ifp->if_flags & IFF_PROMISC && 3724 !(sc->bge_if_flags & IFF_PROMISC)) { 3725 BGE_SETBIT(sc, BGE_RX_MODE, 3726 BGE_RXMODE_RX_PROMISC); 3727 } else if (ifp->if_flags & IFF_RUNNING && 3728 !(ifp->if_flags & IFF_PROMISC) && 3729 sc->bge_if_flags & IFF_PROMISC) { 3730 BGE_CLRBIT(sc, BGE_RX_MODE, 3731 BGE_RXMODE_RX_PROMISC); 3732 } else 3733 bge_init(ifp); 3734 } else { 3735 if (ifp->if_flags & IFF_RUNNING) { 3736 bge_stop(sc); 3737 } 3738 } 3739 sc->bge_if_flags = ifp->if_flags; 3740 error = 0; 3741 break; 3742 case SIOCSIFMEDIA: 3743 /* XXX Flow control is not supported for 1000BASE-SX */ 3744 if (sc->bge_tbi) { 3745 ifr->ifr_media &= ~IFM_ETH_FMASK; 3746 sc->bge_flowflags = 0; 3747 } 3748 3749 /* Flow control requires full-duplex mode. */ 3750 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 3751 (ifr->ifr_media & IFM_FDX) == 0) { 3752 ifr->ifr_media &= ~IFM_ETH_FMASK; 3753 } 3754 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 3755 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 3756 /* We an do both TXPAUSE and RXPAUSE. */ 3757 ifr->ifr_media |= 3758 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 3759 } 3760 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 3761 } 3762 /* FALLTHROUGH */ 3763 case SIOCGIFMEDIA: 3764 if (sc->bge_tbi) { 3765 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3766 command); 3767 } else { 3768 mii = &sc->bge_mii; 3769 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3770 command); 3771 } 3772 break; 3773 default: 3774 error = ether_ioctl(ifp, command, data); 3775 if (error == ENETRESET) { 3776 if (ifp->if_flags & IFF_RUNNING) 3777 bge_setmulti(sc); 3778 error = 0; 3779 } 3780 break; 3781 } 3782 3783 splx(s); 3784 3785 return(error); 3786 } 3787 3788 void 3789 bge_watchdog(ifp) 3790 struct ifnet *ifp; 3791 { 3792 struct bge_softc *sc; 3793 3794 sc = ifp->if_softc; 3795 3796 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3797 3798 ifp->if_flags &= ~IFF_RUNNING; 3799 bge_init(ifp); 3800 3801 ifp->if_oerrors++; 3802 } 3803 3804 static void 3805 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 3806 { 3807 int i; 3808 3809 BGE_CLRBIT(sc, reg, bit); 3810 3811 for (i = 0; i < BGE_TIMEOUT; i++) { 3812 if ((CSR_READ_4(sc, reg) & bit) == 0) 3813 return; 3814 delay(100); 3815 } 3816 3817 printf("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3818 sc->bge_dev.dv_xname, (u_long) reg, bit); 3819 } 3820 3821 /* 3822 * Stop the adapter and free any mbufs allocated to the 3823 * RX and TX lists. 3824 */ 3825 void 3826 bge_stop(sc) 3827 struct bge_softc *sc; 3828 { 3829 struct ifnet *ifp = &sc->ethercom.ec_if; 3830 3831 callout_stop(&sc->bge_timeout); 3832 3833 /* 3834 * Disable all of the receiver blocks 3835 */ 3836 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3837 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3838 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3839 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3840 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3841 } 3842 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3843 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3844 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3845 3846 /* 3847 * Disable all of the transmit blocks 3848 */ 3849 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3850 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3851 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3852 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3853 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3854 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3855 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3856 } 3857 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3858 3859 /* 3860 * Shut down all of the memory managers and related 3861 * state machines. 3862 */ 3863 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3864 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3865 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3866 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3867 } 3868 3869 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3870 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3871 3872 if ((sc->bge_quirks & BGE_QUIRK_5705_CORE) == 0) { 3873 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3874 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3875 } 3876 3877 /* Disable host interrupts. */ 3878 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3879 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3880 3881 /* 3882 * Tell firmware we're shutting down. 3883 */ 3884 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3885 3886 /* Free the RX lists. */ 3887 bge_free_rx_ring_std(sc); 3888 3889 /* Free jumbo RX list. */ 3890 bge_free_rx_ring_jumbo(sc); 3891 3892 /* Free TX buffers. */ 3893 bge_free_tx_ring(sc); 3894 3895 /* 3896 * Isolate/power down the PHY. 3897 */ 3898 if (!sc->bge_tbi) 3899 mii_down(&sc->bge_mii); 3900 3901 sc->bge_link = 0; 3902 3903 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3904 3905 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3906 } 3907 3908 /* 3909 * Stop all chip I/O so that the kernel's probe routines don't 3910 * get confused by errant DMAs when rebooting. 3911 */ 3912 void 3913 bge_shutdown(xsc) 3914 void *xsc; 3915 { 3916 struct bge_softc *sc = (struct bge_softc *)xsc; 3917 3918 bge_stop(sc); 3919 bge_reset(sc); 3920 } 3921 3922 3923 static int 3924 sysctl_bge_verify(SYSCTLFN_ARGS) 3925 { 3926 int error, t; 3927 struct sysctlnode node; 3928 3929 node = *rnode; 3930 t = *(int*)rnode->sysctl_data; 3931 node.sysctl_data = &t; 3932 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3933 if (error || newp == NULL) 3934 return (error); 3935 3936 #if 0 3937 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 3938 node.sysctl_num, rnode->sysctl_num)); 3939 #endif 3940 3941 if (node.sysctl_num == bge_rxthresh_nodenum) { 3942 if (t < 0 || t >= NBGE_RX_THRESH) 3943 return (EINVAL); 3944 bge_update_all_threshes(t); 3945 } else 3946 return (EINVAL); 3947 3948 *(int*)rnode->sysctl_data = t; 3949 3950 return (0); 3951 } 3952 3953 /* 3954 * Set up sysctl(3) MIB, hw.bge.*. 3955 * 3956 * TBD condition SYSCTL_PERMANENT on being an LKM or not 3957 */ 3958 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 3959 { 3960 int rc, bge_root_num; 3961 const struct sysctlnode *node; 3962 3963 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3964 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 3965 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3966 goto err; 3967 } 3968 3969 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3970 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 3971 SYSCTL_DESCR("BGE interface controls"), 3972 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3973 goto err; 3974 } 3975 3976 bge_root_num = node->sysctl_num; 3977 3978 /* BGE Rx interrupt mitigation level */ 3979 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3980 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 3981 CTLTYPE_INT, "rx_lvl", 3982 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 3983 sysctl_bge_verify, 0, 3984 &bge_rx_thresh_lvl, 3985 0, CTL_HW, bge_root_num, CTL_CREATE, 3986 CTL_EOL)) != 0) { 3987 goto err; 3988 } 3989 3990 bge_rxthresh_nodenum = node->sysctl_num; 3991 3992 return; 3993 3994 err: 3995 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 3996 } 3997 3998 void 3999 bge_powerhook(int why, void *hdl) 4000 { 4001 struct bge_softc *sc = (struct bge_softc *)hdl; 4002 struct ifnet *ifp = &sc->ethercom.ec_if; 4003 struct pci_attach_args *pa = &(sc->bge_pa); 4004 pci_chipset_tag_t pc = pa->pa_pc; 4005 pcitag_t tag = pa->pa_tag; 4006 4007 switch (why) { 4008 case PWR_SOFTSUSPEND: 4009 case PWR_SOFTSTANDBY: 4010 bge_shutdown(sc); 4011 break; 4012 case PWR_SOFTRESUME: 4013 if (ifp->if_flags & IFF_UP) { 4014 ifp->if_flags &= ~IFF_RUNNING; 4015 bge_init(ifp); 4016 } 4017 break; 4018 case PWR_SUSPEND: 4019 case PWR_STANDBY: 4020 pci_conf_capture(pc, tag, &sc->bge_pciconf); 4021 break; 4022 case PWR_RESUME: 4023 pci_conf_restore(pc, tag, &sc->bge_pciconf); 4024 break; 4025 } 4026 4027 return; 4028 } 4029