1 /* $NetBSD: if_bge.c,v 1.162 2009/04/19 11:10:36 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl@wasabisystems.com> 44 * Jason Thorpe <thorpej@wasabisystems.com> 45 * Jonathan Stone <jonathan@dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul@windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.162 2009/04/19 11:10:36 msaitoh Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/device.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NRND > 0 105 #include <sys/rnd.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/in_var.h> 112 #include <netinet/ip.h> 113 #endif 114 115 /* Headers for TCP Segmentation Offload (TSO) */ 116 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 117 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 118 #include <netinet/ip.h> /* for struct ip */ 119 #include <netinet/tcp.h> /* for struct tcphdr */ 120 121 122 #if NBPFILTER > 0 123 #include <net/bpf.h> 124 #endif 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 #include <dev/mii/miidevs.h> 133 #include <dev/mii/brgphyreg.h> 134 135 #include <dev/pci/if_bgereg.h> 136 137 #include <uvm/uvm_extern.h> 138 139 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 140 141 142 /* 143 * Tunable thresholds for rx-side bge interrupt mitigation. 144 */ 145 146 /* 147 * The pairs of values below were obtained from empirical measurement 148 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 149 * interrupt for every N packets received, where N is, approximately, 150 * the second value (rx_max_bds) in each pair. The values are chosen 151 * such that moving from one pair to the succeeding pair was observed 152 * to roughly halve interrupt rate under sustained input packet load. 153 * The values were empirically chosen to avoid overflowing internal 154 * limits on the bcm5700: inreasing rx_ticks much beyond 600 155 * results in internal wrapping and higher interrupt rates. 156 * The limit of 46 frames was chosen to match NFS workloads. 157 * 158 * These values also work well on bcm5701, bcm5704C, and (less 159 * tested) bcm5703. On other chipsets, (including the Altima chip 160 * family), the larger values may overflow internal chip limits, 161 * leading to increasing interrupt rates rather than lower interrupt 162 * rates. 163 * 164 * Applications using heavy interrupt mitigation (interrupting every 165 * 32 or 46 frames) in both directions may need to increase the TCP 166 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 167 * full link bandwidth, due to ACKs and window updates lingering 168 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 169 */ 170 static const struct bge_load_rx_thresh { 171 int rx_ticks; 172 int rx_max_bds; } 173 bge_rx_threshes[] = { 174 { 32, 2 }, 175 { 50, 4 }, 176 { 100, 8 }, 177 { 192, 16 }, 178 { 416, 32 }, 179 { 598, 46 } 180 }; 181 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 182 183 /* XXX patchable; should be sysctl'able */ 184 static int bge_auto_thresh = 1; 185 static int bge_rx_thresh_lvl; 186 187 static int bge_rxthresh_nodenum; 188 189 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, u_int8_t[]); 190 191 static int bge_probe(device_t, cfdata_t, void *); 192 static void bge_attach(device_t, device_t, void *); 193 static void bge_release_resources(struct bge_softc *); 194 static void bge_txeof(struct bge_softc *); 195 static void bge_rxeof(struct bge_softc *); 196 197 static int bge_get_eaddr_mem(struct bge_softc *, u_int8_t[]); 198 static int bge_get_eaddr_nvram(struct bge_softc *, u_int8_t[]); 199 static int bge_get_eaddr_eeprom(struct bge_softc *, u_int8_t[]); 200 static int bge_get_eaddr(struct bge_softc *, u_int8_t[]); 201 202 static void bge_tick(void *); 203 static void bge_stats_update(struct bge_softc *); 204 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 205 206 static int bge_intr(void *); 207 static void bge_start(struct ifnet *); 208 static int bge_ioctl(struct ifnet *, u_long, void *); 209 static int bge_init(struct ifnet *); 210 static void bge_stop(struct ifnet *, int); 211 static void bge_watchdog(struct ifnet *); 212 static int bge_ifmedia_upd(struct ifnet *); 213 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 214 215 static void bge_setmulti(struct bge_softc *); 216 217 static void bge_handle_events(struct bge_softc *); 218 static int bge_alloc_jumbo_mem(struct bge_softc *); 219 #if 0 /* XXX */ 220 static void bge_free_jumbo_mem(struct bge_softc *); 221 #endif 222 static void *bge_jalloc(struct bge_softc *); 223 static void bge_jfree(struct mbuf *, void *, size_t, void *); 224 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 225 bus_dmamap_t); 226 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 227 static int bge_init_rx_ring_std(struct bge_softc *); 228 static void bge_free_rx_ring_std(struct bge_softc *); 229 static int bge_init_rx_ring_jumbo(struct bge_softc *); 230 static void bge_free_rx_ring_jumbo(struct bge_softc *); 231 static void bge_free_tx_ring(struct bge_softc *); 232 static int bge_init_tx_ring(struct bge_softc *); 233 234 static int bge_chipinit(struct bge_softc *); 235 static int bge_blockinit(struct bge_softc *); 236 static int bge_setpowerstate(struct bge_softc *, int); 237 238 static void bge_reset(struct bge_softc *); 239 static void bge_link_upd(struct bge_softc *); 240 241 #define BGE_DEBUG 242 #ifdef BGE_DEBUG 243 #define DPRINTF(x) if (bgedebug) printf x 244 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 245 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 246 int bgedebug = 0; 247 int bge_tso_debug = 0; 248 #else 249 #define DPRINTF(x) 250 #define DPRINTFN(n,x) 251 #define BGE_TSO_PRINTF(x) 252 #endif 253 254 #ifdef BGE_EVENT_COUNTERS 255 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 256 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 257 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 258 #else 259 #define BGE_EVCNT_INCR(ev) /* nothing */ 260 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 261 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 262 #endif 263 264 static const struct bge_product { 265 pci_vendor_id_t bp_vendor; 266 pci_product_id_t bp_product; 267 const char *bp_name; 268 } bge_products[] = { 269 /* 270 * The BCM5700 documentation seems to indicate that the hardware 271 * still has the Alteon vendor ID burned into it, though it 272 * should always be overridden by the value in the EEPROM. We'll 273 * check for it anyway. 274 */ 275 { PCI_VENDOR_ALTEON, 276 PCI_PRODUCT_ALTEON_BCM5700, 277 "Broadcom BCM5700 Gigabit Ethernet", 278 }, 279 { PCI_VENDOR_ALTEON, 280 PCI_PRODUCT_ALTEON_BCM5701, 281 "Broadcom BCM5701 Gigabit Ethernet", 282 }, 283 { PCI_VENDOR_ALTIMA, 284 PCI_PRODUCT_ALTIMA_AC1000, 285 "Altima AC1000 Gigabit Ethernet", 286 }, 287 { PCI_VENDOR_ALTIMA, 288 PCI_PRODUCT_ALTIMA_AC1001, 289 "Altima AC1001 Gigabit Ethernet", 290 }, 291 { PCI_VENDOR_ALTIMA, 292 PCI_PRODUCT_ALTIMA_AC9100, 293 "Altima AC9100 Gigabit Ethernet", 294 }, 295 { PCI_VENDOR_BROADCOM, 296 PCI_PRODUCT_BROADCOM_BCM5700, 297 "Broadcom BCM5700 Gigabit Ethernet", 298 }, 299 { PCI_VENDOR_BROADCOM, 300 PCI_PRODUCT_BROADCOM_BCM5701, 301 "Broadcom BCM5701 Gigabit Ethernet", 302 }, 303 { PCI_VENDOR_BROADCOM, 304 PCI_PRODUCT_BROADCOM_BCM5702, 305 "Broadcom BCM5702 Gigabit Ethernet", 306 }, 307 { PCI_VENDOR_BROADCOM, 308 PCI_PRODUCT_BROADCOM_BCM5702X, 309 "Broadcom BCM5702X Gigabit Ethernet" }, 310 { PCI_VENDOR_BROADCOM, 311 PCI_PRODUCT_BROADCOM_BCM5703, 312 "Broadcom BCM5703 Gigabit Ethernet", 313 }, 314 { PCI_VENDOR_BROADCOM, 315 PCI_PRODUCT_BROADCOM_BCM5703X, 316 "Broadcom BCM5703X Gigabit Ethernet", 317 }, 318 { PCI_VENDOR_BROADCOM, 319 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 320 "Broadcom BCM5703 Gigabit Ethernet", 321 }, 322 { PCI_VENDOR_BROADCOM, 323 PCI_PRODUCT_BROADCOM_BCM5704C, 324 "Broadcom BCM5704C Dual Gigabit Ethernet", 325 }, 326 { PCI_VENDOR_BROADCOM, 327 PCI_PRODUCT_BROADCOM_BCM5704S, 328 "Broadcom BCM5704S Dual Gigabit Ethernet", 329 }, 330 { PCI_VENDOR_BROADCOM, 331 PCI_PRODUCT_BROADCOM_BCM5705, 332 "Broadcom BCM5705 Gigabit Ethernet", 333 }, 334 { PCI_VENDOR_BROADCOM, 335 PCI_PRODUCT_BROADCOM_BCM5705K, 336 "Broadcom BCM5705K Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5705M, 340 "Broadcom BCM5705M Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 344 "Broadcom BCM5705M Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5714, 348 "Broadcom BCM5714/5715 Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5715, 352 "Broadcom BCM5714/5715 Gigabit Ethernet", 353 }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5789, 356 "Broadcom BCM5789 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5721, 360 "Broadcom BCM5721 Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5722, 364 "Broadcom BCM5722 Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5750, 368 "Broadcom BCM5750 Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5750M, 372 "Broadcom BCM5750M Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5751, 376 "Broadcom BCM5751 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5751M, 380 "Broadcom BCM5751M Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5752, 384 "Broadcom BCM5752 Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5752M, 388 "Broadcom BCM5752M Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5753, 392 "Broadcom BCM5753 Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5753M, 396 "Broadcom BCM5753M Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5754, 400 "Broadcom BCM5754 Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5754M, 404 "Broadcom BCM5754M Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5755, 408 "Broadcom BCM5755 Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5755M, 412 "Broadcom BCM5755M Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5780, 416 "Broadcom BCM5780 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5780S, 420 "Broadcom BCM5780S Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5782, 424 "Broadcom BCM5782 Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5786, 428 "Broadcom BCM5786 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5787, 432 "Broadcom BCM5787 Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5787M, 436 "Broadcom BCM5787M Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5788, 440 "Broadcom BCM5788 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5789, 444 "Broadcom BCM5789 Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5901, 448 "Broadcom BCM5901 Fast Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5901A2, 452 "Broadcom BCM5901A2 Fast Ethernet", 453 }, 454 { PCI_VENDOR_SCHNEIDERKOCH, 455 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 456 "SysKonnect SK-9Dx1 Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_3COM, 459 PCI_PRODUCT_3COM_3C996, 460 "3Com 3c996 Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5906, 464 "Broadcom BCM5906 Fast Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5906M, 468 "Broadcom BCM5906M Fast Ethernet", 469 }, 470 { 0, 471 0, 472 NULL }, 473 }; 474 475 /* 476 * XXX: how to handle variants based on 5750 and derivatives: 477 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 478 * in general behave like a 5705, except with additional quirks. 479 * This driver's current handling of the 5721 is wrong; 480 * how we map ASIC revision to "quirks" needs more thought. 481 * (defined here until the thought is done). 482 */ 483 #define BGE_IS_5714_FAMILY(sc) \ 484 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 485 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 486 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 487 488 #define BGE_IS_5750_OR_BEYOND(sc) \ 489 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 490 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 493 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \ 494 BGE_IS_5714_FAMILY(sc) ) 495 496 #define BGE_IS_5705_OR_BEYOND(sc) \ 497 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ 498 (BGE_IS_5750_OR_BEYOND(sc))) 499 500 static const struct bge_revision { 501 uint32_t br_chipid; 502 const char *br_name; 503 } bge_revisions[] = { 504 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 505 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 506 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 507 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 508 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 509 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 510 /* This is treated like a BCM5700 Bx */ 511 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 512 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 513 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 514 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 515 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 516 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 517 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 518 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 519 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 520 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 521 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 522 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 523 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 524 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 525 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 526 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 527 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 528 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 529 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 530 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 531 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 532 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 533 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 534 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 535 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 536 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 537 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 538 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 539 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 540 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 541 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 542 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 543 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 544 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 545 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 546 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 547 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 548 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 549 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 550 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 551 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 552 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 553 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 554 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 555 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 556 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 557 { 0, NULL } 558 }; 559 560 /* 561 * Some defaults for major revisions, so that newer steppings 562 * that we don't know about have a shot at working. 563 */ 564 static const struct bge_revision bge_majorrevs[] = { 565 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 566 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 567 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 568 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 569 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 570 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 571 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 572 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 573 { BGE_ASICREV_BCM5752, "unknown BCM5752 family" }, 574 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 575 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 576 /* 5754 and 5787 share the same ASIC ID */ 577 { BGE_ASICREV_BCM5787, "unknown BCM5787/5787" }, 578 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 579 { 0, NULL } 580 }; 581 582 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 583 bge_probe, bge_attach, NULL, NULL); 584 585 static u_int32_t 586 bge_readmem_ind(struct bge_softc *sc, int off) 587 { 588 pcireg_t val; 589 590 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 591 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 592 return val; 593 } 594 595 static void 596 bge_writemem_ind(struct bge_softc *sc, int off, int val) 597 { 598 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 599 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 600 } 601 602 #ifdef notdef 603 static u_int32_t 604 bge_readreg_ind(struct bge_softc *sc, int off) 605 { 606 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 607 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 608 } 609 #endif 610 611 static void 612 bge_writereg_ind(struct bge_softc *sc, int off, int val) 613 { 614 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 615 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 616 } 617 618 static void 619 bge_writemem_direct(struct bge_softc *sc, int off, int val) 620 { 621 CSR_WRITE_4(sc, off, val); 622 } 623 624 static void 625 bge_writembx(struct bge_softc *sc, int off, int val) 626 { 627 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 628 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 629 630 CSR_WRITE_4(sc, off, val); 631 } 632 633 static u_int8_t 634 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 635 { 636 u_int32_t access, byte = 0; 637 int i; 638 639 /* Lock. */ 640 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 641 for (i = 0; i < 8000; i++) { 642 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 643 break; 644 DELAY(20); 645 } 646 if (i == 8000) 647 return (1); 648 649 /* Enable access. */ 650 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 651 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 652 653 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 654 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 655 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 656 DELAY(10); 657 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 658 DELAY(10); 659 break; 660 } 661 } 662 663 if (i == BGE_TIMEOUT * 10) { 664 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 665 return (1); 666 } 667 668 /* Get result. */ 669 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 670 671 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 672 673 /* Disable access. */ 674 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 675 676 /* Unlock. */ 677 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 678 CSR_READ_4(sc, BGE_NVRAM_SWARB); 679 680 return (0); 681 } 682 683 /* 684 * Read a sequence of bytes from NVRAM. 685 */ 686 static int 687 bge_read_nvram(struct bge_softc *sc, u_int8_t *dest, int off, int cnt) 688 { 689 int err = 0, i; 690 u_int8_t byte = 0; 691 692 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 693 return (1); 694 695 for (i = 0; i < cnt; i++) { 696 err = bge_nvram_getbyte(sc, off + i, &byte); 697 if (err) 698 break; 699 *(dest + i) = byte; 700 } 701 702 return (err ? 1 : 0); 703 } 704 705 /* 706 * Read a byte of data stored in the EEPROM at address 'addr.' The 707 * BCM570x supports both the traditional bitbang interface and an 708 * auto access interface for reading the EEPROM. We use the auto 709 * access method. 710 */ 711 static u_int8_t 712 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 713 { 714 int i; 715 u_int32_t byte = 0; 716 717 /* 718 * Enable use of auto EEPROM access so we can avoid 719 * having to use the bitbang method. 720 */ 721 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 722 723 /* Reset the EEPROM, load the clock period. */ 724 CSR_WRITE_4(sc, BGE_EE_ADDR, 725 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 726 DELAY(20); 727 728 /* Issue the read EEPROM command. */ 729 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 730 731 /* Wait for completion */ 732 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 733 DELAY(10); 734 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 735 break; 736 } 737 738 if (i == BGE_TIMEOUT) { 739 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 740 return (0); 741 } 742 743 /* Get result. */ 744 byte = CSR_READ_4(sc, BGE_EE_DATA); 745 746 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 747 748 return (0); 749 } 750 751 /* 752 * Read a sequence of bytes from the EEPROM. 753 */ 754 static int 755 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 756 { 757 int err = 0, i; 758 u_int8_t byte = 0; 759 char *dest = destv; 760 761 for (i = 0; i < cnt; i++) { 762 err = bge_eeprom_getbyte(sc, off + i, &byte); 763 if (err) 764 break; 765 *(dest + i) = byte; 766 } 767 768 return (err ? 1 : 0); 769 } 770 771 static int 772 bge_miibus_readreg(device_t dev, int phy, int reg) 773 { 774 struct bge_softc *sc = device_private(dev); 775 u_int32_t val; 776 u_int32_t saved_autopoll; 777 int i; 778 779 /* 780 * Broadcom's own driver always assumes the internal 781 * PHY is at GMII address 1. On some chips, the PHY responds 782 * to accesses at all addresses, which could cause us to 783 * bogusly attach the PHY 32 times at probe type. Always 784 * restricting the lookup to address 1 is simpler than 785 * trying to figure out which chips revisions should be 786 * special-cased. 787 */ 788 if (phy != 1) 789 return (0); 790 791 /* Reading with autopolling on may trigger PCI errors */ 792 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 793 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 794 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 795 CSR_WRITE_4(sc, BGE_MI_MODE, 796 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 797 DELAY(40); 798 } 799 800 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 801 BGE_MIPHY(phy)|BGE_MIREG(reg)); 802 803 for (i = 0; i < BGE_TIMEOUT; i++) { 804 val = CSR_READ_4(sc, BGE_MI_COMM); 805 if (!(val & BGE_MICOMM_BUSY)) 806 break; 807 delay(10); 808 } 809 810 if (i == BGE_TIMEOUT) { 811 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 812 val = 0; 813 goto done; 814 } 815 816 val = CSR_READ_4(sc, BGE_MI_COMM); 817 818 done: 819 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 820 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 821 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 822 DELAY(40); 823 } 824 825 if (val & BGE_MICOMM_READFAIL) 826 return (0); 827 828 return (val & 0xFFFF); 829 } 830 831 static void 832 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 833 { 834 struct bge_softc *sc = device_private(dev); 835 u_int32_t saved_autopoll; 836 int i; 837 838 if (phy!=1) { 839 return; 840 } 841 842 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 843 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 844 return; 845 } 846 847 /* Reading with autopolling on may trigger PCI errors */ 848 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 849 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 850 delay(40); 851 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 852 CSR_WRITE_4(sc, BGE_MI_MODE, 853 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 854 delay(10); /* 40 usec is supposed to be adequate */ 855 } 856 857 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 858 BGE_MIPHY(phy) | BGE_MIREG(reg)|val); 859 860 for (i = 0; i < BGE_TIMEOUT; i++) { 861 delay(10); 862 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 863 delay(5); 864 CSR_READ_4(sc, BGE_MI_COMM); 865 break; 866 } 867 } 868 869 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 870 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 871 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 872 delay(40); 873 } 874 875 if (i == BGE_TIMEOUT) 876 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 877 } 878 879 static void 880 bge_miibus_statchg(device_t dev) 881 { 882 struct bge_softc *sc = device_private(dev); 883 struct mii_data *mii = &sc->bge_mii; 884 885 /* 886 * Get flow control negotiation result. 887 */ 888 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 889 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 890 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 891 mii->mii_media_active &= ~IFM_ETH_FMASK; 892 } 893 894 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 895 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 896 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 897 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 898 else 899 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 900 901 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 902 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 903 else 904 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 905 906 /* 907 * 802.3x flow control 908 */ 909 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 910 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 911 else 912 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 913 914 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 915 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 916 else 917 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 918 } 919 920 /* 921 * Update rx threshold levels to values in a particular slot 922 * of the interrupt-mitigation table bge_rx_threshes. 923 */ 924 static void 925 bge_set_thresh(struct ifnet *ifp, int lvl) 926 { 927 struct bge_softc *sc = ifp->if_softc; 928 int s; 929 930 /* For now, just save the new Rx-intr thresholds and record 931 * that a threshold update is pending. Updating the hardware 932 * registers here (even at splhigh()) is observed to 933 * occasionaly cause glitches where Rx-interrupts are not 934 * honoured for up to 10 seconds. jonathan@NetBSD.org, 2003-04-05 935 */ 936 s = splnet(); 937 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 938 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 939 sc->bge_pending_rxintr_change = 1; 940 splx(s); 941 942 return; 943 } 944 945 946 /* 947 * Update Rx thresholds of all bge devices 948 */ 949 static void 950 bge_update_all_threshes(int lvl) 951 { 952 struct ifnet *ifp; 953 const char * const namebuf = "bge"; 954 int namelen; 955 956 if (lvl < 0) 957 lvl = 0; 958 else if( lvl >= NBGE_RX_THRESH) 959 lvl = NBGE_RX_THRESH - 1; 960 961 namelen = strlen(namebuf); 962 /* 963 * Now search all the interfaces for this name/number 964 */ 965 IFNET_FOREACH(ifp) { 966 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 967 continue; 968 /* We got a match: update if doing auto-threshold-tuning */ 969 if (bge_auto_thresh) 970 bge_set_thresh(ifp, lvl); 971 } 972 } 973 974 /* 975 * Handle events that have triggered interrupts. 976 */ 977 static void 978 bge_handle_events(struct bge_softc *sc) 979 { 980 981 return; 982 } 983 984 /* 985 * Memory management for jumbo frames. 986 */ 987 988 static int 989 bge_alloc_jumbo_mem(struct bge_softc *sc) 990 { 991 char *ptr, *kva; 992 bus_dma_segment_t seg; 993 int i, rseg, state, error; 994 struct bge_jpool_entry *entry; 995 996 state = error = 0; 997 998 /* Grab a big chunk o' storage. */ 999 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1000 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1001 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1002 return ENOBUFS; 1003 } 1004 1005 state = 1; 1006 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1007 BUS_DMA_NOWAIT)) { 1008 aprint_error_dev(sc->bge_dev, 1009 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1010 error = ENOBUFS; 1011 goto out; 1012 } 1013 1014 state = 2; 1015 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1016 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1017 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1018 error = ENOBUFS; 1019 goto out; 1020 } 1021 1022 state = 3; 1023 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1024 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1025 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1026 error = ENOBUFS; 1027 goto out; 1028 } 1029 1030 state = 4; 1031 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1032 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1033 1034 SLIST_INIT(&sc->bge_jfree_listhead); 1035 SLIST_INIT(&sc->bge_jinuse_listhead); 1036 1037 /* 1038 * Now divide it up into 9K pieces and save the addresses 1039 * in an array. 1040 */ 1041 ptr = sc->bge_cdata.bge_jumbo_buf; 1042 for (i = 0; i < BGE_JSLOTS; i++) { 1043 sc->bge_cdata.bge_jslots[i] = ptr; 1044 ptr += BGE_JLEN; 1045 entry = malloc(sizeof(struct bge_jpool_entry), 1046 M_DEVBUF, M_NOWAIT); 1047 if (entry == NULL) { 1048 aprint_error_dev(sc->bge_dev, 1049 "no memory for jumbo buffer queue!\n"); 1050 error = ENOBUFS; 1051 goto out; 1052 } 1053 entry->slot = i; 1054 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1055 entry, jpool_entries); 1056 } 1057 out: 1058 if (error != 0) { 1059 switch (state) { 1060 case 4: 1061 bus_dmamap_unload(sc->bge_dmatag, 1062 sc->bge_cdata.bge_rx_jumbo_map); 1063 case 3: 1064 bus_dmamap_destroy(sc->bge_dmatag, 1065 sc->bge_cdata.bge_rx_jumbo_map); 1066 case 2: 1067 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1068 case 1: 1069 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1070 break; 1071 default: 1072 break; 1073 } 1074 } 1075 1076 return error; 1077 } 1078 1079 /* 1080 * Allocate a jumbo buffer. 1081 */ 1082 static void * 1083 bge_jalloc(struct bge_softc *sc) 1084 { 1085 struct bge_jpool_entry *entry; 1086 1087 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1088 1089 if (entry == NULL) { 1090 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1091 return (NULL); 1092 } 1093 1094 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1095 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1096 return (sc->bge_cdata.bge_jslots[entry->slot]); 1097 } 1098 1099 /* 1100 * Release a jumbo buffer. 1101 */ 1102 static void 1103 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1104 { 1105 struct bge_jpool_entry *entry; 1106 struct bge_softc *sc; 1107 int i, s; 1108 1109 /* Extract the softc struct pointer. */ 1110 sc = (struct bge_softc *)arg; 1111 1112 if (sc == NULL) 1113 panic("bge_jfree: can't find softc pointer!"); 1114 1115 /* calculate the slot this buffer belongs to */ 1116 1117 i = ((char *)buf 1118 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1119 1120 if ((i < 0) || (i >= BGE_JSLOTS)) 1121 panic("bge_jfree: asked to free buffer that we don't manage!"); 1122 1123 s = splvm(); 1124 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1125 if (entry == NULL) 1126 panic("bge_jfree: buffer not in use!"); 1127 entry->slot = i; 1128 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1129 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1130 1131 if (__predict_true(m != NULL)) 1132 pool_cache_put(mb_cache, m); 1133 splx(s); 1134 } 1135 1136 1137 /* 1138 * Intialize a standard receive ring descriptor. 1139 */ 1140 static int 1141 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1142 { 1143 struct mbuf *m_new = NULL; 1144 struct bge_rx_bd *r; 1145 int error; 1146 1147 if (dmamap == NULL) { 1148 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1149 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1150 if (error != 0) 1151 return error; 1152 } 1153 1154 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1155 1156 if (m == NULL) { 1157 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1158 if (m_new == NULL) 1159 return (ENOBUFS); 1160 1161 MCLGET(m_new, M_DONTWAIT); 1162 if (!(m_new->m_flags & M_EXT)) { 1163 m_freem(m_new); 1164 return (ENOBUFS); 1165 } 1166 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1167 1168 } else { 1169 m_new = m; 1170 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1171 m_new->m_data = m_new->m_ext.ext_buf; 1172 } 1173 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1174 m_adj(m_new, ETHER_ALIGN); 1175 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1176 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1177 return (ENOBUFS); 1178 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1179 BUS_DMASYNC_PREREAD); 1180 1181 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1182 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1183 bge_set_hostaddr(&r->bge_addr, 1184 dmamap->dm_segs[0].ds_addr); 1185 r->bge_flags = BGE_RXBDFLAG_END; 1186 r->bge_len = m_new->m_len; 1187 r->bge_idx = i; 1188 1189 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1190 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1191 i * sizeof (struct bge_rx_bd), 1192 sizeof (struct bge_rx_bd), 1193 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1194 1195 return (0); 1196 } 1197 1198 /* 1199 * Initialize a jumbo receive ring descriptor. This allocates 1200 * a jumbo buffer from the pool managed internally by the driver. 1201 */ 1202 static int 1203 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1204 { 1205 struct mbuf *m_new = NULL; 1206 struct bge_rx_bd *r; 1207 void *buf = NULL; 1208 1209 if (m == NULL) { 1210 1211 /* Allocate the mbuf. */ 1212 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1213 if (m_new == NULL) 1214 return (ENOBUFS); 1215 1216 /* Allocate the jumbo buffer */ 1217 buf = bge_jalloc(sc); 1218 if (buf == NULL) { 1219 m_freem(m_new); 1220 aprint_error_dev(sc->bge_dev, 1221 "jumbo allocation failed -- packet dropped!\n"); 1222 return (ENOBUFS); 1223 } 1224 1225 /* Attach the buffer to the mbuf. */ 1226 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1227 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1228 bge_jfree, sc); 1229 m_new->m_flags |= M_EXT_RW; 1230 } else { 1231 m_new = m; 1232 buf = m_new->m_data = m_new->m_ext.ext_buf; 1233 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1234 } 1235 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1236 m_adj(m_new, ETHER_ALIGN); 1237 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1238 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1239 BUS_DMASYNC_PREREAD); 1240 /* Set up the descriptor. */ 1241 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1242 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1243 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1244 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1245 r->bge_len = m_new->m_len; 1246 r->bge_idx = i; 1247 1248 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1249 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1250 i * sizeof (struct bge_rx_bd), 1251 sizeof (struct bge_rx_bd), 1252 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1253 1254 return (0); 1255 } 1256 1257 /* 1258 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1259 * that's 1MB or memory, which is a lot. For now, we fill only the first 1260 * 256 ring entries and hope that our CPU is fast enough to keep up with 1261 * the NIC. 1262 */ 1263 static int 1264 bge_init_rx_ring_std(struct bge_softc *sc) 1265 { 1266 int i; 1267 1268 if (sc->bge_flags & BGE_RXRING_VALID) 1269 return 0; 1270 1271 for (i = 0; i < BGE_SSLOTS; i++) { 1272 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1273 return (ENOBUFS); 1274 } 1275 1276 sc->bge_std = i - 1; 1277 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1278 1279 sc->bge_flags |= BGE_RXRING_VALID; 1280 1281 return (0); 1282 } 1283 1284 static void 1285 bge_free_rx_ring_std(struct bge_softc *sc) 1286 { 1287 int i; 1288 1289 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1290 return; 1291 1292 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1293 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1294 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1295 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1296 bus_dmamap_destroy(sc->bge_dmatag, 1297 sc->bge_cdata.bge_rx_std_map[i]); 1298 } 1299 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1300 sizeof(struct bge_rx_bd)); 1301 } 1302 1303 sc->bge_flags &= ~BGE_RXRING_VALID; 1304 } 1305 1306 static int 1307 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1308 { 1309 int i; 1310 volatile struct bge_rcb *rcb; 1311 1312 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1313 return 0; 1314 1315 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1316 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1317 return (ENOBUFS); 1318 }; 1319 1320 sc->bge_jumbo = i - 1; 1321 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1322 1323 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1324 rcb->bge_maxlen_flags = 0; 1325 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1326 1327 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1328 1329 return (0); 1330 } 1331 1332 static void 1333 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1334 { 1335 int i; 1336 1337 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1338 return; 1339 1340 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1341 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1342 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1343 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1344 } 1345 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1346 sizeof(struct bge_rx_bd)); 1347 } 1348 1349 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1350 } 1351 1352 static void 1353 bge_free_tx_ring(struct bge_softc *sc) 1354 { 1355 int i, freed; 1356 struct txdmamap_pool_entry *dma; 1357 1358 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1359 return; 1360 1361 freed = 0; 1362 1363 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1364 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1365 freed++; 1366 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1367 sc->bge_cdata.bge_tx_chain[i] = NULL; 1368 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1369 link); 1370 sc->txdma[i] = 0; 1371 } 1372 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1373 sizeof(struct bge_tx_bd)); 1374 } 1375 1376 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1377 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1378 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1379 free(dma, M_DEVBUF); 1380 } 1381 1382 sc->bge_flags &= ~BGE_TXRING_VALID; 1383 } 1384 1385 static int 1386 bge_init_tx_ring(struct bge_softc *sc) 1387 { 1388 int i; 1389 bus_dmamap_t dmamap; 1390 struct txdmamap_pool_entry *dma; 1391 1392 if (sc->bge_flags & BGE_TXRING_VALID) 1393 return 0; 1394 1395 sc->bge_txcnt = 0; 1396 sc->bge_tx_saved_considx = 0; 1397 1398 /* Initialize transmit producer index for host-memory send ring. */ 1399 sc->bge_tx_prodidx = 0; 1400 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1401 /* 5700 b2 errata */ 1402 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1403 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1404 1405 /* NIC-memory send ring not used; initialize to zero. */ 1406 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1407 /* 5700 b2 errata */ 1408 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1409 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1410 1411 SLIST_INIT(&sc->txdma_list); 1412 for (i = 0; i < BGE_RSLOTS; i++) { 1413 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1414 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1415 &dmamap)) 1416 return (ENOBUFS); 1417 if (dmamap == NULL) 1418 panic("dmamap NULL in bge_init_tx_ring"); 1419 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1420 if (dma == NULL) { 1421 aprint_error_dev(sc->bge_dev, 1422 "can't alloc txdmamap_pool_entry\n"); 1423 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1424 return (ENOMEM); 1425 } 1426 dma->dmamap = dmamap; 1427 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1428 } 1429 1430 sc->bge_flags |= BGE_TXRING_VALID; 1431 1432 return (0); 1433 } 1434 1435 static void 1436 bge_setmulti(struct bge_softc *sc) 1437 { 1438 struct ethercom *ac = &sc->ethercom; 1439 struct ifnet *ifp = &ac->ec_if; 1440 struct ether_multi *enm; 1441 struct ether_multistep step; 1442 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1443 u_int32_t h; 1444 int i; 1445 1446 if (ifp->if_flags & IFF_PROMISC) 1447 goto allmulti; 1448 1449 /* Now program new ones. */ 1450 ETHER_FIRST_MULTI(step, ac, enm); 1451 while (enm != NULL) { 1452 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1453 /* 1454 * We must listen to a range of multicast addresses. 1455 * For now, just accept all multicasts, rather than 1456 * trying to set only those filter bits needed to match 1457 * the range. (At this time, the only use of address 1458 * ranges is for IP multicast routing, for which the 1459 * range is big enough to require all bits set.) 1460 */ 1461 goto allmulti; 1462 } 1463 1464 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1465 1466 /* Just want the 7 least-significant bits. */ 1467 h &= 0x7f; 1468 1469 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1470 ETHER_NEXT_MULTI(step, enm); 1471 } 1472 1473 ifp->if_flags &= ~IFF_ALLMULTI; 1474 goto setit; 1475 1476 allmulti: 1477 ifp->if_flags |= IFF_ALLMULTI; 1478 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1479 1480 setit: 1481 for (i = 0; i < 4; i++) 1482 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1483 } 1484 1485 const int bge_swapbits[] = { 1486 0, 1487 BGE_MODECTL_BYTESWAP_DATA, 1488 BGE_MODECTL_WORDSWAP_DATA, 1489 BGE_MODECTL_BYTESWAP_NONFRAME, 1490 BGE_MODECTL_WORDSWAP_NONFRAME, 1491 1492 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1493 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1494 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1495 1496 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1497 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1498 1499 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1500 1501 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1502 BGE_MODECTL_BYTESWAP_NONFRAME, 1503 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1504 BGE_MODECTL_WORDSWAP_NONFRAME, 1505 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1506 BGE_MODECTL_WORDSWAP_NONFRAME, 1507 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1508 BGE_MODECTL_WORDSWAP_NONFRAME, 1509 1510 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1511 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1512 }; 1513 1514 int bge_swapindex = 0; 1515 1516 /* 1517 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1518 * self-test results. 1519 */ 1520 static int 1521 bge_chipinit(struct bge_softc *sc) 1522 { 1523 u_int32_t cachesize; 1524 int i; 1525 u_int32_t dma_rw_ctl; 1526 1527 1528 /* Set endianness before we access any non-PCI registers. */ 1529 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1530 BGE_INIT); 1531 1532 /* Set power state to D0. */ 1533 bge_setpowerstate(sc, 0); 1534 1535 /* 1536 * Check the 'ROM failed' bit on the RX CPU to see if 1537 * self-tests passed. 1538 */ 1539 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1540 aprint_error_dev(sc->bge_dev, 1541 "RX CPU self-diagnostics failed!\n"); 1542 return (ENODEV); 1543 } 1544 1545 /* Clear the MAC control register */ 1546 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1547 1548 /* 1549 * Clear the MAC statistics block in the NIC's 1550 * internal memory. 1551 */ 1552 for (i = BGE_STATS_BLOCK; 1553 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1554 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1555 1556 for (i = BGE_STATUS_BLOCK; 1557 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1558 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1559 1560 /* Set up the PCI DMA control register. */ 1561 if (sc->bge_flags & BGE_PCIE) { 1562 u_int32_t device_ctl; 1563 1564 /* From FreeBSD */ 1565 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1566 device_xname(sc->bge_dev))); 1567 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1568 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1569 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1570 1571 /* jonathan: alternative from Linux driver */ 1572 #define DMA_CTRL_WRITE_PCIE_H20MARK_128 0x00180000 1573 #define DMA_CTRL_WRITE_PCIE_H20MARK_256 0x00380000 1574 1575 dma_rw_ctl = 0x76000000; /* XXX XXX XXX */; 1576 device_ctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 1577 BGE_PCI_CONF_DEV_CTRL); 1578 aprint_debug_dev(sc->bge_dev, "pcie mode=0x%x\n", device_ctl); 1579 1580 if ((device_ctl & 0x00e0) && 0) { 1581 /* 1582 * XXX jonathan@NetBSD.org: 1583 * This clause is exactly what the Broadcom-supplied 1584 * Linux does; but given overall register programming 1585 * by if_bge(4), this larger DMA-write watermark 1586 * value causes bcm5721 chips to totally wedge. 1587 */ 1588 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256; 1589 } else { 1590 dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128; 1591 } 1592 } else if (sc->bge_flags & BGE_PCIX){ 1593 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1594 device_xname(sc->bge_dev))); 1595 /* PCI-X bus */ 1596 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1597 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1598 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1599 (0x0F); 1600 /* 1601 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1602 * for hardware bugs, which means we should also clear 1603 * the low-order MINDMA bits. In addition, the 5704 1604 * uses a different encoding of read/write watermarks. 1605 */ 1606 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1607 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1608 /* should be 0x1f0000 */ 1609 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1610 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1611 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1612 } 1613 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1614 dma_rw_ctl &= 0xfffffff0; 1615 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1616 } 1617 else if (BGE_IS_5714_FAMILY(sc)) { 1618 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1619 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1620 /* XXX magic values, Broadcom-supplied Linux driver */ 1621 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1622 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1623 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1624 else 1625 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1626 } 1627 } else { 1628 /* Conventional PCI bus */ 1629 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1630 device_xname(sc->bge_dev))); 1631 dma_rw_ctl = (BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1632 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1633 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT)); 1634 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1635 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1636 dma_rw_ctl |= 0x0F; 1637 } 1638 1639 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1640 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1641 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1642 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1643 1644 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1646 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1647 1648 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1649 1650 /* 1651 * Set up general mode register. 1652 */ 1653 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1654 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1655 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1656 1657 /* Get cache line size. */ 1658 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 1659 1660 /* 1661 * Avoid violating PCI spec on certain chip revs. 1662 */ 1663 if (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD) & 1664 PCIM_CMD_MWIEN) { 1665 switch(cachesize) { 1666 case 1: 1667 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1668 BGE_PCI_WRITE_BNDRY_16BYTES); 1669 break; 1670 case 2: 1671 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1672 BGE_PCI_WRITE_BNDRY_32BYTES); 1673 break; 1674 case 4: 1675 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1676 BGE_PCI_WRITE_BNDRY_64BYTES); 1677 break; 1678 case 8: 1679 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1680 BGE_PCI_WRITE_BNDRY_128BYTES); 1681 break; 1682 case 16: 1683 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1684 BGE_PCI_WRITE_BNDRY_256BYTES); 1685 break; 1686 case 32: 1687 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1688 BGE_PCI_WRITE_BNDRY_512BYTES); 1689 break; 1690 case 64: 1691 PCI_SETBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1692 BGE_PCI_WRITE_BNDRY_1024BYTES); 1693 break; 1694 default: 1695 /* Disable PCI memory write and invalidate. */ 1696 #if 0 1697 if (bootverbose) 1698 aprint_error_dev(sc->bge_dev, 1699 "cache line size %d not supported " 1700 "disabling PCI MWI\n", 1701 #endif 1702 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, 1703 PCIM_CMD_MWIEN); 1704 break; 1705 } 1706 } 1707 1708 /* 1709 * Disable memory write invalidate. Apparently it is not supported 1710 * properly by these devices. 1711 */ 1712 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1713 1714 1715 #ifdef __brokenalpha__ 1716 /* 1717 * Must insure that we do not cross an 8K (bytes) boundary 1718 * for DMA reads. Our highest limit is 1K bytes. This is a 1719 * restriction on some ALPHA platforms with early revision 1720 * 21174 PCI chipsets, such as the AlphaPC 164lx 1721 */ 1722 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1723 #endif 1724 1725 /* Set the timer prescaler (always 66MHz) */ 1726 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1727 1728 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1729 DELAY(40); /* XXX */ 1730 1731 /* Put PHY into ready state */ 1732 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1733 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1734 DELAY(40); 1735 } 1736 1737 return (0); 1738 } 1739 1740 static int 1741 bge_blockinit(struct bge_softc *sc) 1742 { 1743 volatile struct bge_rcb *rcb; 1744 bus_size_t rcb_addr; 1745 int i; 1746 struct ifnet *ifp = &sc->ethercom.ec_if; 1747 bge_hostaddr taddr; 1748 u_int32_t val; 1749 1750 /* 1751 * Initialize the memory window pointer register so that 1752 * we can access the first 32K of internal NIC RAM. This will 1753 * allow us to set up the TX send ring RCBs and the RX return 1754 * ring RCBs, plus other things which live in NIC memory. 1755 */ 1756 1757 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1758 1759 /* Configure mbuf memory pool */ 1760 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1761 if (sc->bge_extram) { 1762 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1763 BGE_EXT_SSRAM); 1764 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1765 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1766 else 1767 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1768 } else { 1769 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1770 BGE_BUFFPOOL_1); 1771 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1772 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1773 else 1774 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1775 } 1776 1777 /* Configure DMA resource pool */ 1778 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1779 BGE_DMA_DESCRIPTORS); 1780 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1781 } 1782 1783 /* Configure mbuf pool watermarks */ 1784 #ifdef ORIG_WPAUL_VALUES 1785 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1786 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1787 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1788 #else 1789 1790 /* new broadcom docs strongly recommend these: */ 1791 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1792 if (ifp->if_mtu > ETHER_MAX_LEN) { 1793 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1794 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1795 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1796 } else { 1797 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1798 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1799 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1800 } 1801 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1802 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1803 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1804 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1805 } else { 1806 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1807 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1808 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1809 } 1810 #endif 1811 1812 /* Configure DMA resource watermarks */ 1813 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1814 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1815 1816 /* Enable buffer manager */ 1817 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1818 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1819 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1820 1821 /* Poll for buffer manager start indication */ 1822 for (i = 0; i < BGE_TIMEOUT; i++) { 1823 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1824 break; 1825 DELAY(10); 1826 } 1827 1828 if (i == BGE_TIMEOUT) { 1829 aprint_error_dev(sc->bge_dev, 1830 "buffer manager failed to start\n"); 1831 return (ENXIO); 1832 } 1833 } 1834 1835 /* Enable flow-through queues */ 1836 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1837 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1838 1839 /* Wait until queue initialization is complete */ 1840 for (i = 0; i < BGE_TIMEOUT; i++) { 1841 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1842 break; 1843 DELAY(10); 1844 } 1845 1846 if (i == BGE_TIMEOUT) { 1847 aprint_error_dev(sc->bge_dev, 1848 "flow-through queue init failed\n"); 1849 return (ENXIO); 1850 } 1851 1852 /* Initialize the standard RX ring control block */ 1853 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1854 bge_set_hostaddr(&rcb->bge_hostaddr, 1855 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1856 if (BGE_IS_5705_OR_BEYOND(sc)) 1857 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1858 else 1859 rcb->bge_maxlen_flags = 1860 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1861 if (sc->bge_extram) 1862 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1863 else 1864 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1865 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1866 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1867 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1868 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1869 1870 if (BGE_IS_5705_OR_BEYOND(sc)) 1871 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1872 else 1873 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1874 1875 /* 1876 * Initialize the jumbo RX ring control block 1877 * We set the 'ring disabled' bit in the flags 1878 * field until we're actually ready to start 1879 * using this ring (i.e. once we set the MTU 1880 * high enough to require it). 1881 */ 1882 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1883 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1884 bge_set_hostaddr(&rcb->bge_hostaddr, 1885 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1886 rcb->bge_maxlen_flags = 1887 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1888 BGE_RCB_FLAG_RING_DISABLED); 1889 if (sc->bge_extram) 1890 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1891 else 1892 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1893 1894 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1895 rcb->bge_hostaddr.bge_addr_hi); 1896 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1897 rcb->bge_hostaddr.bge_addr_lo); 1898 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1899 rcb->bge_maxlen_flags); 1900 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1901 1902 /* Set up dummy disabled mini ring RCB */ 1903 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1904 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1905 BGE_RCB_FLAG_RING_DISABLED); 1906 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1907 rcb->bge_maxlen_flags); 1908 1909 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1910 offsetof(struct bge_ring_data, bge_info), 1911 sizeof (struct bge_gib), 1912 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1913 } 1914 1915 /* 1916 * Set the BD ring replenish thresholds. The recommended 1917 * values are 1/8th the number of descriptors allocated to 1918 * each ring. 1919 */ 1920 i = BGE_STD_RX_RING_CNT / 8; 1921 1922 /* 1923 * Use a value of 8 for the following chips to workaround HW errata. 1924 * Some of these chips have been added based on empirical 1925 * evidence (they don't work unless this is done). 1926 */ 1927 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1928 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1929 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1930 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1931 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 1932 i = 8; 1933 1934 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1935 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 1936 1937 /* 1938 * Disable all unused send rings by setting the 'ring disabled' 1939 * bit in the flags field of all the TX send ring control blocks. 1940 * These are located in NIC memory. 1941 */ 1942 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1943 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1944 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1945 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1946 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1947 rcb_addr += sizeof(struct bge_rcb); 1948 } 1949 1950 /* Configure TX RCB 0 (we use only the first ring) */ 1951 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1952 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1953 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1954 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1955 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1956 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1957 if (!(BGE_IS_5705_OR_BEYOND(sc))) 1958 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1959 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1960 1961 /* Disable all unused RX return rings */ 1962 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1963 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1964 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1965 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1966 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1967 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1968 BGE_RCB_FLAG_RING_DISABLED)); 1969 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1970 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1971 (i * (sizeof(u_int64_t))), 0); 1972 rcb_addr += sizeof(struct bge_rcb); 1973 } 1974 1975 /* Initialize RX ring indexes */ 1976 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1977 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1978 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1979 1980 /* 1981 * Set up RX return ring 0 1982 * Note that the NIC address for RX return rings is 0x00000000. 1983 * The return rings live entirely within the host, so the 1984 * nicaddr field in the RCB isn't used. 1985 */ 1986 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1987 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1988 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1989 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1990 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1991 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1992 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1993 1994 /* Set random backoff seed for TX */ 1995 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1996 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1997 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1998 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1999 BGE_TX_BACKOFF_SEED_MASK); 2000 2001 /* Set inter-packet gap */ 2002 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2003 2004 /* 2005 * Specify which ring to use for packets that don't match 2006 * any RX rules. 2007 */ 2008 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2009 2010 /* 2011 * Configure number of RX lists. One interrupt distribution 2012 * list, sixteen active lists, one bad frames class. 2013 */ 2014 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2015 2016 /* Inialize RX list placement stats mask. */ 2017 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2018 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2019 2020 /* Disable host coalescing until we get it set up */ 2021 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2022 2023 /* Poll to make sure it's shut down. */ 2024 for (i = 0; i < BGE_TIMEOUT; i++) { 2025 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2026 break; 2027 DELAY(10); 2028 } 2029 2030 if (i == BGE_TIMEOUT) { 2031 aprint_error_dev(sc->bge_dev, 2032 "host coalescing engine failed to idle\n"); 2033 return (ENXIO); 2034 } 2035 2036 /* Set up host coalescing defaults */ 2037 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2038 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2039 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2040 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2041 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2042 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2043 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2044 } 2045 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2046 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2047 2048 /* Set up address of statistics block */ 2049 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2050 bge_set_hostaddr(&taddr, 2051 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2052 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2053 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2054 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2055 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2056 } 2057 2058 /* Set up address of status block */ 2059 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2060 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2061 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2062 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2063 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2064 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2065 2066 /* Turn on host coalescing state machine */ 2067 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2068 2069 /* Turn on RX BD completion state machine and enable attentions */ 2070 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2071 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2072 2073 /* Turn on RX list placement state machine */ 2074 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2075 2076 /* Turn on RX list selector state machine. */ 2077 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2078 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2079 2080 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2081 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2082 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2083 BGE_MACMODE_FRMHDR_DMA_ENB; 2084 2085 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2086 val |= BGE_PORTMODE_TBI; 2087 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2088 val |= BGE_PORTMODE_GMII; 2089 else 2090 val |= BGE_PORTMODE_MII; 2091 2092 /* Turn on DMA, clear stats */ 2093 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2094 2095 2096 /* Set misc. local control, enable interrupts on attentions */ 2097 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2098 2099 #ifdef notdef 2100 /* Assert GPIO pins for PHY reset */ 2101 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2102 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2103 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2104 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2105 #endif 2106 2107 #if defined(not_quite_yet) 2108 /* Linux driver enables enable gpio pin #1 on 5700s */ 2109 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2110 sc->bge_local_ctrl_reg |= 2111 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2112 } 2113 #endif 2114 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2115 2116 /* Turn on DMA completion state machine */ 2117 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2118 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2119 2120 /* Turn on write DMA state machine */ 2121 { 2122 uint32_t bge_wdma_mode = 2123 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2124 2125 /* Enable host coalescing bug fix; see Linux tg3.c */ 2126 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2127 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2128 bge_wdma_mode |= (1 << 29); 2129 2130 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2131 } 2132 2133 /* Turn on read DMA state machine */ 2134 { 2135 uint32_t dma_read_modebits; 2136 2137 dma_read_modebits = 2138 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2139 2140 if ((sc->bge_flags & BGE_PCIE) && 0) { 2141 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2142 } else if (BGE_IS_5705_OR_BEYOND(sc)) { 2143 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 2144 } 2145 2146 /* XXX broadcom-supplied linux driver; undocumented */ 2147 if (BGE_IS_5750_OR_BEYOND(sc)) { 2148 /* 2149 * XXX: magic values. 2150 * From Broadcom-supplied Linux driver; apparently 2151 * required to workaround a DMA bug affecting TSO 2152 * on bcm575x/bcm5721? 2153 */ 2154 dma_read_modebits |= (1 << 27); 2155 } 2156 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2157 } 2158 2159 /* Turn on RX data completion state machine */ 2160 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2161 2162 /* Turn on RX BD initiator state machine */ 2163 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2164 2165 /* Turn on RX data and RX BD initiator state machine */ 2166 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2167 2168 /* Turn on Mbuf cluster free state machine */ 2169 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2170 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2171 2172 /* Turn on send BD completion state machine */ 2173 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2174 2175 /* Turn on send data completion state machine */ 2176 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2177 2178 /* Turn on send data initiator state machine */ 2179 if (BGE_IS_5750_OR_BEYOND(sc)) { 2180 /* XXX: magic value from Linux driver */ 2181 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2182 } else { 2183 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2184 } 2185 2186 /* Turn on send BD initiator state machine */ 2187 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2188 2189 /* Turn on send BD selector state machine */ 2190 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2191 2192 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2193 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2194 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2195 2196 /* ack/clear link change events */ 2197 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2198 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2199 BGE_MACSTAT_CFG_CHANGED); 2200 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2201 2202 /* Enable PHY auto polling (for MII/GMII only) */ 2203 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2204 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2205 } else { 2206 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2207 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2208 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2209 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2210 BGE_EVTENB_MI_INTERRUPT); 2211 } 2212 2213 /* 2214 * Clear any pending link state attention. 2215 * Otherwise some link state change events may be lost until attention 2216 * is cleared by bge_intr() -> bge_link_upd() sequence. 2217 * It's not necessary on newer BCM chips - perhaps enabling link 2218 * state change attentions implies clearing pending attention. 2219 */ 2220 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2221 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2222 BGE_MACSTAT_LINK_CHANGED); 2223 2224 /* Enable link state change attentions. */ 2225 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2226 2227 return (0); 2228 } 2229 2230 static const struct bge_revision * 2231 bge_lookup_rev(uint32_t chipid) 2232 { 2233 const struct bge_revision *br; 2234 2235 for (br = bge_revisions; br->br_name != NULL; br++) { 2236 if (br->br_chipid == chipid) 2237 return (br); 2238 } 2239 2240 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2241 if (br->br_chipid == BGE_ASICREV(chipid)) 2242 return (br); 2243 } 2244 2245 return (NULL); 2246 } 2247 2248 static const struct bge_product * 2249 bge_lookup(const struct pci_attach_args *pa) 2250 { 2251 const struct bge_product *bp; 2252 2253 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2254 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2255 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2256 return (bp); 2257 } 2258 2259 return (NULL); 2260 } 2261 2262 static int 2263 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2264 { 2265 #ifdef NOTYET 2266 u_int32_t pm_ctl = 0; 2267 2268 /* XXX FIXME: make sure indirect accesses enabled? */ 2269 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2270 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2271 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2272 2273 /* clear the PME_assert bit and power state bits, enable PME */ 2274 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2275 pm_ctl &= ~PCIM_PSTAT_DMASK; 2276 pm_ctl |= (1 << 8); 2277 2278 if (powerlevel == 0) { 2279 pm_ctl |= PCIM_PSTAT_D0; 2280 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2281 pm_ctl, 2); 2282 DELAY(10000); 2283 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2284 DELAY(10000); 2285 2286 #ifdef NOTYET 2287 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2288 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2289 #endif 2290 DELAY(40); DELAY(40); DELAY(40); 2291 DELAY(10000); /* above not quite adequate on 5700 */ 2292 return 0; 2293 } 2294 2295 2296 /* 2297 * Entering ACPI power states D1-D3 is achieved by wiggling 2298 * GMII gpio pins. Example code assumes all hardware vendors 2299 * followed Broadom's sample pcb layout. Until we verify that 2300 * for all supported OEM cards, states D1-D3 are unsupported. 2301 */ 2302 aprint_error_dev(sc->bge_dev, 2303 "power state %d unimplemented; check GPIO pins\n", 2304 powerlevel); 2305 #endif 2306 return EOPNOTSUPP; 2307 } 2308 2309 2310 /* 2311 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2312 * against our list and return its name if we find a match. Note 2313 * that since the Broadcom controller contains VPD support, we 2314 * can get the device name string from the controller itself instead 2315 * of the compiled-in string. This is a little slow, but it guarantees 2316 * we'll always announce the right product name. 2317 */ 2318 static int 2319 bge_probe(device_t parent, cfdata_t match, void *aux) 2320 { 2321 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2322 2323 if (bge_lookup(pa) != NULL) 2324 return (1); 2325 2326 return (0); 2327 } 2328 2329 static void 2330 bge_attach(device_t parent, device_t self, void *aux) 2331 { 2332 struct bge_softc *sc = device_private(self); 2333 struct pci_attach_args *pa = aux; 2334 const struct bge_product *bp; 2335 const struct bge_revision *br; 2336 pci_chipset_tag_t pc; 2337 pci_intr_handle_t ih; 2338 const char *intrstr = NULL; 2339 bus_dma_segment_t seg; 2340 int rseg; 2341 u_int32_t hwcfg = 0; 2342 u_int32_t command; 2343 struct ifnet *ifp; 2344 u_int32_t misccfg; 2345 void * kva; 2346 u_char eaddr[ETHER_ADDR_LEN]; 2347 pcireg_t memtype; 2348 bus_addr_t memaddr; 2349 bus_size_t memsize; 2350 u_int32_t pm_ctl; 2351 2352 bp = bge_lookup(pa); 2353 KASSERT(bp != NULL); 2354 2355 sc->sc_pc = pa->pa_pc; 2356 sc->sc_pcitag = pa->pa_tag; 2357 sc->bge_dev = self; 2358 2359 aprint_naive(": Ethernet controller\n"); 2360 aprint_normal(": %s\n", bp->bp_name); 2361 2362 /* 2363 * Map control/status registers. 2364 */ 2365 DPRINTFN(5, ("Map control/status regs\n")); 2366 pc = sc->sc_pc; 2367 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2368 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2369 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2370 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2371 2372 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2373 aprint_error_dev(sc->bge_dev, 2374 "failed to enable memory mapping!\n"); 2375 return; 2376 } 2377 2378 DPRINTFN(5, ("pci_mem_find\n")); 2379 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2380 switch (memtype) { 2381 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2382 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2383 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2384 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2385 &memaddr, &memsize) == 0) 2386 break; 2387 default: 2388 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2389 return; 2390 } 2391 2392 DPRINTFN(5, ("pci_intr_map\n")); 2393 if (pci_intr_map(pa, &ih)) { 2394 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2395 return; 2396 } 2397 2398 DPRINTFN(5, ("pci_intr_string\n")); 2399 intrstr = pci_intr_string(pc, ih); 2400 2401 DPRINTFN(5, ("pci_intr_establish\n")); 2402 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2403 2404 if (sc->bge_intrhand == NULL) { 2405 aprint_error_dev(sc->bge_dev, 2406 "couldn't establish interrupt%s%s\n", 2407 intrstr ? " at " : "", intrstr ? intrstr : ""); 2408 return; 2409 } 2410 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2411 2412 /* 2413 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2414 * can clobber the chip's PCI config-space power control registers, 2415 * leaving the card in D3 powersave state. 2416 * We do not have memory-mapped registers in this state, 2417 * so force device into D0 state before starting initialization. 2418 */ 2419 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2420 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2421 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2422 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2423 DELAY(1000); /* 27 usec is allegedly sufficent */ 2424 2425 /* 2426 * Save ASIC rev. 2427 */ 2428 sc->bge_chipid = 2429 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2430 BGE_PCIMISCCTL_ASICREV; 2431 2432 /* 2433 * Detect PCI-Express devices 2434 * XXX: guessed from Linux/FreeBSD; no documentation 2435 */ 2436 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2437 NULL, NULL) != 0) 2438 sc->bge_flags |= BGE_PCIE; 2439 2440 /* 2441 * PCI-X check. 2442 */ 2443 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2444 BGE_PCISTATE_PCI_BUSMODE) == 0) 2445 sc->bge_flags |= BGE_PCIX; 2446 2447 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2448 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2449 sc->bge_flags |= BGE_PHY_CRC_BUG; 2450 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2451 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2452 sc->bge_flags |= BGE_PHY_ADC_BUG; 2453 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2454 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2455 2456 if (BGE_IS_5705_OR_BEYOND(sc)) { 2457 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2458 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2459 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2460 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2461 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2462 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2463 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2464 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2465 sc->bge_flags |= BGE_PHY_BER_BUG; 2466 } 2467 2468 /* Try to reset the chip. */ 2469 DPRINTFN(5, ("bge_reset\n")); 2470 bge_reset(sc); 2471 2472 if (bge_chipinit(sc)) { 2473 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2474 bge_release_resources(sc); 2475 return; 2476 } 2477 2478 /* 2479 * Get station address from the EEPROM. 2480 */ 2481 if (bge_get_eaddr(sc, eaddr)) { 2482 aprint_error_dev(sc->bge_dev, 2483 "failed to reade station address\n"); 2484 bge_release_resources(sc); 2485 return; 2486 } 2487 2488 br = bge_lookup_rev(sc->bge_chipid); 2489 2490 if (br == NULL) { 2491 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2492 sc->bge_chipid >> 16); 2493 } else { 2494 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2495 br->br_name, sc->bge_chipid >> 16); 2496 } 2497 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2498 2499 /* Allocate the general information block and ring buffers. */ 2500 if (pci_dma64_available(pa)) 2501 sc->bge_dmatag = pa->pa_dmat64; 2502 else 2503 sc->bge_dmatag = pa->pa_dmat; 2504 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2505 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2506 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2507 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2508 return; 2509 } 2510 DPRINTFN(5, ("bus_dmamem_map\n")); 2511 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2512 sizeof(struct bge_ring_data), &kva, 2513 BUS_DMA_NOWAIT)) { 2514 aprint_error_dev(sc->bge_dev, 2515 "can't map DMA buffers (%zu bytes)\n", 2516 sizeof(struct bge_ring_data)); 2517 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2518 return; 2519 } 2520 DPRINTFN(5, ("bus_dmamem_create\n")); 2521 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2522 sizeof(struct bge_ring_data), 0, 2523 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2524 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2525 bus_dmamem_unmap(sc->bge_dmatag, kva, 2526 sizeof(struct bge_ring_data)); 2527 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2528 return; 2529 } 2530 DPRINTFN(5, ("bus_dmamem_load\n")); 2531 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2532 sizeof(struct bge_ring_data), NULL, 2533 BUS_DMA_NOWAIT)) { 2534 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2535 bus_dmamem_unmap(sc->bge_dmatag, kva, 2536 sizeof(struct bge_ring_data)); 2537 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2538 return; 2539 } 2540 2541 DPRINTFN(5, ("bzero\n")); 2542 sc->bge_rdata = (struct bge_ring_data *)kva; 2543 2544 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2545 2546 /* Try to allocate memory for jumbo buffers. */ 2547 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 2548 if (bge_alloc_jumbo_mem(sc)) { 2549 aprint_error_dev(sc->bge_dev, 2550 "jumbo buffer allocation failed\n"); 2551 } else 2552 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2553 } 2554 2555 /* Set default tuneable values. */ 2556 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2557 sc->bge_rx_coal_ticks = 150; 2558 sc->bge_rx_max_coal_bds = 64; 2559 #ifdef ORIG_WPAUL_VALUES 2560 sc->bge_tx_coal_ticks = 150; 2561 sc->bge_tx_max_coal_bds = 128; 2562 #else 2563 sc->bge_tx_coal_ticks = 300; 2564 sc->bge_tx_max_coal_bds = 400; 2565 #endif 2566 if (BGE_IS_5705_OR_BEYOND(sc)) { 2567 sc->bge_tx_coal_ticks = (12 * 5); 2568 sc->bge_tx_max_coal_bds = (12 * 5); 2569 aprint_verbose_dev(sc->bge_dev, 2570 "setting short Tx thresholds\n"); 2571 } 2572 2573 /* Set up ifnet structure */ 2574 ifp = &sc->ethercom.ec_if; 2575 ifp->if_softc = sc; 2576 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2577 ifp->if_ioctl = bge_ioctl; 2578 ifp->if_stop = bge_stop; 2579 ifp->if_start = bge_start; 2580 ifp->if_init = bge_init; 2581 ifp->if_watchdog = bge_watchdog; 2582 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2583 IFQ_SET_READY(&ifp->if_snd); 2584 DPRINTFN(5, ("strcpy if_xname\n")); 2585 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2586 2587 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2588 sc->ethercom.ec_if.if_capabilities |= 2589 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2590 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2591 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2592 sc->ethercom.ec_capabilities |= 2593 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2594 2595 if (sc->bge_flags & BGE_PCIE) 2596 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2597 2598 /* 2599 * Do MII setup. 2600 */ 2601 DPRINTFN(5, ("mii setup\n")); 2602 sc->bge_mii.mii_ifp = ifp; 2603 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2604 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2605 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2606 2607 /* 2608 * Figure out what sort of media we have by checking the 2609 * hardware config word in the first 32k of NIC internal memory, 2610 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2611 * cards, this value appears to be unset. If that's the 2612 * case, we have to rely on identifying the NIC by its PCI 2613 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2614 */ 2615 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2616 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2617 } else { 2618 bge_read_eeprom(sc, (void *)&hwcfg, 2619 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2620 hwcfg = be32toh(hwcfg); 2621 } 2622 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2623 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2624 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2625 if (BGE_IS_5714_FAMILY(sc)) 2626 sc->bge_flags |= BGE_PHY_FIBER_MII; 2627 else 2628 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2629 } 2630 2631 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2632 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2633 bge_ifmedia_sts); 2634 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2635 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2636 0, NULL); 2637 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2638 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2639 /* Pretend the user requested this setting */ 2640 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2641 } else { 2642 /* 2643 * Do transceiver setup. 2644 */ 2645 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2646 bge_ifmedia_sts); 2647 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2648 MII_PHY_ANY, MII_OFFSET_ANY, 2649 MIIF_FORCEANEG|MIIF_DOPAUSE); 2650 2651 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2652 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2653 ifmedia_add(&sc->bge_mii.mii_media, 2654 IFM_ETHER|IFM_MANUAL, 0, NULL); 2655 ifmedia_set(&sc->bge_mii.mii_media, 2656 IFM_ETHER|IFM_MANUAL); 2657 } else 2658 ifmedia_set(&sc->bge_mii.mii_media, 2659 IFM_ETHER|IFM_AUTO); 2660 } 2661 2662 /* 2663 * When using the BCM5701 in PCI-X mode, data corruption has 2664 * been observed in the first few bytes of some received packets. 2665 * Aligning the packet buffer in memory eliminates the corruption. 2666 * Unfortunately, this misaligns the packet payloads. On platforms 2667 * which do not support unaligned accesses, we will realign the 2668 * payloads by copying the received packets. 2669 */ 2670 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2671 sc->bge_flags & BGE_PCIX) 2672 sc->bge_flags |= BGE_RX_ALIGNBUG; 2673 2674 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2675 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2676 2677 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2678 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2679 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2680 sc->bge_flags |= BGE_IS_5788; 2681 2682 /* 2683 * Call MI attach routine. 2684 */ 2685 DPRINTFN(5, ("if_attach\n")); 2686 if_attach(ifp); 2687 DPRINTFN(5, ("ether_ifattach\n")); 2688 ether_ifattach(ifp, eaddr); 2689 #if NRND > 0 2690 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2691 RND_TYPE_NET, 0); 2692 #endif 2693 #ifdef BGE_EVENT_COUNTERS 2694 /* 2695 * Attach event counters. 2696 */ 2697 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2698 NULL, device_xname(sc->bge_dev), "intr"); 2699 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2700 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2701 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2702 NULL, device_xname(sc->bge_dev), "tx_xon"); 2703 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2704 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2705 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2706 NULL, device_xname(sc->bge_dev), "rx_xon"); 2707 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2708 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2709 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2710 NULL, device_xname(sc->bge_dev), "xoffentered"); 2711 #endif /* BGE_EVENT_COUNTERS */ 2712 DPRINTFN(5, ("callout_init\n")); 2713 callout_init(&sc->bge_timeout, 0); 2714 2715 if (!pmf_device_register(self, NULL, NULL)) 2716 aprint_error_dev(self, "couldn't establish power handler\n"); 2717 else 2718 pmf_class_network_register(self, ifp); 2719 } 2720 2721 static void 2722 bge_release_resources(struct bge_softc *sc) 2723 { 2724 if (sc->bge_vpd_prodname != NULL) 2725 free(sc->bge_vpd_prodname, M_DEVBUF); 2726 2727 if (sc->bge_vpd_readonly != NULL) 2728 free(sc->bge_vpd_readonly, M_DEVBUF); 2729 } 2730 2731 static void 2732 bge_reset(struct bge_softc *sc) 2733 { 2734 u_int32_t cachesize, command, pcistate, new_pcistate; 2735 int i, val; 2736 void (*write_op)(struct bge_softc *, int, int); 2737 2738 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2739 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2740 if (sc->bge_flags & BGE_PCIE) { 2741 write_op = bge_writemem_direct; 2742 } else { 2743 write_op = bge_writemem_ind; 2744 } 2745 } else { 2746 write_op = bge_writereg_ind; 2747 } 2748 2749 2750 /* Save some important PCI state. */ 2751 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2752 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2753 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2754 2755 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2756 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2757 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2758 2759 /* Disable fastboot on controllers that support it. */ 2760 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2761 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2762 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2763 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2764 2765 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2766 /* 2767 * XXX: from FreeBSD/Linux; no documentation 2768 */ 2769 if (sc->bge_flags & BGE_PCIE) { 2770 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2771 /* PCI Express 1.0 system */ 2772 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2773 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2774 /* 2775 * Prevent PCI Express link training 2776 * during global reset. 2777 */ 2778 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2779 val |= (1<<29); 2780 } 2781 } 2782 2783 /* 2784 * Set GPHY Power Down Override to leave GPHY 2785 * powered up in D0 uninitialized. 2786 */ 2787 if (BGE_IS_5705_OR_BEYOND(sc)) 2788 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 2789 2790 /* Issue global reset */ 2791 write_op(sc, BGE_MISC_CFG, val); 2792 2793 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2794 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2795 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2796 i | BGE_VCPU_STATUS_DRV_RESET); 2797 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2798 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2799 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2800 } 2801 2802 DELAY(1000); 2803 2804 /* 2805 * XXX: from FreeBSD/Linux; no documentation 2806 */ 2807 if (sc->bge_flags & BGE_PCIE) { 2808 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2809 pcireg_t reg; 2810 2811 DELAY(500000); 2812 /* XXX: Magic Numbers */ 2813 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0); 2814 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0, 2815 reg | (1 << 15)); 2816 } 2817 /* 2818 * XXX: Magic Numbers. 2819 * Sets maximal PCI-e payload and clears any PCI-e errors. 2820 * Should be replaced with references to PCI config-space 2821 * capability block for PCI-Express. 2822 */ 2823 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2824 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2825 2826 } 2827 2828 /* Reset some of the PCI state that got zapped by reset */ 2829 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2830 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2831 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2832 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2833 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2834 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2835 2836 /* Enable memory arbiter. */ 2837 { 2838 uint32_t marbmode = 0; 2839 if (BGE_IS_5714_FAMILY(sc)) { 2840 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2841 } 2842 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2843 } 2844 2845 2846 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2847 for (i = 0; i < BGE_TIMEOUT; i++) { 2848 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2849 if (val & BGE_VCPU_STATUS_INIT_DONE) 2850 break; 2851 DELAY(100); 2852 } 2853 if (i == BGE_TIMEOUT) { 2854 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2855 return; 2856 } 2857 } else { 2858 /* 2859 * Write the magic number to the firmware mailbox at 0xb50 2860 * so that the driver can synchronize with the firmware. 2861 */ 2862 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2863 2864 /* 2865 * Poll the value location we just wrote until 2866 * we see the 1's complement of the magic number. 2867 * This indicates that the firmware initialization 2868 * is complete. 2869 */ 2870 for (i = 0; i < BGE_TIMEOUT; i++) { 2871 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2872 if (val == ~BGE_MAGIC_NUMBER) 2873 break; 2874 DELAY(1000); 2875 } 2876 2877 if (i >= BGE_TIMEOUT) { 2878 aprint_error_dev(sc->bge_dev, 2879 "firmware handshake timed out, val = %x\n", val); 2880 /* 2881 * XXX: occasionally fired on bcm5721, but without 2882 * apparent harm. For now, keep going if we timeout 2883 * against PCI-E devices. 2884 */ 2885 if ((sc->bge_flags & BGE_PCIE) == 0) 2886 return; 2887 } 2888 } 2889 2890 /* 2891 * XXX Wait for the value of the PCISTATE register to 2892 * return to its original pre-reset state. This is a 2893 * fairly good indicator of reset completion. If we don't 2894 * wait for the reset to fully complete, trying to read 2895 * from the device's non-PCI registers may yield garbage 2896 * results. 2897 */ 2898 for (i = 0; i < 10000; i++) { 2899 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2900 BGE_PCI_PCISTATE); 2901 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2902 (pcistate & ~BGE_PCISTATE_RESERVED)) 2903 break; 2904 DELAY(10); 2905 } 2906 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2907 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2908 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 2909 } 2910 2911 /* Enable memory arbiter. */ 2912 /* XXX why do this twice? */ 2913 { 2914 uint32_t marbmode = 0; 2915 if (BGE_IS_5714_FAMILY(sc)) { 2916 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2917 } 2918 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2919 } 2920 2921 /* Fix up byte swapping */ 2922 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2923 2924 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2925 2926 /* 2927 * The 5704 in TBI mode apparently needs some special 2928 * adjustment to insure the SERDES drive level is set 2929 * to 1.2V. 2930 */ 2931 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 2932 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2933 u_int32_t serdescfg; 2934 2935 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2936 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2937 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2938 } 2939 2940 /* XXX: from FreeBSD/Linux; no documentation */ 2941 if (sc->bge_flags & BGE_PCIE && 2942 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2943 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2944 DELAY(10000); 2945 } 2946 2947 /* 2948 * Frame reception handling. This is called if there's a frame 2949 * on the receive return list. 2950 * 2951 * Note: we have to be able to handle two possibilities here: 2952 * 1) the frame is from the jumbo recieve ring 2953 * 2) the frame is from the standard receive ring 2954 */ 2955 2956 static void 2957 bge_rxeof(struct bge_softc *sc) 2958 { 2959 struct ifnet *ifp; 2960 int stdcnt = 0, jumbocnt = 0; 2961 bus_dmamap_t dmamap; 2962 bus_addr_t offset, toff; 2963 bus_size_t tlen; 2964 int tosync; 2965 2966 ifp = &sc->ethercom.ec_if; 2967 2968 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2969 offsetof(struct bge_ring_data, bge_status_block), 2970 sizeof (struct bge_status_block), 2971 BUS_DMASYNC_POSTREAD); 2972 2973 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2974 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2975 sc->bge_rx_saved_considx; 2976 2977 #if NRND > 0 2978 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 2979 rnd_add_uint32(&sc->rnd_source, tosync); 2980 #endif 2981 2982 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2983 2984 if (tosync < 0) { 2985 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2986 sizeof (struct bge_rx_bd); 2987 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2988 toff, tlen, BUS_DMASYNC_POSTREAD); 2989 tosync = -tosync; 2990 } 2991 2992 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2993 offset, tosync * sizeof (struct bge_rx_bd), 2994 BUS_DMASYNC_POSTREAD); 2995 2996 while(sc->bge_rx_saved_considx != 2997 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2998 struct bge_rx_bd *cur_rx; 2999 u_int32_t rxidx; 3000 struct mbuf *m = NULL; 3001 3002 cur_rx = &sc->bge_rdata-> 3003 bge_rx_return_ring[sc->bge_rx_saved_considx]; 3004 3005 rxidx = cur_rx->bge_idx; 3006 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 3007 3008 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3009 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3010 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3011 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3012 jumbocnt++; 3013 bus_dmamap_sync(sc->bge_dmatag, 3014 sc->bge_cdata.bge_rx_jumbo_map, 3015 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3016 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3017 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3018 ifp->if_ierrors++; 3019 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3020 continue; 3021 } 3022 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3023 NULL)== ENOBUFS) { 3024 ifp->if_ierrors++; 3025 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3026 continue; 3027 } 3028 } else { 3029 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3030 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3031 3032 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3033 stdcnt++; 3034 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3035 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3036 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3037 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3038 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3039 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3040 ifp->if_ierrors++; 3041 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3042 continue; 3043 } 3044 if (bge_newbuf_std(sc, sc->bge_std, 3045 NULL, dmamap) == ENOBUFS) { 3046 ifp->if_ierrors++; 3047 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3048 continue; 3049 } 3050 } 3051 3052 ifp->if_ipackets++; 3053 #ifndef __NO_STRICT_ALIGNMENT 3054 /* 3055 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3056 * the Rx buffer has the layer-2 header unaligned. 3057 * If our CPU requires alignment, re-align by copying. 3058 */ 3059 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3060 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3061 cur_rx->bge_len); 3062 m->m_data += ETHER_ALIGN; 3063 } 3064 #endif 3065 3066 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3067 m->m_pkthdr.rcvif = ifp; 3068 3069 #if NBPFILTER > 0 3070 /* 3071 * Handle BPF listeners. Let the BPF user see the packet. 3072 */ 3073 if (ifp->if_bpf) 3074 bpf_mtap(ifp->if_bpf, m); 3075 #endif 3076 3077 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3078 3079 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3080 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3081 /* 3082 * Rx transport checksum-offload may also 3083 * have bugs with packets which, when transmitted, 3084 * were `runts' requiring padding. 3085 */ 3086 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3087 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3088 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3089 m->m_pkthdr.csum_data = 3090 cur_rx->bge_tcp_udp_csum; 3091 m->m_pkthdr.csum_flags |= 3092 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3093 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3094 } 3095 3096 /* 3097 * If we received a packet with a vlan tag, pass it 3098 * to vlan_input() instead of ether_input(). 3099 */ 3100 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3101 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3102 } 3103 3104 (*ifp->if_input)(ifp, m); 3105 } 3106 3107 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3108 if (stdcnt) 3109 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3110 if (jumbocnt) 3111 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3112 } 3113 3114 static void 3115 bge_txeof(struct bge_softc *sc) 3116 { 3117 struct bge_tx_bd *cur_tx = NULL; 3118 struct ifnet *ifp; 3119 struct txdmamap_pool_entry *dma; 3120 bus_addr_t offset, toff; 3121 bus_size_t tlen; 3122 int tosync; 3123 struct mbuf *m; 3124 3125 ifp = &sc->ethercom.ec_if; 3126 3127 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3128 offsetof(struct bge_ring_data, bge_status_block), 3129 sizeof (struct bge_status_block), 3130 BUS_DMASYNC_POSTREAD); 3131 3132 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3133 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3134 sc->bge_tx_saved_considx; 3135 3136 #if NRND > 0 3137 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3138 rnd_add_uint32(&sc->rnd_source, tosync); 3139 #endif 3140 3141 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3142 3143 if (tosync < 0) { 3144 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3145 sizeof (struct bge_tx_bd); 3146 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3147 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3148 tosync = -tosync; 3149 } 3150 3151 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3152 offset, tosync * sizeof (struct bge_tx_bd), 3153 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3154 3155 /* 3156 * Go through our tx ring and free mbufs for those 3157 * frames that have been sent. 3158 */ 3159 while (sc->bge_tx_saved_considx != 3160 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3161 u_int32_t idx = 0; 3162 3163 idx = sc->bge_tx_saved_considx; 3164 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3165 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3166 ifp->if_opackets++; 3167 m = sc->bge_cdata.bge_tx_chain[idx]; 3168 if (m != NULL) { 3169 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3170 dma = sc->txdma[idx]; 3171 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3172 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3173 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3174 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3175 sc->txdma[idx] = NULL; 3176 3177 m_freem(m); 3178 } 3179 sc->bge_txcnt--; 3180 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3181 ifp->if_timer = 0; 3182 } 3183 3184 if (cur_tx != NULL) 3185 ifp->if_flags &= ~IFF_OACTIVE; 3186 } 3187 3188 static int 3189 bge_intr(void *xsc) 3190 { 3191 struct bge_softc *sc; 3192 struct ifnet *ifp; 3193 uint32_t statusword; 3194 3195 sc = xsc; 3196 ifp = &sc->ethercom.ec_if; 3197 3198 /* It is possible for the interrupt to arrive before 3199 * the status block is updated prior to the interrupt. 3200 * Reading the PCI State register will confirm whether the 3201 * interrupt is ours and will flush the status block. 3202 */ 3203 3204 /* read status word from status block */ 3205 statusword = sc->bge_rdata->bge_status_block.bge_status; 3206 3207 if ((statusword & BGE_STATFLAG_UPDATED) || 3208 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3209 /* Ack interrupt and stop others from occuring. */ 3210 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3211 3212 BGE_EVCNT_INCR(sc->bge_ev_intr); 3213 3214 /* clear status word */ 3215 sc->bge_rdata->bge_status_block.bge_status = 0; 3216 3217 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3218 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3219 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3220 bge_link_upd(sc); 3221 3222 if (ifp->if_flags & IFF_RUNNING) { 3223 /* Check RX return ring producer/consumer */ 3224 bge_rxeof(sc); 3225 3226 /* Check TX ring producer/consumer */ 3227 bge_txeof(sc); 3228 } 3229 3230 if (sc->bge_pending_rxintr_change) { 3231 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3232 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3233 uint32_t junk; 3234 3235 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3236 DELAY(10); 3237 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3238 3239 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3240 DELAY(10); 3241 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3242 3243 sc->bge_pending_rxintr_change = 0; 3244 } 3245 bge_handle_events(sc); 3246 3247 /* Re-enable interrupts. */ 3248 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3249 3250 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3251 bge_start(ifp); 3252 3253 return (1); 3254 } else 3255 return (0); 3256 } 3257 3258 static void 3259 bge_tick(void *xsc) 3260 { 3261 struct bge_softc *sc = xsc; 3262 struct mii_data *mii = &sc->bge_mii; 3263 int s; 3264 3265 s = splnet(); 3266 3267 bge_stats_update(sc); 3268 3269 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3270 /* 3271 * Since in TBI mode auto-polling can't be used we should poll 3272 * link status manually. Here we register pending link event 3273 * and trigger interrupt. 3274 */ 3275 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3276 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3277 } else { 3278 /* 3279 * Do not touch PHY if we have link up. This could break 3280 * IPMI/ASF mode or produce extra input errors. 3281 * (extra input errors was reported for bcm5701 & bcm5704). 3282 */ 3283 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3284 mii_tick(mii); 3285 } 3286 3287 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3288 3289 splx(s); 3290 } 3291 3292 static void 3293 bge_stats_update(struct bge_softc *sc) 3294 { 3295 struct ifnet *ifp = &sc->ethercom.ec_if; 3296 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3297 bus_size_t rstats = BGE_RX_STATS; 3298 3299 #define READ_RSTAT(sc, stats, stat) \ 3300 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3301 3302 if (BGE_IS_5705_OR_BEYOND(sc)) { 3303 ifp->if_collisions += 3304 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3305 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3306 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3307 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3308 3309 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3310 READ_RSTAT(sc, rstats, outXoffSent)); 3311 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3312 READ_RSTAT(sc, rstats, outXonSent)); 3313 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3314 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3315 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3316 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3317 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3318 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3319 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3320 READ_RSTAT(sc, rstats, xoffStateEntered)); 3321 return; 3322 } 3323 3324 #undef READ_RSTAT 3325 #define READ_STAT(sc, stats, stat) \ 3326 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3327 3328 ifp->if_collisions += 3329 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3330 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3331 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3332 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3333 ifp->if_collisions; 3334 3335 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3336 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3337 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3338 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3339 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3340 READ_STAT(sc, stats, 3341 xoffPauseFramesReceived.bge_addr_lo)); 3342 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3343 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3344 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3345 READ_STAT(sc, stats, 3346 macControlFramesReceived.bge_addr_lo)); 3347 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3348 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3349 3350 #undef READ_STAT 3351 3352 #ifdef notdef 3353 ifp->if_collisions += 3354 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3355 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3356 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3357 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3358 ifp->if_collisions; 3359 #endif 3360 } 3361 3362 /* 3363 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3364 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3365 * but when such padded frames employ the bge IP/TCP checksum offload, 3366 * the hardware checksum assist gives incorrect results (possibly 3367 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3368 * If we pad such runts with zeros, the onboard checksum comes out correct. 3369 */ 3370 static inline int 3371 bge_cksum_pad(struct mbuf *pkt) 3372 { 3373 struct mbuf *last = NULL; 3374 int padlen; 3375 3376 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3377 3378 /* if there's only the packet-header and we can pad there, use it. */ 3379 if (pkt->m_pkthdr.len == pkt->m_len && 3380 M_TRAILINGSPACE(pkt) >= padlen) { 3381 last = pkt; 3382 } else { 3383 /* 3384 * Walk packet chain to find last mbuf. We will either 3385 * pad there, or append a new mbuf and pad it 3386 * (thus perhaps avoiding the bcm5700 dma-min bug). 3387 */ 3388 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3389 continue; /* do nothing */ 3390 } 3391 3392 /* `last' now points to last in chain. */ 3393 if (M_TRAILINGSPACE(last) < padlen) { 3394 /* Allocate new empty mbuf, pad it. Compact later. */ 3395 struct mbuf *n; 3396 MGET(n, M_DONTWAIT, MT_DATA); 3397 if (n == NULL) 3398 return ENOBUFS; 3399 n->m_len = 0; 3400 last->m_next = n; 3401 last = n; 3402 } 3403 } 3404 3405 KDASSERT(!M_READONLY(last)); 3406 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3407 3408 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3409 memset(mtod(last, char *) + last->m_len, 0, padlen); 3410 last->m_len += padlen; 3411 pkt->m_pkthdr.len += padlen; 3412 return 0; 3413 } 3414 3415 /* 3416 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3417 */ 3418 static inline int 3419 bge_compact_dma_runt(struct mbuf *pkt) 3420 { 3421 struct mbuf *m, *prev; 3422 int totlen, prevlen; 3423 3424 prev = NULL; 3425 totlen = 0; 3426 prevlen = -1; 3427 3428 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3429 int mlen = m->m_len; 3430 int shortfall = 8 - mlen ; 3431 3432 totlen += mlen; 3433 if (mlen == 0) { 3434 continue; 3435 } 3436 if (mlen >= 8) 3437 continue; 3438 3439 /* If we get here, mbuf data is too small for DMA engine. 3440 * Try to fix by shuffling data to prev or next in chain. 3441 * If that fails, do a compacting deep-copy of the whole chain. 3442 */ 3443 3444 /* Internal frag. If fits in prev, copy it there. */ 3445 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3446 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3447 prev->m_len += mlen; 3448 m->m_len = 0; 3449 /* XXX stitch chain */ 3450 prev->m_next = m_free(m); 3451 m = prev; 3452 continue; 3453 } 3454 else if (m->m_next != NULL && 3455 M_TRAILINGSPACE(m) >= shortfall && 3456 m->m_next->m_len >= (8 + shortfall)) { 3457 /* m is writable and have enough data in next, pull up. */ 3458 3459 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3460 shortfall); 3461 m->m_len += shortfall; 3462 m->m_next->m_len -= shortfall; 3463 m->m_next->m_data += shortfall; 3464 } 3465 else if (m->m_next == NULL || 1) { 3466 /* Got a runt at the very end of the packet. 3467 * borrow data from the tail of the preceding mbuf and 3468 * update its length in-place. (The original data is still 3469 * valid, so we can do this even if prev is not writable.) 3470 */ 3471 3472 /* if we'd make prev a runt, just move all of its data. */ 3473 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3474 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3475 3476 if ((prev->m_len - shortfall) < 8) 3477 shortfall = prev->m_len; 3478 3479 #ifdef notyet /* just do the safe slow thing for now */ 3480 if (!M_READONLY(m)) { 3481 if (M_LEADINGSPACE(m) < shorfall) { 3482 void *m_dat; 3483 m_dat = (m->m_flags & M_PKTHDR) ? 3484 m->m_pktdat : m->dat; 3485 memmove(m_dat, mtod(m, void*), m->m_len); 3486 m->m_data = m_dat; 3487 } 3488 } else 3489 #endif /* just do the safe slow thing */ 3490 { 3491 struct mbuf * n = NULL; 3492 int newprevlen = prev->m_len - shortfall; 3493 3494 MGET(n, M_NOWAIT, MT_DATA); 3495 if (n == NULL) 3496 return ENOBUFS; 3497 KASSERT(m->m_len + shortfall < MLEN 3498 /*, 3499 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3500 3501 /* first copy the data we're stealing from prev */ 3502 memcpy(n->m_data, prev->m_data + newprevlen, 3503 shortfall); 3504 3505 /* update prev->m_len accordingly */ 3506 prev->m_len -= shortfall; 3507 3508 /* copy data from runt m */ 3509 memcpy(n->m_data + shortfall, m->m_data, 3510 m->m_len); 3511 3512 /* n holds what we stole from prev, plus m */ 3513 n->m_len = shortfall + m->m_len; 3514 3515 /* stitch n into chain and free m */ 3516 n->m_next = m->m_next; 3517 prev->m_next = n; 3518 /* KASSERT(m->m_next == NULL); */ 3519 m->m_next = NULL; 3520 m_free(m); 3521 m = n; /* for continuing loop */ 3522 } 3523 } 3524 prevlen = m->m_len; 3525 } 3526 return 0; 3527 } 3528 3529 /* 3530 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3531 * pointers to descriptors. 3532 */ 3533 static int 3534 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3535 { 3536 struct bge_tx_bd *f = NULL; 3537 u_int32_t frag, cur; 3538 u_int16_t csum_flags = 0; 3539 u_int16_t txbd_tso_flags = 0; 3540 struct txdmamap_pool_entry *dma; 3541 bus_dmamap_t dmamap; 3542 int i = 0; 3543 struct m_tag *mtag; 3544 int use_tso, maxsegsize, error; 3545 3546 cur = frag = *txidx; 3547 3548 if (m_head->m_pkthdr.csum_flags) { 3549 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3550 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3551 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3552 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3553 } 3554 3555 /* 3556 * If we were asked to do an outboard checksum, and the NIC 3557 * has the bug where it sometimes adds in the Ethernet padding, 3558 * explicitly pad with zeros so the cksum will be correct either way. 3559 * (For now, do this for all chip versions, until newer 3560 * are confirmed to not require the workaround.) 3561 */ 3562 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3563 #ifdef notyet 3564 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3565 #endif 3566 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3567 goto check_dma_bug; 3568 3569 if (bge_cksum_pad(m_head) != 0) { 3570 return ENOBUFS; 3571 } 3572 3573 check_dma_bug: 3574 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3575 goto doit; 3576 3577 /* 3578 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3579 * less than eight bytes. If we encounter a teeny mbuf 3580 * at the end of a chain, we can pad. Otherwise, copy. 3581 */ 3582 if (bge_compact_dma_runt(m_head) != 0) 3583 return ENOBUFS; 3584 3585 doit: 3586 dma = SLIST_FIRST(&sc->txdma_list); 3587 if (dma == NULL) 3588 return ENOBUFS; 3589 dmamap = dma->dmamap; 3590 3591 /* 3592 * Set up any necessary TSO state before we start packing... 3593 */ 3594 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3595 if (!use_tso) { 3596 maxsegsize = 0; 3597 } else { /* TSO setup */ 3598 unsigned mss; 3599 struct ether_header *eh; 3600 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3601 struct mbuf * m0 = m_head; 3602 struct ip *ip; 3603 struct tcphdr *th; 3604 int iphl, hlen; 3605 3606 /* 3607 * XXX It would be nice if the mbuf pkthdr had offset 3608 * fields for the protocol headers. 3609 */ 3610 3611 eh = mtod(m0, struct ether_header *); 3612 switch (htons(eh->ether_type)) { 3613 case ETHERTYPE_IP: 3614 offset = ETHER_HDR_LEN; 3615 break; 3616 3617 case ETHERTYPE_VLAN: 3618 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3619 break; 3620 3621 default: 3622 /* 3623 * Don't support this protocol or encapsulation. 3624 */ 3625 return (ENOBUFS); 3626 } 3627 3628 /* 3629 * TCP/IP headers are in the first mbuf; we can do 3630 * this the easy way. 3631 */ 3632 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3633 hlen = iphl + offset; 3634 if (__predict_false(m0->m_len < 3635 (hlen + sizeof(struct tcphdr)))) { 3636 3637 aprint_debug_dev(sc->bge_dev, 3638 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3639 "not handled yet\n", 3640 m0->m_len, hlen+ sizeof(struct tcphdr)); 3641 #ifdef NOTYET 3642 /* 3643 * XXX jonathan@NetBSD.org: untested. 3644 * how to force this branch to be taken? 3645 */ 3646 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3647 3648 m_copydata(m0, offset, sizeof(ip), &ip); 3649 m_copydata(m0, hlen, sizeof(th), &th); 3650 3651 ip.ip_len = 0; 3652 3653 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3654 sizeof(ip.ip_len), &ip.ip_len); 3655 3656 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3657 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3658 3659 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3660 sizeof(th.th_sum), &th.th_sum); 3661 3662 hlen += th.th_off << 2; 3663 iptcp_opt_words = hlen; 3664 #else 3665 /* 3666 * if_wm "hard" case not yet supported, can we not 3667 * mandate it out of existence? 3668 */ 3669 (void) ip; (void)th; (void) ip_tcp_hlen; 3670 3671 return ENOBUFS; 3672 #endif 3673 } else { 3674 ip = (struct ip *) (mtod(m0, char *) + offset); 3675 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3676 ip_tcp_hlen = iphl + (th->th_off << 2); 3677 3678 /* Total IP/TCP options, in 32-bit words */ 3679 iptcp_opt_words = (ip_tcp_hlen 3680 - sizeof(struct tcphdr) 3681 - sizeof(struct ip)) >> 2; 3682 } 3683 if (BGE_IS_5750_OR_BEYOND(sc)) { 3684 th->th_sum = 0; 3685 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3686 } else { 3687 /* 3688 * XXX jonathan@NetBSD.org: 5705 untested. 3689 * Requires TSO firmware patch for 5701/5703/5704. 3690 */ 3691 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3692 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3693 } 3694 3695 mss = m_head->m_pkthdr.segsz; 3696 txbd_tso_flags |= 3697 BGE_TXBDFLAG_CPU_PRE_DMA | 3698 BGE_TXBDFLAG_CPU_POST_DMA; 3699 3700 /* 3701 * Our NIC TSO-assist assumes TSO has standard, optionless 3702 * IPv4 and TCP headers, which total 40 bytes. By default, 3703 * the NIC copies 40 bytes of IP/TCP header from the 3704 * supplied header into the IP/TCP header portion of 3705 * each post-TSO-segment. If the supplied packet has IP or 3706 * TCP options, we need to tell the NIC to copy those extra 3707 * bytes into each post-TSO header, in addition to the normal 3708 * 40-byte IP/TCP header (and to leave space accordingly). 3709 * Unfortunately, the driver encoding of option length 3710 * varies across different ASIC families. 3711 */ 3712 tcp_seg_flags = 0; 3713 if (iptcp_opt_words) { 3714 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3715 tcp_seg_flags = 3716 iptcp_opt_words << 11; 3717 } else { 3718 txbd_tso_flags |= 3719 iptcp_opt_words << 12; 3720 } 3721 } 3722 maxsegsize = mss | tcp_seg_flags; 3723 ip->ip_len = htons(mss + ip_tcp_hlen); 3724 3725 } /* TSO setup */ 3726 3727 /* 3728 * Start packing the mbufs in this chain into 3729 * the fragment pointers. Stop when we run out 3730 * of fragments or hit the end of the mbuf chain. 3731 */ 3732 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3733 BUS_DMA_NOWAIT); 3734 if (error) { 3735 return (ENOBUFS); 3736 } 3737 /* 3738 * Sanity check: avoid coming within 16 descriptors 3739 * of the end of the ring. 3740 */ 3741 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3742 BGE_TSO_PRINTF(("%s: " 3743 " dmamap_load_mbuf too close to ring wrap\n", 3744 device_xname(sc->bge_dev))); 3745 goto fail_unload; 3746 } 3747 3748 mtag = sc->ethercom.ec_nvlans ? 3749 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3750 3751 3752 /* Iterate over dmap-map fragments. */ 3753 for (i = 0; i < dmamap->dm_nsegs; i++) { 3754 f = &sc->bge_rdata->bge_tx_ring[frag]; 3755 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3756 break; 3757 3758 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3759 f->bge_len = dmamap->dm_segs[i].ds_len; 3760 3761 /* 3762 * For 5751 and follow-ons, for TSO we must turn 3763 * off checksum-assist flag in the tx-descr, and 3764 * supply the ASIC-revision-specific encoding 3765 * of TSO flags and segsize. 3766 */ 3767 if (use_tso) { 3768 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3769 f->bge_rsvd = maxsegsize; 3770 f->bge_flags = csum_flags | txbd_tso_flags; 3771 } else { 3772 f->bge_rsvd = 0; 3773 f->bge_flags = 3774 (csum_flags | txbd_tso_flags) & 0x0fff; 3775 } 3776 } else { 3777 f->bge_rsvd = 0; 3778 f->bge_flags = csum_flags; 3779 } 3780 3781 if (mtag != NULL) { 3782 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3783 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3784 } else { 3785 f->bge_vlan_tag = 0; 3786 } 3787 cur = frag; 3788 BGE_INC(frag, BGE_TX_RING_CNT); 3789 } 3790 3791 if (i < dmamap->dm_nsegs) { 3792 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3793 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3794 goto fail_unload; 3795 } 3796 3797 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3798 BUS_DMASYNC_PREWRITE); 3799 3800 if (frag == sc->bge_tx_saved_considx) { 3801 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3802 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3803 3804 goto fail_unload; 3805 } 3806 3807 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3808 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3809 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3810 sc->txdma[cur] = dma; 3811 sc->bge_txcnt += dmamap->dm_nsegs; 3812 3813 *txidx = frag; 3814 3815 return (0); 3816 3817 fail_unload: 3818 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3819 3820 return ENOBUFS; 3821 } 3822 3823 /* 3824 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3825 * to the mbuf data regions directly in the transmit descriptors. 3826 */ 3827 static void 3828 bge_start(struct ifnet *ifp) 3829 { 3830 struct bge_softc *sc; 3831 struct mbuf *m_head = NULL; 3832 u_int32_t prodidx; 3833 int pkts = 0; 3834 3835 sc = ifp->if_softc; 3836 3837 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3838 return; 3839 3840 prodidx = sc->bge_tx_prodidx; 3841 3842 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3843 IFQ_POLL(&ifp->if_snd, m_head); 3844 if (m_head == NULL) 3845 break; 3846 3847 #if 0 3848 /* 3849 * XXX 3850 * safety overkill. If this is a fragmented packet chain 3851 * with delayed TCP/UDP checksums, then only encapsulate 3852 * it if we have enough descriptors to handle the entire 3853 * chain at once. 3854 * (paranoia -- may not actually be needed) 3855 */ 3856 if (m_head->m_flags & M_FIRSTFRAG && 3857 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3858 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3859 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3860 ifp->if_flags |= IFF_OACTIVE; 3861 break; 3862 } 3863 } 3864 #endif 3865 3866 /* 3867 * Pack the data into the transmit ring. If we 3868 * don't have room, set the OACTIVE flag and wait 3869 * for the NIC to drain the ring. 3870 */ 3871 if (bge_encap(sc, m_head, &prodidx)) { 3872 ifp->if_flags |= IFF_OACTIVE; 3873 break; 3874 } 3875 3876 /* now we are committed to transmit the packet */ 3877 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3878 pkts++; 3879 3880 #if NBPFILTER > 0 3881 /* 3882 * If there's a BPF listener, bounce a copy of this frame 3883 * to him. 3884 */ 3885 if (ifp->if_bpf) 3886 bpf_mtap(ifp->if_bpf, m_head); 3887 #endif 3888 } 3889 if (pkts == 0) 3890 return; 3891 3892 /* Transmit */ 3893 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3894 /* 5700 b2 errata */ 3895 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 3896 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3897 3898 sc->bge_tx_prodidx = prodidx; 3899 3900 /* 3901 * Set a timeout in case the chip goes out to lunch. 3902 */ 3903 ifp->if_timer = 5; 3904 } 3905 3906 static int 3907 bge_init(struct ifnet *ifp) 3908 { 3909 struct bge_softc *sc = ifp->if_softc; 3910 const u_int16_t *m; 3911 int s, error = 0; 3912 3913 s = splnet(); 3914 3915 ifp = &sc->ethercom.ec_if; 3916 3917 /* Cancel pending I/O and flush buffers. */ 3918 bge_stop(ifp, 0); 3919 bge_reset(sc); 3920 bge_chipinit(sc); 3921 3922 /* 3923 * Init the various state machines, ring 3924 * control blocks and firmware. 3925 */ 3926 error = bge_blockinit(sc); 3927 if (error != 0) { 3928 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 3929 error); 3930 splx(s); 3931 return error; 3932 } 3933 3934 ifp = &sc->ethercom.ec_if; 3935 3936 /* Specify MTU. */ 3937 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3938 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3939 3940 /* Load our MAC address. */ 3941 m = (const u_int16_t *)&(CLLADDR(ifp->if_sadl)[0]); 3942 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3943 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3944 3945 /* Enable or disable promiscuous mode as needed. */ 3946 if (ifp->if_flags & IFF_PROMISC) { 3947 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3948 } else { 3949 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3950 } 3951 3952 /* Program multicast filter. */ 3953 bge_setmulti(sc); 3954 3955 /* Init RX ring. */ 3956 bge_init_rx_ring_std(sc); 3957 3958 /* 3959 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3960 * memory to insure that the chip has in fact read the first 3961 * entry of the ring. 3962 */ 3963 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3964 u_int32_t v, i; 3965 for (i = 0; i < 10; i++) { 3966 DELAY(20); 3967 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3968 if (v == (MCLBYTES - ETHER_ALIGN)) 3969 break; 3970 } 3971 if (i == 10) 3972 aprint_error_dev(sc->bge_dev, 3973 "5705 A0 chip failed to load RX ring\n"); 3974 } 3975 3976 /* Init jumbo RX ring. */ 3977 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3978 bge_init_rx_ring_jumbo(sc); 3979 3980 /* Init our RX return ring index */ 3981 sc->bge_rx_saved_considx = 0; 3982 3983 /* Init TX ring. */ 3984 bge_init_tx_ring(sc); 3985 3986 /* Turn on transmitter */ 3987 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3988 3989 /* Turn on receiver */ 3990 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3991 3992 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3993 3994 /* Tell firmware we're alive. */ 3995 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3996 3997 /* Enable host interrupts. */ 3998 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3999 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4000 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4001 4002 if ((error = bge_ifmedia_upd(ifp)) != 0) 4003 goto out; 4004 4005 ifp->if_flags |= IFF_RUNNING; 4006 ifp->if_flags &= ~IFF_OACTIVE; 4007 4008 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4009 4010 out: 4011 splx(s); 4012 4013 return error; 4014 } 4015 4016 /* 4017 * Set media options. 4018 */ 4019 static int 4020 bge_ifmedia_upd(struct ifnet *ifp) 4021 { 4022 struct bge_softc *sc = ifp->if_softc; 4023 struct mii_data *mii = &sc->bge_mii; 4024 struct ifmedia *ifm = &sc->bge_ifmedia; 4025 int rc; 4026 4027 /* If this is a 1000baseX NIC, enable the TBI port. */ 4028 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4029 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4030 return (EINVAL); 4031 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4032 case IFM_AUTO: 4033 /* 4034 * The BCM5704 ASIC appears to have a special 4035 * mechanism for programming the autoneg 4036 * advertisement registers in TBI mode. 4037 */ 4038 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4039 u_int32_t sgdig; 4040 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4041 if (sgdig & BGE_SGDIGSTS_DONE) { 4042 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4043 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4044 sgdig |= BGE_SGDIGCFG_AUTO | 4045 BGE_SGDIGCFG_PAUSE_CAP | 4046 BGE_SGDIGCFG_ASYM_PAUSE; 4047 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4048 sgdig | BGE_SGDIGCFG_SEND); 4049 DELAY(5); 4050 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4051 } 4052 } 4053 break; 4054 case IFM_1000_SX: 4055 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4056 BGE_CLRBIT(sc, BGE_MAC_MODE, 4057 BGE_MACMODE_HALF_DUPLEX); 4058 } else { 4059 BGE_SETBIT(sc, BGE_MAC_MODE, 4060 BGE_MACMODE_HALF_DUPLEX); 4061 } 4062 break; 4063 default: 4064 return (EINVAL); 4065 } 4066 /* XXX 802.3x flow control for 1000BASE-SX */ 4067 return (0); 4068 } 4069 4070 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4071 if ((rc = mii_mediachg(mii)) == ENXIO) 4072 return 0; 4073 4074 /* 4075 * Force an interrupt so that we will call bge_link_upd 4076 * if needed and clear any pending link state attention. 4077 * Without this we are not getting any further interrupts 4078 * for link state changes and thus will not UP the link and 4079 * not be able to send in bge_start. The only way to get 4080 * things working was to receive a packet and get a RX intr. 4081 */ 4082 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4083 sc->bge_flags & BGE_IS_5788) 4084 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4085 else 4086 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4087 4088 return rc; 4089 } 4090 4091 /* 4092 * Report current media status. 4093 */ 4094 static void 4095 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4096 { 4097 struct bge_softc *sc = ifp->if_softc; 4098 struct mii_data *mii = &sc->bge_mii; 4099 4100 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4101 ifmr->ifm_status = IFM_AVALID; 4102 ifmr->ifm_active = IFM_ETHER; 4103 if (CSR_READ_4(sc, BGE_MAC_STS) & 4104 BGE_MACSTAT_TBI_PCS_SYNCHED) 4105 ifmr->ifm_status |= IFM_ACTIVE; 4106 ifmr->ifm_active |= IFM_1000_SX; 4107 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4108 ifmr->ifm_active |= IFM_HDX; 4109 else 4110 ifmr->ifm_active |= IFM_FDX; 4111 return; 4112 } 4113 4114 mii_pollstat(mii); 4115 ifmr->ifm_status = mii->mii_media_status; 4116 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4117 sc->bge_flowflags; 4118 } 4119 4120 static int 4121 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4122 { 4123 struct bge_softc *sc = ifp->if_softc; 4124 struct ifreq *ifr = (struct ifreq *) data; 4125 int s, error = 0; 4126 struct mii_data *mii; 4127 4128 s = splnet(); 4129 4130 switch(command) { 4131 case SIOCSIFFLAGS: 4132 if ((error = ifioctl_common(ifp, command, data)) != 0) 4133 break; 4134 if (ifp->if_flags & IFF_UP) { 4135 /* 4136 * If only the state of the PROMISC flag changed, 4137 * then just use the 'set promisc mode' command 4138 * instead of reinitializing the entire NIC. Doing 4139 * a full re-init means reloading the firmware and 4140 * waiting for it to start up, which may take a 4141 * second or two. 4142 */ 4143 if (ifp->if_flags & IFF_RUNNING && 4144 ifp->if_flags & IFF_PROMISC && 4145 !(sc->bge_if_flags & IFF_PROMISC)) { 4146 BGE_SETBIT(sc, BGE_RX_MODE, 4147 BGE_RXMODE_RX_PROMISC); 4148 } else if (ifp->if_flags & IFF_RUNNING && 4149 !(ifp->if_flags & IFF_PROMISC) && 4150 sc->bge_if_flags & IFF_PROMISC) { 4151 BGE_CLRBIT(sc, BGE_RX_MODE, 4152 BGE_RXMODE_RX_PROMISC); 4153 } else if (!(sc->bge_if_flags & IFF_UP)) 4154 bge_init(ifp); 4155 } else { 4156 if (ifp->if_flags & IFF_RUNNING) 4157 bge_stop(ifp, 1); 4158 } 4159 sc->bge_if_flags = ifp->if_flags; 4160 error = 0; 4161 break; 4162 case SIOCSIFMEDIA: 4163 /* XXX Flow control is not supported for 1000BASE-SX */ 4164 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4165 ifr->ifr_media &= ~IFM_ETH_FMASK; 4166 sc->bge_flowflags = 0; 4167 } 4168 4169 /* Flow control requires full-duplex mode. */ 4170 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4171 (ifr->ifr_media & IFM_FDX) == 0) { 4172 ifr->ifr_media &= ~IFM_ETH_FMASK; 4173 } 4174 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4175 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4176 /* We can do both TXPAUSE and RXPAUSE. */ 4177 ifr->ifr_media |= 4178 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4179 } 4180 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4181 } 4182 /* FALLTHROUGH */ 4183 case SIOCGIFMEDIA: 4184 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4185 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4186 command); 4187 } else { 4188 mii = &sc->bge_mii; 4189 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4190 command); 4191 } 4192 break; 4193 default: 4194 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4195 break; 4196 4197 error = 0; 4198 4199 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4200 ; 4201 else if (ifp->if_flags & IFF_RUNNING) 4202 bge_setmulti(sc); 4203 break; 4204 } 4205 4206 splx(s); 4207 4208 return (error); 4209 } 4210 4211 static void 4212 bge_watchdog(struct ifnet *ifp) 4213 { 4214 struct bge_softc *sc; 4215 4216 sc = ifp->if_softc; 4217 4218 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4219 4220 ifp->if_flags &= ~IFF_RUNNING; 4221 bge_init(ifp); 4222 4223 ifp->if_oerrors++; 4224 } 4225 4226 static void 4227 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4228 { 4229 int i; 4230 4231 BGE_CLRBIT(sc, reg, bit); 4232 4233 for (i = 0; i < BGE_TIMEOUT; i++) { 4234 if ((CSR_READ_4(sc, reg) & bit) == 0) 4235 return; 4236 delay(100); 4237 if (sc->bge_flags & BGE_PCIE) 4238 DELAY(1000); 4239 } 4240 4241 aprint_error_dev(sc->bge_dev, 4242 "block failed to stop: reg 0x%lx, bit 0x%08x\n", (u_long)reg, bit); 4243 } 4244 4245 /* 4246 * Stop the adapter and free any mbufs allocated to the 4247 * RX and TX lists. 4248 */ 4249 static void 4250 bge_stop(struct ifnet *ifp, int disable) 4251 { 4252 struct bge_softc *sc = ifp->if_softc; 4253 4254 callout_stop(&sc->bge_timeout); 4255 4256 /* 4257 * Disable all of the receiver blocks 4258 */ 4259 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4260 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4261 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4262 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4263 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4264 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4265 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4266 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4267 4268 /* 4269 * Disable all of the transmit blocks 4270 */ 4271 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4272 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4273 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4274 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4275 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4276 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4277 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4278 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4279 4280 /* 4281 * Shut down all of the memory managers and related 4282 * state machines. 4283 */ 4284 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4285 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4286 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4287 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4288 4289 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4290 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4291 4292 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 4293 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4294 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4295 } 4296 4297 /* Disable host interrupts. */ 4298 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4299 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4300 4301 /* 4302 * Tell firmware we're shutting down. 4303 */ 4304 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4305 4306 /* Free the RX lists. */ 4307 bge_free_rx_ring_std(sc); 4308 4309 /* Free jumbo RX list. */ 4310 bge_free_rx_ring_jumbo(sc); 4311 4312 /* Free TX buffers. */ 4313 bge_free_tx_ring(sc); 4314 4315 /* 4316 * Isolate/power down the PHY. 4317 */ 4318 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4319 mii_down(&sc->bge_mii); 4320 4321 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4322 4323 /* Clear MAC's link state (PHY may still have link UP). */ 4324 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4325 4326 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4327 } 4328 4329 static void 4330 bge_link_upd(struct bge_softc *sc) 4331 { 4332 struct ifnet *ifp = &sc->ethercom.ec_if; 4333 struct mii_data *mii = &sc->bge_mii; 4334 u_int32_t status; 4335 int link; 4336 4337 /* Clear 'pending link event' flag */ 4338 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4339 4340 /* 4341 * Process link state changes. 4342 * Grrr. The link status word in the status block does 4343 * not work correctly on the BCM5700 rev AX and BX chips, 4344 * according to all available information. Hence, we have 4345 * to enable MII interrupts in order to properly obtain 4346 * async link changes. Unfortunately, this also means that 4347 * we have to read the MAC status register to detect link 4348 * changes, thereby adding an additional register access to 4349 * the interrupt handler. 4350 */ 4351 4352 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4353 status = CSR_READ_4(sc, BGE_MAC_STS); 4354 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4355 mii_pollstat(mii); 4356 4357 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4358 mii->mii_media_status & IFM_ACTIVE && 4359 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4360 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4361 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4362 (!(mii->mii_media_status & IFM_ACTIVE) || 4363 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4364 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4365 4366 /* Clear the interrupt */ 4367 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4368 BGE_EVTENB_MI_INTERRUPT); 4369 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4370 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4371 BRGPHY_INTRS); 4372 } 4373 return; 4374 } 4375 4376 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4377 status = CSR_READ_4(sc, BGE_MAC_STS); 4378 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4379 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4380 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4381 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4382 BGE_CLRBIT(sc, BGE_MAC_MODE, 4383 BGE_MACMODE_TBI_SEND_CFGS); 4384 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4385 if_link_state_change(ifp, LINK_STATE_UP); 4386 } 4387 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4388 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4389 if_link_state_change(ifp, LINK_STATE_DOWN); 4390 } 4391 /* 4392 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4393 * This should not happen since mii callouts are locked now, but 4394 * we keep this check for debug. 4395 */ 4396 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4397 /* 4398 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4399 * bit in status word always set. Workaround this bug by 4400 * reading PHY link status directly. 4401 */ 4402 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4403 BGE_STS_LINK : 0; 4404 4405 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4406 mii_pollstat(mii); 4407 4408 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4409 mii->mii_media_status & IFM_ACTIVE && 4410 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4411 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4412 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4413 (!(mii->mii_media_status & IFM_ACTIVE) || 4414 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4415 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4416 } 4417 } 4418 4419 /* Clear the attention */ 4420 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4421 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4422 BGE_MACSTAT_LINK_CHANGED); 4423 } 4424 4425 static int 4426 sysctl_bge_verify(SYSCTLFN_ARGS) 4427 { 4428 int error, t; 4429 struct sysctlnode node; 4430 4431 node = *rnode; 4432 t = *(int*)rnode->sysctl_data; 4433 node.sysctl_data = &t; 4434 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4435 if (error || newp == NULL) 4436 return (error); 4437 4438 #if 0 4439 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4440 node.sysctl_num, rnode->sysctl_num)); 4441 #endif 4442 4443 if (node.sysctl_num == bge_rxthresh_nodenum) { 4444 if (t < 0 || t >= NBGE_RX_THRESH) 4445 return (EINVAL); 4446 bge_update_all_threshes(t); 4447 } else 4448 return (EINVAL); 4449 4450 *(int*)rnode->sysctl_data = t; 4451 4452 return (0); 4453 } 4454 4455 /* 4456 * Set up sysctl(3) MIB, hw.bge.*. 4457 * 4458 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4459 */ 4460 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4461 { 4462 int rc, bge_root_num; 4463 const struct sysctlnode *node; 4464 4465 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4466 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4467 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4468 goto err; 4469 } 4470 4471 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4472 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4473 SYSCTL_DESCR("BGE interface controls"), 4474 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4475 goto err; 4476 } 4477 4478 bge_root_num = node->sysctl_num; 4479 4480 /* BGE Rx interrupt mitigation level */ 4481 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4482 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4483 CTLTYPE_INT, "rx_lvl", 4484 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4485 sysctl_bge_verify, 0, 4486 &bge_rx_thresh_lvl, 4487 0, CTL_HW, bge_root_num, CTL_CREATE, 4488 CTL_EOL)) != 0) { 4489 goto err; 4490 } 4491 4492 bge_rxthresh_nodenum = node->sysctl_num; 4493 4494 return; 4495 4496 err: 4497 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4498 } 4499 4500 static int 4501 bge_get_eaddr_mem(struct bge_softc *sc, u_int8_t ether_addr[]) 4502 { 4503 u_int32_t mac_addr; 4504 4505 mac_addr = bge_readmem_ind(sc, 0x0c14); 4506 if ((mac_addr >> 16) == 0x484b) { 4507 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4508 ether_addr[1] = (uint8_t)mac_addr; 4509 mac_addr = bge_readmem_ind(sc, 0x0c18); 4510 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4511 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4512 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4513 ether_addr[5] = (uint8_t)mac_addr; 4514 return (0); 4515 } 4516 return (1); 4517 } 4518 4519 static int 4520 bge_get_eaddr_nvram(struct bge_softc *sc, u_int8_t ether_addr[]) 4521 { 4522 int mac_offset = BGE_EE_MAC_OFFSET; 4523 4524 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4525 mac_offset = BGE_EE_MAC_OFFSET_5906; 4526 } 4527 4528 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4529 ETHER_ADDR_LEN)); 4530 } 4531 4532 static int 4533 bge_get_eaddr_eeprom(struct bge_softc *sc, u_int8_t ether_addr[]) 4534 { 4535 4536 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4537 return (1); 4538 } 4539 4540 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4541 ETHER_ADDR_LEN)); 4542 } 4543 4544 static int 4545 bge_get_eaddr(struct bge_softc *sc, u_int8_t eaddr[]) 4546 { 4547 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4548 /* NOTE: Order is critical */ 4549 bge_get_eaddr_mem, 4550 bge_get_eaddr_nvram, 4551 bge_get_eaddr_eeprom, 4552 NULL 4553 }; 4554 const bge_eaddr_fcn_t *func; 4555 4556 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4557 if ((*func)(sc, eaddr) == 0) 4558 break; 4559 } 4560 return (*func == NULL ? ENXIO : 0); 4561 } 4562