1 /* $NetBSD: if_bge.c,v 1.188 2010/11/13 13:52:06 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl@wasabisystems.com> 44 * Jason Thorpe <thorpej@wasabisystems.com> 45 * Jonathan Stone <jonathan@dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul@windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.188 2010/11/13 13:52:06 uebayasi Exp $"); 83 84 #include "vlan.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/device.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NRND > 0 104 #include <sys/rnd.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/in_systm.h> 110 #include <netinet/in_var.h> 111 #include <netinet/ip.h> 112 #endif 113 114 /* Headers for TCP Segmentation Offload (TSO) */ 115 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 116 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 117 #include <netinet/ip.h> /* for struct ip */ 118 #include <netinet/tcp.h> /* for struct tcphdr */ 119 120 121 #include <net/bpf.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #include <dev/mii/miidevs.h> 130 #include <dev/mii/brgphyreg.h> 131 132 #include <dev/pci/if_bgereg.h> 133 #include <dev/pci/if_bgevar.h> 134 135 #include <prop/proplib.h> 136 137 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 138 139 140 /* 141 * Tunable thresholds for rx-side bge interrupt mitigation. 142 */ 143 144 /* 145 * The pairs of values below were obtained from empirical measurement 146 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 147 * interrupt for every N packets received, where N is, approximately, 148 * the second value (rx_max_bds) in each pair. The values are chosen 149 * such that moving from one pair to the succeeding pair was observed 150 * to roughly halve interrupt rate under sustained input packet load. 151 * The values were empirically chosen to avoid overflowing internal 152 * limits on the bcm5700: increasing rx_ticks much beyond 600 153 * results in internal wrapping and higher interrupt rates. 154 * The limit of 46 frames was chosen to match NFS workloads. 155 * 156 * These values also work well on bcm5701, bcm5704C, and (less 157 * tested) bcm5703. On other chipsets, (including the Altima chip 158 * family), the larger values may overflow internal chip limits, 159 * leading to increasing interrupt rates rather than lower interrupt 160 * rates. 161 * 162 * Applications using heavy interrupt mitigation (interrupting every 163 * 32 or 46 frames) in both directions may need to increase the TCP 164 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 165 * full link bandwidth, due to ACKs and window updates lingering 166 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 167 */ 168 static const struct bge_load_rx_thresh { 169 int rx_ticks; 170 int rx_max_bds; } 171 bge_rx_threshes[] = { 172 { 32, 2 }, 173 { 50, 4 }, 174 { 100, 8 }, 175 { 192, 16 }, 176 { 416, 32 }, 177 { 598, 46 } 178 }; 179 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 180 181 /* XXX patchable; should be sysctl'able */ 182 static int bge_auto_thresh = 1; 183 static int bge_rx_thresh_lvl; 184 185 static int bge_rxthresh_nodenum; 186 187 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 188 189 static int bge_probe(device_t, cfdata_t, void *); 190 static void bge_attach(device_t, device_t, void *); 191 static void bge_release_resources(struct bge_softc *); 192 193 static int bge_get_eaddr_fw(struct bge_softc *, uint8_t[]); 194 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 195 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 196 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 197 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 198 199 static void bge_txeof(struct bge_softc *); 200 static void bge_rxeof(struct bge_softc *); 201 202 static void bge_asf_driver_up (struct bge_softc *); 203 static void bge_tick(void *); 204 static void bge_stats_update(struct bge_softc *); 205 static void bge_stats_update_regs(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ifflags_cb(struct ethercom *); 211 static int bge_ioctl(struct ifnet *, u_long, void *); 212 static int bge_init(struct ifnet *); 213 static void bge_stop(struct ifnet *, int); 214 static void bge_watchdog(struct ifnet *); 215 static int bge_ifmedia_upd(struct ifnet *); 216 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 217 218 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 219 static int bge_read_nvram(struct bge_softc *, uint8_t *, int, int); 220 221 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 222 static int bge_read_eeprom(struct bge_softc *, void *, int, int); 223 static void bge_setmulti(struct bge_softc *); 224 225 static void bge_handle_events(struct bge_softc *); 226 static int bge_alloc_jumbo_mem(struct bge_softc *); 227 #if 0 /* XXX */ 228 static void bge_free_jumbo_mem(struct bge_softc *); 229 #endif 230 static void *bge_jalloc(struct bge_softc *); 231 static void bge_jfree(struct mbuf *, void *, size_t, void *); 232 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 233 bus_dmamap_t); 234 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 235 static int bge_init_rx_ring_std(struct bge_softc *); 236 static void bge_free_rx_ring_std(struct bge_softc *); 237 static int bge_init_rx_ring_jumbo(struct bge_softc *); 238 static void bge_free_rx_ring_jumbo(struct bge_softc *); 239 static void bge_free_tx_ring(struct bge_softc *); 240 static int bge_init_tx_ring(struct bge_softc *); 241 242 static int bge_chipinit(struct bge_softc *); 243 static int bge_blockinit(struct bge_softc *); 244 static int bge_setpowerstate(struct bge_softc *, int); 245 static uint32_t bge_readmem_ind(struct bge_softc *, int); 246 static void bge_writemem_ind(struct bge_softc *, int, int); 247 static void bge_writembx(struct bge_softc *, int, int); 248 static void bge_writemem_direct(struct bge_softc *, int, int); 249 static void bge_writereg_ind(struct bge_softc *, int, int); 250 static void bge_set_max_readrq(struct bge_softc *); 251 252 static int bge_miibus_readreg(device_t, int, int); 253 static void bge_miibus_writereg(device_t, int, int, int); 254 static void bge_miibus_statchg(device_t); 255 256 #define BGE_RESET_START 1 257 #define BGE_RESET_STOP 2 258 static void bge_sig_post_reset(struct bge_softc *, int); 259 static void bge_sig_legacy(struct bge_softc *, int); 260 static void bge_sig_pre_reset(struct bge_softc *, int); 261 static void bge_stop_fw(struct bge_softc *); 262 static int bge_reset(struct bge_softc *); 263 static void bge_link_upd(struct bge_softc *); 264 265 #ifdef BGE_DEBUG 266 #define DPRINTF(x) if (bgedebug) printf x 267 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 268 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 269 int bgedebug = 0; 270 int bge_tso_debug = 0; 271 void bge_debug_info(struct bge_softc *); 272 #else 273 #define DPRINTF(x) 274 #define DPRINTFN(n,x) 275 #define BGE_TSO_PRINTF(x) 276 #endif 277 278 #ifdef BGE_EVENT_COUNTERS 279 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 280 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 281 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 282 #else 283 #define BGE_EVCNT_INCR(ev) /* nothing */ 284 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 285 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 286 #endif 287 288 static const struct bge_product { 289 pci_vendor_id_t bp_vendor; 290 pci_product_id_t bp_product; 291 const char *bp_name; 292 } bge_products[] = { 293 /* 294 * The BCM5700 documentation seems to indicate that the hardware 295 * still has the Alteon vendor ID burned into it, though it 296 * should always be overridden by the value in the EEPROM. We'll 297 * check for it anyway. 298 */ 299 { PCI_VENDOR_ALTEON, 300 PCI_PRODUCT_ALTEON_BCM5700, 301 "Broadcom BCM5700 Gigabit Ethernet", 302 }, 303 { PCI_VENDOR_ALTEON, 304 PCI_PRODUCT_ALTEON_BCM5701, 305 "Broadcom BCM5701 Gigabit Ethernet", 306 }, 307 { PCI_VENDOR_ALTIMA, 308 PCI_PRODUCT_ALTIMA_AC1000, 309 "Altima AC1000 Gigabit Ethernet", 310 }, 311 { PCI_VENDOR_ALTIMA, 312 PCI_PRODUCT_ALTIMA_AC1001, 313 "Altima AC1001 Gigabit Ethernet", 314 }, 315 { PCI_VENDOR_ALTIMA, 316 PCI_PRODUCT_ALTIMA_AC9100, 317 "Altima AC9100 Gigabit Ethernet", 318 }, 319 { PCI_VENDOR_BROADCOM, 320 PCI_PRODUCT_BROADCOM_BCM5700, 321 "Broadcom BCM5700 Gigabit Ethernet", 322 }, 323 { PCI_VENDOR_BROADCOM, 324 PCI_PRODUCT_BROADCOM_BCM5701, 325 "Broadcom BCM5701 Gigabit Ethernet", 326 }, 327 { PCI_VENDOR_BROADCOM, 328 PCI_PRODUCT_BROADCOM_BCM5702, 329 "Broadcom BCM5702 Gigabit Ethernet", 330 }, 331 { PCI_VENDOR_BROADCOM, 332 PCI_PRODUCT_BROADCOM_BCM5702X, 333 "Broadcom BCM5702X Gigabit Ethernet" }, 334 { PCI_VENDOR_BROADCOM, 335 PCI_PRODUCT_BROADCOM_BCM5703, 336 "Broadcom BCM5703 Gigabit Ethernet", 337 }, 338 { PCI_VENDOR_BROADCOM, 339 PCI_PRODUCT_BROADCOM_BCM5703X, 340 "Broadcom BCM5703X Gigabit Ethernet", 341 }, 342 { PCI_VENDOR_BROADCOM, 343 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 344 "Broadcom BCM5703 Gigabit Ethernet", 345 }, 346 { PCI_VENDOR_BROADCOM, 347 PCI_PRODUCT_BROADCOM_BCM5704C, 348 "Broadcom BCM5704C Dual Gigabit Ethernet", 349 }, 350 { PCI_VENDOR_BROADCOM, 351 PCI_PRODUCT_BROADCOM_BCM5704S, 352 "Broadcom BCM5704S Dual Gigabit Ethernet", 353 }, 354 { PCI_VENDOR_BROADCOM, 355 PCI_PRODUCT_BROADCOM_BCM5705, 356 "Broadcom BCM5705 Gigabit Ethernet", 357 }, 358 { PCI_VENDOR_BROADCOM, 359 PCI_PRODUCT_BROADCOM_BCM5705F, 360 "Broadcom BCM5705F Gigabit Ethernet", 361 }, 362 { PCI_VENDOR_BROADCOM, 363 PCI_PRODUCT_BROADCOM_BCM5705K, 364 "Broadcom BCM5705K Gigabit Ethernet", 365 }, 366 { PCI_VENDOR_BROADCOM, 367 PCI_PRODUCT_BROADCOM_BCM5705M, 368 "Broadcom BCM5705M Gigabit Ethernet", 369 }, 370 { PCI_VENDOR_BROADCOM, 371 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 372 "Broadcom BCM5705M Gigabit Ethernet", 373 }, 374 { PCI_VENDOR_BROADCOM, 375 PCI_PRODUCT_BROADCOM_BCM5714, 376 "Broadcom BCM5714 Gigabit Ethernet", 377 }, 378 { PCI_VENDOR_BROADCOM, 379 PCI_PRODUCT_BROADCOM_BCM5714S, 380 "Broadcom BCM5714S Gigabit Ethernet", 381 }, 382 { PCI_VENDOR_BROADCOM, 383 PCI_PRODUCT_BROADCOM_BCM5715, 384 "Broadcom BCM5715 Gigabit Ethernet", 385 }, 386 { PCI_VENDOR_BROADCOM, 387 PCI_PRODUCT_BROADCOM_BCM5715S, 388 "Broadcom BCM5715S Gigabit Ethernet", 389 }, 390 { PCI_VENDOR_BROADCOM, 391 PCI_PRODUCT_BROADCOM_BCM5717, 392 "Broadcom BCM5717 Gigabit Ethernet", 393 }, 394 { PCI_VENDOR_BROADCOM, 395 PCI_PRODUCT_BROADCOM_BCM5718, 396 "Broadcom BCM5718 Gigabit Ethernet", 397 }, 398 { PCI_VENDOR_BROADCOM, 399 PCI_PRODUCT_BROADCOM_BCM5720, 400 "Broadcom BCM5720 Gigabit Ethernet", 401 }, 402 { PCI_VENDOR_BROADCOM, 403 PCI_PRODUCT_BROADCOM_BCM5721, 404 "Broadcom BCM5721 Gigabit Ethernet", 405 }, 406 { PCI_VENDOR_BROADCOM, 407 PCI_PRODUCT_BROADCOM_BCM5722, 408 "Broadcom BCM5722 Gigabit Ethernet", 409 }, 410 { PCI_VENDOR_BROADCOM, 411 PCI_PRODUCT_BROADCOM_BCM5723, 412 "Broadcom BCM5723 Gigabit Ethernet", 413 }, 414 { PCI_VENDOR_BROADCOM, 415 PCI_PRODUCT_BROADCOM_BCM5724, 416 "Broadcom BCM5724 Gigabit Ethernet", 417 }, 418 { PCI_VENDOR_BROADCOM, 419 PCI_PRODUCT_BROADCOM_BCM5750, 420 "Broadcom BCM5750 Gigabit Ethernet", 421 }, 422 { PCI_VENDOR_BROADCOM, 423 PCI_PRODUCT_BROADCOM_BCM5750M, 424 "Broadcom BCM5750M Gigabit Ethernet", 425 }, 426 { PCI_VENDOR_BROADCOM, 427 PCI_PRODUCT_BROADCOM_BCM5751, 428 "Broadcom BCM5751 Gigabit Ethernet", 429 }, 430 { PCI_VENDOR_BROADCOM, 431 PCI_PRODUCT_BROADCOM_BCM5751F, 432 "Broadcom BCM5751F Gigabit Ethernet", 433 }, 434 { PCI_VENDOR_BROADCOM, 435 PCI_PRODUCT_BROADCOM_BCM5751M, 436 "Broadcom BCM5751M Gigabit Ethernet", 437 }, 438 { PCI_VENDOR_BROADCOM, 439 PCI_PRODUCT_BROADCOM_BCM5752, 440 "Broadcom BCM5752 Gigabit Ethernet", 441 }, 442 { PCI_VENDOR_BROADCOM, 443 PCI_PRODUCT_BROADCOM_BCM5752M, 444 "Broadcom BCM5752M Gigabit Ethernet", 445 }, 446 { PCI_VENDOR_BROADCOM, 447 PCI_PRODUCT_BROADCOM_BCM5753, 448 "Broadcom BCM5753 Gigabit Ethernet", 449 }, 450 { PCI_VENDOR_BROADCOM, 451 PCI_PRODUCT_BROADCOM_BCM5753F, 452 "Broadcom BCM5753F Gigabit Ethernet", 453 }, 454 { PCI_VENDOR_BROADCOM, 455 PCI_PRODUCT_BROADCOM_BCM5753M, 456 "Broadcom BCM5753M Gigabit Ethernet", 457 }, 458 { PCI_VENDOR_BROADCOM, 459 PCI_PRODUCT_BROADCOM_BCM5754, 460 "Broadcom BCM5754 Gigabit Ethernet", 461 }, 462 { PCI_VENDOR_BROADCOM, 463 PCI_PRODUCT_BROADCOM_BCM5754M, 464 "Broadcom BCM5754M Gigabit Ethernet", 465 }, 466 { PCI_VENDOR_BROADCOM, 467 PCI_PRODUCT_BROADCOM_BCM5755, 468 "Broadcom BCM5755 Gigabit Ethernet", 469 }, 470 { PCI_VENDOR_BROADCOM, 471 PCI_PRODUCT_BROADCOM_BCM5755M, 472 "Broadcom BCM5755M Gigabit Ethernet", 473 }, 474 { PCI_VENDOR_BROADCOM, 475 PCI_PRODUCT_BROADCOM_BCM5756, 476 "Broadcom BCM5756 Gigabit Ethernet", 477 }, 478 { PCI_VENDOR_BROADCOM, 479 PCI_PRODUCT_BROADCOM_BCM5761, 480 "Broadcom BCM5761 Gigabit Ethernet", 481 }, 482 { PCI_VENDOR_BROADCOM, 483 PCI_PRODUCT_BROADCOM_BCM5761E, 484 "Broadcom BCM5761E Gigabit Ethernet", 485 }, 486 { PCI_VENDOR_BROADCOM, 487 PCI_PRODUCT_BROADCOM_BCM5761S, 488 "Broadcom BCM5761S Gigabit Ethernet", 489 }, 490 { PCI_VENDOR_BROADCOM, 491 PCI_PRODUCT_BROADCOM_BCM5761SE, 492 "Broadcom BCM5761SE Gigabit Ethernet", 493 }, 494 { PCI_VENDOR_BROADCOM, 495 PCI_PRODUCT_BROADCOM_BCM5764, 496 "Broadcom BCM5764 Gigabit Ethernet", 497 }, 498 { PCI_VENDOR_BROADCOM, 499 PCI_PRODUCT_BROADCOM_BCM5780, 500 "Broadcom BCM5780 Gigabit Ethernet", 501 }, 502 { PCI_VENDOR_BROADCOM, 503 PCI_PRODUCT_BROADCOM_BCM5780S, 504 "Broadcom BCM5780S Gigabit Ethernet", 505 }, 506 { PCI_VENDOR_BROADCOM, 507 PCI_PRODUCT_BROADCOM_BCM5781, 508 "Broadcom BCM5781 Gigabit Ethernet", 509 }, 510 { PCI_VENDOR_BROADCOM, 511 PCI_PRODUCT_BROADCOM_BCM5782, 512 "Broadcom BCM5782 Gigabit Ethernet", 513 }, 514 { PCI_VENDOR_BROADCOM, 515 PCI_PRODUCT_BROADCOM_BCM5784M, 516 "BCM5784M NetLink 1000baseT Ethernet", 517 }, 518 { PCI_VENDOR_BROADCOM, 519 PCI_PRODUCT_BROADCOM_BCM5786, 520 "Broadcom BCM5786 Gigabit Ethernet", 521 }, 522 { PCI_VENDOR_BROADCOM, 523 PCI_PRODUCT_BROADCOM_BCM5787, 524 "Broadcom BCM5787 Gigabit Ethernet", 525 }, 526 { PCI_VENDOR_BROADCOM, 527 PCI_PRODUCT_BROADCOM_BCM5787M, 528 "Broadcom BCM5787M Gigabit Ethernet", 529 }, 530 { PCI_VENDOR_BROADCOM, 531 PCI_PRODUCT_BROADCOM_BCM5788, 532 "Broadcom BCM5788 Gigabit Ethernet", 533 }, 534 { PCI_VENDOR_BROADCOM, 535 PCI_PRODUCT_BROADCOM_BCM5789, 536 "Broadcom BCM5789 Gigabit Ethernet", 537 }, 538 { PCI_VENDOR_BROADCOM, 539 PCI_PRODUCT_BROADCOM_BCM5901, 540 "Broadcom BCM5901 Fast Ethernet", 541 }, 542 { PCI_VENDOR_BROADCOM, 543 PCI_PRODUCT_BROADCOM_BCM5901A2, 544 "Broadcom BCM5901A2 Fast Ethernet", 545 }, 546 { PCI_VENDOR_BROADCOM, 547 PCI_PRODUCT_BROADCOM_BCM5903M, 548 "Broadcom BCM5903M Fast Ethernet", 549 }, 550 { PCI_VENDOR_BROADCOM, 551 PCI_PRODUCT_BROADCOM_BCM5906, 552 "Broadcom BCM5906 Fast Ethernet", 553 }, 554 { PCI_VENDOR_BROADCOM, 555 PCI_PRODUCT_BROADCOM_BCM5906M, 556 "Broadcom BCM5906M Fast Ethernet", 557 }, 558 { PCI_VENDOR_BROADCOM, 559 PCI_PRODUCT_BROADCOM_BCM57760, 560 "Broadcom BCM57760 Fast Ethernet", 561 }, 562 { PCI_VENDOR_BROADCOM, 563 PCI_PRODUCT_BROADCOM_BCM57761, 564 "Broadcom BCM57761 Fast Ethernet", 565 }, 566 { PCI_VENDOR_BROADCOM, 567 PCI_PRODUCT_BROADCOM_BCM57765, 568 "Broadcom BCM57765 Fast Ethernet", 569 }, 570 { PCI_VENDOR_BROADCOM, 571 PCI_PRODUCT_BROADCOM_BCM57780, 572 "Broadcom BCM57780 Fast Ethernet", 573 }, 574 { PCI_VENDOR_BROADCOM, 575 PCI_PRODUCT_BROADCOM_BCM57781, 576 "Broadcom BCM57781 Fast Ethernet", 577 }, 578 { PCI_VENDOR_BROADCOM, 579 PCI_PRODUCT_BROADCOM_BCM57785, 580 "Broadcom BCM57785 Fast Ethernet", 581 }, 582 { PCI_VENDOR_BROADCOM, 583 PCI_PRODUCT_BROADCOM_BCM57788, 584 "Broadcom BCM57788 Fast Ethernet", 585 }, 586 { PCI_VENDOR_BROADCOM, 587 PCI_PRODUCT_BROADCOM_BCM57790, 588 "Broadcom BCM57790 Fast Ethernet", 589 }, 590 { PCI_VENDOR_BROADCOM, 591 PCI_PRODUCT_BROADCOM_BCM57791, 592 "Broadcom BCM57791 Fast Ethernet", 593 }, 594 { PCI_VENDOR_BROADCOM, 595 PCI_PRODUCT_BROADCOM_BCM57795, 596 "Broadcom BCM57795 Fast Ethernet", 597 }, 598 { PCI_VENDOR_SCHNEIDERKOCH, 599 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 600 "SysKonnect SK-9Dx1 Gigabit Ethernet", 601 }, 602 { PCI_VENDOR_3COM, 603 PCI_PRODUCT_3COM_3C996, 604 "3Com 3c996 Gigabit Ethernet", 605 }, 606 { 0, 607 0, 608 NULL }, 609 }; 610 611 /* 612 * XXX: how to handle variants based on 5750 and derivatives: 613 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 614 * in general behave like a 5705, except with additional quirks. 615 * This driver's current handling of the 5721 is wrong; 616 * how we map ASIC revision to "quirks" needs more thought. 617 * (defined here until the thought is done). 618 */ 619 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 620 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 621 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 622 #define BGE_IS_5750_OR_BEYOND(sc) ((sc)->bge_flags & BGE_5750_PLUS) 623 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 624 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 625 626 static const struct bge_revision { 627 uint32_t br_chipid; 628 const char *br_name; 629 } bge_revisions[] = { 630 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 631 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 632 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 633 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 634 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 635 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 636 /* This is treated like a BCM5700 Bx */ 637 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 638 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 639 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 640 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 641 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 642 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 643 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 644 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 645 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 646 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 647 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 648 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 649 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 650 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 651 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 652 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 653 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 654 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 655 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 656 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 657 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 658 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 659 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 660 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 661 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 662 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 663 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 664 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 665 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 666 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 667 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 668 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 669 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 670 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 671 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 672 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 673 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 674 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 675 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 676 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 677 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 678 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 679 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 680 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 681 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 682 /* 5754 and 5787 share the same ASIC ID */ 683 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 684 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 685 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 686 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 687 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 688 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 689 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 690 691 { 0, NULL } 692 }; 693 694 /* 695 * Some defaults for major revisions, so that newer steppings 696 * that we don't know about have a shot at working. 697 */ 698 static const struct bge_revision bge_majorrevs[] = { 699 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 700 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 701 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 702 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 703 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 704 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 705 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 706 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 707 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 708 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 709 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 710 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 711 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 712 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 713 /* 5754 and 5787 share the same ASIC ID */ 714 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 715 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 716 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 717 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 718 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 719 720 { 0, NULL } 721 }; 722 723 static int bge_allow_asf = 1; 724 725 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 726 bge_probe, bge_attach, NULL, NULL); 727 728 static uint32_t 729 bge_readmem_ind(struct bge_softc *sc, int off) 730 { 731 pcireg_t val; 732 733 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 734 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 735 return val; 736 } 737 738 static void 739 bge_writemem_ind(struct bge_softc *sc, int off, int val) 740 { 741 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 742 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 743 } 744 745 /* 746 * PCI Express only 747 */ 748 static void 749 bge_set_max_readrq(struct bge_softc *sc) 750 { 751 pcireg_t val; 752 753 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 754 + PCI_PCIE_DCSR); 755 if ((val & PCI_PCIE_DCSR_MAX_READ_REQ) != 756 BGE_PCIE_DEVCTL_MAX_READRQ_4096) { 757 aprint_verbose("adjust device control 0x%04x ", val); 758 val &= ~PCI_PCIE_DCSR_MAX_READ_REQ; 759 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096; 760 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pciecap 761 + PCI_PCIE_DCSR, val); 762 aprint_verbose("-> 0x%04x\n", val); 763 } 764 } 765 766 #ifdef notdef 767 static uint32_t 768 bge_readreg_ind(struct bge_softc *sc, int off) 769 { 770 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 771 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 772 } 773 #endif 774 775 static void 776 bge_writereg_ind(struct bge_softc *sc, int off, int val) 777 { 778 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 779 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 780 } 781 782 static void 783 bge_writemem_direct(struct bge_softc *sc, int off, int val) 784 { 785 CSR_WRITE_4(sc, off, val); 786 } 787 788 static void 789 bge_writembx(struct bge_softc *sc, int off, int val) 790 { 791 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 792 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 793 794 CSR_WRITE_4(sc, off, val); 795 } 796 797 static uint8_t 798 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 799 { 800 uint32_t access, byte = 0; 801 int i; 802 803 /* Lock. */ 804 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 805 for (i = 0; i < 8000; i++) { 806 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 807 break; 808 DELAY(20); 809 } 810 if (i == 8000) 811 return 1; 812 813 /* Enable access. */ 814 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 815 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 816 817 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 818 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 819 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 820 DELAY(10); 821 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 822 DELAY(10); 823 break; 824 } 825 } 826 827 if (i == BGE_TIMEOUT * 10) { 828 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 829 return 1; 830 } 831 832 /* Get result. */ 833 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 834 835 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 836 837 /* Disable access. */ 838 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 839 840 /* Unlock. */ 841 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 842 CSR_READ_4(sc, BGE_NVRAM_SWARB); 843 844 return 0; 845 } 846 847 /* 848 * Read a sequence of bytes from NVRAM. 849 */ 850 static int 851 bge_read_nvram(struct bge_softc *sc, uint8_t *dest, int off, int cnt) 852 { 853 int err = 0, i; 854 uint8_t byte = 0; 855 856 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 857 return 1; 858 859 for (i = 0; i < cnt; i++) { 860 err = bge_nvram_getbyte(sc, off + i, &byte); 861 if (err) 862 break; 863 *(dest + i) = byte; 864 } 865 866 return (err ? 1 : 0); 867 } 868 869 /* 870 * Read a byte of data stored in the EEPROM at address 'addr.' The 871 * BCM570x supports both the traditional bitbang interface and an 872 * auto access interface for reading the EEPROM. We use the auto 873 * access method. 874 */ 875 static uint8_t 876 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 877 { 878 int i; 879 uint32_t byte = 0; 880 881 /* 882 * Enable use of auto EEPROM access so we can avoid 883 * having to use the bitbang method. 884 */ 885 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 886 887 /* Reset the EEPROM, load the clock period. */ 888 CSR_WRITE_4(sc, BGE_EE_ADDR, 889 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 890 DELAY(20); 891 892 /* Issue the read EEPROM command. */ 893 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 894 895 /* Wait for completion */ 896 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 897 DELAY(10); 898 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 899 break; 900 } 901 902 if (i == BGE_TIMEOUT * 10) { 903 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 904 return 1; 905 } 906 907 /* Get result. */ 908 byte = CSR_READ_4(sc, BGE_EE_DATA); 909 910 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 911 912 return 0; 913 } 914 915 /* 916 * Read a sequence of bytes from the EEPROM. 917 */ 918 static int 919 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 920 { 921 int err = 0, i; 922 uint8_t byte = 0; 923 char *dest = destv; 924 925 for (i = 0; i < cnt; i++) { 926 err = bge_eeprom_getbyte(sc, off + i, &byte); 927 if (err) 928 break; 929 *(dest + i) = byte; 930 } 931 932 return (err ? 1 : 0); 933 } 934 935 static int 936 bge_miibus_readreg(device_t dev, int phy, int reg) 937 { 938 struct bge_softc *sc = device_private(dev); 939 uint32_t val; 940 uint32_t autopoll; 941 int i; 942 943 /* 944 * Broadcom's own driver always assumes the internal 945 * PHY is at GMII address 1. On some chips, the PHY responds 946 * to accesses at all addresses, which could cause us to 947 * bogusly attach the PHY 32 times at probe type. Always 948 * restricting the lookup to address 1 is simpler than 949 * trying to figure out which chips revisions should be 950 * special-cased. 951 */ 952 if (phy != 1) 953 return 0; 954 955 /* Reading with autopolling on may trigger PCI errors */ 956 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 957 if (autopoll & BGE_MIMODE_AUTOPOLL) { 958 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 959 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 960 DELAY(40); 961 } 962 963 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 964 BGE_MIPHY(phy) | BGE_MIREG(reg)); 965 966 for (i = 0; i < BGE_TIMEOUT; i++) { 967 val = CSR_READ_4(sc, BGE_MI_COMM); 968 if (!(val & BGE_MICOMM_BUSY)) 969 break; 970 delay(10); 971 } 972 973 if (i == BGE_TIMEOUT) { 974 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 975 val = 0; 976 goto done; 977 } 978 979 val = CSR_READ_4(sc, BGE_MI_COMM); 980 981 done: 982 if (autopoll & BGE_MIMODE_AUTOPOLL) { 983 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 984 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 985 DELAY(40); 986 } 987 988 if (val & BGE_MICOMM_READFAIL) 989 return 0; 990 991 return (val & 0xFFFF); 992 } 993 994 static void 995 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 996 { 997 struct bge_softc *sc = device_private(dev); 998 uint32_t autopoll; 999 int i; 1000 1001 if (phy!=1) { 1002 return; 1003 } 1004 1005 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1006 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 1007 return; 1008 } 1009 1010 /* Reading with autopolling on may trigger PCI errors */ 1011 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1012 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1013 delay(40); 1014 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1015 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1016 delay(10); /* 40 usec is supposed to be adequate */ 1017 } 1018 1019 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1020 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1021 1022 for (i = 0; i < BGE_TIMEOUT; i++) { 1023 delay(10); 1024 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1025 delay(5); 1026 CSR_READ_4(sc, BGE_MI_COMM); 1027 break; 1028 } 1029 } 1030 1031 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1032 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1033 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1034 delay(40); 1035 } 1036 1037 if (i == BGE_TIMEOUT) 1038 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 1039 } 1040 1041 static void 1042 bge_miibus_statchg(device_t dev) 1043 { 1044 struct bge_softc *sc = device_private(dev); 1045 struct mii_data *mii = &sc->bge_mii; 1046 1047 /* 1048 * Get flow control negotiation result. 1049 */ 1050 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1051 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 1052 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1053 mii->mii_media_active &= ~IFM_ETH_FMASK; 1054 } 1055 1056 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 1057 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1058 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1059 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 1060 else 1061 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 1062 1063 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1064 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1065 else 1066 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 1067 1068 /* 1069 * 802.3x flow control 1070 */ 1071 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1072 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1073 else 1074 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 1075 1076 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1077 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1078 else 1079 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 1080 } 1081 1082 /* 1083 * Update rx threshold levels to values in a particular slot 1084 * of the interrupt-mitigation table bge_rx_threshes. 1085 */ 1086 static void 1087 bge_set_thresh(struct ifnet *ifp, int lvl) 1088 { 1089 struct bge_softc *sc = ifp->if_softc; 1090 int s; 1091 1092 /* For now, just save the new Rx-intr thresholds and record 1093 * that a threshold update is pending. Updating the hardware 1094 * registers here (even at splhigh()) is observed to 1095 * occasionaly cause glitches where Rx-interrupts are not 1096 * honoured for up to 10 seconds. jonathan@NetBSD.org, 2003-04-05 1097 */ 1098 s = splnet(); 1099 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 1100 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 1101 sc->bge_pending_rxintr_change = 1; 1102 splx(s); 1103 1104 return; 1105 } 1106 1107 1108 /* 1109 * Update Rx thresholds of all bge devices 1110 */ 1111 static void 1112 bge_update_all_threshes(int lvl) 1113 { 1114 struct ifnet *ifp; 1115 const char * const namebuf = "bge"; 1116 int namelen; 1117 1118 if (lvl < 0) 1119 lvl = 0; 1120 else if (lvl >= NBGE_RX_THRESH) 1121 lvl = NBGE_RX_THRESH - 1; 1122 1123 namelen = strlen(namebuf); 1124 /* 1125 * Now search all the interfaces for this name/number 1126 */ 1127 IFNET_FOREACH(ifp) { 1128 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 1129 continue; 1130 /* We got a match: update if doing auto-threshold-tuning */ 1131 if (bge_auto_thresh) 1132 bge_set_thresh(ifp, lvl); 1133 } 1134 } 1135 1136 /* 1137 * Handle events that have triggered interrupts. 1138 */ 1139 static void 1140 bge_handle_events(struct bge_softc *sc) 1141 { 1142 1143 return; 1144 } 1145 1146 /* 1147 * Memory management for jumbo frames. 1148 */ 1149 1150 static int 1151 bge_alloc_jumbo_mem(struct bge_softc *sc) 1152 { 1153 char *ptr, *kva; 1154 bus_dma_segment_t seg; 1155 int i, rseg, state, error; 1156 struct bge_jpool_entry *entry; 1157 1158 state = error = 0; 1159 1160 /* Grab a big chunk o' storage. */ 1161 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1162 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1163 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1164 return ENOBUFS; 1165 } 1166 1167 state = 1; 1168 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1169 BUS_DMA_NOWAIT)) { 1170 aprint_error_dev(sc->bge_dev, 1171 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1172 error = ENOBUFS; 1173 goto out; 1174 } 1175 1176 state = 2; 1177 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1178 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1179 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1180 error = ENOBUFS; 1181 goto out; 1182 } 1183 1184 state = 3; 1185 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1186 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1187 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1188 error = ENOBUFS; 1189 goto out; 1190 } 1191 1192 state = 4; 1193 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1194 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1195 1196 SLIST_INIT(&sc->bge_jfree_listhead); 1197 SLIST_INIT(&sc->bge_jinuse_listhead); 1198 1199 /* 1200 * Now divide it up into 9K pieces and save the addresses 1201 * in an array. 1202 */ 1203 ptr = sc->bge_cdata.bge_jumbo_buf; 1204 for (i = 0; i < BGE_JSLOTS; i++) { 1205 sc->bge_cdata.bge_jslots[i] = ptr; 1206 ptr += BGE_JLEN; 1207 entry = malloc(sizeof(struct bge_jpool_entry), 1208 M_DEVBUF, M_NOWAIT); 1209 if (entry == NULL) { 1210 aprint_error_dev(sc->bge_dev, 1211 "no memory for jumbo buffer queue!\n"); 1212 error = ENOBUFS; 1213 goto out; 1214 } 1215 entry->slot = i; 1216 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1217 entry, jpool_entries); 1218 } 1219 out: 1220 if (error != 0) { 1221 switch (state) { 1222 case 4: 1223 bus_dmamap_unload(sc->bge_dmatag, 1224 sc->bge_cdata.bge_rx_jumbo_map); 1225 case 3: 1226 bus_dmamap_destroy(sc->bge_dmatag, 1227 sc->bge_cdata.bge_rx_jumbo_map); 1228 case 2: 1229 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1230 case 1: 1231 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1232 break; 1233 default: 1234 break; 1235 } 1236 } 1237 1238 return error; 1239 } 1240 1241 /* 1242 * Allocate a jumbo buffer. 1243 */ 1244 static void * 1245 bge_jalloc(struct bge_softc *sc) 1246 { 1247 struct bge_jpool_entry *entry; 1248 1249 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1250 1251 if (entry == NULL) { 1252 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1253 return NULL; 1254 } 1255 1256 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1257 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1258 return (sc->bge_cdata.bge_jslots[entry->slot]); 1259 } 1260 1261 /* 1262 * Release a jumbo buffer. 1263 */ 1264 static void 1265 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1266 { 1267 struct bge_jpool_entry *entry; 1268 struct bge_softc *sc; 1269 int i, s; 1270 1271 /* Extract the softc struct pointer. */ 1272 sc = (struct bge_softc *)arg; 1273 1274 if (sc == NULL) 1275 panic("bge_jfree: can't find softc pointer!"); 1276 1277 /* calculate the slot this buffer belongs to */ 1278 1279 i = ((char *)buf 1280 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1281 1282 if ((i < 0) || (i >= BGE_JSLOTS)) 1283 panic("bge_jfree: asked to free buffer that we don't manage!"); 1284 1285 s = splvm(); 1286 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1287 if (entry == NULL) 1288 panic("bge_jfree: buffer not in use!"); 1289 entry->slot = i; 1290 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1291 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1292 1293 if (__predict_true(m != NULL)) 1294 pool_cache_put(mb_cache, m); 1295 splx(s); 1296 } 1297 1298 1299 /* 1300 * Initialize a standard receive ring descriptor. 1301 */ 1302 static int 1303 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, 1304 bus_dmamap_t dmamap) 1305 { 1306 struct mbuf *m_new = NULL; 1307 struct bge_rx_bd *r; 1308 int error; 1309 1310 if (dmamap == NULL) { 1311 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1312 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1313 if (error != 0) 1314 return error; 1315 } 1316 1317 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1318 1319 if (m == NULL) { 1320 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1321 if (m_new == NULL) 1322 return ENOBUFS; 1323 1324 MCLGET(m_new, M_DONTWAIT); 1325 if (!(m_new->m_flags & M_EXT)) { 1326 m_freem(m_new); 1327 return ENOBUFS; 1328 } 1329 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1330 1331 } else { 1332 m_new = m; 1333 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1334 m_new->m_data = m_new->m_ext.ext_buf; 1335 } 1336 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1337 m_adj(m_new, ETHER_ALIGN); 1338 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1339 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1340 return ENOBUFS; 1341 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1342 BUS_DMASYNC_PREREAD); 1343 1344 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1345 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1346 BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr); 1347 r->bge_flags = BGE_RXBDFLAG_END; 1348 r->bge_len = m_new->m_len; 1349 r->bge_idx = i; 1350 1351 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1352 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1353 i * sizeof (struct bge_rx_bd), 1354 sizeof (struct bge_rx_bd), 1355 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1356 1357 return 0; 1358 } 1359 1360 /* 1361 * Initialize a jumbo receive ring descriptor. This allocates 1362 * a jumbo buffer from the pool managed internally by the driver. 1363 */ 1364 static int 1365 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1366 { 1367 struct mbuf *m_new = NULL; 1368 struct bge_rx_bd *r; 1369 void *buf = NULL; 1370 1371 if (m == NULL) { 1372 1373 /* Allocate the mbuf. */ 1374 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1375 if (m_new == NULL) 1376 return ENOBUFS; 1377 1378 /* Allocate the jumbo buffer */ 1379 buf = bge_jalloc(sc); 1380 if (buf == NULL) { 1381 m_freem(m_new); 1382 aprint_error_dev(sc->bge_dev, 1383 "jumbo allocation failed -- packet dropped!\n"); 1384 return ENOBUFS; 1385 } 1386 1387 /* Attach the buffer to the mbuf. */ 1388 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1389 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1390 bge_jfree, sc); 1391 m_new->m_flags |= M_EXT_RW; 1392 } else { 1393 m_new = m; 1394 buf = m_new->m_data = m_new->m_ext.ext_buf; 1395 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1396 } 1397 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1398 m_adj(m_new, ETHER_ALIGN); 1399 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1400 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1401 BUS_DMASYNC_PREREAD); 1402 /* Set up the descriptor. */ 1403 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1404 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1405 BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1406 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1407 r->bge_len = m_new->m_len; 1408 r->bge_idx = i; 1409 1410 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1411 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1412 i * sizeof (struct bge_rx_bd), 1413 sizeof (struct bge_rx_bd), 1414 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1415 1416 return 0; 1417 } 1418 1419 /* 1420 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1421 * that's 1MB or memory, which is a lot. For now, we fill only the first 1422 * 256 ring entries and hope that our CPU is fast enough to keep up with 1423 * the NIC. 1424 */ 1425 static int 1426 bge_init_rx_ring_std(struct bge_softc *sc) 1427 { 1428 int i; 1429 1430 if (sc->bge_flags & BGE_RXRING_VALID) 1431 return 0; 1432 1433 for (i = 0; i < BGE_SSLOTS; i++) { 1434 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1435 return ENOBUFS; 1436 } 1437 1438 sc->bge_std = i - 1; 1439 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1440 1441 sc->bge_flags |= BGE_RXRING_VALID; 1442 1443 return 0; 1444 } 1445 1446 static void 1447 bge_free_rx_ring_std(struct bge_softc *sc) 1448 { 1449 int i; 1450 1451 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1452 return; 1453 1454 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1455 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1456 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1457 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1458 bus_dmamap_destroy(sc->bge_dmatag, 1459 sc->bge_cdata.bge_rx_std_map[i]); 1460 } 1461 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1462 sizeof(struct bge_rx_bd)); 1463 } 1464 1465 sc->bge_flags &= ~BGE_RXRING_VALID; 1466 } 1467 1468 static int 1469 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1470 { 1471 int i; 1472 volatile struct bge_rcb *rcb; 1473 1474 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1475 return 0; 1476 1477 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1478 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1479 return ENOBUFS; 1480 }; 1481 1482 sc->bge_jumbo = i - 1; 1483 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1484 1485 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1486 rcb->bge_maxlen_flags = 0; 1487 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1488 1489 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1490 1491 return 0; 1492 } 1493 1494 static void 1495 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1496 { 1497 int i; 1498 1499 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1500 return; 1501 1502 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1503 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1504 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1505 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1506 } 1507 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1508 sizeof(struct bge_rx_bd)); 1509 } 1510 1511 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1512 } 1513 1514 static void 1515 bge_free_tx_ring(struct bge_softc *sc) 1516 { 1517 int i, freed; 1518 struct txdmamap_pool_entry *dma; 1519 1520 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1521 return; 1522 1523 freed = 0; 1524 1525 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1526 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1527 freed++; 1528 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1529 sc->bge_cdata.bge_tx_chain[i] = NULL; 1530 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1531 link); 1532 sc->txdma[i] = 0; 1533 } 1534 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1535 sizeof(struct bge_tx_bd)); 1536 } 1537 1538 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1539 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1540 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1541 free(dma, M_DEVBUF); 1542 } 1543 1544 sc->bge_flags &= ~BGE_TXRING_VALID; 1545 } 1546 1547 static int 1548 bge_init_tx_ring(struct bge_softc *sc) 1549 { 1550 int i; 1551 bus_dmamap_t dmamap; 1552 struct txdmamap_pool_entry *dma; 1553 1554 if (sc->bge_flags & BGE_TXRING_VALID) 1555 return 0; 1556 1557 sc->bge_txcnt = 0; 1558 sc->bge_tx_saved_considx = 0; 1559 1560 /* Initialize transmit producer index for host-memory send ring. */ 1561 sc->bge_tx_prodidx = 0; 1562 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1563 /* 5700 b2 errata */ 1564 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1565 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1566 1567 /* NIC-memory send ring not used; initialize to zero. */ 1568 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1569 /* 5700 b2 errata */ 1570 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1571 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1572 1573 SLIST_INIT(&sc->txdma_list); 1574 for (i = 0; i < BGE_RSLOTS; i++) { 1575 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1576 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1577 &dmamap)) 1578 return ENOBUFS; 1579 if (dmamap == NULL) 1580 panic("dmamap NULL in bge_init_tx_ring"); 1581 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1582 if (dma == NULL) { 1583 aprint_error_dev(sc->bge_dev, 1584 "can't alloc txdmamap_pool_entry\n"); 1585 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1586 return ENOMEM; 1587 } 1588 dma->dmamap = dmamap; 1589 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1590 } 1591 1592 sc->bge_flags |= BGE_TXRING_VALID; 1593 1594 return 0; 1595 } 1596 1597 static void 1598 bge_setmulti(struct bge_softc *sc) 1599 { 1600 struct ethercom *ac = &sc->ethercom; 1601 struct ifnet *ifp = &ac->ec_if; 1602 struct ether_multi *enm; 1603 struct ether_multistep step; 1604 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1605 uint32_t h; 1606 int i; 1607 1608 if (ifp->if_flags & IFF_PROMISC) 1609 goto allmulti; 1610 1611 /* Now program new ones. */ 1612 ETHER_FIRST_MULTI(step, ac, enm); 1613 while (enm != NULL) { 1614 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1615 /* 1616 * We must listen to a range of multicast addresses. 1617 * For now, just accept all multicasts, rather than 1618 * trying to set only those filter bits needed to match 1619 * the range. (At this time, the only use of address 1620 * ranges is for IP multicast routing, for which the 1621 * range is big enough to require all bits set.) 1622 */ 1623 goto allmulti; 1624 } 1625 1626 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1627 1628 /* Just want the 7 least-significant bits. */ 1629 h &= 0x7f; 1630 1631 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1632 ETHER_NEXT_MULTI(step, enm); 1633 } 1634 1635 ifp->if_flags &= ~IFF_ALLMULTI; 1636 goto setit; 1637 1638 allmulti: 1639 ifp->if_flags |= IFF_ALLMULTI; 1640 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1641 1642 setit: 1643 for (i = 0; i < 4; i++) 1644 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1645 } 1646 1647 static void 1648 bge_sig_pre_reset(struct bge_softc *sc, int type) 1649 { 1650 /* 1651 * Some chips don't like this so only do this if ASF is enabled 1652 */ 1653 if (sc->bge_asf_mode) 1654 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1655 1656 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1657 switch (type) { 1658 case BGE_RESET_START: 1659 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1660 break; 1661 case BGE_RESET_STOP: 1662 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1663 break; 1664 } 1665 } 1666 } 1667 1668 static void 1669 bge_sig_post_reset(struct bge_softc *sc, int type) 1670 { 1671 1672 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1673 switch (type) { 1674 case BGE_RESET_START: 1675 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1676 /* START DONE */ 1677 break; 1678 case BGE_RESET_STOP: 1679 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1680 break; 1681 } 1682 } 1683 } 1684 1685 static void 1686 bge_sig_legacy(struct bge_softc *sc, int type) 1687 { 1688 1689 if (sc->bge_asf_mode) { 1690 switch (type) { 1691 case BGE_RESET_START: 1692 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1693 break; 1694 case BGE_RESET_STOP: 1695 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1696 break; 1697 } 1698 } 1699 } 1700 1701 static void 1702 bge_stop_fw(struct bge_softc *sc) 1703 { 1704 int i; 1705 1706 if (sc->bge_asf_mode) { 1707 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1708 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1709 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1710 1711 for (i = 0; i < 100; i++) { 1712 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1713 break; 1714 DELAY(10); 1715 } 1716 } 1717 } 1718 1719 static int 1720 bge_poll_fw(struct bge_softc *sc) 1721 { 1722 uint32_t val; 1723 int i; 1724 1725 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1726 for (i = 0; i < BGE_TIMEOUT; i++) { 1727 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 1728 if (val & BGE_VCPU_STATUS_INIT_DONE) 1729 break; 1730 DELAY(100); 1731 } 1732 if (i >= BGE_TIMEOUT) { 1733 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 1734 return -1; 1735 } 1736 } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) { 1737 /* 1738 * Poll the value location we just wrote until 1739 * we see the 1's complement of the magic number. 1740 * This indicates that the firmware initialization 1741 * is complete. 1742 * XXX 1000ms for Flash and 10000ms for SEEPROM. 1743 */ 1744 for (i = 0; i < BGE_TIMEOUT; i++) { 1745 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1746 if (val == ~BGE_MAGIC_NUMBER) 1747 break; 1748 DELAY(10); 1749 } 1750 1751 if (i >= BGE_TIMEOUT) { 1752 aprint_error_dev(sc->bge_dev, 1753 "firmware handshake timed out, val = %x\n", val); 1754 return -1; 1755 } 1756 } 1757 1758 return 0; 1759 } 1760 1761 /* 1762 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1763 * self-test results. 1764 */ 1765 static int 1766 bge_chipinit(struct bge_softc *sc) 1767 { 1768 int i; 1769 uint32_t dma_rw_ctl; 1770 1771 /* Set endianness before we access any non-PCI registers. */ 1772 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1773 BGE_INIT); 1774 1775 /* Set power state to D0. */ 1776 bge_setpowerstate(sc, 0); 1777 1778 /* Clear the MAC control register */ 1779 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1780 1781 /* 1782 * Clear the MAC statistics block in the NIC's 1783 * internal memory. 1784 */ 1785 for (i = BGE_STATS_BLOCK; 1786 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1787 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1788 1789 for (i = BGE_STATUS_BLOCK; 1790 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1791 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1792 1793 /* Set up the PCI DMA control register. */ 1794 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1795 if (sc->bge_flags & BGE_PCIE) { 1796 /* Read watermark not used, 128 bytes for write. */ 1797 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1798 device_xname(sc->bge_dev))); 1799 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1800 } else if (sc->bge_flags & BGE_PCIX) { 1801 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1802 device_xname(sc->bge_dev))); 1803 /* PCI-X bus */ 1804 if (BGE_IS_5714_FAMILY(sc)) { 1805 /* 256 bytes for read and write. */ 1806 dma_rw_ctl |= (0x02 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1807 (0x02 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1808 1809 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1810 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1811 else 1812 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1813 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1814 /* 1536 bytes for read, 384 bytes for write. */ 1815 dma_rw_ctl |= 1816 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1817 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1818 } else { 1819 /* 384 bytes for read and write. */ 1820 dma_rw_ctl |= (0x03 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1821 (0x03 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1822 (0x0F); 1823 } 1824 1825 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1826 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1827 uint32_t tmp; 1828 1829 /* Set ONEDMA_ATONCE for hardware workaround. */ 1830 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1831 if (tmp == 6 || tmp == 7) 1832 dma_rw_ctl |= 1833 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1834 1835 /* Set PCI-X DMA write workaround. */ 1836 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1837 } 1838 } else { 1839 /* Conventional PCI bus: 256 bytes for read and write. */ 1840 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1841 device_xname(sc->bge_dev))); 1842 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1843 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1844 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1845 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1846 dma_rw_ctl |= 0x0F; 1847 } 1848 1849 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1850 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1851 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1852 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1853 1854 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1855 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1856 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1857 1858 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, 1859 dma_rw_ctl); 1860 1861 /* 1862 * Set up general mode register. 1863 */ 1864 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1865 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1866 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1867 1868 /* 1869 * BCM5701 B5 have a bug causing data corruption when using 1870 * 64-bit DMA reads, which can be terminated early and then 1871 * completed later as 32-bit accesses, in combination with 1872 * certain bridges. 1873 */ 1874 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1875 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1876 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1877 1878 /* 1879 * Tell the firmware the driver is running 1880 */ 1881 if (sc->bge_asf_mode & ASF_STACKUP) 1882 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1883 1884 /* 1885 * Disable memory write invalidate. Apparently it is not supported 1886 * properly by these devices. 1887 */ 1888 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 1889 PCI_COMMAND_INVALIDATE_ENABLE); 1890 1891 #ifdef __brokenalpha__ 1892 /* 1893 * Must insure that we do not cross an 8K (bytes) boundary 1894 * for DMA reads. Our highest limit is 1K bytes. This is a 1895 * restriction on some ALPHA platforms with early revision 1896 * 21174 PCI chipsets, such as the AlphaPC 164lx 1897 */ 1898 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1899 #endif 1900 1901 /* Set the timer prescaler (always 66MHz) */ 1902 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1903 1904 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1905 DELAY(40); /* XXX */ 1906 1907 /* Put PHY into ready state */ 1908 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1909 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1910 DELAY(40); 1911 } 1912 1913 return 0; 1914 } 1915 1916 static int 1917 bge_blockinit(struct bge_softc *sc) 1918 { 1919 volatile struct bge_rcb *rcb; 1920 bus_size_t rcb_addr; 1921 int i; 1922 struct ifnet *ifp = &sc->ethercom.ec_if; 1923 bge_hostaddr taddr; 1924 uint32_t val; 1925 1926 /* 1927 * Initialize the memory window pointer register so that 1928 * we can access the first 32K of internal NIC RAM. This will 1929 * allow us to set up the TX send ring RCBs and the RX return 1930 * ring RCBs, plus other things which live in NIC memory. 1931 */ 1932 1933 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1934 1935 /* Step 33: Configure mbuf memory pool */ 1936 if (BGE_IS_5700_FAMILY(sc)) { 1937 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1938 BGE_BUFFPOOL_1); 1939 1940 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1941 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1942 else 1943 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1944 1945 /* Configure DMA resource pool */ 1946 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1947 BGE_DMA_DESCRIPTORS); 1948 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1949 } 1950 1951 /* Step 35: Configure mbuf pool watermarks */ 1952 #ifdef ORIG_WPAUL_VALUES 1953 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1954 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1955 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1956 #else 1957 1958 /* new broadcom docs strongly recommend these: */ 1959 if (!BGE_IS_5705_PLUS(sc)) { 1960 if (ifp->if_mtu > ETHER_MAX_LEN) { 1961 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1962 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1963 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1964 } else { 1965 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1966 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1967 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1968 } 1969 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1970 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1973 } else { 1974 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1975 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1976 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1977 } 1978 #endif 1979 1980 /* Step 36: Configure DMA resource watermarks */ 1981 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1982 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1983 1984 /* Step 38: Enable buffer manager */ 1985 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1986 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1987 1988 /* Step 39: Poll for buffer manager start indication */ 1989 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 1990 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1991 break; 1992 DELAY(10); 1993 } 1994 1995 if (i == BGE_TIMEOUT * 2) { 1996 aprint_error_dev(sc->bge_dev, 1997 "buffer manager failed to start\n"); 1998 return ENXIO; 1999 } 2000 2001 /* Step 40: Enable flow-through queues */ 2002 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2003 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2004 2005 /* Wait until queue initialization is complete */ 2006 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2007 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2008 break; 2009 DELAY(10); 2010 } 2011 2012 if (i == BGE_TIMEOUT * 2) { 2013 aprint_error_dev(sc->bge_dev, 2014 "flow-through queue init failed\n"); 2015 return ENXIO; 2016 } 2017 2018 /* Step 41: Initialize the standard RX ring control block */ 2019 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 2020 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 2021 if (BGE_IS_5705_PLUS(sc)) 2022 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2023 else 2024 rcb->bge_maxlen_flags = 2025 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2026 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2027 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2028 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2029 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2030 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2031 2032 /* 2033 * Step 42: Initialize the jumbo RX ring control block 2034 * We set the 'ring disabled' bit in the flags 2035 * field until we're actually ready to start 2036 * using this ring (i.e. once we set the MTU 2037 * high enough to require it). 2038 */ 2039 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2040 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 2041 BGE_HOSTADDR(rcb->bge_hostaddr, 2042 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 2043 rcb->bge_maxlen_flags = 2044 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 2045 BGE_RCB_FLAG_RING_DISABLED); 2046 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2047 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2048 rcb->bge_hostaddr.bge_addr_hi); 2049 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2050 rcb->bge_hostaddr.bge_addr_lo); 2051 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2052 rcb->bge_maxlen_flags); 2053 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2054 2055 /* Set up dummy disabled mini ring RCB */ 2056 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2057 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2058 BGE_RCB_FLAG_RING_DISABLED); 2059 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2060 rcb->bge_maxlen_flags); 2061 2062 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2063 offsetof(struct bge_ring_data, bge_info), 2064 sizeof (struct bge_gib), 2065 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2066 } 2067 2068 /* 2069 * Set the BD ring replenish thresholds. The recommended 2070 * values are 1/8th the number of descriptors allocated to 2071 * each ring. 2072 */ 2073 i = BGE_STD_RX_RING_CNT / 8; 2074 2075 /* 2076 * Use a value of 8 for the following chips to workaround HW errata. 2077 * Some of these chips have been added based on empirical 2078 * evidence (they don't work unless this is done). 2079 */ 2080 if (BGE_IS_5705_PLUS(sc)) 2081 i = 8; 2082 2083 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 2084 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 2085 2086 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2087 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 2088 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2089 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2090 } 2091 2092 /* 2093 * Disable all unused send rings by setting the 'ring disabled' 2094 * bit in the flags field of all the TX send ring control blocks. 2095 * These are located in NIC memory. 2096 */ 2097 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2098 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 2099 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2100 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2101 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2102 rcb_addr += sizeof(struct bge_rcb); 2103 } 2104 2105 /* Configure TX RCB 0 (we use only the first ring) */ 2106 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2107 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2108 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2109 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2110 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2111 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2112 if (BGE_IS_5700_FAMILY(sc)) 2113 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2114 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2115 2116 /* Disable all unused RX return rings */ 2117 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2118 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 2119 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2120 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2121 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2122 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2123 BGE_RCB_FLAG_RING_DISABLED)); 2124 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2125 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2126 (i * (sizeof(uint64_t))), 0); 2127 rcb_addr += sizeof(struct bge_rcb); 2128 } 2129 2130 /* Initialize RX ring indexes */ 2131 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2132 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2133 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2134 2135 /* 2136 * Set up RX return ring 0 2137 * Note that the NIC address for RX return rings is 0x00000000. 2138 * The return rings live entirely within the host, so the 2139 * nicaddr field in the RCB isn't used. 2140 */ 2141 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2142 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2143 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2144 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2145 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2146 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2147 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2148 2149 /* Set random backoff seed for TX */ 2150 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2151 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 2152 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 2153 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 2154 BGE_TX_BACKOFF_SEED_MASK); 2155 2156 /* Set inter-packet gap */ 2157 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 2158 2159 /* 2160 * Specify which ring to use for packets that don't match 2161 * any RX rules. 2162 */ 2163 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2164 2165 /* 2166 * Configure number of RX lists. One interrupt distribution 2167 * list, sixteen active lists, one bad frames class. 2168 */ 2169 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2170 2171 /* Inialize RX list placement stats mask. */ 2172 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2173 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2174 2175 /* Disable host coalescing until we get it set up */ 2176 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2177 2178 /* Poll to make sure it's shut down. */ 2179 for (i = 0; i < BGE_TIMEOUT * 2; i++) { 2180 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2181 break; 2182 DELAY(10); 2183 } 2184 2185 if (i == BGE_TIMEOUT * 2) { 2186 aprint_error_dev(sc->bge_dev, 2187 "host coalescing engine failed to idle\n"); 2188 return ENXIO; 2189 } 2190 2191 /* Set up host coalescing defaults */ 2192 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2193 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2194 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2195 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2196 if (BGE_IS_5700_FAMILY(sc)) { 2197 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2198 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2199 } 2200 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2201 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2202 2203 /* Set up address of statistics block */ 2204 if (BGE_IS_5700_FAMILY(sc)) { 2205 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2206 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2207 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2208 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2209 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2210 } 2211 2212 /* Set up address of status block */ 2213 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2214 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2215 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2216 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2217 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2218 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2219 2220 /* Turn on host coalescing state machine */ 2221 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2222 2223 /* Turn on RX BD completion state machine and enable attentions */ 2224 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2225 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2226 2227 /* Turn on RX list placement state machine */ 2228 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2229 2230 /* Turn on RX list selector state machine. */ 2231 if (BGE_IS_5700_FAMILY(sc)) 2232 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2233 2234 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2235 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2236 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2237 BGE_MACMODE_FRMHDR_DMA_ENB; 2238 2239 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2240 val |= BGE_PORTMODE_TBI; 2241 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2242 val |= BGE_PORTMODE_GMII; 2243 else 2244 val |= BGE_PORTMODE_MII; 2245 2246 /* Turn on DMA, clear stats */ 2247 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2248 2249 /* Set misc. local control, enable interrupts on attentions */ 2250 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2251 2252 #ifdef notdef 2253 /* Assert GPIO pins for PHY reset */ 2254 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2255 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2256 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2257 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2258 #endif 2259 2260 #if defined(not_quite_yet) 2261 /* Linux driver enables enable gpio pin #1 on 5700s */ 2262 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2263 sc->bge_local_ctrl_reg |= 2264 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2265 } 2266 #endif 2267 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2268 2269 /* Turn on DMA completion state machine */ 2270 if (BGE_IS_5700_FAMILY(sc)) 2271 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2272 2273 /* Turn on write DMA state machine */ 2274 { 2275 uint32_t bge_wdma_mode = 2276 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2277 2278 /* Enable host coalescing bug fix; see Linux tg3.c */ 2279 if (BGE_IS_5755_PLUS(sc)) 2280 bge_wdma_mode |= BGE_WDMAMODE_STATUS_TAG_FIX; 2281 2282 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2283 } 2284 2285 /* Turn on read DMA state machine */ 2286 { 2287 uint32_t dma_read_modebits; 2288 2289 dma_read_modebits = 2290 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2291 2292 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2293 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2294 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2295 dma_read_modebits |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2296 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2297 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2298 2299 if (sc->bge_flags & BGE_PCIE) 2300 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2301 if (sc->bge_flags & BGE_TSO) 2302 dma_read_modebits |= BGE_RDMAMODE_TSO4_ENABLE; 2303 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2304 delay(40); 2305 } 2306 2307 /* Turn on RX data completion state machine */ 2308 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2309 2310 /* Turn on RX BD initiator state machine */ 2311 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2312 2313 /* Turn on RX data and RX BD initiator state machine */ 2314 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2315 2316 /* Turn on Mbuf cluster free state machine */ 2317 if (BGE_IS_5700_FAMILY(sc)) 2318 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2319 2320 /* Turn on send BD completion state machine */ 2321 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2322 2323 /* Turn on send data completion state machine */ 2324 val = BGE_SDCMODE_ENABLE; 2325 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2326 val |= BGE_SDCMODE_CDELAY; 2327 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2328 2329 /* Turn on send data initiator state machine */ 2330 if (sc->bge_flags & BGE_TSO) { 2331 /* XXX: magic value from Linux driver */ 2332 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2333 } else 2334 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2335 2336 /* Turn on send BD initiator state machine */ 2337 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2338 2339 /* Turn on send BD selector state machine */ 2340 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2341 2342 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2343 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2344 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2345 2346 /* ack/clear link change events */ 2347 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2348 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2349 BGE_MACSTAT_LINK_CHANGED); 2350 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2351 2352 /* Enable PHY auto polling (for MII/GMII only) */ 2353 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2354 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2355 } else { 2356 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2357 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2358 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2359 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2360 BGE_EVTENB_MI_INTERRUPT); 2361 } 2362 2363 /* 2364 * Clear any pending link state attention. 2365 * Otherwise some link state change events may be lost until attention 2366 * is cleared by bge_intr() -> bge_link_upd() sequence. 2367 * It's not necessary on newer BCM chips - perhaps enabling link 2368 * state change attentions implies clearing pending attention. 2369 */ 2370 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2371 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2372 BGE_MACSTAT_LINK_CHANGED); 2373 2374 /* Enable link state change attentions. */ 2375 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2376 2377 return 0; 2378 } 2379 2380 static const struct bge_revision * 2381 bge_lookup_rev(uint32_t chipid) 2382 { 2383 const struct bge_revision *br; 2384 2385 for (br = bge_revisions; br->br_name != NULL; br++) { 2386 if (br->br_chipid == chipid) 2387 return br; 2388 } 2389 2390 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2391 if (br->br_chipid == BGE_ASICREV(chipid)) 2392 return br; 2393 } 2394 2395 return NULL; 2396 } 2397 2398 static const struct bge_product * 2399 bge_lookup(const struct pci_attach_args *pa) 2400 { 2401 const struct bge_product *bp; 2402 2403 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2404 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2405 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2406 return bp; 2407 } 2408 2409 return NULL; 2410 } 2411 2412 static int 2413 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2414 { 2415 #ifdef NOTYET 2416 uint32_t pm_ctl = 0; 2417 2418 /* XXX FIXME: make sure indirect accesses enabled? */ 2419 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2420 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2421 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2422 2423 /* clear the PME_assert bit and power state bits, enable PME */ 2424 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2425 pm_ctl &= ~PCIM_PSTAT_DMASK; 2426 pm_ctl |= (1 << 8); 2427 2428 if (powerlevel == 0) { 2429 pm_ctl |= PCIM_PSTAT_D0; 2430 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2431 pm_ctl, 2); 2432 DELAY(10000); 2433 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2434 DELAY(10000); 2435 2436 #ifdef NOTYET 2437 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2438 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2439 #endif 2440 DELAY(40); DELAY(40); DELAY(40); 2441 DELAY(10000); /* above not quite adequate on 5700 */ 2442 return 0; 2443 } 2444 2445 2446 /* 2447 * Entering ACPI power states D1-D3 is achieved by wiggling 2448 * GMII gpio pins. Example code assumes all hardware vendors 2449 * followed Broadcom's sample pcb layout. Until we verify that 2450 * for all supported OEM cards, states D1-D3 are unsupported. 2451 */ 2452 aprint_error_dev(sc->bge_dev, 2453 "power state %d unimplemented; check GPIO pins\n", 2454 powerlevel); 2455 #endif 2456 return EOPNOTSUPP; 2457 } 2458 2459 2460 /* 2461 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2462 * against our list and return its name if we find a match. Note 2463 * that since the Broadcom controller contains VPD support, we 2464 * can get the device name string from the controller itself instead 2465 * of the compiled-in string. This is a little slow, but it guarantees 2466 * we'll always announce the right product name. 2467 */ 2468 static int 2469 bge_probe(device_t parent, cfdata_t match, void *aux) 2470 { 2471 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2472 2473 if (bge_lookup(pa) != NULL) 2474 return 1; 2475 2476 return 0; 2477 } 2478 2479 static void 2480 bge_attach(device_t parent, device_t self, void *aux) 2481 { 2482 struct bge_softc *sc = device_private(self); 2483 struct pci_attach_args *pa = aux; 2484 prop_dictionary_t dict; 2485 const struct bge_product *bp; 2486 const struct bge_revision *br; 2487 pci_chipset_tag_t pc; 2488 pci_intr_handle_t ih; 2489 const char *intrstr = NULL; 2490 bus_dma_segment_t seg; 2491 int rseg; 2492 uint32_t hwcfg = 0; 2493 uint32_t command; 2494 struct ifnet *ifp; 2495 uint32_t misccfg; 2496 void * kva; 2497 u_char eaddr[ETHER_ADDR_LEN]; 2498 pcireg_t memtype, subid; 2499 bus_addr_t memaddr; 2500 bus_size_t memsize; 2501 uint32_t pm_ctl; 2502 bool no_seeprom; 2503 2504 bp = bge_lookup(pa); 2505 KASSERT(bp != NULL); 2506 2507 sc->sc_pc = pa->pa_pc; 2508 sc->sc_pcitag = pa->pa_tag; 2509 sc->bge_dev = self; 2510 2511 pc = sc->sc_pc; 2512 subid = pci_conf_read(pc, sc->sc_pcitag, PCI_SUBSYS_ID_REG); 2513 2514 aprint_naive(": Ethernet controller\n"); 2515 aprint_normal(": %s\n", bp->bp_name); 2516 2517 /* 2518 * Map control/status registers. 2519 */ 2520 DPRINTFN(5, ("Map control/status regs\n")); 2521 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2522 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2523 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2524 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2525 2526 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2527 aprint_error_dev(sc->bge_dev, 2528 "failed to enable memory mapping!\n"); 2529 return; 2530 } 2531 2532 DPRINTFN(5, ("pci_mem_find\n")); 2533 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2534 switch (memtype) { 2535 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2536 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2537 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2538 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2539 &memaddr, &memsize) == 0) 2540 break; 2541 default: 2542 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2543 return; 2544 } 2545 2546 DPRINTFN(5, ("pci_intr_map\n")); 2547 if (pci_intr_map(pa, &ih)) { 2548 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2549 return; 2550 } 2551 2552 DPRINTFN(5, ("pci_intr_string\n")); 2553 intrstr = pci_intr_string(pc, ih); 2554 2555 DPRINTFN(5, ("pci_intr_establish\n")); 2556 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2557 2558 if (sc->bge_intrhand == NULL) { 2559 aprint_error_dev(sc->bge_dev, 2560 "couldn't establish interrupt%s%s\n", 2561 intrstr ? " at " : "", intrstr ? intrstr : ""); 2562 return; 2563 } 2564 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2565 2566 /* 2567 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2568 * can clobber the chip's PCI config-space power control registers, 2569 * leaving the card in D3 powersave state. 2570 * We do not have memory-mapped registers in this state, 2571 * so force device into D0 state before starting initialization. 2572 */ 2573 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2574 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2575 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2576 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2577 DELAY(1000); /* 27 usec is allegedly sufficent */ 2578 2579 /* 2580 * Save ASIC rev. 2581 */ 2582 sc->bge_chipid = 2583 pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2584 >> BGE_PCIMISCCTL_ASICREV_SHIFT; 2585 2586 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2587 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5717 || 2588 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 || 2589 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5724) 2590 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2591 BGE_PCI_GEN2_PRODID_ASICREV); 2592 else if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57761 || 2593 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57765 || 2594 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57781 || 2595 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57785 || 2596 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 2597 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795) 2598 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2599 BGE_PCI_GEN15_PRODID_ASICREV); 2600 else 2601 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2602 BGE_PCI_PRODID_ASICREV); 2603 } 2604 2605 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2606 &sc->bge_pciecap, NULL) != 0) { 2607 /* PCIe */ 2608 sc->bge_flags |= BGE_PCIE; 2609 bge_set_max_readrq(sc); 2610 } else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2611 BGE_PCISTATE_PCI_BUSMODE) == 0) { 2612 /* PCI-X */ 2613 sc->bge_flags |= BGE_PCIX; 2614 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 2615 &sc->bge_pcixcap, NULL) == 0) 2616 aprint_error_dev(sc->bge_dev, 2617 "unable to find PCIX capability\n"); 2618 } 2619 2620 /* chipid */ 2621 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2622 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 2623 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 2624 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 2625 sc->bge_flags |= BGE_5700_FAMILY; 2626 2627 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 2628 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 2629 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 2630 sc->bge_flags |= BGE_5714_FAMILY; 2631 2632 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 2633 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2634 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2635 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2636 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2637 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2638 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 2639 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 2640 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2641 sc->bge_flags |= BGE_5755_PLUS; 2642 2643 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 2644 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2645 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 2646 BGE_IS_5755_PLUS(sc) || 2647 BGE_IS_5714_FAMILY(sc)) 2648 sc->bge_flags |= BGE_5750_PLUS; 2649 2650 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 2651 BGE_IS_5750_OR_BEYOND(sc)) 2652 sc->bge_flags |= BGE_5705_PLUS; 2653 2654 /* 2655 * When using the BCM5701 in PCI-X mode, data corruption has 2656 * been observed in the first few bytes of some received packets. 2657 * Aligning the packet buffer in memory eliminates the corruption. 2658 * Unfortunately, this misaligns the packet payloads. On platforms 2659 * which do not support unaligned accesses, we will realign the 2660 * payloads by copying the received packets. 2661 */ 2662 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2663 sc->bge_flags & BGE_PCIX) 2664 sc->bge_flags |= BGE_RX_ALIGNBUG; 2665 2666 if (BGE_IS_5700_FAMILY(sc)) 2667 sc->bge_flags |= BGE_JUMBO_CAPABLE; 2668 2669 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2670 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2671 PCI_VENDOR(subid) == PCI_VENDOR_DELL) 2672 sc->bge_flags |= BGE_NO_3LED; 2673 2674 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2675 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2676 2677 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2678 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2679 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2680 sc->bge_flags |= BGE_IS_5788; 2681 2682 /* 2683 * Some controllers seem to require a special firmware to use 2684 * TSO. But the firmware is not available to FreeBSD and Linux 2685 * claims that the TSO performed by the firmware is slower than 2686 * hardware based TSO. Moreover the firmware based TSO has one 2687 * known bug which can't handle TSO if ethernet header + IP/TCP 2688 * header is greater than 80 bytes. The workaround for the TSO 2689 * bug exist but it seems it's too expensive than not using 2690 * TSO at all. Some hardwares also have the TSO bug so limit 2691 * the TSO to the controllers that are not affected TSO issues 2692 * (e.g. 5755 or higher). 2693 */ 2694 if (BGE_IS_5755_PLUS(sc)) { 2695 /* 2696 * BCM5754 and BCM5787 shares the same ASIC id so 2697 * explicit device id check is required. 2698 */ 2699 if ((PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754) && 2700 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5754M)) 2701 sc->bge_flags |= BGE_TSO; 2702 } 2703 2704 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2705 (misccfg == 0x4000 || misccfg == 0x8000)) || 2706 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2707 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2708 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2709 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2710 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2711 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2712 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2713 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2714 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2715 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2716 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2717 sc->bge_flags |= BGE_10_100_ONLY; 2718 2719 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2720 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2721 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2722 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2723 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2724 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2725 2726 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2727 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2728 sc->bge_flags |= BGE_PHY_CRC_BUG; 2729 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2730 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2731 sc->bge_flags |= BGE_PHY_ADC_BUG; 2732 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2733 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2734 2735 if (BGE_IS_5705_PLUS(sc) && 2736 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2737 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2738 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2739 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2740 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2741 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2742 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2743 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2744 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2745 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2746 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2747 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2748 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2749 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2750 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2751 sc->bge_flags |= BGE_PHY_BER_BUG; 2752 } 2753 2754 /* 2755 * SEEPROM check. 2756 * First check if firmware knows we do not have SEEPROM. 2757 */ 2758 if (prop_dictionary_get_bool(device_properties(self), 2759 "without-seeprom", &no_seeprom) && no_seeprom) 2760 sc->bge_flags |= BGE_NO_EEPROM; 2761 2762 /* Now check the 'ROM failed' bit on the RX CPU */ 2763 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) 2764 sc->bge_flags |= BGE_NO_EEPROM; 2765 2766 /* Try to reset the chip. */ 2767 DPRINTFN(5, ("bge_reset\n")); 2768 bge_reset(sc); 2769 2770 sc->bge_asf_mode = 0; 2771 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2772 == BGE_MAGIC_NUMBER)) { 2773 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2774 & BGE_HWCFG_ASF) { 2775 sc->bge_asf_mode |= ASF_ENABLE; 2776 sc->bge_asf_mode |= ASF_STACKUP; 2777 if (BGE_IS_5750_OR_BEYOND(sc)) { 2778 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2779 } 2780 } 2781 } 2782 2783 /* Try to reset the chip again the nice way. */ 2784 bge_stop_fw(sc); 2785 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2786 if (bge_reset(sc)) 2787 aprint_error_dev(sc->bge_dev, "chip reset failed\n"); 2788 2789 bge_sig_legacy(sc, BGE_RESET_STOP); 2790 bge_sig_post_reset(sc, BGE_RESET_STOP); 2791 2792 if (bge_chipinit(sc)) { 2793 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2794 bge_release_resources(sc); 2795 return; 2796 } 2797 2798 /* 2799 * Get station address from the EEPROM 2800 */ 2801 if (bge_get_eaddr(sc, eaddr)) { 2802 aprint_error_dev(sc->bge_dev, 2803 "failed to read station address\n"); 2804 bge_release_resources(sc); 2805 return; 2806 } 2807 2808 br = bge_lookup_rev(sc->bge_chipid); 2809 2810 if (br == NULL) { 2811 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%x)", 2812 sc->bge_chipid); 2813 } else { 2814 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%x)", 2815 br->br_name, sc->bge_chipid); 2816 } 2817 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2818 2819 /* Allocate the general information block and ring buffers. */ 2820 if (pci_dma64_available(pa)) 2821 sc->bge_dmatag = pa->pa_dmat64; 2822 else 2823 sc->bge_dmatag = pa->pa_dmat; 2824 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2825 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2826 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2827 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2828 return; 2829 } 2830 DPRINTFN(5, ("bus_dmamem_map\n")); 2831 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2832 sizeof(struct bge_ring_data), &kva, 2833 BUS_DMA_NOWAIT)) { 2834 aprint_error_dev(sc->bge_dev, 2835 "can't map DMA buffers (%zu bytes)\n", 2836 sizeof(struct bge_ring_data)); 2837 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2838 return; 2839 } 2840 DPRINTFN(5, ("bus_dmamem_create\n")); 2841 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2842 sizeof(struct bge_ring_data), 0, 2843 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2844 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2845 bus_dmamem_unmap(sc->bge_dmatag, kva, 2846 sizeof(struct bge_ring_data)); 2847 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2848 return; 2849 } 2850 DPRINTFN(5, ("bus_dmamem_load\n")); 2851 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2852 sizeof(struct bge_ring_data), NULL, 2853 BUS_DMA_NOWAIT)) { 2854 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2855 bus_dmamem_unmap(sc->bge_dmatag, kva, 2856 sizeof(struct bge_ring_data)); 2857 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2858 return; 2859 } 2860 2861 DPRINTFN(5, ("bzero\n")); 2862 sc->bge_rdata = (struct bge_ring_data *)kva; 2863 2864 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2865 2866 /* Try to allocate memory for jumbo buffers. */ 2867 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2868 if (bge_alloc_jumbo_mem(sc)) { 2869 aprint_error_dev(sc->bge_dev, 2870 "jumbo buffer allocation failed\n"); 2871 } else 2872 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2873 } 2874 2875 /* Set default tuneable values. */ 2876 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2877 sc->bge_rx_coal_ticks = 150; 2878 sc->bge_rx_max_coal_bds = 64; 2879 #ifdef ORIG_WPAUL_VALUES 2880 sc->bge_tx_coal_ticks = 150; 2881 sc->bge_tx_max_coal_bds = 128; 2882 #else 2883 sc->bge_tx_coal_ticks = 300; 2884 sc->bge_tx_max_coal_bds = 400; 2885 #endif 2886 if (BGE_IS_5705_PLUS(sc)) { 2887 sc->bge_tx_coal_ticks = (12 * 5); 2888 sc->bge_tx_max_coal_bds = (12 * 5); 2889 aprint_verbose_dev(sc->bge_dev, 2890 "setting short Tx thresholds\n"); 2891 } 2892 2893 if (BGE_IS_5705_PLUS(sc)) 2894 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2895 else 2896 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2897 2898 /* Set up ifnet structure */ 2899 ifp = &sc->ethercom.ec_if; 2900 ifp->if_softc = sc; 2901 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2902 ifp->if_ioctl = bge_ioctl; 2903 ifp->if_stop = bge_stop; 2904 ifp->if_start = bge_start; 2905 ifp->if_init = bge_init; 2906 ifp->if_watchdog = bge_watchdog; 2907 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2908 IFQ_SET_READY(&ifp->if_snd); 2909 DPRINTFN(5, ("strcpy if_xname\n")); 2910 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2911 2912 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2913 sc->ethercom.ec_if.if_capabilities |= 2914 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2915 #if 1 /* XXX TCP/UDP checksum offload breaks with pf(4) */ 2916 sc->ethercom.ec_if.if_capabilities |= 2917 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2918 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2919 #endif 2920 sc->ethercom.ec_capabilities |= 2921 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2922 2923 if (sc->bge_flags & BGE_TSO) 2924 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2925 2926 /* 2927 * Do MII setup. 2928 */ 2929 DPRINTFN(5, ("mii setup\n")); 2930 sc->bge_mii.mii_ifp = ifp; 2931 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2932 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2933 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2934 2935 /* 2936 * Figure out what sort of media we have by checking the 2937 * hardware config word in the first 32k of NIC internal memory, 2938 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2939 * cards, this value appears to be unset. If that's the 2940 * case, we have to rely on identifying the NIC by its PCI 2941 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2942 */ 2943 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2944 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2945 } else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2946 bge_read_eeprom(sc, (void *)&hwcfg, 2947 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2948 hwcfg = be32toh(hwcfg); 2949 } 2950 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2951 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2952 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2953 if (BGE_IS_5714_FAMILY(sc)) 2954 sc->bge_flags |= BGE_PHY_FIBER_MII; 2955 else 2956 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2957 } 2958 2959 /* set phyflags before mii_attach() */ 2960 dict = device_properties(self); 2961 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2962 2963 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2964 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2965 bge_ifmedia_sts); 2966 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER |IFM_1000_SX, 0, NULL); 2967 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX|IFM_FDX, 2968 0, NULL); 2969 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2970 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2971 /* Pretend the user requested this setting */ 2972 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2973 } else { 2974 /* 2975 * Do transceiver setup and tell the firmware the 2976 * driver is down so we can try to get access the 2977 * probe if ASF is running. Retry a couple of times 2978 * if we get a conflict with the ASF firmware accessing 2979 * the PHY. 2980 */ 2981 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2982 bge_asf_driver_up(sc); 2983 2984 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2985 bge_ifmedia_sts); 2986 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2987 MII_PHY_ANY, MII_OFFSET_ANY, 2988 MIIF_FORCEANEG|MIIF_DOPAUSE); 2989 2990 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2991 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2992 ifmedia_add(&sc->bge_mii.mii_media, 2993 IFM_ETHER|IFM_MANUAL, 0, NULL); 2994 ifmedia_set(&sc->bge_mii.mii_media, 2995 IFM_ETHER|IFM_MANUAL); 2996 } else 2997 ifmedia_set(&sc->bge_mii.mii_media, 2998 IFM_ETHER|IFM_AUTO); 2999 3000 /* 3001 * Now tell the firmware we are going up after probing the PHY 3002 */ 3003 if (sc->bge_asf_mode & ASF_STACKUP) 3004 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3005 } 3006 3007 /* 3008 * Call MI attach routine. 3009 */ 3010 DPRINTFN(5, ("if_attach\n")); 3011 if_attach(ifp); 3012 DPRINTFN(5, ("ether_ifattach\n")); 3013 ether_ifattach(ifp, eaddr); 3014 ether_set_ifflags_cb(&sc->ethercom, bge_ifflags_cb); 3015 #if NRND > 0 3016 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 3017 RND_TYPE_NET, 0); 3018 #endif 3019 #ifdef BGE_EVENT_COUNTERS 3020 /* 3021 * Attach event counters. 3022 */ 3023 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 3024 NULL, device_xname(sc->bge_dev), "intr"); 3025 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 3026 NULL, device_xname(sc->bge_dev), "tx_xoff"); 3027 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 3028 NULL, device_xname(sc->bge_dev), "tx_xon"); 3029 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 3030 NULL, device_xname(sc->bge_dev), "rx_xoff"); 3031 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 3032 NULL, device_xname(sc->bge_dev), "rx_xon"); 3033 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 3034 NULL, device_xname(sc->bge_dev), "rx_macctl"); 3035 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 3036 NULL, device_xname(sc->bge_dev), "xoffentered"); 3037 #endif /* BGE_EVENT_COUNTERS */ 3038 DPRINTFN(5, ("callout_init\n")); 3039 callout_init(&sc->bge_timeout, 0); 3040 3041 if (pmf_device_register(self, NULL, NULL)) 3042 pmf_class_network_register(self, ifp); 3043 else 3044 aprint_error_dev(self, "couldn't establish power handler\n"); 3045 3046 #ifdef BGE_DEBUG 3047 bge_debug_info(sc); 3048 #endif 3049 } 3050 3051 static void 3052 bge_release_resources(struct bge_softc *sc) 3053 { 3054 if (sc->bge_vpd_prodname != NULL) 3055 free(sc->bge_vpd_prodname, M_DEVBUF); 3056 3057 if (sc->bge_vpd_readonly != NULL) 3058 free(sc->bge_vpd_readonly, M_DEVBUF); 3059 } 3060 3061 static int 3062 bge_reset(struct bge_softc *sc) 3063 { 3064 uint32_t cachesize, command, pcistate, marbmode; 3065 #if 0 3066 uint32_t new_pcistate; 3067 #endif 3068 pcireg_t devctl, reg; 3069 int i, val; 3070 void (*write_op)(struct bge_softc *, int, int); 3071 3072 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) 3073 && (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 3074 if (sc->bge_flags & BGE_PCIE) 3075 write_op = bge_writemem_direct; 3076 else 3077 write_op = bge_writemem_ind; 3078 } else 3079 write_op = bge_writereg_ind; 3080 3081 /* Save some important PCI state. */ 3082 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 3083 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3084 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 3085 3086 /* Step 5a: Enable memory arbiter. */ 3087 marbmode = 0; 3088 if (BGE_IS_5714_FAMILY(sc)) 3089 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3090 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3091 3092 /* Step 5b-5d: */ 3093 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3094 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3095 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW); 3096 3097 /* XXX ???: Disable fastboot on controllers that support it. */ 3098 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3099 BGE_IS_5755_PLUS(sc)) 3100 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3101 3102 /* 3103 * Step 6: Write the magic number to SRAM at offset 0xB50. 3104 * When firmware finishes its initialization it will 3105 * write ~BGE_MAGIC_NUMBER to the same location. 3106 */ 3107 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3108 3109 /* Step 7: */ 3110 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 3111 /* 3112 * XXX: from FreeBSD/Linux; no documentation 3113 */ 3114 if (sc->bge_flags & BGE_PCIE) { 3115 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 3116 /* PCI Express 1.0 system */ 3117 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 3118 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3119 /* 3120 * Prevent PCI Express link training 3121 * during global reset. 3122 */ 3123 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3124 val |= (1<<29); 3125 } 3126 } 3127 3128 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3129 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 3130 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3131 i | BGE_VCPU_STATUS_DRV_RESET); 3132 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3133 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3134 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3135 } 3136 3137 /* 3138 * Set GPHY Power Down Override to leave GPHY 3139 * powered up in D0 uninitialized. 3140 */ 3141 if (BGE_IS_5705_PLUS(sc)) 3142 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 3143 3144 /* XXX 5721, 5751 and 5752 */ 3145 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) 3146 val |= BGE_MISCCFG_GRC_RESET_DISABLE; 3147 3148 /* Issue global reset */ 3149 write_op(sc, BGE_MISC_CFG, val); 3150 3151 /* Step 8: wait for complete */ 3152 if (sc->bge_flags & BGE_PCIE) 3153 delay(100*1000); /* too big */ 3154 else 3155 delay(100); 3156 3157 /* From Linux: dummy read to flush PCI posted writes */ 3158 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 3159 3160 /* Step 9-10: Reset some of the PCI state that got zapped by reset */ 3161 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 3162 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3163 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW 3164 | BGE_PCIMISCCTL_CLOCKCTL_RW); 3165 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 3166 write_op(sc, BGE_MISC_CFG, (65 << 1)); 3167 3168 /* Step 11: disable PCI-X Relaxed Ordering. */ 3169 if (sc->bge_flags & BGE_PCIX) { 3170 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3171 + PCI_PCIX_CMD); 3172 pci_conf_write(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap 3173 + PCI_PCIX_CMD, reg & ~PCI_PCIX_CMD_RELAXED_ORDER); 3174 } 3175 3176 if (sc->bge_flags & BGE_PCIE) { 3177 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3178 DELAY(500000); 3179 /* XXX: Magic Numbers */ 3180 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3181 BGE_PCI_UNKNOWN0); 3182 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3183 BGE_PCI_UNKNOWN0, 3184 reg | (1 << 15)); 3185 } 3186 devctl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3187 sc->bge_pciecap + PCI_PCIE_DCSR); 3188 /* Clear enable no snoop and disable relaxed ordering. */ 3189 devctl &= ~(0x0010 | PCI_PCIE_DCSR_ENA_NO_SNOOP); 3190 /* Set PCIE max payload size to 128. */ 3191 devctl &= ~(0x00e0); 3192 /* Clear device status register. Write 1b to clear */ 3193 devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED 3194 | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED; 3195 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3196 sc->bge_pciecap + PCI_PCIE_DCSR, devctl); 3197 } 3198 3199 /* Step 12: Enable memory arbiter. */ 3200 marbmode = 0; 3201 if (BGE_IS_5714_FAMILY(sc)) 3202 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 3203 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 3204 3205 /* Step 17: Poll until the firmware initialization is complete */ 3206 bge_poll_fw(sc); 3207 3208 /* XXX 5721, 5751 and 5752 */ 3209 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750) { 3210 /* Step 19: */ 3211 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, 1 << 29 | 1 << 25); 3212 /* Step 20: */ 3213 BGE_SETBIT(sc, BGE_TLP_CONTROL_REG, BGE_TLP_DATA_FIFO_PROTECT); 3214 } 3215 3216 /* 3217 * Step 18: wirte mac mode 3218 * XXX Write 0x0c for 5703S and 5704S 3219 */ 3220 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3221 3222 3223 /* Step 21: 5822 B0 errata */ 3224 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_BX) { 3225 pcireg_t msidata; 3226 3227 msidata = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3228 BGE_PCI_MSI_DATA); 3229 msidata |= ((1 << 13 | 1 << 12 | 1 << 10) << 16); 3230 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MSI_DATA, 3231 msidata); 3232 } 3233 3234 /* Step 23: restore cache line size */ 3235 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 3236 3237 #if 0 3238 /* 3239 * XXX Wait for the value of the PCISTATE register to 3240 * return to its original pre-reset state. This is a 3241 * fairly good indicator of reset completion. If we don't 3242 * wait for the reset to fully complete, trying to read 3243 * from the device's non-PCI registers may yield garbage 3244 * results. 3245 */ 3246 for (i = 0; i < BGE_TIMEOUT; i++) { 3247 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3248 BGE_PCI_PCISTATE); 3249 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 3250 (pcistate & ~BGE_PCISTATE_RESERVED)) 3251 break; 3252 DELAY(10); 3253 } 3254 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 3255 (pcistate & ~BGE_PCISTATE_RESERVED)) { 3256 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 3257 } 3258 #endif 3259 3260 /* Step 28: Fix up byte swapping */ 3261 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 3262 3263 /* Tell the ASF firmware we are up */ 3264 if (sc->bge_asf_mode & ASF_STACKUP) 3265 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3266 3267 /* 3268 * The 5704 in TBI mode apparently needs some special 3269 * adjustment to insure the SERDES drive level is set 3270 * to 1.2V. 3271 */ 3272 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 3273 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3274 uint32_t serdescfg; 3275 3276 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 3277 serdescfg = (serdescfg & ~0xFFF) | 0x880; 3278 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 3279 } 3280 3281 if (sc->bge_flags & BGE_PCIE && 3282 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3283 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3284 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3285 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) { 3286 uint32_t v; 3287 3288 /* Enable PCI Express bug fix */ 3289 v = CSR_READ_4(sc, 0x7c00); 3290 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 3291 } 3292 DELAY(10000); 3293 3294 return 0; 3295 } 3296 3297 /* 3298 * Frame reception handling. This is called if there's a frame 3299 * on the receive return list. 3300 * 3301 * Note: we have to be able to handle two possibilities here: 3302 * 1) the frame is from the jumbo receive ring 3303 * 2) the frame is from the standard receive ring 3304 */ 3305 3306 static void 3307 bge_rxeof(struct bge_softc *sc) 3308 { 3309 struct ifnet *ifp; 3310 uint16_t rx_prod, rx_cons; 3311 int stdcnt = 0, jumbocnt = 0; 3312 bus_dmamap_t dmamap; 3313 bus_addr_t offset, toff; 3314 bus_size_t tlen; 3315 int tosync; 3316 3317 rx_cons = sc->bge_rx_saved_considx; 3318 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3319 3320 /* Nothing to do */ 3321 if (rx_cons == rx_prod) 3322 return; 3323 3324 ifp = &sc->ethercom.ec_if; 3325 3326 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3327 offsetof(struct bge_ring_data, bge_status_block), 3328 sizeof (struct bge_status_block), 3329 BUS_DMASYNC_POSTREAD); 3330 3331 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3332 tosync = rx_prod - rx_cons; 3333 3334 #if NRND > 0 3335 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3336 rnd_add_uint32(&sc->rnd_source, tosync); 3337 #endif 3338 3339 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3340 3341 if (tosync < 0) { 3342 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3343 sizeof (struct bge_rx_bd); 3344 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3345 toff, tlen, BUS_DMASYNC_POSTREAD); 3346 tosync = -tosync; 3347 } 3348 3349 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3350 offset, tosync * sizeof (struct bge_rx_bd), 3351 BUS_DMASYNC_POSTREAD); 3352 3353 while (rx_cons != rx_prod) { 3354 struct bge_rx_bd *cur_rx; 3355 uint32_t rxidx; 3356 struct mbuf *m = NULL; 3357 3358 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3359 3360 rxidx = cur_rx->bge_idx; 3361 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3362 3363 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3364 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3365 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3366 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3367 jumbocnt++; 3368 bus_dmamap_sync(sc->bge_dmatag, 3369 sc->bge_cdata.bge_rx_jumbo_map, 3370 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 3371 BGE_JLEN, BUS_DMASYNC_POSTREAD); 3372 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3373 ifp->if_ierrors++; 3374 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3375 continue; 3376 } 3377 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 3378 NULL)== ENOBUFS) { 3379 ifp->if_ierrors++; 3380 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 3381 continue; 3382 } 3383 } else { 3384 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3385 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3386 3387 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3388 stdcnt++; 3389 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3390 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 3391 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3392 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3393 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3394 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3395 ifp->if_ierrors++; 3396 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3397 continue; 3398 } 3399 if (bge_newbuf_std(sc, sc->bge_std, 3400 NULL, dmamap) == ENOBUFS) { 3401 ifp->if_ierrors++; 3402 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 3403 continue; 3404 } 3405 } 3406 3407 ifp->if_ipackets++; 3408 #ifndef __NO_STRICT_ALIGNMENT 3409 /* 3410 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 3411 * the Rx buffer has the layer-2 header unaligned. 3412 * If our CPU requires alignment, re-align by copying. 3413 */ 3414 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3415 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 3416 cur_rx->bge_len); 3417 m->m_data += ETHER_ALIGN; 3418 } 3419 #endif 3420 3421 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3422 m->m_pkthdr.rcvif = ifp; 3423 3424 /* 3425 * Handle BPF listeners. Let the BPF user see the packet. 3426 */ 3427 bpf_mtap(ifp, m); 3428 3429 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3430 3431 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3432 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3433 /* 3434 * Rx transport checksum-offload may also 3435 * have bugs with packets which, when transmitted, 3436 * were `runts' requiring padding. 3437 */ 3438 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3439 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3440 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3441 m->m_pkthdr.csum_data = 3442 cur_rx->bge_tcp_udp_csum; 3443 m->m_pkthdr.csum_flags |= 3444 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3445 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3446 } 3447 3448 /* 3449 * If we received a packet with a vlan tag, pass it 3450 * to vlan_input() instead of ether_input(). 3451 */ 3452 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3453 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3454 } 3455 3456 (*ifp->if_input)(ifp, m); 3457 } 3458 3459 sc->bge_rx_saved_considx = rx_cons; 3460 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3461 if (stdcnt) 3462 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3463 if (jumbocnt) 3464 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3465 } 3466 3467 static void 3468 bge_txeof(struct bge_softc *sc) 3469 { 3470 struct bge_tx_bd *cur_tx = NULL; 3471 struct ifnet *ifp; 3472 struct txdmamap_pool_entry *dma; 3473 bus_addr_t offset, toff; 3474 bus_size_t tlen; 3475 int tosync; 3476 struct mbuf *m; 3477 3478 ifp = &sc->ethercom.ec_if; 3479 3480 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3481 offsetof(struct bge_ring_data, bge_status_block), 3482 sizeof (struct bge_status_block), 3483 BUS_DMASYNC_POSTREAD); 3484 3485 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3486 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3487 sc->bge_tx_saved_considx; 3488 3489 #if NRND > 0 3490 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3491 rnd_add_uint32(&sc->rnd_source, tosync); 3492 #endif 3493 3494 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3495 3496 if (tosync < 0) { 3497 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3498 sizeof (struct bge_tx_bd); 3499 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3500 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3501 tosync = -tosync; 3502 } 3503 3504 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3505 offset, tosync * sizeof (struct bge_tx_bd), 3506 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3507 3508 /* 3509 * Go through our tx ring and free mbufs for those 3510 * frames that have been sent. 3511 */ 3512 while (sc->bge_tx_saved_considx != 3513 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3514 uint32_t idx = 0; 3515 3516 idx = sc->bge_tx_saved_considx; 3517 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3518 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3519 ifp->if_opackets++; 3520 m = sc->bge_cdata.bge_tx_chain[idx]; 3521 if (m != NULL) { 3522 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3523 dma = sc->txdma[idx]; 3524 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3525 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3526 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3527 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3528 sc->txdma[idx] = NULL; 3529 3530 m_freem(m); 3531 } 3532 sc->bge_txcnt--; 3533 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3534 ifp->if_timer = 0; 3535 } 3536 3537 if (cur_tx != NULL) 3538 ifp->if_flags &= ~IFF_OACTIVE; 3539 } 3540 3541 static int 3542 bge_intr(void *xsc) 3543 { 3544 struct bge_softc *sc; 3545 struct ifnet *ifp; 3546 uint32_t statusword; 3547 3548 sc = xsc; 3549 ifp = &sc->ethercom.ec_if; 3550 3551 /* It is possible for the interrupt to arrive before 3552 * the status block is updated prior to the interrupt. 3553 * Reading the PCI State register will confirm whether the 3554 * interrupt is ours and will flush the status block. 3555 */ 3556 3557 /* read status word from status block */ 3558 statusword = sc->bge_rdata->bge_status_block.bge_status; 3559 3560 if ((statusword & BGE_STATFLAG_UPDATED) || 3561 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3562 /* Ack interrupt and stop others from occuring. */ 3563 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3564 3565 BGE_EVCNT_INCR(sc->bge_ev_intr); 3566 3567 /* clear status word */ 3568 sc->bge_rdata->bge_status_block.bge_status = 0; 3569 3570 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3571 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3572 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3573 bge_link_upd(sc); 3574 3575 if (ifp->if_flags & IFF_RUNNING) { 3576 /* Check RX return ring producer/consumer */ 3577 bge_rxeof(sc); 3578 3579 /* Check TX ring producer/consumer */ 3580 bge_txeof(sc); 3581 } 3582 3583 if (sc->bge_pending_rxintr_change) { 3584 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3585 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3586 uint32_t junk; 3587 3588 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3589 DELAY(10); 3590 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3591 3592 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3593 DELAY(10); 3594 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3595 3596 sc->bge_pending_rxintr_change = 0; 3597 } 3598 bge_handle_events(sc); 3599 3600 /* Re-enable interrupts. */ 3601 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3602 3603 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3604 bge_start(ifp); 3605 3606 return 1; 3607 } else 3608 return 0; 3609 } 3610 3611 static void 3612 bge_asf_driver_up(struct bge_softc *sc) 3613 { 3614 if (sc->bge_asf_mode & ASF_STACKUP) { 3615 /* Send ASF heartbeat aprox. every 2s */ 3616 if (sc->bge_asf_count) 3617 sc->bge_asf_count --; 3618 else { 3619 sc->bge_asf_count = 2; 3620 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3621 BGE_FW_DRV_ALIVE); 3622 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3623 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3624 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3625 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3626 } 3627 } 3628 } 3629 3630 static void 3631 bge_tick(void *xsc) 3632 { 3633 struct bge_softc *sc = xsc; 3634 struct mii_data *mii = &sc->bge_mii; 3635 int s; 3636 3637 s = splnet(); 3638 3639 if (BGE_IS_5705_PLUS(sc)) 3640 bge_stats_update_regs(sc); 3641 else 3642 bge_stats_update(sc); 3643 3644 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3645 /* 3646 * Since in TBI mode auto-polling can't be used we should poll 3647 * link status manually. Here we register pending link event 3648 * and trigger interrupt. 3649 */ 3650 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3651 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3652 } else { 3653 /* 3654 * Do not touch PHY if we have link up. This could break 3655 * IPMI/ASF mode or produce extra input errors. 3656 * (extra input errors was reported for bcm5701 & bcm5704). 3657 */ 3658 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3659 mii_tick(mii); 3660 } 3661 3662 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3663 3664 splx(s); 3665 } 3666 3667 static void 3668 bge_stats_update_regs(struct bge_softc *sc) 3669 { 3670 struct ifnet *ifp = &sc->ethercom.ec_if; 3671 3672 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3673 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3674 3675 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3676 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3677 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3678 } 3679 3680 static void 3681 bge_stats_update(struct bge_softc *sc) 3682 { 3683 struct ifnet *ifp = &sc->ethercom.ec_if; 3684 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3685 3686 #define READ_STAT(sc, stats, stat) \ 3687 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3688 3689 ifp->if_collisions += 3690 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3691 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3692 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3693 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3694 ifp->if_collisions; 3695 3696 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3697 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3698 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3699 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3700 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3701 READ_STAT(sc, stats, 3702 xoffPauseFramesReceived.bge_addr_lo)); 3703 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3704 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3705 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3706 READ_STAT(sc, stats, 3707 macControlFramesReceived.bge_addr_lo)); 3708 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3709 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3710 3711 #undef READ_STAT 3712 3713 #ifdef notdef 3714 ifp->if_collisions += 3715 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3716 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3717 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3718 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3719 ifp->if_collisions; 3720 #endif 3721 } 3722 3723 /* 3724 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3725 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3726 * but when such padded frames employ the bge IP/TCP checksum offload, 3727 * the hardware checksum assist gives incorrect results (possibly 3728 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3729 * If we pad such runts with zeros, the onboard checksum comes out correct. 3730 */ 3731 static inline int 3732 bge_cksum_pad(struct mbuf *pkt) 3733 { 3734 struct mbuf *last = NULL; 3735 int padlen; 3736 3737 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3738 3739 /* if there's only the packet-header and we can pad there, use it. */ 3740 if (pkt->m_pkthdr.len == pkt->m_len && 3741 M_TRAILINGSPACE(pkt) >= padlen) { 3742 last = pkt; 3743 } else { 3744 /* 3745 * Walk packet chain to find last mbuf. We will either 3746 * pad there, or append a new mbuf and pad it 3747 * (thus perhaps avoiding the bcm5700 dma-min bug). 3748 */ 3749 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3750 continue; /* do nothing */ 3751 } 3752 3753 /* `last' now points to last in chain. */ 3754 if (M_TRAILINGSPACE(last) < padlen) { 3755 /* Allocate new empty mbuf, pad it. Compact later. */ 3756 struct mbuf *n; 3757 MGET(n, M_DONTWAIT, MT_DATA); 3758 if (n == NULL) 3759 return ENOBUFS; 3760 n->m_len = 0; 3761 last->m_next = n; 3762 last = n; 3763 } 3764 } 3765 3766 KDASSERT(!M_READONLY(last)); 3767 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3768 3769 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3770 memset(mtod(last, char *) + last->m_len, 0, padlen); 3771 last->m_len += padlen; 3772 pkt->m_pkthdr.len += padlen; 3773 return 0; 3774 } 3775 3776 /* 3777 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3778 */ 3779 static inline int 3780 bge_compact_dma_runt(struct mbuf *pkt) 3781 { 3782 struct mbuf *m, *prev; 3783 int totlen, prevlen; 3784 3785 prev = NULL; 3786 totlen = 0; 3787 prevlen = -1; 3788 3789 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3790 int mlen = m->m_len; 3791 int shortfall = 8 - mlen ; 3792 3793 totlen += mlen; 3794 if (mlen == 0) { 3795 continue; 3796 } 3797 if (mlen >= 8) 3798 continue; 3799 3800 /* If we get here, mbuf data is too small for DMA engine. 3801 * Try to fix by shuffling data to prev or next in chain. 3802 * If that fails, do a compacting deep-copy of the whole chain. 3803 */ 3804 3805 /* Internal frag. If fits in prev, copy it there. */ 3806 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3807 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3808 prev->m_len += mlen; 3809 m->m_len = 0; 3810 /* XXX stitch chain */ 3811 prev->m_next = m_free(m); 3812 m = prev; 3813 continue; 3814 } 3815 else if (m->m_next != NULL && 3816 M_TRAILINGSPACE(m) >= shortfall && 3817 m->m_next->m_len >= (8 + shortfall)) { 3818 /* m is writable and have enough data in next, pull up. */ 3819 3820 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3821 shortfall); 3822 m->m_len += shortfall; 3823 m->m_next->m_len -= shortfall; 3824 m->m_next->m_data += shortfall; 3825 } 3826 else if (m->m_next == NULL || 1) { 3827 /* Got a runt at the very end of the packet. 3828 * borrow data from the tail of the preceding mbuf and 3829 * update its length in-place. (The original data is still 3830 * valid, so we can do this even if prev is not writable.) 3831 */ 3832 3833 /* if we'd make prev a runt, just move all of its data. */ 3834 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3835 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3836 3837 if ((prev->m_len - shortfall) < 8) 3838 shortfall = prev->m_len; 3839 3840 #ifdef notyet /* just do the safe slow thing for now */ 3841 if (!M_READONLY(m)) { 3842 if (M_LEADINGSPACE(m) < shorfall) { 3843 void *m_dat; 3844 m_dat = (m->m_flags & M_PKTHDR) ? 3845 m->m_pktdat : m->dat; 3846 memmove(m_dat, mtod(m, void*), m->m_len); 3847 m->m_data = m_dat; 3848 } 3849 } else 3850 #endif /* just do the safe slow thing */ 3851 { 3852 struct mbuf * n = NULL; 3853 int newprevlen = prev->m_len - shortfall; 3854 3855 MGET(n, M_NOWAIT, MT_DATA); 3856 if (n == NULL) 3857 return ENOBUFS; 3858 KASSERT(m->m_len + shortfall < MLEN 3859 /*, 3860 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3861 3862 /* first copy the data we're stealing from prev */ 3863 memcpy(n->m_data, prev->m_data + newprevlen, 3864 shortfall); 3865 3866 /* update prev->m_len accordingly */ 3867 prev->m_len -= shortfall; 3868 3869 /* copy data from runt m */ 3870 memcpy(n->m_data + shortfall, m->m_data, 3871 m->m_len); 3872 3873 /* n holds what we stole from prev, plus m */ 3874 n->m_len = shortfall + m->m_len; 3875 3876 /* stitch n into chain and free m */ 3877 n->m_next = m->m_next; 3878 prev->m_next = n; 3879 /* KASSERT(m->m_next == NULL); */ 3880 m->m_next = NULL; 3881 m_free(m); 3882 m = n; /* for continuing loop */ 3883 } 3884 } 3885 prevlen = m->m_len; 3886 } 3887 return 0; 3888 } 3889 3890 /* 3891 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3892 * pointers to descriptors. 3893 */ 3894 static int 3895 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 3896 { 3897 struct bge_tx_bd *f = NULL; 3898 uint32_t frag, cur; 3899 uint16_t csum_flags = 0; 3900 uint16_t txbd_tso_flags = 0; 3901 struct txdmamap_pool_entry *dma; 3902 bus_dmamap_t dmamap; 3903 int i = 0; 3904 struct m_tag *mtag; 3905 int use_tso, maxsegsize, error; 3906 3907 cur = frag = *txidx; 3908 3909 if (m_head->m_pkthdr.csum_flags) { 3910 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3911 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3912 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3913 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3914 } 3915 3916 /* 3917 * If we were asked to do an outboard checksum, and the NIC 3918 * has the bug where it sometimes adds in the Ethernet padding, 3919 * explicitly pad with zeros so the cksum will be correct either way. 3920 * (For now, do this for all chip versions, until newer 3921 * are confirmed to not require the workaround.) 3922 */ 3923 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3924 #ifdef notyet 3925 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3926 #endif 3927 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3928 goto check_dma_bug; 3929 3930 if (bge_cksum_pad(m_head) != 0) 3931 return ENOBUFS; 3932 3933 check_dma_bug: 3934 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3935 goto doit; 3936 3937 /* 3938 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3939 * less than eight bytes. If we encounter a teeny mbuf 3940 * at the end of a chain, we can pad. Otherwise, copy. 3941 */ 3942 if (bge_compact_dma_runt(m_head) != 0) 3943 return ENOBUFS; 3944 3945 doit: 3946 dma = SLIST_FIRST(&sc->txdma_list); 3947 if (dma == NULL) 3948 return ENOBUFS; 3949 dmamap = dma->dmamap; 3950 3951 /* 3952 * Set up any necessary TSO state before we start packing... 3953 */ 3954 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3955 if (!use_tso) { 3956 maxsegsize = 0; 3957 } else { /* TSO setup */ 3958 unsigned mss; 3959 struct ether_header *eh; 3960 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3961 struct mbuf * m0 = m_head; 3962 struct ip *ip; 3963 struct tcphdr *th; 3964 int iphl, hlen; 3965 3966 /* 3967 * XXX It would be nice if the mbuf pkthdr had offset 3968 * fields for the protocol headers. 3969 */ 3970 3971 eh = mtod(m0, struct ether_header *); 3972 switch (htons(eh->ether_type)) { 3973 case ETHERTYPE_IP: 3974 offset = ETHER_HDR_LEN; 3975 break; 3976 3977 case ETHERTYPE_VLAN: 3978 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3979 break; 3980 3981 default: 3982 /* 3983 * Don't support this protocol or encapsulation. 3984 */ 3985 return ENOBUFS; 3986 } 3987 3988 /* 3989 * TCP/IP headers are in the first mbuf; we can do 3990 * this the easy way. 3991 */ 3992 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3993 hlen = iphl + offset; 3994 if (__predict_false(m0->m_len < 3995 (hlen + sizeof(struct tcphdr)))) { 3996 3997 aprint_debug_dev(sc->bge_dev, 3998 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3999 "not handled yet\n", 4000 m0->m_len, hlen+ sizeof(struct tcphdr)); 4001 #ifdef NOTYET 4002 /* 4003 * XXX jonathan@NetBSD.org: untested. 4004 * how to force this branch to be taken? 4005 */ 4006 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 4007 4008 m_copydata(m0, offset, sizeof(ip), &ip); 4009 m_copydata(m0, hlen, sizeof(th), &th); 4010 4011 ip.ip_len = 0; 4012 4013 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 4014 sizeof(ip.ip_len), &ip.ip_len); 4015 4016 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 4017 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 4018 4019 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 4020 sizeof(th.th_sum), &th.th_sum); 4021 4022 hlen += th.th_off << 2; 4023 iptcp_opt_words = hlen; 4024 #else 4025 /* 4026 * if_wm "hard" case not yet supported, can we not 4027 * mandate it out of existence? 4028 */ 4029 (void) ip; (void)th; (void) ip_tcp_hlen; 4030 4031 return ENOBUFS; 4032 #endif 4033 } else { 4034 ip = (struct ip *) (mtod(m0, char *) + offset); 4035 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 4036 ip_tcp_hlen = iphl + (th->th_off << 2); 4037 4038 /* Total IP/TCP options, in 32-bit words */ 4039 iptcp_opt_words = (ip_tcp_hlen 4040 - sizeof(struct tcphdr) 4041 - sizeof(struct ip)) >> 2; 4042 } 4043 if (BGE_IS_5750_OR_BEYOND(sc)) { 4044 th->th_sum = 0; 4045 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 4046 } else { 4047 /* 4048 * XXX jonathan@NetBSD.org: 5705 untested. 4049 * Requires TSO firmware patch for 5701/5703/5704. 4050 */ 4051 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 4052 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 4053 } 4054 4055 mss = m_head->m_pkthdr.segsz; 4056 txbd_tso_flags |= 4057 BGE_TXBDFLAG_CPU_PRE_DMA | 4058 BGE_TXBDFLAG_CPU_POST_DMA; 4059 4060 /* 4061 * Our NIC TSO-assist assumes TSO has standard, optionless 4062 * IPv4 and TCP headers, which total 40 bytes. By default, 4063 * the NIC copies 40 bytes of IP/TCP header from the 4064 * supplied header into the IP/TCP header portion of 4065 * each post-TSO-segment. If the supplied packet has IP or 4066 * TCP options, we need to tell the NIC to copy those extra 4067 * bytes into each post-TSO header, in addition to the normal 4068 * 40-byte IP/TCP header (and to leave space accordingly). 4069 * Unfortunately, the driver encoding of option length 4070 * varies across different ASIC families. 4071 */ 4072 tcp_seg_flags = 0; 4073 if (iptcp_opt_words) { 4074 if (BGE_IS_5705_PLUS(sc)) { 4075 tcp_seg_flags = 4076 iptcp_opt_words << 11; 4077 } else { 4078 txbd_tso_flags |= 4079 iptcp_opt_words << 12; 4080 } 4081 } 4082 maxsegsize = mss | tcp_seg_flags; 4083 ip->ip_len = htons(mss + ip_tcp_hlen); 4084 4085 } /* TSO setup */ 4086 4087 /* 4088 * Start packing the mbufs in this chain into 4089 * the fragment pointers. Stop when we run out 4090 * of fragments or hit the end of the mbuf chain. 4091 */ 4092 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 4093 BUS_DMA_NOWAIT); 4094 if (error) 4095 return ENOBUFS; 4096 /* 4097 * Sanity check: avoid coming within 16 descriptors 4098 * of the end of the ring. 4099 */ 4100 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 4101 BGE_TSO_PRINTF(("%s: " 4102 " dmamap_load_mbuf too close to ring wrap\n", 4103 device_xname(sc->bge_dev))); 4104 goto fail_unload; 4105 } 4106 4107 mtag = sc->ethercom.ec_nvlans ? 4108 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 4109 4110 4111 /* Iterate over dmap-map fragments. */ 4112 for (i = 0; i < dmamap->dm_nsegs; i++) { 4113 f = &sc->bge_rdata->bge_tx_ring[frag]; 4114 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4115 break; 4116 4117 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4118 f->bge_len = dmamap->dm_segs[i].ds_len; 4119 4120 /* 4121 * For 5751 and follow-ons, for TSO we must turn 4122 * off checksum-assist flag in the tx-descr, and 4123 * supply the ASIC-revision-specific encoding 4124 * of TSO flags and segsize. 4125 */ 4126 if (use_tso) { 4127 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 4128 f->bge_rsvd = maxsegsize; 4129 f->bge_flags = csum_flags | txbd_tso_flags; 4130 } else { 4131 f->bge_rsvd = 0; 4132 f->bge_flags = 4133 (csum_flags | txbd_tso_flags) & 0x0fff; 4134 } 4135 } else { 4136 f->bge_rsvd = 0; 4137 f->bge_flags = csum_flags; 4138 } 4139 4140 if (mtag != NULL) { 4141 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4142 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 4143 } else { 4144 f->bge_vlan_tag = 0; 4145 } 4146 cur = frag; 4147 BGE_INC(frag, BGE_TX_RING_CNT); 4148 } 4149 4150 if (i < dmamap->dm_nsegs) { 4151 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 4152 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 4153 goto fail_unload; 4154 } 4155 4156 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4157 BUS_DMASYNC_PREWRITE); 4158 4159 if (frag == sc->bge_tx_saved_considx) { 4160 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 4161 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 4162 4163 goto fail_unload; 4164 } 4165 4166 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4167 sc->bge_cdata.bge_tx_chain[cur] = m_head; 4168 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 4169 sc->txdma[cur] = dma; 4170 sc->bge_txcnt += dmamap->dm_nsegs; 4171 4172 *txidx = frag; 4173 4174 return 0; 4175 4176 fail_unload: 4177 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4178 4179 return ENOBUFS; 4180 } 4181 4182 /* 4183 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4184 * to the mbuf data regions directly in the transmit descriptors. 4185 */ 4186 static void 4187 bge_start(struct ifnet *ifp) 4188 { 4189 struct bge_softc *sc; 4190 struct mbuf *m_head = NULL; 4191 uint32_t prodidx; 4192 int pkts = 0; 4193 4194 sc = ifp->if_softc; 4195 4196 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 4197 return; 4198 4199 prodidx = sc->bge_tx_prodidx; 4200 4201 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 4202 IFQ_POLL(&ifp->if_snd, m_head); 4203 if (m_head == NULL) 4204 break; 4205 4206 #if 0 4207 /* 4208 * XXX 4209 * safety overkill. If this is a fragmented packet chain 4210 * with delayed TCP/UDP checksums, then only encapsulate 4211 * it if we have enough descriptors to handle the entire 4212 * chain at once. 4213 * (paranoia -- may not actually be needed) 4214 */ 4215 if (m_head->m_flags & M_FIRSTFRAG && 4216 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4217 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4218 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 4219 ifp->if_flags |= IFF_OACTIVE; 4220 break; 4221 } 4222 } 4223 #endif 4224 4225 /* 4226 * Pack the data into the transmit ring. If we 4227 * don't have room, set the OACTIVE flag and wait 4228 * for the NIC to drain the ring. 4229 */ 4230 if (bge_encap(sc, m_head, &prodidx)) { 4231 ifp->if_flags |= IFF_OACTIVE; 4232 break; 4233 } 4234 4235 /* now we are committed to transmit the packet */ 4236 IFQ_DEQUEUE(&ifp->if_snd, m_head); 4237 pkts++; 4238 4239 /* 4240 * If there's a BPF listener, bounce a copy of this frame 4241 * to him. 4242 */ 4243 bpf_mtap(ifp, m_head); 4244 } 4245 if (pkts == 0) 4246 return; 4247 4248 /* Transmit */ 4249 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4250 /* 5700 b2 errata */ 4251 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4252 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4253 4254 sc->bge_tx_prodidx = prodidx; 4255 4256 /* 4257 * Set a timeout in case the chip goes out to lunch. 4258 */ 4259 ifp->if_timer = 5; 4260 } 4261 4262 static int 4263 bge_init(struct ifnet *ifp) 4264 { 4265 struct bge_softc *sc = ifp->if_softc; 4266 const uint16_t *m; 4267 int s, error = 0; 4268 4269 s = splnet(); 4270 4271 ifp = &sc->ethercom.ec_if; 4272 4273 /* Cancel pending I/O and flush buffers. */ 4274 bge_stop(ifp, 0); 4275 4276 bge_stop_fw(sc); 4277 bge_sig_pre_reset(sc, BGE_RESET_START); 4278 bge_reset(sc); 4279 bge_sig_legacy(sc, BGE_RESET_START); 4280 bge_sig_post_reset(sc, BGE_RESET_START); 4281 4282 bge_chipinit(sc); 4283 4284 /* 4285 * Init the various state machines, ring 4286 * control blocks and firmware. 4287 */ 4288 error = bge_blockinit(sc); 4289 if (error != 0) { 4290 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 4291 error); 4292 splx(s); 4293 return error; 4294 } 4295 4296 ifp = &sc->ethercom.ec_if; 4297 4298 /* Specify MTU. */ 4299 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4300 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 4301 4302 /* Load our MAC address. */ 4303 m = (const uint16_t *)&(CLLADDR(ifp->if_sadl)[0]); 4304 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4305 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4306 4307 /* Enable or disable promiscuous mode as needed. */ 4308 if (ifp->if_flags & IFF_PROMISC) 4309 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4310 else 4311 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4312 4313 /* Program multicast filter. */ 4314 bge_setmulti(sc); 4315 4316 /* Init RX ring. */ 4317 bge_init_rx_ring_std(sc); 4318 4319 /* 4320 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4321 * memory to insure that the chip has in fact read the first 4322 * entry of the ring. 4323 */ 4324 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4325 uint32_t v, i; 4326 for (i = 0; i < 10; i++) { 4327 DELAY(20); 4328 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4329 if (v == (MCLBYTES - ETHER_ALIGN)) 4330 break; 4331 } 4332 if (i == 10) 4333 aprint_error_dev(sc->bge_dev, 4334 "5705 A0 chip failed to load RX ring\n"); 4335 } 4336 4337 /* Init jumbo RX ring. */ 4338 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 4339 bge_init_rx_ring_jumbo(sc); 4340 4341 /* Init our RX return ring index */ 4342 sc->bge_rx_saved_considx = 0; 4343 4344 /* Init TX ring. */ 4345 bge_init_tx_ring(sc); 4346 4347 /* Turn on transmitter */ 4348 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4349 4350 /* Turn on receiver */ 4351 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4352 4353 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4354 4355 /* Tell firmware we're alive. */ 4356 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4357 4358 /* Enable host interrupts. */ 4359 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4360 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4361 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4362 4363 if ((error = bge_ifmedia_upd(ifp)) != 0) 4364 goto out; 4365 4366 ifp->if_flags |= IFF_RUNNING; 4367 ifp->if_flags &= ~IFF_OACTIVE; 4368 4369 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 4370 4371 out: 4372 sc->bge_if_flags = ifp->if_flags; 4373 splx(s); 4374 4375 return error; 4376 } 4377 4378 /* 4379 * Set media options. 4380 */ 4381 static int 4382 bge_ifmedia_upd(struct ifnet *ifp) 4383 { 4384 struct bge_softc *sc = ifp->if_softc; 4385 struct mii_data *mii = &sc->bge_mii; 4386 struct ifmedia *ifm = &sc->bge_ifmedia; 4387 int rc; 4388 4389 /* If this is a 1000baseX NIC, enable the TBI port. */ 4390 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4391 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4392 return EINVAL; 4393 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4394 case IFM_AUTO: 4395 /* 4396 * The BCM5704 ASIC appears to have a special 4397 * mechanism for programming the autoneg 4398 * advertisement registers in TBI mode. 4399 */ 4400 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4401 uint32_t sgdig; 4402 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4403 if (sgdig & BGE_SGDIGSTS_DONE) { 4404 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4405 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4406 sgdig |= BGE_SGDIGCFG_AUTO | 4407 BGE_SGDIGCFG_PAUSE_CAP | 4408 BGE_SGDIGCFG_ASYM_PAUSE; 4409 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4410 sgdig | BGE_SGDIGCFG_SEND); 4411 DELAY(5); 4412 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4413 } 4414 } 4415 break; 4416 case IFM_1000_SX: 4417 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4418 BGE_CLRBIT(sc, BGE_MAC_MODE, 4419 BGE_MACMODE_HALF_DUPLEX); 4420 } else { 4421 BGE_SETBIT(sc, BGE_MAC_MODE, 4422 BGE_MACMODE_HALF_DUPLEX); 4423 } 4424 break; 4425 default: 4426 return EINVAL; 4427 } 4428 /* XXX 802.3x flow control for 1000BASE-SX */ 4429 return 0; 4430 } 4431 4432 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4433 if ((rc = mii_mediachg(mii)) == ENXIO) 4434 return 0; 4435 4436 /* 4437 * Force an interrupt so that we will call bge_link_upd 4438 * if needed and clear any pending link state attention. 4439 * Without this we are not getting any further interrupts 4440 * for link state changes and thus will not UP the link and 4441 * not be able to send in bge_start. The only way to get 4442 * things working was to receive a packet and get a RX intr. 4443 */ 4444 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4445 sc->bge_flags & BGE_IS_5788) 4446 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4447 else 4448 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4449 4450 return rc; 4451 } 4452 4453 /* 4454 * Report current media status. 4455 */ 4456 static void 4457 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4458 { 4459 struct bge_softc *sc = ifp->if_softc; 4460 struct mii_data *mii = &sc->bge_mii; 4461 4462 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4463 ifmr->ifm_status = IFM_AVALID; 4464 ifmr->ifm_active = IFM_ETHER; 4465 if (CSR_READ_4(sc, BGE_MAC_STS) & 4466 BGE_MACSTAT_TBI_PCS_SYNCHED) 4467 ifmr->ifm_status |= IFM_ACTIVE; 4468 ifmr->ifm_active |= IFM_1000_SX; 4469 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4470 ifmr->ifm_active |= IFM_HDX; 4471 else 4472 ifmr->ifm_active |= IFM_FDX; 4473 return; 4474 } 4475 4476 mii_pollstat(mii); 4477 ifmr->ifm_status = mii->mii_media_status; 4478 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4479 sc->bge_flowflags; 4480 } 4481 4482 static int 4483 bge_ifflags_cb(struct ethercom *ec) 4484 { 4485 struct ifnet *ifp = &ec->ec_if; 4486 struct bge_softc *sc = ifp->if_softc; 4487 int change = ifp->if_flags ^ sc->bge_if_flags; 4488 4489 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 4490 return ENETRESET; 4491 else if ((change & (IFF_PROMISC | IFF_ALLMULTI)) == 0) 4492 return 0; 4493 4494 if ((ifp->if_flags & IFF_PROMISC) == 0) 4495 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4496 else 4497 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 4498 4499 bge_setmulti(sc); 4500 4501 sc->bge_if_flags = ifp->if_flags; 4502 return 0; 4503 } 4504 4505 static int 4506 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4507 { 4508 struct bge_softc *sc = ifp->if_softc; 4509 struct ifreq *ifr = (struct ifreq *) data; 4510 int s, error = 0; 4511 struct mii_data *mii; 4512 4513 s = splnet(); 4514 4515 switch (command) { 4516 case SIOCSIFMEDIA: 4517 /* XXX Flow control is not supported for 1000BASE-SX */ 4518 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4519 ifr->ifr_media &= ~IFM_ETH_FMASK; 4520 sc->bge_flowflags = 0; 4521 } 4522 4523 /* Flow control requires full-duplex mode. */ 4524 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4525 (ifr->ifr_media & IFM_FDX) == 0) { 4526 ifr->ifr_media &= ~IFM_ETH_FMASK; 4527 } 4528 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4529 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4530 /* We can do both TXPAUSE and RXPAUSE. */ 4531 ifr->ifr_media |= 4532 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4533 } 4534 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4535 } 4536 /* FALLTHROUGH */ 4537 case SIOCGIFMEDIA: 4538 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4539 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4540 command); 4541 } else { 4542 mii = &sc->bge_mii; 4543 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4544 command); 4545 } 4546 break; 4547 default: 4548 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4549 break; 4550 4551 error = 0; 4552 4553 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4554 ; 4555 else if (ifp->if_flags & IFF_RUNNING) 4556 bge_setmulti(sc); 4557 break; 4558 } 4559 4560 splx(s); 4561 4562 return error; 4563 } 4564 4565 static void 4566 bge_watchdog(struct ifnet *ifp) 4567 { 4568 struct bge_softc *sc; 4569 4570 sc = ifp->if_softc; 4571 4572 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4573 4574 ifp->if_flags &= ~IFF_RUNNING; 4575 bge_init(ifp); 4576 4577 ifp->if_oerrors++; 4578 } 4579 4580 static void 4581 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4582 { 4583 int i; 4584 4585 BGE_CLRBIT(sc, reg, bit); 4586 4587 for (i = 0; i < 1000; i++) { 4588 if ((CSR_READ_4(sc, reg) & bit) == 0) 4589 return; 4590 delay(100); 4591 } 4592 4593 /* 4594 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4595 * on some environment (and once after boot?) 4596 */ 4597 if (reg != BGE_SRS_MODE) 4598 aprint_error_dev(sc->bge_dev, 4599 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4600 (u_long)reg, bit); 4601 } 4602 4603 /* 4604 * Stop the adapter and free any mbufs allocated to the 4605 * RX and TX lists. 4606 */ 4607 static void 4608 bge_stop(struct ifnet *ifp, int disable) 4609 { 4610 struct bge_softc *sc = ifp->if_softc; 4611 4612 callout_stop(&sc->bge_timeout); 4613 4614 /* 4615 * Tell firmware we're shutting down. 4616 */ 4617 bge_stop_fw(sc); 4618 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4619 4620 /* Disable host interrupts. */ 4621 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4622 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4623 4624 /* 4625 * Disable all of the receiver blocks 4626 */ 4627 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4628 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4629 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4630 if (BGE_IS_5700_FAMILY(sc)) 4631 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4632 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4633 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4634 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4635 4636 /* 4637 * Disable all of the transmit blocks 4638 */ 4639 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4640 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4641 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4642 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4643 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4644 if (BGE_IS_5700_FAMILY(sc)) 4645 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4646 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4647 4648 /* 4649 * Shut down all of the memory managers and related 4650 * state machines. 4651 */ 4652 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4653 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4654 if (BGE_IS_5700_FAMILY(sc)) 4655 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4656 4657 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4658 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4659 4660 if (BGE_IS_5700_FAMILY(sc)) { 4661 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4662 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4663 } 4664 4665 bge_reset(sc); 4666 bge_sig_legacy(sc, BGE_RESET_STOP); 4667 bge_sig_post_reset(sc, BGE_RESET_STOP); 4668 4669 /* 4670 * Keep the ASF firmware running if up. 4671 */ 4672 if (sc->bge_asf_mode & ASF_STACKUP) 4673 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4674 else 4675 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4676 4677 /* Free the RX lists. */ 4678 bge_free_rx_ring_std(sc); 4679 4680 /* Free jumbo RX list. */ 4681 if (BGE_IS_JUMBO_CAPABLE(sc)) 4682 bge_free_rx_ring_jumbo(sc); 4683 4684 /* Free TX buffers. */ 4685 bge_free_tx_ring(sc); 4686 4687 /* 4688 * Isolate/power down the PHY. 4689 */ 4690 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4691 mii_down(&sc->bge_mii); 4692 4693 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4694 4695 /* Clear MAC's link state (PHY may still have link UP). */ 4696 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4697 4698 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4699 } 4700 4701 static void 4702 bge_link_upd(struct bge_softc *sc) 4703 { 4704 struct ifnet *ifp = &sc->ethercom.ec_if; 4705 struct mii_data *mii = &sc->bge_mii; 4706 uint32_t status; 4707 int link; 4708 4709 /* Clear 'pending link event' flag */ 4710 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4711 4712 /* 4713 * Process link state changes. 4714 * Grrr. The link status word in the status block does 4715 * not work correctly on the BCM5700 rev AX and BX chips, 4716 * according to all available information. Hence, we have 4717 * to enable MII interrupts in order to properly obtain 4718 * async link changes. Unfortunately, this also means that 4719 * we have to read the MAC status register to detect link 4720 * changes, thereby adding an additional register access to 4721 * the interrupt handler. 4722 */ 4723 4724 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4725 status = CSR_READ_4(sc, BGE_MAC_STS); 4726 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4727 mii_pollstat(mii); 4728 4729 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4730 mii->mii_media_status & IFM_ACTIVE && 4731 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4732 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4733 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4734 (!(mii->mii_media_status & IFM_ACTIVE) || 4735 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4736 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4737 4738 /* Clear the interrupt */ 4739 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4740 BGE_EVTENB_MI_INTERRUPT); 4741 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4742 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4743 BRGPHY_INTRS); 4744 } 4745 return; 4746 } 4747 4748 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4749 status = CSR_READ_4(sc, BGE_MAC_STS); 4750 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4751 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4752 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4753 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4754 BGE_CLRBIT(sc, BGE_MAC_MODE, 4755 BGE_MACMODE_TBI_SEND_CFGS); 4756 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4757 if_link_state_change(ifp, LINK_STATE_UP); 4758 } 4759 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4760 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4761 if_link_state_change(ifp, LINK_STATE_DOWN); 4762 } 4763 /* 4764 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4765 * This should not happen since mii callouts are locked now, but 4766 * we keep this check for debug. 4767 */ 4768 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4769 /* 4770 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4771 * bit in status word always set. Workaround this bug by 4772 * reading PHY link status directly. 4773 */ 4774 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4775 BGE_STS_LINK : 0; 4776 4777 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4778 mii_pollstat(mii); 4779 4780 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4781 mii->mii_media_status & IFM_ACTIVE && 4782 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4783 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4784 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4785 (!(mii->mii_media_status & IFM_ACTIVE) || 4786 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4787 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4788 } 4789 } 4790 4791 /* Clear the attention */ 4792 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4793 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4794 BGE_MACSTAT_LINK_CHANGED); 4795 } 4796 4797 static int 4798 sysctl_bge_verify(SYSCTLFN_ARGS) 4799 { 4800 int error, t; 4801 struct sysctlnode node; 4802 4803 node = *rnode; 4804 t = *(int*)rnode->sysctl_data; 4805 node.sysctl_data = &t; 4806 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4807 if (error || newp == NULL) 4808 return error; 4809 4810 #if 0 4811 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4812 node.sysctl_num, rnode->sysctl_num)); 4813 #endif 4814 4815 if (node.sysctl_num == bge_rxthresh_nodenum) { 4816 if (t < 0 || t >= NBGE_RX_THRESH) 4817 return EINVAL; 4818 bge_update_all_threshes(t); 4819 } else 4820 return EINVAL; 4821 4822 *(int*)rnode->sysctl_data = t; 4823 4824 return 0; 4825 } 4826 4827 /* 4828 * Set up sysctl(3) MIB, hw.bge.*. 4829 * 4830 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4831 */ 4832 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4833 { 4834 int rc, bge_root_num; 4835 const struct sysctlnode *node; 4836 4837 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4838 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4839 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4840 goto err; 4841 } 4842 4843 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4844 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4845 SYSCTL_DESCR("BGE interface controls"), 4846 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4847 goto err; 4848 } 4849 4850 bge_root_num = node->sysctl_num; 4851 4852 /* BGE Rx interrupt mitigation level */ 4853 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4854 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4855 CTLTYPE_INT, "rx_lvl", 4856 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4857 sysctl_bge_verify, 0, 4858 &bge_rx_thresh_lvl, 4859 0, CTL_HW, bge_root_num, CTL_CREATE, 4860 CTL_EOL)) != 0) { 4861 goto err; 4862 } 4863 4864 bge_rxthresh_nodenum = node->sysctl_num; 4865 4866 return; 4867 4868 err: 4869 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4870 } 4871 4872 #ifdef BGE_DEBUG 4873 void 4874 bge_debug_info(struct bge_softc *sc) 4875 { 4876 4877 printf("Hardware Flags:\n"); 4878 if (BGE_IS_5755_PLUS(sc)) 4879 printf(" - 5755 Plus\n"); 4880 if (BGE_IS_5750_OR_BEYOND(sc)) 4881 printf(" - 5750 Plus\n"); 4882 if (BGE_IS_5705_PLUS(sc)) 4883 printf(" - 5705 Plus\n"); 4884 if (BGE_IS_5714_FAMILY(sc)) 4885 printf(" - 5714 Family\n"); 4886 if (BGE_IS_5700_FAMILY(sc)) 4887 printf(" - 5700 Family\n"); 4888 if (sc->bge_flags & BGE_IS_5788) 4889 printf(" - 5788\n"); 4890 if (sc->bge_flags & BGE_JUMBO_CAPABLE) 4891 printf(" - Supports Jumbo Frames\n"); 4892 if (sc->bge_flags & BGE_NO_EEPROM) 4893 printf(" - No EEPROM\n"); 4894 if (sc->bge_flags & BGE_PCIX) 4895 printf(" - PCI-X Bus\n"); 4896 if (sc->bge_flags & BGE_PCIE) 4897 printf(" - PCI Express Bus\n"); 4898 if (sc->bge_flags & BGE_NO_3LED) 4899 printf(" - No 3 LEDs\n"); 4900 if (sc->bge_flags & BGE_RX_ALIGNBUG) 4901 printf(" - RX Alignment Bug\n"); 4902 if (sc->bge_flags & BGE_TSO) 4903 printf(" - TSO\n"); 4904 } 4905 #endif /* BGE_DEBUG */ 4906 4907 static int 4908 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 4909 { 4910 prop_dictionary_t dict; 4911 prop_data_t ea; 4912 4913 if ((sc->bge_flags & BGE_NO_EEPROM) == 0) 4914 return 1; 4915 4916 dict = device_properties(sc->bge_dev); 4917 ea = prop_dictionary_get(dict, "mac-address"); 4918 if (ea != NULL) { 4919 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 4920 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 4921 memcpy(ether_addr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 4922 return 0; 4923 } 4924 4925 return 1; 4926 } 4927 4928 static int 4929 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 4930 { 4931 uint32_t mac_addr; 4932 4933 mac_addr = bge_readmem_ind(sc, 0x0c14); 4934 if ((mac_addr >> 16) == 0x484b) { 4935 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4936 ether_addr[1] = (uint8_t)mac_addr; 4937 mac_addr = bge_readmem_ind(sc, 0x0c18); 4938 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4939 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4940 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4941 ether_addr[5] = (uint8_t)mac_addr; 4942 return 0; 4943 } 4944 return 1; 4945 } 4946 4947 static int 4948 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 4949 { 4950 int mac_offset = BGE_EE_MAC_OFFSET; 4951 4952 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4953 mac_offset = BGE_EE_MAC_OFFSET_5906; 4954 4955 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4956 ETHER_ADDR_LEN)); 4957 } 4958 4959 static int 4960 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 4961 { 4962 4963 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4964 return 1; 4965 4966 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4967 ETHER_ADDR_LEN)); 4968 } 4969 4970 static int 4971 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 4972 { 4973 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4974 /* NOTE: Order is critical */ 4975 bge_get_eaddr_fw, 4976 bge_get_eaddr_mem, 4977 bge_get_eaddr_nvram, 4978 bge_get_eaddr_eeprom, 4979 NULL 4980 }; 4981 const bge_eaddr_fcn_t *func; 4982 4983 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4984 if ((*func)(sc, eaddr) == 0) 4985 break; 4986 } 4987 return (*func == NULL ? ENXIO : 0); 4988 } 4989