1 /* $NetBSD: if_bge.c,v 1.168 2009/09/05 14:09:55 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.13 2002/04/04 06:01:31 wpaul Exp $ 36 */ 37 38 /* 39 * Broadcom BCM570x family gigabit ethernet driver for NetBSD. 40 * 41 * NetBSD version by: 42 * 43 * Frank van der Linden <fvdl@wasabisystems.com> 44 * Jason Thorpe <thorpej@wasabisystems.com> 45 * Jonathan Stone <jonathan@dsg.stanford.edu> 46 * 47 * Originally written for FreeBSD by Bill Paul <wpaul@windriver.com> 48 * Senior Engineer, Wind River Systems 49 */ 50 51 /* 52 * The Broadcom BCM5700 is based on technology originally developed by 53 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 54 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 55 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 56 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 57 * frames, highly configurable RX filtering, and 16 RX and TX queues 58 * (which, along with RX filter rules, can be used for QOS applications). 59 * Other features, such as TCP segmentation, may be available as part 60 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 61 * firmware images can be stored in hardware and need not be compiled 62 * into the driver. 63 * 64 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 65 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 66 * 67 * The BCM5701 is a single-chip solution incorporating both the BCM5700 68 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 69 * does not support external SSRAM. 70 * 71 * Broadcom also produces a variation of the BCM5700 under the "Altima" 72 * brand name, which is functionally similar but lacks PCI-X support. 73 * 74 * Without external SSRAM, you can only have at most 4 TX rings, 75 * and the use of the mini RX ring is disabled. This seems to imply 76 * that these features are simply not available on the BCM5701. As a 77 * result, this driver does not implement any support for the mini RX 78 * ring. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.168 2009/09/05 14:09:55 tsutsui Exp $"); 83 84 #include "bpfilter.h" 85 #include "vlan.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/device.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NRND > 0 105 #include <sys/rnd.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/in_var.h> 112 #include <netinet/ip.h> 113 #endif 114 115 /* Headers for TCP Segmentation Offload (TSO) */ 116 #include <netinet/in_systm.h> /* n_time for <netinet/ip.h>... */ 117 #include <netinet/in.h> /* ip_{src,dst}, for <netinet/ip.h> */ 118 #include <netinet/ip.h> /* for struct ip */ 119 #include <netinet/tcp.h> /* for struct tcphdr */ 120 121 122 #if NBPFILTER > 0 123 #include <net/bpf.h> 124 #endif 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 #include <dev/pci/pcidevs.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 #include <dev/mii/miidevs.h> 133 #include <dev/mii/brgphyreg.h> 134 135 #include <dev/pci/if_bgereg.h> 136 #include <dev/pci/if_bgevar.h> 137 138 #include <uvm/uvm_extern.h> 139 #include <prop/proplib.h> 140 141 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 142 143 144 /* 145 * Tunable thresholds for rx-side bge interrupt mitigation. 146 */ 147 148 /* 149 * The pairs of values below were obtained from empirical measurement 150 * on bcm5700 rev B2; they ar designed to give roughly 1 receive 151 * interrupt for every N packets received, where N is, approximately, 152 * the second value (rx_max_bds) in each pair. The values are chosen 153 * such that moving from one pair to the succeeding pair was observed 154 * to roughly halve interrupt rate under sustained input packet load. 155 * The values were empirically chosen to avoid overflowing internal 156 * limits on the bcm5700: inreasing rx_ticks much beyond 600 157 * results in internal wrapping and higher interrupt rates. 158 * The limit of 46 frames was chosen to match NFS workloads. 159 * 160 * These values also work well on bcm5701, bcm5704C, and (less 161 * tested) bcm5703. On other chipsets, (including the Altima chip 162 * family), the larger values may overflow internal chip limits, 163 * leading to increasing interrupt rates rather than lower interrupt 164 * rates. 165 * 166 * Applications using heavy interrupt mitigation (interrupting every 167 * 32 or 46 frames) in both directions may need to increase the TCP 168 * windowsize to above 131072 bytes (e.g., to 199608 bytes) to sustain 169 * full link bandwidth, due to ACKs and window updates lingering 170 * in the RX queue during the 30-to-40-frame interrupt-mitigation window. 171 */ 172 static const struct bge_load_rx_thresh { 173 int rx_ticks; 174 int rx_max_bds; } 175 bge_rx_threshes[] = { 176 { 32, 2 }, 177 { 50, 4 }, 178 { 100, 8 }, 179 { 192, 16 }, 180 { 416, 32 }, 181 { 598, 46 } 182 }; 183 #define NBGE_RX_THRESH (sizeof(bge_rx_threshes) / sizeof(bge_rx_threshes[0])) 184 185 /* XXX patchable; should be sysctl'able */ 186 static int bge_auto_thresh = 1; 187 static int bge_rx_thresh_lvl; 188 189 static int bge_rxthresh_nodenum; 190 191 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, u_int8_t[]); 192 193 static int bge_probe(device_t, cfdata_t, void *); 194 static void bge_attach(device_t, device_t, void *); 195 static void bge_release_resources(struct bge_softc *); 196 static void bge_txeof(struct bge_softc *); 197 static void bge_rxeof(struct bge_softc *); 198 199 static int bge_get_eaddr_mem(struct bge_softc *, u_int8_t[]); 200 static int bge_get_eaddr_nvram(struct bge_softc *, u_int8_t[]); 201 static int bge_get_eaddr_eeprom(struct bge_softc *, u_int8_t[]); 202 static int bge_get_eaddr(struct bge_softc *, u_int8_t[]); 203 204 static void bge_tick(void *); 205 static void bge_stats_update(struct bge_softc *); 206 static int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 207 208 static int bge_intr(void *); 209 static void bge_start(struct ifnet *); 210 static int bge_ioctl(struct ifnet *, u_long, void *); 211 static int bge_init(struct ifnet *); 212 static void bge_stop(struct ifnet *, int); 213 static void bge_watchdog(struct ifnet *); 214 static int bge_ifmedia_upd(struct ifnet *); 215 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 216 217 static void bge_setmulti(struct bge_softc *); 218 219 static void bge_handle_events(struct bge_softc *); 220 static int bge_alloc_jumbo_mem(struct bge_softc *); 221 #if 0 /* XXX */ 222 static void bge_free_jumbo_mem(struct bge_softc *); 223 #endif 224 static void *bge_jalloc(struct bge_softc *); 225 static void bge_jfree(struct mbuf *, void *, size_t, void *); 226 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, 227 bus_dmamap_t); 228 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 229 static int bge_init_rx_ring_std(struct bge_softc *); 230 static void bge_free_rx_ring_std(struct bge_softc *); 231 static int bge_init_rx_ring_jumbo(struct bge_softc *); 232 static void bge_free_rx_ring_jumbo(struct bge_softc *); 233 static void bge_free_tx_ring(struct bge_softc *); 234 static int bge_init_tx_ring(struct bge_softc *); 235 236 static int bge_chipinit(struct bge_softc *); 237 static int bge_blockinit(struct bge_softc *); 238 static int bge_setpowerstate(struct bge_softc *, int); 239 240 static void bge_reset(struct bge_softc *); 241 static void bge_link_upd(struct bge_softc *); 242 243 #define BGE_DEBUG 244 #ifdef BGE_DEBUG 245 #define DPRINTF(x) if (bgedebug) printf x 246 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 247 #define BGE_TSO_PRINTF(x) do { if (bge_tso_debug) printf x ;} while (0) 248 int bgedebug = 0; 249 int bge_tso_debug = 0; 250 #else 251 #define DPRINTF(x) 252 #define DPRINTFN(n,x) 253 #define BGE_TSO_PRINTF(x) 254 #endif 255 256 #ifdef BGE_EVENT_COUNTERS 257 #define BGE_EVCNT_INCR(ev) (ev).ev_count++ 258 #define BGE_EVCNT_ADD(ev, val) (ev).ev_count += (val) 259 #define BGE_EVCNT_UPD(ev, val) (ev).ev_count = (val) 260 #else 261 #define BGE_EVCNT_INCR(ev) /* nothing */ 262 #define BGE_EVCNT_ADD(ev, val) /* nothing */ 263 #define BGE_EVCNT_UPD(ev, val) /* nothing */ 264 #endif 265 266 static const struct bge_product { 267 pci_vendor_id_t bp_vendor; 268 pci_product_id_t bp_product; 269 const char *bp_name; 270 } bge_products[] = { 271 /* 272 * The BCM5700 documentation seems to indicate that the hardware 273 * still has the Alteon vendor ID burned into it, though it 274 * should always be overridden by the value in the EEPROM. We'll 275 * check for it anyway. 276 */ 277 { PCI_VENDOR_ALTEON, 278 PCI_PRODUCT_ALTEON_BCM5700, 279 "Broadcom BCM5700 Gigabit Ethernet", 280 }, 281 { PCI_VENDOR_ALTEON, 282 PCI_PRODUCT_ALTEON_BCM5701, 283 "Broadcom BCM5701 Gigabit Ethernet", 284 }, 285 { PCI_VENDOR_ALTIMA, 286 PCI_PRODUCT_ALTIMA_AC1000, 287 "Altima AC1000 Gigabit Ethernet", 288 }, 289 { PCI_VENDOR_ALTIMA, 290 PCI_PRODUCT_ALTIMA_AC1001, 291 "Altima AC1001 Gigabit Ethernet", 292 }, 293 { PCI_VENDOR_ALTIMA, 294 PCI_PRODUCT_ALTIMA_AC9100, 295 "Altima AC9100 Gigabit Ethernet", 296 }, 297 { PCI_VENDOR_BROADCOM, 298 PCI_PRODUCT_BROADCOM_BCM5700, 299 "Broadcom BCM5700 Gigabit Ethernet", 300 }, 301 { PCI_VENDOR_BROADCOM, 302 PCI_PRODUCT_BROADCOM_BCM5701, 303 "Broadcom BCM5701 Gigabit Ethernet", 304 }, 305 { PCI_VENDOR_BROADCOM, 306 PCI_PRODUCT_BROADCOM_BCM5702, 307 "Broadcom BCM5702 Gigabit Ethernet", 308 }, 309 { PCI_VENDOR_BROADCOM, 310 PCI_PRODUCT_BROADCOM_BCM5702X, 311 "Broadcom BCM5702X Gigabit Ethernet" }, 312 { PCI_VENDOR_BROADCOM, 313 PCI_PRODUCT_BROADCOM_BCM5703, 314 "Broadcom BCM5703 Gigabit Ethernet", 315 }, 316 { PCI_VENDOR_BROADCOM, 317 PCI_PRODUCT_BROADCOM_BCM5703X, 318 "Broadcom BCM5703X Gigabit Ethernet", 319 }, 320 { PCI_VENDOR_BROADCOM, 321 PCI_PRODUCT_BROADCOM_BCM5703_ALT, 322 "Broadcom BCM5703 Gigabit Ethernet", 323 }, 324 { PCI_VENDOR_BROADCOM, 325 PCI_PRODUCT_BROADCOM_BCM5704C, 326 "Broadcom BCM5704C Dual Gigabit Ethernet", 327 }, 328 { PCI_VENDOR_BROADCOM, 329 PCI_PRODUCT_BROADCOM_BCM5704S, 330 "Broadcom BCM5704S Dual Gigabit Ethernet", 331 }, 332 { PCI_VENDOR_BROADCOM, 333 PCI_PRODUCT_BROADCOM_BCM5705, 334 "Broadcom BCM5705 Gigabit Ethernet", 335 }, 336 { PCI_VENDOR_BROADCOM, 337 PCI_PRODUCT_BROADCOM_BCM5705K, 338 "Broadcom BCM5705K Gigabit Ethernet", 339 }, 340 { PCI_VENDOR_BROADCOM, 341 PCI_PRODUCT_BROADCOM_BCM5705M, 342 "Broadcom BCM5705M Gigabit Ethernet", 343 }, 344 { PCI_VENDOR_BROADCOM, 345 PCI_PRODUCT_BROADCOM_BCM5705M_ALT, 346 "Broadcom BCM5705M Gigabit Ethernet", 347 }, 348 { PCI_VENDOR_BROADCOM, 349 PCI_PRODUCT_BROADCOM_BCM5714, 350 "Broadcom BCM5714/5715 Gigabit Ethernet", 351 }, 352 { PCI_VENDOR_BROADCOM, 353 PCI_PRODUCT_BROADCOM_BCM5715, 354 "Broadcom BCM5714/5715 Gigabit Ethernet", 355 }, 356 { PCI_VENDOR_BROADCOM, 357 PCI_PRODUCT_BROADCOM_BCM5789, 358 "Broadcom BCM5789 Gigabit Ethernet", 359 }, 360 { PCI_VENDOR_BROADCOM, 361 PCI_PRODUCT_BROADCOM_BCM5721, 362 "Broadcom BCM5721 Gigabit Ethernet", 363 }, 364 { PCI_VENDOR_BROADCOM, 365 PCI_PRODUCT_BROADCOM_BCM5722, 366 "Broadcom BCM5722 Gigabit Ethernet", 367 }, 368 { PCI_VENDOR_BROADCOM, 369 PCI_PRODUCT_BROADCOM_BCM5750, 370 "Broadcom BCM5750 Gigabit Ethernet", 371 }, 372 { PCI_VENDOR_BROADCOM, 373 PCI_PRODUCT_BROADCOM_BCM5750M, 374 "Broadcom BCM5750M Gigabit Ethernet", 375 }, 376 { PCI_VENDOR_BROADCOM, 377 PCI_PRODUCT_BROADCOM_BCM5751, 378 "Broadcom BCM5751 Gigabit Ethernet", 379 }, 380 { PCI_VENDOR_BROADCOM, 381 PCI_PRODUCT_BROADCOM_BCM5751M, 382 "Broadcom BCM5751M Gigabit Ethernet", 383 }, 384 { PCI_VENDOR_BROADCOM, 385 PCI_PRODUCT_BROADCOM_BCM5752, 386 "Broadcom BCM5752 Gigabit Ethernet", 387 }, 388 { PCI_VENDOR_BROADCOM, 389 PCI_PRODUCT_BROADCOM_BCM5752M, 390 "Broadcom BCM5752M Gigabit Ethernet", 391 }, 392 { PCI_VENDOR_BROADCOM, 393 PCI_PRODUCT_BROADCOM_BCM5753, 394 "Broadcom BCM5753 Gigabit Ethernet", 395 }, 396 { PCI_VENDOR_BROADCOM, 397 PCI_PRODUCT_BROADCOM_BCM5753M, 398 "Broadcom BCM5753M Gigabit Ethernet", 399 }, 400 { PCI_VENDOR_BROADCOM, 401 PCI_PRODUCT_BROADCOM_BCM5754, 402 "Broadcom BCM5754 Gigabit Ethernet", 403 }, 404 { PCI_VENDOR_BROADCOM, 405 PCI_PRODUCT_BROADCOM_BCM5754M, 406 "Broadcom BCM5754M Gigabit Ethernet", 407 }, 408 { PCI_VENDOR_BROADCOM, 409 PCI_PRODUCT_BROADCOM_BCM5755, 410 "Broadcom BCM5755 Gigabit Ethernet", 411 }, 412 { PCI_VENDOR_BROADCOM, 413 PCI_PRODUCT_BROADCOM_BCM5755M, 414 "Broadcom BCM5755M Gigabit Ethernet", 415 }, 416 { PCI_VENDOR_BROADCOM, 417 PCI_PRODUCT_BROADCOM_BCM5780, 418 "Broadcom BCM5780 Gigabit Ethernet", 419 }, 420 { PCI_VENDOR_BROADCOM, 421 PCI_PRODUCT_BROADCOM_BCM5780S, 422 "Broadcom BCM5780S Gigabit Ethernet", 423 }, 424 { PCI_VENDOR_BROADCOM, 425 PCI_PRODUCT_BROADCOM_BCM5782, 426 "Broadcom BCM5782 Gigabit Ethernet", 427 }, 428 { PCI_VENDOR_BROADCOM, 429 PCI_PRODUCT_BROADCOM_BCM5786, 430 "Broadcom BCM5786 Gigabit Ethernet", 431 }, 432 { PCI_VENDOR_BROADCOM, 433 PCI_PRODUCT_BROADCOM_BCM5787, 434 "Broadcom BCM5787 Gigabit Ethernet", 435 }, 436 { PCI_VENDOR_BROADCOM, 437 PCI_PRODUCT_BROADCOM_BCM5787M, 438 "Broadcom BCM5787M Gigabit Ethernet", 439 }, 440 { PCI_VENDOR_BROADCOM, 441 PCI_PRODUCT_BROADCOM_BCM5788, 442 "Broadcom BCM5788 Gigabit Ethernet", 443 }, 444 { PCI_VENDOR_BROADCOM, 445 PCI_PRODUCT_BROADCOM_BCM5789, 446 "Broadcom BCM5789 Gigabit Ethernet", 447 }, 448 { PCI_VENDOR_BROADCOM, 449 PCI_PRODUCT_BROADCOM_BCM5901, 450 "Broadcom BCM5901 Fast Ethernet", 451 }, 452 { PCI_VENDOR_BROADCOM, 453 PCI_PRODUCT_BROADCOM_BCM5901A2, 454 "Broadcom BCM5901A2 Fast Ethernet", 455 }, 456 { PCI_VENDOR_SCHNEIDERKOCH, 457 PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1, 458 "SysKonnect SK-9Dx1 Gigabit Ethernet", 459 }, 460 { PCI_VENDOR_3COM, 461 PCI_PRODUCT_3COM_3C996, 462 "3Com 3c996 Gigabit Ethernet", 463 }, 464 { PCI_VENDOR_BROADCOM, 465 PCI_PRODUCT_BROADCOM_BCM5906, 466 "Broadcom BCM5906 Fast Ethernet", 467 }, 468 { PCI_VENDOR_BROADCOM, 469 PCI_PRODUCT_BROADCOM_BCM5906M, 470 "Broadcom BCM5906M Fast Ethernet", 471 }, 472 { 0, 473 0, 474 NULL }, 475 }; 476 477 /* 478 * XXX: how to handle variants based on 5750 and derivatives: 479 * 5750 5751, 5721, possibly 5714, 5752, and 5708?, which 480 * in general behave like a 5705, except with additional quirks. 481 * This driver's current handling of the 5721 is wrong; 482 * how we map ASIC revision to "quirks" needs more thought. 483 * (defined here until the thought is done). 484 */ 485 #define BGE_IS_5714_FAMILY(sc) \ 486 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \ 487 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || \ 488 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714 ) 489 490 #define BGE_IS_5750_OR_BEYOND(sc) \ 491 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || \ 492 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || \ 493 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || \ 494 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || \ 495 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || \ 496 BGE_IS_5714_FAMILY(sc) ) 497 498 #define BGE_IS_5705_OR_BEYOND(sc) \ 499 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || \ 500 (BGE_IS_5750_OR_BEYOND(sc))) 501 502 #define BGE_IS_JUMBO_CAPABLE(sc) \ 503 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || \ 504 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || \ 505 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || \ 506 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 507 508 509 static const struct bge_revision { 510 uint32_t br_chipid; 511 const char *br_name; 512 } bge_revisions[] = { 513 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 514 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 515 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 516 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 517 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 518 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 519 /* This is treated like a BCM5700 Bx */ 520 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 521 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 522 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 523 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 524 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 525 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 526 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 527 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 528 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 529 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 530 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 531 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 532 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 533 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 534 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 535 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 536 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 537 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 538 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 539 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 540 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 541 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 542 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 543 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 544 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 545 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 546 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 547 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 548 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 549 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 550 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 551 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 552 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 553 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 554 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 555 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 556 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 557 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 558 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 559 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 560 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 561 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 562 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 563 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 564 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 565 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 566 { 0, NULL } 567 }; 568 569 /* 570 * Some defaults for major revisions, so that newer steppings 571 * that we don't know about have a shot at working. 572 */ 573 static const struct bge_revision bge_majorrevs[] = { 574 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 575 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 576 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 577 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 578 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 579 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 580 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 581 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 582 { BGE_ASICREV_BCM5752, "unknown BCM5752 family" }, 583 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 584 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 585 /* 5754 and 5787 share the same ASIC ID */ 586 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 587 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 588 { 0, NULL } 589 }; 590 591 CFATTACH_DECL_NEW(bge, sizeof(struct bge_softc), 592 bge_probe, bge_attach, NULL, NULL); 593 594 static u_int32_t 595 bge_readmem_ind(struct bge_softc *sc, int off) 596 { 597 pcireg_t val; 598 599 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 600 val = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA); 601 return val; 602 } 603 604 static void 605 bge_writemem_ind(struct bge_softc *sc, int off, int val) 606 { 607 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, off); 608 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_DATA, val); 609 } 610 611 #ifdef notdef 612 static u_int32_t 613 bge_readreg_ind(struct bge_softc *sc, int off) 614 { 615 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 616 return (pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA)); 617 } 618 #endif 619 620 static void 621 bge_writereg_ind(struct bge_softc *sc, int off, int val) 622 { 623 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_BASEADDR, off); 624 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_REG_DATA, val); 625 } 626 627 static void 628 bge_writemem_direct(struct bge_softc *sc, int off, int val) 629 { 630 CSR_WRITE_4(sc, off, val); 631 } 632 633 static void 634 bge_writembx(struct bge_softc *sc, int off, int val) 635 { 636 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 637 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 638 639 CSR_WRITE_4(sc, off, val); 640 } 641 642 static u_int8_t 643 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 644 { 645 u_int32_t access, byte = 0; 646 int i; 647 648 /* Lock. */ 649 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 650 for (i = 0; i < 8000; i++) { 651 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 652 break; 653 DELAY(20); 654 } 655 if (i == 8000) 656 return (1); 657 658 /* Enable access. */ 659 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 660 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 661 662 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 663 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 664 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 665 DELAY(10); 666 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 667 DELAY(10); 668 break; 669 } 670 } 671 672 if (i == BGE_TIMEOUT * 10) { 673 aprint_error_dev(sc->bge_dev, "nvram read timed out\n"); 674 return (1); 675 } 676 677 /* Get result. */ 678 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 679 680 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 681 682 /* Disable access. */ 683 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 684 685 /* Unlock. */ 686 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 687 CSR_READ_4(sc, BGE_NVRAM_SWARB); 688 689 return (0); 690 } 691 692 /* 693 * Read a sequence of bytes from NVRAM. 694 */ 695 static int 696 bge_read_nvram(struct bge_softc *sc, u_int8_t *dest, int off, int cnt) 697 { 698 int err = 0, i; 699 u_int8_t byte = 0; 700 701 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 702 return (1); 703 704 for (i = 0; i < cnt; i++) { 705 err = bge_nvram_getbyte(sc, off + i, &byte); 706 if (err) 707 break; 708 *(dest + i) = byte; 709 } 710 711 return (err ? 1 : 0); 712 } 713 714 /* 715 * Read a byte of data stored in the EEPROM at address 'addr.' The 716 * BCM570x supports both the traditional bitbang interface and an 717 * auto access interface for reading the EEPROM. We use the auto 718 * access method. 719 */ 720 static u_int8_t 721 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 722 { 723 int i; 724 u_int32_t byte = 0; 725 726 /* 727 * Enable use of auto EEPROM access so we can avoid 728 * having to use the bitbang method. 729 */ 730 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 731 732 /* Reset the EEPROM, load the clock period. */ 733 CSR_WRITE_4(sc, BGE_EE_ADDR, 734 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 735 DELAY(20); 736 737 /* Issue the read EEPROM command. */ 738 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 739 740 /* Wait for completion */ 741 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 742 DELAY(10); 743 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 744 break; 745 } 746 747 if (i == BGE_TIMEOUT) { 748 aprint_error_dev(sc->bge_dev, "eeprom read timed out\n"); 749 return (0); 750 } 751 752 /* Get result. */ 753 byte = CSR_READ_4(sc, BGE_EE_DATA); 754 755 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 756 757 return (0); 758 } 759 760 /* 761 * Read a sequence of bytes from the EEPROM. 762 */ 763 static int 764 bge_read_eeprom(struct bge_softc *sc, void *destv, int off, int cnt) 765 { 766 int err = 0, i; 767 u_int8_t byte = 0; 768 char *dest = destv; 769 770 for (i = 0; i < cnt; i++) { 771 err = bge_eeprom_getbyte(sc, off + i, &byte); 772 if (err) 773 break; 774 *(dest + i) = byte; 775 } 776 777 return (err ? 1 : 0); 778 } 779 780 static int 781 bge_miibus_readreg(device_t dev, int phy, int reg) 782 { 783 struct bge_softc *sc = device_private(dev); 784 u_int32_t val; 785 u_int32_t saved_autopoll; 786 int i; 787 788 /* 789 * Broadcom's own driver always assumes the internal 790 * PHY is at GMII address 1. On some chips, the PHY responds 791 * to accesses at all addresses, which could cause us to 792 * bogusly attach the PHY 32 times at probe type. Always 793 * restricting the lookup to address 1 is simpler than 794 * trying to figure out which chips revisions should be 795 * special-cased. 796 */ 797 if (phy != 1) 798 return (0); 799 800 /* Reading with autopolling on may trigger PCI errors */ 801 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 802 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 803 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 804 CSR_WRITE_4(sc, BGE_MI_MODE, 805 saved_autopoll &~ BGE_MIMODE_AUTOPOLL); 806 DELAY(40); 807 } 808 809 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 810 BGE_MIPHY(phy)|BGE_MIREG(reg)); 811 812 for (i = 0; i < BGE_TIMEOUT; i++) { 813 val = CSR_READ_4(sc, BGE_MI_COMM); 814 if (!(val & BGE_MICOMM_BUSY)) 815 break; 816 delay(10); 817 } 818 819 if (i == BGE_TIMEOUT) { 820 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 821 val = 0; 822 goto done; 823 } 824 825 val = CSR_READ_4(sc, BGE_MI_COMM); 826 827 done: 828 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 829 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 830 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 831 DELAY(40); 832 } 833 834 if (val & BGE_MICOMM_READFAIL) 835 return (0); 836 837 return (val & 0xFFFF); 838 } 839 840 static void 841 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 842 { 843 struct bge_softc *sc = device_private(dev); 844 u_int32_t saved_autopoll; 845 int i; 846 847 if (phy!=1) { 848 return; 849 } 850 851 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 852 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) { 853 return; 854 } 855 856 /* Reading with autopolling on may trigger PCI errors */ 857 saved_autopoll = CSR_READ_4(sc, BGE_MI_MODE); 858 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 859 delay(40); 860 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 861 CSR_WRITE_4(sc, BGE_MI_MODE, 862 saved_autopoll & (~BGE_MIMODE_AUTOPOLL)); 863 delay(10); /* 40 usec is supposed to be adequate */ 864 } 865 866 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 867 BGE_MIPHY(phy) | BGE_MIREG(reg)|val); 868 869 for (i = 0; i < BGE_TIMEOUT; i++) { 870 delay(10); 871 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 872 delay(5); 873 CSR_READ_4(sc, BGE_MI_COMM); 874 break; 875 } 876 } 877 878 if (saved_autopoll & BGE_MIMODE_AUTOPOLL) { 879 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 880 CSR_WRITE_4(sc, BGE_MI_MODE, saved_autopoll); 881 delay(40); 882 } 883 884 if (i == BGE_TIMEOUT) 885 aprint_error_dev(sc->bge_dev, "PHY read timed out\n"); 886 } 887 888 static void 889 bge_miibus_statchg(device_t dev) 890 { 891 struct bge_softc *sc = device_private(dev); 892 struct mii_data *mii = &sc->bge_mii; 893 894 /* 895 * Get flow control negotiation result. 896 */ 897 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 898 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 899 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 900 mii->mii_media_active &= ~IFM_ETH_FMASK; 901 } 902 903 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 904 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 905 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 906 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 907 else 908 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 909 910 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 911 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 912 else 913 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 914 915 /* 916 * 802.3x flow control 917 */ 918 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 919 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 920 else 921 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 922 923 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 924 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 925 else 926 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 927 } 928 929 /* 930 * Update rx threshold levels to values in a particular slot 931 * of the interrupt-mitigation table bge_rx_threshes. 932 */ 933 static void 934 bge_set_thresh(struct ifnet *ifp, int lvl) 935 { 936 struct bge_softc *sc = ifp->if_softc; 937 int s; 938 939 /* For now, just save the new Rx-intr thresholds and record 940 * that a threshold update is pending. Updating the hardware 941 * registers here (even at splhigh()) is observed to 942 * occasionaly cause glitches where Rx-interrupts are not 943 * honoured for up to 10 seconds. jonathan@NetBSD.org, 2003-04-05 944 */ 945 s = splnet(); 946 sc->bge_rx_coal_ticks = bge_rx_threshes[lvl].rx_ticks; 947 sc->bge_rx_max_coal_bds = bge_rx_threshes[lvl].rx_max_bds; 948 sc->bge_pending_rxintr_change = 1; 949 splx(s); 950 951 return; 952 } 953 954 955 /* 956 * Update Rx thresholds of all bge devices 957 */ 958 static void 959 bge_update_all_threshes(int lvl) 960 { 961 struct ifnet *ifp; 962 const char * const namebuf = "bge"; 963 int namelen; 964 965 if (lvl < 0) 966 lvl = 0; 967 else if( lvl >= NBGE_RX_THRESH) 968 lvl = NBGE_RX_THRESH - 1; 969 970 namelen = strlen(namebuf); 971 /* 972 * Now search all the interfaces for this name/number 973 */ 974 IFNET_FOREACH(ifp) { 975 if (strncmp(ifp->if_xname, namebuf, namelen) != 0) 976 continue; 977 /* We got a match: update if doing auto-threshold-tuning */ 978 if (bge_auto_thresh) 979 bge_set_thresh(ifp, lvl); 980 } 981 } 982 983 /* 984 * Handle events that have triggered interrupts. 985 */ 986 static void 987 bge_handle_events(struct bge_softc *sc) 988 { 989 990 return; 991 } 992 993 /* 994 * Memory management for jumbo frames. 995 */ 996 997 static int 998 bge_alloc_jumbo_mem(struct bge_softc *sc) 999 { 1000 char *ptr, *kva; 1001 bus_dma_segment_t seg; 1002 int i, rseg, state, error; 1003 struct bge_jpool_entry *entry; 1004 1005 state = error = 0; 1006 1007 /* Grab a big chunk o' storage. */ 1008 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 1009 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1010 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 1011 return ENOBUFS; 1012 } 1013 1014 state = 1; 1015 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, (void **)&kva, 1016 BUS_DMA_NOWAIT)) { 1017 aprint_error_dev(sc->bge_dev, 1018 "can't map DMA buffers (%d bytes)\n", (int)BGE_JMEM); 1019 error = ENOBUFS; 1020 goto out; 1021 } 1022 1023 state = 2; 1024 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 1025 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 1026 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 1027 error = ENOBUFS; 1028 goto out; 1029 } 1030 1031 state = 3; 1032 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1033 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1034 aprint_error_dev(sc->bge_dev, "can't load DMA map\n"); 1035 error = ENOBUFS; 1036 goto out; 1037 } 1038 1039 state = 4; 1040 sc->bge_cdata.bge_jumbo_buf = (void *)kva; 1041 DPRINTFN(1,("bge_jumbo_buf = %p\n", sc->bge_cdata.bge_jumbo_buf)); 1042 1043 SLIST_INIT(&sc->bge_jfree_listhead); 1044 SLIST_INIT(&sc->bge_jinuse_listhead); 1045 1046 /* 1047 * Now divide it up into 9K pieces and save the addresses 1048 * in an array. 1049 */ 1050 ptr = sc->bge_cdata.bge_jumbo_buf; 1051 for (i = 0; i < BGE_JSLOTS; i++) { 1052 sc->bge_cdata.bge_jslots[i] = ptr; 1053 ptr += BGE_JLEN; 1054 entry = malloc(sizeof(struct bge_jpool_entry), 1055 M_DEVBUF, M_NOWAIT); 1056 if (entry == NULL) { 1057 aprint_error_dev(sc->bge_dev, 1058 "no memory for jumbo buffer queue!\n"); 1059 error = ENOBUFS; 1060 goto out; 1061 } 1062 entry->slot = i; 1063 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 1064 entry, jpool_entries); 1065 } 1066 out: 1067 if (error != 0) { 1068 switch (state) { 1069 case 4: 1070 bus_dmamap_unload(sc->bge_dmatag, 1071 sc->bge_cdata.bge_rx_jumbo_map); 1072 case 3: 1073 bus_dmamap_destroy(sc->bge_dmatag, 1074 sc->bge_cdata.bge_rx_jumbo_map); 1075 case 2: 1076 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 1077 case 1: 1078 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1079 break; 1080 default: 1081 break; 1082 } 1083 } 1084 1085 return error; 1086 } 1087 1088 /* 1089 * Allocate a jumbo buffer. 1090 */ 1091 static void * 1092 bge_jalloc(struct bge_softc *sc) 1093 { 1094 struct bge_jpool_entry *entry; 1095 1096 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 1097 1098 if (entry == NULL) { 1099 aprint_error_dev(sc->bge_dev, "no free jumbo buffers\n"); 1100 return (NULL); 1101 } 1102 1103 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 1104 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 1105 return (sc->bge_cdata.bge_jslots[entry->slot]); 1106 } 1107 1108 /* 1109 * Release a jumbo buffer. 1110 */ 1111 static void 1112 bge_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1113 { 1114 struct bge_jpool_entry *entry; 1115 struct bge_softc *sc; 1116 int i, s; 1117 1118 /* Extract the softc struct pointer. */ 1119 sc = (struct bge_softc *)arg; 1120 1121 if (sc == NULL) 1122 panic("bge_jfree: can't find softc pointer!"); 1123 1124 /* calculate the slot this buffer belongs to */ 1125 1126 i = ((char *)buf 1127 - (char *)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 1128 1129 if ((i < 0) || (i >= BGE_JSLOTS)) 1130 panic("bge_jfree: asked to free buffer that we don't manage!"); 1131 1132 s = splvm(); 1133 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 1134 if (entry == NULL) 1135 panic("bge_jfree: buffer not in use!"); 1136 entry->slot = i; 1137 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 1138 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 1139 1140 if (__predict_true(m != NULL)) 1141 pool_cache_put(mb_cache, m); 1142 splx(s); 1143 } 1144 1145 1146 /* 1147 * Intialize a standard receive ring descriptor. 1148 */ 1149 static int 1150 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 1151 { 1152 struct mbuf *m_new = NULL; 1153 struct bge_rx_bd *r; 1154 int error; 1155 1156 if (dmamap == NULL) { 1157 error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, 1158 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap); 1159 if (error != 0) 1160 return error; 1161 } 1162 1163 sc->bge_cdata.bge_rx_std_map[i] = dmamap; 1164 1165 if (m == NULL) { 1166 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1167 if (m_new == NULL) 1168 return (ENOBUFS); 1169 1170 MCLGET(m_new, M_DONTWAIT); 1171 if (!(m_new->m_flags & M_EXT)) { 1172 m_freem(m_new); 1173 return (ENOBUFS); 1174 } 1175 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1176 1177 } else { 1178 m_new = m; 1179 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1180 m_new->m_data = m_new->m_ext.ext_buf; 1181 } 1182 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1183 m_adj(m_new, ETHER_ALIGN); 1184 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new, 1185 BUS_DMA_READ|BUS_DMA_NOWAIT)) 1186 return (ENOBUFS); 1187 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 1188 BUS_DMASYNC_PREREAD); 1189 1190 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 1191 r = &sc->bge_rdata->bge_rx_std_ring[i]; 1192 bge_set_hostaddr(&r->bge_addr, 1193 dmamap->dm_segs[0].ds_addr); 1194 r->bge_flags = BGE_RXBDFLAG_END; 1195 r->bge_len = m_new->m_len; 1196 r->bge_idx = i; 1197 1198 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1199 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1200 i * sizeof (struct bge_rx_bd), 1201 sizeof (struct bge_rx_bd), 1202 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1203 1204 return (0); 1205 } 1206 1207 /* 1208 * Initialize a jumbo receive ring descriptor. This allocates 1209 * a jumbo buffer from the pool managed internally by the driver. 1210 */ 1211 static int 1212 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 1213 { 1214 struct mbuf *m_new = NULL; 1215 struct bge_rx_bd *r; 1216 void *buf = NULL; 1217 1218 if (m == NULL) { 1219 1220 /* Allocate the mbuf. */ 1221 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1222 if (m_new == NULL) 1223 return (ENOBUFS); 1224 1225 /* Allocate the jumbo buffer */ 1226 buf = bge_jalloc(sc); 1227 if (buf == NULL) { 1228 m_freem(m_new); 1229 aprint_error_dev(sc->bge_dev, 1230 "jumbo allocation failed -- packet dropped!\n"); 1231 return (ENOBUFS); 1232 } 1233 1234 /* Attach the buffer to the mbuf. */ 1235 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1236 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, M_DEVBUF, 1237 bge_jfree, sc); 1238 m_new->m_flags |= M_EXT_RW; 1239 } else { 1240 m_new = m; 1241 buf = m_new->m_data = m_new->m_ext.ext_buf; 1242 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 1243 } 1244 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1245 m_adj(m_new, ETHER_ALIGN); 1246 bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 1247 mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN, 1248 BUS_DMASYNC_PREREAD); 1249 /* Set up the descriptor. */ 1250 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1251 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 1252 bge_set_hostaddr(&r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new)); 1253 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 1254 r->bge_len = m_new->m_len; 1255 r->bge_idx = i; 1256 1257 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1258 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1259 i * sizeof (struct bge_rx_bd), 1260 sizeof (struct bge_rx_bd), 1261 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1262 1263 return (0); 1264 } 1265 1266 /* 1267 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1268 * that's 1MB or memory, which is a lot. For now, we fill only the first 1269 * 256 ring entries and hope that our CPU is fast enough to keep up with 1270 * the NIC. 1271 */ 1272 static int 1273 bge_init_rx_ring_std(struct bge_softc *sc) 1274 { 1275 int i; 1276 1277 if (sc->bge_flags & BGE_RXRING_VALID) 1278 return 0; 1279 1280 for (i = 0; i < BGE_SSLOTS; i++) { 1281 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1282 return (ENOBUFS); 1283 } 1284 1285 sc->bge_std = i - 1; 1286 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1287 1288 sc->bge_flags |= BGE_RXRING_VALID; 1289 1290 return (0); 1291 } 1292 1293 static void 1294 bge_free_rx_ring_std(struct bge_softc *sc) 1295 { 1296 int i; 1297 1298 if (!(sc->bge_flags & BGE_RXRING_VALID)) 1299 return; 1300 1301 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1302 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1303 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1304 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1305 bus_dmamap_destroy(sc->bge_dmatag, 1306 sc->bge_cdata.bge_rx_std_map[i]); 1307 } 1308 memset((char *)&sc->bge_rdata->bge_rx_std_ring[i], 0, 1309 sizeof(struct bge_rx_bd)); 1310 } 1311 1312 sc->bge_flags &= ~BGE_RXRING_VALID; 1313 } 1314 1315 static int 1316 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1317 { 1318 int i; 1319 volatile struct bge_rcb *rcb; 1320 1321 if (sc->bge_flags & BGE_JUMBO_RXRING_VALID) 1322 return 0; 1323 1324 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1325 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1326 return (ENOBUFS); 1327 }; 1328 1329 sc->bge_jumbo = i - 1; 1330 sc->bge_flags |= BGE_JUMBO_RXRING_VALID; 1331 1332 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1333 rcb->bge_maxlen_flags = 0; 1334 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1335 1336 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1337 1338 return (0); 1339 } 1340 1341 static void 1342 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1343 { 1344 int i; 1345 1346 if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID)) 1347 return; 1348 1349 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1350 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1351 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1352 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1353 } 1354 memset((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 0, 1355 sizeof(struct bge_rx_bd)); 1356 } 1357 1358 sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID; 1359 } 1360 1361 static void 1362 bge_free_tx_ring(struct bge_softc *sc) 1363 { 1364 int i, freed; 1365 struct txdmamap_pool_entry *dma; 1366 1367 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1368 return; 1369 1370 freed = 0; 1371 1372 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1373 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1374 freed++; 1375 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1376 sc->bge_cdata.bge_tx_chain[i] = NULL; 1377 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1378 link); 1379 sc->txdma[i] = 0; 1380 } 1381 memset((char *)&sc->bge_rdata->bge_tx_ring[i], 0, 1382 sizeof(struct bge_tx_bd)); 1383 } 1384 1385 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1386 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1387 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1388 free(dma, M_DEVBUF); 1389 } 1390 1391 sc->bge_flags &= ~BGE_TXRING_VALID; 1392 } 1393 1394 static int 1395 bge_init_tx_ring(struct bge_softc *sc) 1396 { 1397 int i; 1398 bus_dmamap_t dmamap; 1399 struct txdmamap_pool_entry *dma; 1400 1401 if (sc->bge_flags & BGE_TXRING_VALID) 1402 return 0; 1403 1404 sc->bge_txcnt = 0; 1405 sc->bge_tx_saved_considx = 0; 1406 1407 /* Initialize transmit producer index for host-memory send ring. */ 1408 sc->bge_tx_prodidx = 0; 1409 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1410 /* 5700 b2 errata */ 1411 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1412 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1413 1414 /* NIC-memory send ring not used; initialize to zero. */ 1415 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1416 /* 5700 b2 errata */ 1417 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1418 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1419 1420 SLIST_INIT(&sc->txdma_list); 1421 for (i = 0; i < BGE_RSLOTS; i++) { 1422 if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX, 1423 BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT, 1424 &dmamap)) 1425 return (ENOBUFS); 1426 if (dmamap == NULL) 1427 panic("dmamap NULL in bge_init_tx_ring"); 1428 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1429 if (dma == NULL) { 1430 aprint_error_dev(sc->bge_dev, 1431 "can't alloc txdmamap_pool_entry\n"); 1432 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1433 return (ENOMEM); 1434 } 1435 dma->dmamap = dmamap; 1436 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1437 } 1438 1439 sc->bge_flags |= BGE_TXRING_VALID; 1440 1441 return (0); 1442 } 1443 1444 static void 1445 bge_setmulti(struct bge_softc *sc) 1446 { 1447 struct ethercom *ac = &sc->ethercom; 1448 struct ifnet *ifp = &ac->ec_if; 1449 struct ether_multi *enm; 1450 struct ether_multistep step; 1451 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1452 u_int32_t h; 1453 int i; 1454 1455 if (ifp->if_flags & IFF_PROMISC) 1456 goto allmulti; 1457 1458 /* Now program new ones. */ 1459 ETHER_FIRST_MULTI(step, ac, enm); 1460 while (enm != NULL) { 1461 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1462 /* 1463 * We must listen to a range of multicast addresses. 1464 * For now, just accept all multicasts, rather than 1465 * trying to set only those filter bits needed to match 1466 * the range. (At this time, the only use of address 1467 * ranges is for IP multicast routing, for which the 1468 * range is big enough to require all bits set.) 1469 */ 1470 goto allmulti; 1471 } 1472 1473 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1474 1475 /* Just want the 7 least-significant bits. */ 1476 h &= 0x7f; 1477 1478 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1479 ETHER_NEXT_MULTI(step, enm); 1480 } 1481 1482 ifp->if_flags &= ~IFF_ALLMULTI; 1483 goto setit; 1484 1485 allmulti: 1486 ifp->if_flags |= IFF_ALLMULTI; 1487 hashes[0] = hashes[1] = hashes[2] = hashes[3] = 0xffffffff; 1488 1489 setit: 1490 for (i = 0; i < 4; i++) 1491 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1492 } 1493 1494 const int bge_swapbits[] = { 1495 0, 1496 BGE_MODECTL_BYTESWAP_DATA, 1497 BGE_MODECTL_WORDSWAP_DATA, 1498 BGE_MODECTL_BYTESWAP_NONFRAME, 1499 BGE_MODECTL_WORDSWAP_NONFRAME, 1500 1501 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA, 1502 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1503 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1504 1505 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME, 1506 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_WORDSWAP_NONFRAME, 1507 1508 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1509 1510 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1511 BGE_MODECTL_BYTESWAP_NONFRAME, 1512 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1513 BGE_MODECTL_WORDSWAP_NONFRAME, 1514 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1515 BGE_MODECTL_WORDSWAP_NONFRAME, 1516 BGE_MODECTL_WORDSWAP_DATA|BGE_MODECTL_BYTESWAP_NONFRAME| 1517 BGE_MODECTL_WORDSWAP_NONFRAME, 1518 1519 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1520 BGE_MODECTL_BYTESWAP_NONFRAME|BGE_MODECTL_WORDSWAP_NONFRAME, 1521 }; 1522 1523 int bge_swapindex = 0; 1524 1525 /* 1526 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1527 * self-test results. 1528 */ 1529 static int 1530 bge_chipinit(struct bge_softc *sc) 1531 { 1532 int i; 1533 u_int32_t dma_rw_ctl; 1534 1535 1536 /* Set endianness before we access any non-PCI registers. */ 1537 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 1538 BGE_INIT); 1539 1540 /* Set power state to D0. */ 1541 bge_setpowerstate(sc, 0); 1542 1543 /* 1544 * Check the 'ROM failed' bit on the RX CPU to see if 1545 * self-tests passed. 1546 */ 1547 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1548 aprint_error_dev(sc->bge_dev, 1549 "RX CPU self-diagnostics failed!\n"); 1550 return (ENODEV); 1551 } 1552 1553 /* Clear the MAC control register */ 1554 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1555 1556 /* 1557 * Clear the MAC statistics block in the NIC's 1558 * internal memory. 1559 */ 1560 for (i = BGE_STATS_BLOCK; 1561 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1562 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1563 1564 for (i = BGE_STATUS_BLOCK; 1565 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1566 BGE_MEMWIN_WRITE(sc->sc_pc, sc->sc_pcitag, i, 0); 1567 1568 /* Set up the PCI DMA control register. */ 1569 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1570 if (sc->bge_flags & BGE_PCIE) { 1571 /* Read watermark not used, 128 bytes for write. */ 1572 DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n", 1573 device_xname(sc->bge_dev))); 1574 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1575 } else if (sc->bge_flags & BGE_PCIX){ 1576 DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n", 1577 device_xname(sc->bge_dev))); 1578 /* PCI-X bus */ 1579 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1580 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1581 (0x0F); 1582 /* 1583 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1584 * for hardware bugs, which means we should also clear 1585 * the low-order MINDMA bits. In addition, the 5704 1586 * uses a different encoding of read/write watermarks. 1587 */ 1588 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1589 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1590 /* should be 0x1f0000 */ 1591 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1592 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1593 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1594 } 1595 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703) { 1596 dma_rw_ctl &= 0xfffffff0; 1597 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1598 } 1599 else if (BGE_IS_5714_FAMILY(sc)) { 1600 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; 1601 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1602 /* XXX magic values, Broadcom-supplied Linux driver */ 1603 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1604 dma_rw_ctl |= (1 << 20) | (1 << 18) | 1605 BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1606 else 1607 dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15); 1608 } 1609 } else { 1610 /* Conventional PCI bus */ 1611 DPRINTFN(4, ("(%s: PCI 2.2 DMA setting)\n", 1612 device_xname(sc->bge_dev))); 1613 dma_rw_ctl = (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1614 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1615 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1616 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1617 dma_rw_ctl |= 0x0F; 1618 } 1619 1620 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1621 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1622 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1623 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1624 1625 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1626 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1627 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1628 1629 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1630 1631 /* 1632 * Set up general mode register. 1633 */ 1634 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1635 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1636 BGE_MODECTL_TX_NO_PHDR_CSUM | BGE_MODECTL_RX_NO_PHDR_CSUM); 1637 1638 /* 1639 * Disable memory write invalidate. Apparently it is not supported 1640 * properly by these devices. 1641 */ 1642 PCI_CLRBIT(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, PCIM_CMD_MWIEN); 1643 1644 1645 #ifdef __brokenalpha__ 1646 /* 1647 * Must insure that we do not cross an 8K (bytes) boundary 1648 * for DMA reads. Our highest limit is 1K bytes. This is a 1649 * restriction on some ALPHA platforms with early revision 1650 * 21174 PCI chipsets, such as the AlphaPC 164lx 1651 */ 1652 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1653 #endif 1654 1655 /* Set the timer prescaler (always 66MHz) */ 1656 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1657 1658 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1659 DELAY(40); /* XXX */ 1660 1661 /* Put PHY into ready state */ 1662 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1663 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1664 DELAY(40); 1665 } 1666 1667 return (0); 1668 } 1669 1670 static int 1671 bge_blockinit(struct bge_softc *sc) 1672 { 1673 volatile struct bge_rcb *rcb; 1674 bus_size_t rcb_addr; 1675 int i; 1676 struct ifnet *ifp = &sc->ethercom.ec_if; 1677 bge_hostaddr taddr; 1678 u_int32_t val; 1679 1680 /* 1681 * Initialize the memory window pointer register so that 1682 * we can access the first 32K of internal NIC RAM. This will 1683 * allow us to set up the TX send ring RCBs and the RX return 1684 * ring RCBs, plus other things which live in NIC memory. 1685 */ 1686 1687 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MEMWIN_BASEADDR, 0); 1688 1689 /* Configure mbuf memory pool */ 1690 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1691 if (sc->bge_extram) { 1692 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1693 BGE_EXT_SSRAM); 1694 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1695 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1696 else 1697 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1698 } else { 1699 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1700 BGE_BUFFPOOL_1); 1701 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1702 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1703 else 1704 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1705 } 1706 1707 /* Configure DMA resource pool */ 1708 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1709 BGE_DMA_DESCRIPTORS); 1710 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1711 } 1712 1713 /* Configure mbuf pool watermarks */ 1714 #ifdef ORIG_WPAUL_VALUES 1715 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1716 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1717 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1718 #else 1719 1720 /* new broadcom docs strongly recommend these: */ 1721 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1722 if (ifp->if_mtu > ETHER_MAX_LEN) { 1723 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1724 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1725 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1726 } else { 1727 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 304); 1728 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 152); 1729 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 380); 1730 } 1731 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1732 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1733 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1734 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1735 } else { 1736 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1737 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1738 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1739 } 1740 #endif 1741 1742 /* Configure DMA resource watermarks */ 1743 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1744 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1745 1746 /* Enable buffer manager */ 1747 if (!BGE_IS_5705_OR_BEYOND(sc)) { 1748 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1749 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1750 1751 /* Poll for buffer manager start indication */ 1752 for (i = 0; i < BGE_TIMEOUT; i++) { 1753 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1754 break; 1755 DELAY(10); 1756 } 1757 1758 if (i == BGE_TIMEOUT) { 1759 aprint_error_dev(sc->bge_dev, 1760 "buffer manager failed to start\n"); 1761 return (ENXIO); 1762 } 1763 } 1764 1765 /* Enable flow-through queues */ 1766 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1767 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1768 1769 /* Wait until queue initialization is complete */ 1770 for (i = 0; i < BGE_TIMEOUT; i++) { 1771 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1772 break; 1773 DELAY(10); 1774 } 1775 1776 if (i == BGE_TIMEOUT) { 1777 aprint_error_dev(sc->bge_dev, 1778 "flow-through queue init failed\n"); 1779 return (ENXIO); 1780 } 1781 1782 /* Initialize the standard RX ring control block */ 1783 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1784 bge_set_hostaddr(&rcb->bge_hostaddr, 1785 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1786 if (BGE_IS_5705_OR_BEYOND(sc)) 1787 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1788 else 1789 rcb->bge_maxlen_flags = 1790 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1791 if (sc->bge_extram) 1792 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1793 else 1794 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1795 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1796 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1797 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1798 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1799 1800 if (BGE_IS_5705_OR_BEYOND(sc)) 1801 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1802 else 1803 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1804 1805 /* 1806 * Initialize the jumbo RX ring control block 1807 * We set the 'ring disabled' bit in the flags 1808 * field until we're actually ready to start 1809 * using this ring (i.e. once we set the MTU 1810 * high enough to require it). 1811 */ 1812 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1813 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1814 bge_set_hostaddr(&rcb->bge_hostaddr, 1815 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1816 rcb->bge_maxlen_flags = 1817 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1818 BGE_RCB_FLAG_RING_DISABLED); 1819 if (sc->bge_extram) 1820 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1821 else 1822 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1823 1824 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1825 rcb->bge_hostaddr.bge_addr_hi); 1826 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1827 rcb->bge_hostaddr.bge_addr_lo); 1828 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1829 rcb->bge_maxlen_flags); 1830 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1831 1832 /* Set up dummy disabled mini ring RCB */ 1833 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1834 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1835 BGE_RCB_FLAG_RING_DISABLED); 1836 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1837 rcb->bge_maxlen_flags); 1838 1839 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1840 offsetof(struct bge_ring_data, bge_info), 1841 sizeof (struct bge_gib), 1842 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1843 } 1844 1845 /* 1846 * Set the BD ring replenish thresholds. The recommended 1847 * values are 1/8th the number of descriptors allocated to 1848 * each ring. 1849 */ 1850 i = BGE_STD_RX_RING_CNT / 8; 1851 1852 /* 1853 * Use a value of 8 for the following chips to workaround HW errata. 1854 * Some of these chips have been added based on empirical 1855 * evidence (they don't work unless this is done). 1856 */ 1857 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1858 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1859 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1860 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1861 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 1862 i = 8; 1863 1864 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i); 1865 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8); 1866 1867 /* 1868 * Disable all unused send rings by setting the 'ring disabled' 1869 * bit in the flags field of all the TX send ring control blocks. 1870 * These are located in NIC memory. 1871 */ 1872 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1873 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1874 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1875 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1876 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1877 rcb_addr += sizeof(struct bge_rcb); 1878 } 1879 1880 /* Configure TX RCB 0 (we use only the first ring) */ 1881 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1882 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1883 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1884 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1885 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1886 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1887 if (!(BGE_IS_5705_OR_BEYOND(sc))) 1888 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1889 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1890 1891 /* Disable all unused RX return rings */ 1892 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1893 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1894 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1895 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1896 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1897 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1898 BGE_RCB_FLAG_RING_DISABLED)); 1899 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1900 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1901 (i * (sizeof(u_int64_t))), 0); 1902 rcb_addr += sizeof(struct bge_rcb); 1903 } 1904 1905 /* Initialize RX ring indexes */ 1906 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1907 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1908 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1909 1910 /* 1911 * Set up RX return ring 0 1912 * Note that the NIC address for RX return rings is 0x00000000. 1913 * The return rings live entirely within the host, so the 1914 * nicaddr field in the RCB isn't used. 1915 */ 1916 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1917 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1918 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1919 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1920 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1921 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1922 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1923 1924 /* Set random backoff seed for TX */ 1925 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1926 CLLADDR(ifp->if_sadl)[0] + CLLADDR(ifp->if_sadl)[1] + 1927 CLLADDR(ifp->if_sadl)[2] + CLLADDR(ifp->if_sadl)[3] + 1928 CLLADDR(ifp->if_sadl)[4] + CLLADDR(ifp->if_sadl)[5] + 1929 BGE_TX_BACKOFF_SEED_MASK); 1930 1931 /* Set inter-packet gap */ 1932 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1933 1934 /* 1935 * Specify which ring to use for packets that don't match 1936 * any RX rules. 1937 */ 1938 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1939 1940 /* 1941 * Configure number of RX lists. One interrupt distribution 1942 * list, sixteen active lists, one bad frames class. 1943 */ 1944 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1945 1946 /* Inialize RX list placement stats mask. */ 1947 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1948 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1949 1950 /* Disable host coalescing until we get it set up */ 1951 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1952 1953 /* Poll to make sure it's shut down. */ 1954 for (i = 0; i < BGE_TIMEOUT; i++) { 1955 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1956 break; 1957 DELAY(10); 1958 } 1959 1960 if (i == BGE_TIMEOUT) { 1961 aprint_error_dev(sc->bge_dev, 1962 "host coalescing engine failed to idle\n"); 1963 return (ENXIO); 1964 } 1965 1966 /* Set up host coalescing defaults */ 1967 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1968 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1969 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1970 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1971 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1972 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1973 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1974 } 1975 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1976 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1977 1978 /* Set up address of statistics block */ 1979 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 1980 bge_set_hostaddr(&taddr, 1981 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1982 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1983 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1984 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 1985 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 1986 } 1987 1988 /* Set up address of status block */ 1989 bge_set_hostaddr(&taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1990 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1991 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1992 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1993 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1994 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1995 1996 /* Turn on host coalescing state machine */ 1997 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1998 1999 /* Turn on RX BD completion state machine and enable attentions */ 2000 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2001 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2002 2003 /* Turn on RX list placement state machine */ 2004 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2005 2006 /* Turn on RX list selector state machine. */ 2007 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2008 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2009 2010 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2011 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2012 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2013 BGE_MACMODE_FRMHDR_DMA_ENB; 2014 2015 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 2016 val |= BGE_PORTMODE_TBI; 2017 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 2018 val |= BGE_PORTMODE_GMII; 2019 else 2020 val |= BGE_PORTMODE_MII; 2021 2022 /* Turn on DMA, clear stats */ 2023 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2024 2025 2026 /* Set misc. local control, enable interrupts on attentions */ 2027 sc->bge_local_ctrl_reg = BGE_MLC_INTR_ONATTN | BGE_MLC_AUTO_EEPROM; 2028 2029 #ifdef notdef 2030 /* Assert GPIO pins for PHY reset */ 2031 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2032 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2033 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2034 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2035 #endif 2036 2037 #if defined(not_quite_yet) 2038 /* Linux driver enables enable gpio pin #1 on 5700s */ 2039 if (sc->bge_chipid == BGE_CHIPID_BCM5700) { 2040 sc->bge_local_ctrl_reg |= 2041 (BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUTEN1); 2042 } 2043 #endif 2044 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2045 2046 /* Turn on DMA completion state machine */ 2047 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2048 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2049 2050 /* Turn on write DMA state machine */ 2051 { 2052 uint32_t bge_wdma_mode = 2053 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2054 2055 /* Enable host coalescing bug fix; see Linux tg3.c */ 2056 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2057 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2058 bge_wdma_mode |= (1 << 29); 2059 2060 CSR_WRITE_4(sc, BGE_WDMA_MODE, bge_wdma_mode); 2061 } 2062 2063 /* Turn on read DMA state machine */ 2064 { 2065 uint32_t dma_read_modebits; 2066 2067 dma_read_modebits = 2068 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2069 2070 if ((sc->bge_flags & BGE_PCIE) && 0) { 2071 dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST; 2072 } else if (BGE_IS_5705_OR_BEYOND(sc)) { 2073 dma_read_modebits |= BGE_RDMA_MODE_FIFO_SIZE_128; 2074 } 2075 2076 /* XXX broadcom-supplied linux driver; undocumented */ 2077 if (BGE_IS_5750_OR_BEYOND(sc)) { 2078 /* 2079 * XXX: magic values. 2080 * From Broadcom-supplied Linux driver; apparently 2081 * required to workaround a DMA bug affecting TSO 2082 * on bcm575x/bcm5721? 2083 */ 2084 dma_read_modebits |= (1 << 27); 2085 } 2086 CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits); 2087 } 2088 2089 /* Turn on RX data completion state machine */ 2090 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2091 2092 /* Turn on RX BD initiator state machine */ 2093 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2094 2095 /* Turn on RX data and RX BD initiator state machine */ 2096 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2097 2098 /* Turn on Mbuf cluster free state machine */ 2099 if (!(BGE_IS_5705_OR_BEYOND(sc))) 2100 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2101 2102 /* Turn on send BD completion state machine */ 2103 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2104 2105 /* Turn on send data completion state machine */ 2106 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2107 2108 /* Turn on send data initiator state machine */ 2109 if (BGE_IS_5750_OR_BEYOND(sc)) { 2110 /* XXX: magic value from Linux driver */ 2111 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 2112 } else { 2113 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2114 } 2115 2116 /* Turn on send BD initiator state machine */ 2117 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2118 2119 /* Turn on send BD selector state machine */ 2120 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2121 2122 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2123 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2124 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2125 2126 /* ack/clear link change events */ 2127 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2128 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2129 BGE_MACSTAT_CFG_CHANGED); 2130 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2131 2132 /* Enable PHY auto polling (for MII/GMII only) */ 2133 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2134 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2135 } else { 2136 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2137 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 2138 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2139 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2140 BGE_EVTENB_MI_INTERRUPT); 2141 } 2142 2143 /* 2144 * Clear any pending link state attention. 2145 * Otherwise some link state change events may be lost until attention 2146 * is cleared by bge_intr() -> bge_link_upd() sequence. 2147 * It's not necessary on newer BCM chips - perhaps enabling link 2148 * state change attentions implies clearing pending attention. 2149 */ 2150 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2151 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2152 BGE_MACSTAT_LINK_CHANGED); 2153 2154 /* Enable link state change attentions. */ 2155 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2156 2157 return (0); 2158 } 2159 2160 static const struct bge_revision * 2161 bge_lookup_rev(uint32_t chipid) 2162 { 2163 const struct bge_revision *br; 2164 2165 for (br = bge_revisions; br->br_name != NULL; br++) { 2166 if (br->br_chipid == chipid) 2167 return (br); 2168 } 2169 2170 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2171 if (br->br_chipid == BGE_ASICREV(chipid)) 2172 return (br); 2173 } 2174 2175 return (NULL); 2176 } 2177 2178 static const struct bge_product * 2179 bge_lookup(const struct pci_attach_args *pa) 2180 { 2181 const struct bge_product *bp; 2182 2183 for (bp = bge_products; bp->bp_name != NULL; bp++) { 2184 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 2185 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 2186 return (bp); 2187 } 2188 2189 return (NULL); 2190 } 2191 2192 static int 2193 bge_setpowerstate(struct bge_softc *sc, int powerlevel) 2194 { 2195 #ifdef NOTYET 2196 u_int32_t pm_ctl = 0; 2197 2198 /* XXX FIXME: make sure indirect accesses enabled? */ 2199 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_MISC_CTL, 4); 2200 pm_ctl |= BGE_PCIMISCCTL_INDIRECT_ACCESS; 2201 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, pm_ctl, 4); 2202 2203 /* clear the PME_assert bit and power state bits, enable PME */ 2204 pm_ctl = pci_conf_read(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2); 2205 pm_ctl &= ~PCIM_PSTAT_DMASK; 2206 pm_ctl |= (1 << 8); 2207 2208 if (powerlevel == 0) { 2209 pm_ctl |= PCIM_PSTAT_D0; 2210 pci_write_config(sc->bge_dev, BGE_PCI_PWRMGMT_CMD, 2211 pm_ctl, 2); 2212 DELAY(10000); 2213 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg); 2214 DELAY(10000); 2215 2216 #ifdef NOTYET 2217 /* XXX FIXME: write 0x02 to phy aux_Ctrl reg */ 2218 bge_miibus_writereg(sc->bge_dev, 1, 0x18, 0x02); 2219 #endif 2220 DELAY(40); DELAY(40); DELAY(40); 2221 DELAY(10000); /* above not quite adequate on 5700 */ 2222 return 0; 2223 } 2224 2225 2226 /* 2227 * Entering ACPI power states D1-D3 is achieved by wiggling 2228 * GMII gpio pins. Example code assumes all hardware vendors 2229 * followed Broadom's sample pcb layout. Until we verify that 2230 * for all supported OEM cards, states D1-D3 are unsupported. 2231 */ 2232 aprint_error_dev(sc->bge_dev, 2233 "power state %d unimplemented; check GPIO pins\n", 2234 powerlevel); 2235 #endif 2236 return EOPNOTSUPP; 2237 } 2238 2239 2240 /* 2241 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2242 * against our list and return its name if we find a match. Note 2243 * that since the Broadcom controller contains VPD support, we 2244 * can get the device name string from the controller itself instead 2245 * of the compiled-in string. This is a little slow, but it guarantees 2246 * we'll always announce the right product name. 2247 */ 2248 static int 2249 bge_probe(device_t parent, cfdata_t match, void *aux) 2250 { 2251 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 2252 2253 if (bge_lookup(pa) != NULL) 2254 return (1); 2255 2256 return (0); 2257 } 2258 2259 static void 2260 bge_attach(device_t parent, device_t self, void *aux) 2261 { 2262 struct bge_softc *sc = device_private(self); 2263 struct pci_attach_args *pa = aux; 2264 prop_dictionary_t dict; 2265 const struct bge_product *bp; 2266 const struct bge_revision *br; 2267 pci_chipset_tag_t pc; 2268 pci_intr_handle_t ih; 2269 const char *intrstr = NULL; 2270 bus_dma_segment_t seg; 2271 int rseg; 2272 u_int32_t hwcfg = 0; 2273 u_int32_t command; 2274 struct ifnet *ifp; 2275 u_int32_t misccfg; 2276 void * kva; 2277 u_char eaddr[ETHER_ADDR_LEN]; 2278 pcireg_t memtype; 2279 bus_addr_t memaddr; 2280 bus_size_t memsize; 2281 u_int32_t pm_ctl; 2282 2283 bp = bge_lookup(pa); 2284 KASSERT(bp != NULL); 2285 2286 sc->sc_pc = pa->pa_pc; 2287 sc->sc_pcitag = pa->pa_tag; 2288 sc->bge_dev = self; 2289 2290 aprint_naive(": Ethernet controller\n"); 2291 aprint_normal(": %s\n", bp->bp_name); 2292 2293 /* 2294 * Map control/status registers. 2295 */ 2296 DPRINTFN(5, ("Map control/status regs\n")); 2297 pc = sc->sc_pc; 2298 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2299 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 2300 pci_conf_write(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, command); 2301 command = pci_conf_read(pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 2302 2303 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 2304 aprint_error_dev(sc->bge_dev, 2305 "failed to enable memory mapping!\n"); 2306 return; 2307 } 2308 2309 DPRINTFN(5, ("pci_mem_find\n")); 2310 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_pcitag, BGE_PCI_BAR0); 2311 switch (memtype) { 2312 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 2313 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 2314 if (pci_mapreg_map(pa, BGE_PCI_BAR0, 2315 memtype, 0, &sc->bge_btag, &sc->bge_bhandle, 2316 &memaddr, &memsize) == 0) 2317 break; 2318 default: 2319 aprint_error_dev(sc->bge_dev, "can't find mem space\n"); 2320 return; 2321 } 2322 2323 DPRINTFN(5, ("pci_intr_map\n")); 2324 if (pci_intr_map(pa, &ih)) { 2325 aprint_error_dev(sc->bge_dev, "couldn't map interrupt\n"); 2326 return; 2327 } 2328 2329 DPRINTFN(5, ("pci_intr_string\n")); 2330 intrstr = pci_intr_string(pc, ih); 2331 2332 DPRINTFN(5, ("pci_intr_establish\n")); 2333 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc); 2334 2335 if (sc->bge_intrhand == NULL) { 2336 aprint_error_dev(sc->bge_dev, 2337 "couldn't establish interrupt%s%s\n", 2338 intrstr ? " at " : "", intrstr ? intrstr : ""); 2339 return; 2340 } 2341 aprint_normal_dev(sc->bge_dev, "interrupting at %s\n", intrstr); 2342 2343 /* 2344 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2345 * can clobber the chip's PCI config-space power control registers, 2346 * leaving the card in D3 powersave state. 2347 * We do not have memory-mapped registers in this state, 2348 * so force device into D0 state before starting initialization. 2349 */ 2350 pm_ctl = pci_conf_read(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD); 2351 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2352 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2353 pci_conf_write(pc, sc->sc_pcitag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2354 DELAY(1000); /* 27 usec is allegedly sufficent */ 2355 2356 /* 2357 * Save ASIC rev. 2358 */ 2359 sc->bge_chipid = 2360 pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL) & 2361 BGE_PCIMISCCTL_ASICREV; 2362 2363 /* 2364 * Detect PCI-Express devices 2365 * XXX: guessed from Linux/FreeBSD; no documentation 2366 */ 2367 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PCIEXPRESS, 2368 NULL, NULL) != 0) 2369 sc->bge_flags |= BGE_PCIE; 2370 2371 /* 2372 * PCI-X check. 2373 */ 2374 if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) & 2375 BGE_PCISTATE_PCI_BUSMODE) == 0) 2376 sc->bge_flags |= BGE_PCIX; 2377 2378 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2379 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2380 sc->bge_flags |= BGE_PHY_CRC_BUG; 2381 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2382 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2383 sc->bge_flags |= BGE_PHY_ADC_BUG; 2384 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2385 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2386 2387 if (BGE_IS_5705_OR_BEYOND(sc)) { 2388 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2389 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2390 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2391 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2392 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2393 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2394 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2395 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 2396 sc->bge_flags |= BGE_PHY_BER_BUG; 2397 } 2398 2399 /* Try to reset the chip. */ 2400 DPRINTFN(5, ("bge_reset\n")); 2401 bge_reset(sc); 2402 2403 if (bge_chipinit(sc)) { 2404 aprint_error_dev(sc->bge_dev, "chip initialization failed\n"); 2405 bge_release_resources(sc); 2406 return; 2407 } 2408 2409 /* 2410 * Get station address from the EEPROM. 2411 */ 2412 if (bge_get_eaddr(sc, eaddr)) { 2413 aprint_error_dev(sc->bge_dev, 2414 "failed to reade station address\n"); 2415 bge_release_resources(sc); 2416 return; 2417 } 2418 2419 br = bge_lookup_rev(sc->bge_chipid); 2420 2421 if (br == NULL) { 2422 aprint_normal_dev(sc->bge_dev, "unknown ASIC (0x%04x)", 2423 sc->bge_chipid >> 16); 2424 } else { 2425 aprint_normal_dev(sc->bge_dev, "ASIC %s (0x%04x)", 2426 br->br_name, sc->bge_chipid >> 16); 2427 } 2428 aprint_normal(", Ethernet address %s\n", ether_sprintf(eaddr)); 2429 2430 /* Allocate the general information block and ring buffers. */ 2431 if (pci_dma64_available(pa)) 2432 sc->bge_dmatag = pa->pa_dmat64; 2433 else 2434 sc->bge_dmatag = pa->pa_dmat; 2435 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2436 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2437 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2438 aprint_error_dev(sc->bge_dev, "can't alloc rx buffers\n"); 2439 return; 2440 } 2441 DPRINTFN(5, ("bus_dmamem_map\n")); 2442 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2443 sizeof(struct bge_ring_data), &kva, 2444 BUS_DMA_NOWAIT)) { 2445 aprint_error_dev(sc->bge_dev, 2446 "can't map DMA buffers (%zu bytes)\n", 2447 sizeof(struct bge_ring_data)); 2448 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2449 return; 2450 } 2451 DPRINTFN(5, ("bus_dmamem_create\n")); 2452 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2453 sizeof(struct bge_ring_data), 0, 2454 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2455 aprint_error_dev(sc->bge_dev, "can't create DMA map\n"); 2456 bus_dmamem_unmap(sc->bge_dmatag, kva, 2457 sizeof(struct bge_ring_data)); 2458 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2459 return; 2460 } 2461 DPRINTFN(5, ("bus_dmamem_load\n")); 2462 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2463 sizeof(struct bge_ring_data), NULL, 2464 BUS_DMA_NOWAIT)) { 2465 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2466 bus_dmamem_unmap(sc->bge_dmatag, kva, 2467 sizeof(struct bge_ring_data)); 2468 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2469 return; 2470 } 2471 2472 DPRINTFN(5, ("bzero\n")); 2473 sc->bge_rdata = (struct bge_ring_data *)kva; 2474 2475 memset(sc->bge_rdata, 0, sizeof(struct bge_ring_data)); 2476 2477 /* Try to allocate memory for jumbo buffers. */ 2478 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2479 if (bge_alloc_jumbo_mem(sc)) { 2480 aprint_error_dev(sc->bge_dev, 2481 "jumbo buffer allocation failed\n"); 2482 } else 2483 sc->ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2484 } 2485 2486 /* Set default tuneable values. */ 2487 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2488 sc->bge_rx_coal_ticks = 150; 2489 sc->bge_rx_max_coal_bds = 64; 2490 #ifdef ORIG_WPAUL_VALUES 2491 sc->bge_tx_coal_ticks = 150; 2492 sc->bge_tx_max_coal_bds = 128; 2493 #else 2494 sc->bge_tx_coal_ticks = 300; 2495 sc->bge_tx_max_coal_bds = 400; 2496 #endif 2497 if (BGE_IS_5705_OR_BEYOND(sc)) { 2498 sc->bge_tx_coal_ticks = (12 * 5); 2499 sc->bge_tx_max_coal_bds = (12 * 5); 2500 aprint_verbose_dev(sc->bge_dev, 2501 "setting short Tx thresholds\n"); 2502 } 2503 2504 /* Set up ifnet structure */ 2505 ifp = &sc->ethercom.ec_if; 2506 ifp->if_softc = sc; 2507 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2508 ifp->if_ioctl = bge_ioctl; 2509 ifp->if_stop = bge_stop; 2510 ifp->if_start = bge_start; 2511 ifp->if_init = bge_init; 2512 ifp->if_watchdog = bge_watchdog; 2513 IFQ_SET_MAXLEN(&ifp->if_snd, max(BGE_TX_RING_CNT - 1, IFQ_MAXLEN)); 2514 IFQ_SET_READY(&ifp->if_snd); 2515 DPRINTFN(5, ("strcpy if_xname\n")); 2516 strcpy(ifp->if_xname, device_xname(sc->bge_dev)); 2517 2518 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2519 sc->ethercom.ec_if.if_capabilities |= 2520 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2521 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2522 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2523 sc->ethercom.ec_capabilities |= 2524 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_VLAN_MTU; 2525 2526 if (sc->bge_flags & BGE_PCIE) 2527 sc->ethercom.ec_if.if_capabilities |= IFCAP_TSOv4; 2528 2529 /* 2530 * Do MII setup. 2531 */ 2532 DPRINTFN(5, ("mii setup\n")); 2533 sc->bge_mii.mii_ifp = ifp; 2534 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2535 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2536 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2537 2538 /* 2539 * Figure out what sort of media we have by checking the 2540 * hardware config word in the first 32k of NIC internal memory, 2541 * or fall back to the config word in the EEPROM. Note: on some BCM5700 2542 * cards, this value appears to be unset. If that's the 2543 * case, we have to rely on identifying the NIC by its PCI 2544 * subsystem ID, as we do below for the SysKonnect SK-9D41. 2545 */ 2546 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) { 2547 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2548 } else { 2549 bge_read_eeprom(sc, (void *)&hwcfg, 2550 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2551 hwcfg = be32toh(hwcfg); 2552 } 2553 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2554 if (PCI_PRODUCT(pa->pa_id) == SK_SUBSYSID_9D41 || 2555 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2556 if (BGE_IS_5714_FAMILY(sc)) 2557 sc->bge_flags |= BGE_PHY_FIBER_MII; 2558 else 2559 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2560 } 2561 2562 /* set phyflags before mii_attach() */ 2563 dict = device_properties(self); 2564 prop_dictionary_set_uint32(dict, "phyflags", sc->bge_flags); 2565 2566 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2567 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2568 bge_ifmedia_sts); 2569 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2570 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2571 0, NULL); 2572 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2573 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2574 /* Pretend the user requested this setting */ 2575 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2576 } else { 2577 /* 2578 * Do transceiver setup. 2579 */ 2580 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2581 bge_ifmedia_sts); 2582 mii_attach(sc->bge_dev, &sc->bge_mii, 0xffffffff, 2583 MII_PHY_ANY, MII_OFFSET_ANY, 2584 MIIF_FORCEANEG|MIIF_DOPAUSE); 2585 2586 if (LIST_EMPTY(&sc->bge_mii.mii_phys)) { 2587 aprint_error_dev(sc->bge_dev, "no PHY found!\n"); 2588 ifmedia_add(&sc->bge_mii.mii_media, 2589 IFM_ETHER|IFM_MANUAL, 0, NULL); 2590 ifmedia_set(&sc->bge_mii.mii_media, 2591 IFM_ETHER|IFM_MANUAL); 2592 } else 2593 ifmedia_set(&sc->bge_mii.mii_media, 2594 IFM_ETHER|IFM_AUTO); 2595 } 2596 2597 /* 2598 * When using the BCM5701 in PCI-X mode, data corruption has 2599 * been observed in the first few bytes of some received packets. 2600 * Aligning the packet buffer in memory eliminates the corruption. 2601 * Unfortunately, this misaligns the packet payloads. On platforms 2602 * which do not support unaligned accesses, we will realign the 2603 * payloads by copying the received packets. 2604 */ 2605 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2606 sc->bge_flags & BGE_PCIX) 2607 sc->bge_flags |= BGE_RX_ALIGNBUG; 2608 2609 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2610 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2611 2612 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2613 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2614 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2615 sc->bge_flags |= BGE_IS_5788; 2616 2617 /* 2618 * Call MI attach routine. 2619 */ 2620 DPRINTFN(5, ("if_attach\n")); 2621 if_attach(ifp); 2622 DPRINTFN(5, ("ether_ifattach\n")); 2623 ether_ifattach(ifp, eaddr); 2624 #if NRND > 0 2625 rnd_attach_source(&sc->rnd_source, device_xname(sc->bge_dev), 2626 RND_TYPE_NET, 0); 2627 #endif 2628 #ifdef BGE_EVENT_COUNTERS 2629 /* 2630 * Attach event counters. 2631 */ 2632 evcnt_attach_dynamic(&sc->bge_ev_intr, EVCNT_TYPE_INTR, 2633 NULL, device_xname(sc->bge_dev), "intr"); 2634 evcnt_attach_dynamic(&sc->bge_ev_tx_xoff, EVCNT_TYPE_MISC, 2635 NULL, device_xname(sc->bge_dev), "tx_xoff"); 2636 evcnt_attach_dynamic(&sc->bge_ev_tx_xon, EVCNT_TYPE_MISC, 2637 NULL, device_xname(sc->bge_dev), "tx_xon"); 2638 evcnt_attach_dynamic(&sc->bge_ev_rx_xoff, EVCNT_TYPE_MISC, 2639 NULL, device_xname(sc->bge_dev), "rx_xoff"); 2640 evcnt_attach_dynamic(&sc->bge_ev_rx_xon, EVCNT_TYPE_MISC, 2641 NULL, device_xname(sc->bge_dev), "rx_xon"); 2642 evcnt_attach_dynamic(&sc->bge_ev_rx_macctl, EVCNT_TYPE_MISC, 2643 NULL, device_xname(sc->bge_dev), "rx_macctl"); 2644 evcnt_attach_dynamic(&sc->bge_ev_xoffentered, EVCNT_TYPE_MISC, 2645 NULL, device_xname(sc->bge_dev), "xoffentered"); 2646 #endif /* BGE_EVENT_COUNTERS */ 2647 DPRINTFN(5, ("callout_init\n")); 2648 callout_init(&sc->bge_timeout, 0); 2649 2650 if (pmf_device_register(self, NULL, NULL)) 2651 pmf_class_network_register(self, ifp); 2652 else 2653 aprint_error_dev(self, "couldn't establish power handler\n"); 2654 } 2655 2656 static void 2657 bge_release_resources(struct bge_softc *sc) 2658 { 2659 if (sc->bge_vpd_prodname != NULL) 2660 free(sc->bge_vpd_prodname, M_DEVBUF); 2661 2662 if (sc->bge_vpd_readonly != NULL) 2663 free(sc->bge_vpd_readonly, M_DEVBUF); 2664 } 2665 2666 static void 2667 bge_reset(struct bge_softc *sc) 2668 { 2669 u_int32_t cachesize, command, pcistate, new_pcistate; 2670 int i, val; 2671 void (*write_op)(struct bge_softc *, int, int); 2672 2673 if (BGE_IS_5750_OR_BEYOND(sc) && !BGE_IS_5714_FAMILY(sc) && 2674 (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)) { 2675 if (sc->bge_flags & BGE_PCIE) { 2676 write_op = bge_writemem_direct; 2677 } else { 2678 write_op = bge_writemem_ind; 2679 } 2680 } else { 2681 write_op = bge_writereg_ind; 2682 } 2683 2684 2685 /* Save some important PCI state. */ 2686 cachesize = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ); 2687 command = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD); 2688 pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE); 2689 2690 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2691 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2692 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2693 2694 /* Disable fastboot on controllers that support it. */ 2695 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2696 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2697 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) 2698 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2699 2700 val = BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1); 2701 /* 2702 * XXX: from FreeBSD/Linux; no documentation 2703 */ 2704 if (sc->bge_flags & BGE_PCIE) { 2705 if (CSR_READ_4(sc, BGE_PCIE_CTL1) == 0x60) 2706 /* PCI Express 1.0 system */ 2707 CSR_WRITE_4(sc, BGE_PCIE_CTL1, 0x20); 2708 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2709 /* 2710 * Prevent PCI Express link training 2711 * during global reset. 2712 */ 2713 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2714 val |= (1<<29); 2715 } 2716 } 2717 2718 /* 2719 * Set GPHY Power Down Override to leave GPHY 2720 * powered up in D0 uninitialized. 2721 */ 2722 if (BGE_IS_5705_OR_BEYOND(sc)) 2723 val |= BGE_MISCCFG_KEEP_GPHY_POWER; 2724 2725 /* Issue global reset */ 2726 write_op(sc, BGE_MISC_CFG, val); 2727 2728 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2729 i = CSR_READ_4(sc, BGE_VCPU_STATUS); 2730 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2731 i | BGE_VCPU_STATUS_DRV_RESET); 2732 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2733 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2734 i & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2735 } 2736 2737 DELAY(1000); 2738 2739 /* 2740 * XXX: from FreeBSD/Linux; no documentation 2741 */ 2742 if (sc->bge_flags & BGE_PCIE) { 2743 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2744 pcireg_t reg; 2745 2746 DELAY(500000); 2747 /* XXX: Magic Numbers */ 2748 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0); 2749 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_UNKNOWN0, 2750 reg | (1 << 15)); 2751 } 2752 /* 2753 * XXX: Magic Numbers. 2754 * Sets maximal PCI-e payload and clears any PCI-e errors. 2755 * Should be replaced with references to PCI config-space 2756 * capability block for PCI-Express. 2757 */ 2758 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 2759 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2760 2761 } 2762 2763 /* Reset some of the PCI state that got zapped by reset */ 2764 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_MISC_CTL, 2765 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2766 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW); 2767 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD, command); 2768 pci_conf_write(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CACHESZ, cachesize); 2769 write_op(sc, BGE_MISC_CFG, (65 << 1)); 2770 2771 /* Enable memory arbiter. */ 2772 { 2773 uint32_t marbmode = 0; 2774 if (BGE_IS_5714_FAMILY(sc)) { 2775 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2776 } 2777 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2778 } 2779 2780 2781 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2782 for (i = 0; i < BGE_TIMEOUT; i++) { 2783 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2784 if (val & BGE_VCPU_STATUS_INIT_DONE) 2785 break; 2786 DELAY(100); 2787 } 2788 if (i == BGE_TIMEOUT) { 2789 aprint_error_dev(sc->bge_dev, "reset timed out\n"); 2790 return; 2791 } 2792 } else { 2793 /* 2794 * Write the magic number to the firmware mailbox at 0xb50 2795 * so that the driver can synchronize with the firmware. 2796 */ 2797 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2798 2799 /* 2800 * Poll the value location we just wrote until 2801 * we see the 1's complement of the magic number. 2802 * This indicates that the firmware initialization 2803 * is complete. 2804 */ 2805 for (i = 0; i < BGE_TIMEOUT; i++) { 2806 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2807 if (val == ~BGE_MAGIC_NUMBER) 2808 break; 2809 DELAY(1000); 2810 } 2811 2812 if (i >= BGE_TIMEOUT) { 2813 aprint_error_dev(sc->bge_dev, 2814 "firmware handshake timed out, val = %x\n", val); 2815 /* 2816 * XXX: occasionally fired on bcm5721, but without 2817 * apparent harm. For now, keep going if we timeout 2818 * against PCI-E devices. 2819 */ 2820 if ((sc->bge_flags & BGE_PCIE) == 0) 2821 return; 2822 } 2823 } 2824 2825 /* 2826 * XXX Wait for the value of the PCISTATE register to 2827 * return to its original pre-reset state. This is a 2828 * fairly good indicator of reset completion. If we don't 2829 * wait for the reset to fully complete, trying to read 2830 * from the device's non-PCI registers may yield garbage 2831 * results. 2832 */ 2833 for (i = 0; i < 10000; i++) { 2834 new_pcistate = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 2835 BGE_PCI_PCISTATE); 2836 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2837 (pcistate & ~BGE_PCISTATE_RESERVED)) 2838 break; 2839 DELAY(10); 2840 } 2841 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2842 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2843 aprint_error_dev(sc->bge_dev, "pcistate failed to revert\n"); 2844 } 2845 2846 /* Enable memory arbiter. */ 2847 /* XXX why do this twice? */ 2848 { 2849 uint32_t marbmode = 0; 2850 if (BGE_IS_5714_FAMILY(sc)) { 2851 marbmode = CSR_READ_4(sc, BGE_MARB_MODE); 2852 } 2853 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | marbmode); 2854 } 2855 2856 /* Fix up byte swapping */ 2857 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2858 2859 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2860 2861 /* 2862 * The 5704 in TBI mode apparently needs some special 2863 * adjustment to insure the SERDES drive level is set 2864 * to 1.2V. 2865 */ 2866 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 2867 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2868 u_int32_t serdescfg; 2869 2870 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2871 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2872 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2873 } 2874 2875 /* XXX: from FreeBSD/Linux; no documentation */ 2876 if (sc->bge_flags & BGE_PCIE && 2877 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) 2878 CSR_WRITE_4(sc, BGE_PCIE_CTL0, CSR_READ_4(sc, BGE_PCIE_CTL0) | (1<<25)); 2879 DELAY(10000); 2880 } 2881 2882 /* 2883 * Frame reception handling. This is called if there's a frame 2884 * on the receive return list. 2885 * 2886 * Note: we have to be able to handle two possibilities here: 2887 * 1) the frame is from the jumbo recieve ring 2888 * 2) the frame is from the standard receive ring 2889 */ 2890 2891 static void 2892 bge_rxeof(struct bge_softc *sc) 2893 { 2894 struct ifnet *ifp; 2895 int stdcnt = 0, jumbocnt = 0; 2896 bus_dmamap_t dmamap; 2897 bus_addr_t offset, toff; 2898 bus_size_t tlen; 2899 int tosync; 2900 2901 ifp = &sc->ethercom.ec_if; 2902 2903 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2904 offsetof(struct bge_ring_data, bge_status_block), 2905 sizeof (struct bge_status_block), 2906 BUS_DMASYNC_POSTREAD); 2907 2908 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2909 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx - 2910 sc->bge_rx_saved_considx; 2911 2912 #if NRND > 0 2913 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 2914 rnd_add_uint32(&sc->rnd_source, tosync); 2915 #endif 2916 2917 toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd)); 2918 2919 if (tosync < 0) { 2920 tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) * 2921 sizeof (struct bge_rx_bd); 2922 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2923 toff, tlen, BUS_DMASYNC_POSTREAD); 2924 tosync = -tosync; 2925 } 2926 2927 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2928 offset, tosync * sizeof (struct bge_rx_bd), 2929 BUS_DMASYNC_POSTREAD); 2930 2931 while(sc->bge_rx_saved_considx != 2932 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 2933 struct bge_rx_bd *cur_rx; 2934 u_int32_t rxidx; 2935 struct mbuf *m = NULL; 2936 2937 cur_rx = &sc->bge_rdata-> 2938 bge_rx_return_ring[sc->bge_rx_saved_considx]; 2939 2940 rxidx = cur_rx->bge_idx; 2941 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2942 2943 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2944 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2945 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2946 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2947 jumbocnt++; 2948 bus_dmamap_sync(sc->bge_dmatag, 2949 sc->bge_cdata.bge_rx_jumbo_map, 2950 mtod(m, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, 2951 BGE_JLEN, BUS_DMASYNC_POSTREAD); 2952 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2953 ifp->if_ierrors++; 2954 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2955 continue; 2956 } 2957 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 2958 NULL)== ENOBUFS) { 2959 ifp->if_ierrors++; 2960 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2961 continue; 2962 } 2963 } else { 2964 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2965 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2966 2967 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2968 stdcnt++; 2969 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2970 sc->bge_cdata.bge_rx_std_map[rxidx] = 0; 2971 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 2972 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2973 bus_dmamap_unload(sc->bge_dmatag, dmamap); 2974 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2975 ifp->if_ierrors++; 2976 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2977 continue; 2978 } 2979 if (bge_newbuf_std(sc, sc->bge_std, 2980 NULL, dmamap) == ENOBUFS) { 2981 ifp->if_ierrors++; 2982 bge_newbuf_std(sc, sc->bge_std, m, dmamap); 2983 continue; 2984 } 2985 } 2986 2987 ifp->if_ipackets++; 2988 #ifndef __NO_STRICT_ALIGNMENT 2989 /* 2990 * XXX: if the 5701 PCIX-Rx-DMA workaround is in effect, 2991 * the Rx buffer has the layer-2 header unaligned. 2992 * If our CPU requires alignment, re-align by copying. 2993 */ 2994 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 2995 memmove(mtod(m, char *) + ETHER_ALIGN, m->m_data, 2996 cur_rx->bge_len); 2997 m->m_data += ETHER_ALIGN; 2998 } 2999 #endif 3000 3001 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3002 m->m_pkthdr.rcvif = ifp; 3003 3004 #if NBPFILTER > 0 3005 /* 3006 * Handle BPF listeners. Let the BPF user see the packet. 3007 */ 3008 if (ifp->if_bpf) 3009 bpf_mtap(ifp->if_bpf, m); 3010 #endif 3011 3012 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 3013 3014 if ((cur_rx->bge_ip_csum ^ 0xffff) != 0) 3015 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 3016 /* 3017 * Rx transport checksum-offload may also 3018 * have bugs with packets which, when transmitted, 3019 * were `runts' requiring padding. 3020 */ 3021 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3022 (/* (sc->_bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 ||*/ 3023 m->m_pkthdr.len >= ETHER_MIN_NOPAD)) { 3024 m->m_pkthdr.csum_data = 3025 cur_rx->bge_tcp_udp_csum; 3026 m->m_pkthdr.csum_flags |= 3027 (M_CSUM_TCPv4|M_CSUM_UDPv4| 3028 M_CSUM_DATA|M_CSUM_NO_PSEUDOHDR); 3029 } 3030 3031 /* 3032 * If we received a packet with a vlan tag, pass it 3033 * to vlan_input() instead of ether_input(). 3034 */ 3035 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3036 VLAN_INPUT_TAG(ifp, m, cur_rx->bge_vlan_tag, continue); 3037 } 3038 3039 (*ifp->if_input)(ifp, m); 3040 } 3041 3042 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3043 if (stdcnt) 3044 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3045 if (jumbocnt) 3046 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3047 } 3048 3049 static void 3050 bge_txeof(struct bge_softc *sc) 3051 { 3052 struct bge_tx_bd *cur_tx = NULL; 3053 struct ifnet *ifp; 3054 struct txdmamap_pool_entry *dma; 3055 bus_addr_t offset, toff; 3056 bus_size_t tlen; 3057 int tosync; 3058 struct mbuf *m; 3059 3060 ifp = &sc->ethercom.ec_if; 3061 3062 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3063 offsetof(struct bge_ring_data, bge_status_block), 3064 sizeof (struct bge_status_block), 3065 BUS_DMASYNC_POSTREAD); 3066 3067 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3068 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 3069 sc->bge_tx_saved_considx; 3070 3071 #if NRND > 0 3072 if (tosync != 0 && RND_ENABLED(&sc->rnd_source)) 3073 rnd_add_uint32(&sc->rnd_source, tosync); 3074 #endif 3075 3076 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 3077 3078 if (tosync < 0) { 3079 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 3080 sizeof (struct bge_tx_bd); 3081 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3082 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3083 tosync = -tosync; 3084 } 3085 3086 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3087 offset, tosync * sizeof (struct bge_tx_bd), 3088 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3089 3090 /* 3091 * Go through our tx ring and free mbufs for those 3092 * frames that have been sent. 3093 */ 3094 while (sc->bge_tx_saved_considx != 3095 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 3096 u_int32_t idx = 0; 3097 3098 idx = sc->bge_tx_saved_considx; 3099 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 3100 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3101 ifp->if_opackets++; 3102 m = sc->bge_cdata.bge_tx_chain[idx]; 3103 if (m != NULL) { 3104 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3105 dma = sc->txdma[idx]; 3106 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 3107 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3108 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 3109 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 3110 sc->txdma[idx] = NULL; 3111 3112 m_freem(m); 3113 } 3114 sc->bge_txcnt--; 3115 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3116 ifp->if_timer = 0; 3117 } 3118 3119 if (cur_tx != NULL) 3120 ifp->if_flags &= ~IFF_OACTIVE; 3121 } 3122 3123 static int 3124 bge_intr(void *xsc) 3125 { 3126 struct bge_softc *sc; 3127 struct ifnet *ifp; 3128 uint32_t statusword; 3129 3130 sc = xsc; 3131 ifp = &sc->ethercom.ec_if; 3132 3133 /* It is possible for the interrupt to arrive before 3134 * the status block is updated prior to the interrupt. 3135 * Reading the PCI State register will confirm whether the 3136 * interrupt is ours and will flush the status block. 3137 */ 3138 3139 /* read status word from status block */ 3140 statusword = sc->bge_rdata->bge_status_block.bge_status; 3141 3142 if ((statusword & BGE_STATFLAG_UPDATED) || 3143 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 3144 /* Ack interrupt and stop others from occuring. */ 3145 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3146 3147 BGE_EVCNT_INCR(sc->bge_ev_intr); 3148 3149 /* clear status word */ 3150 sc->bge_rdata->bge_status_block.bge_status = 0; 3151 3152 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3153 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3154 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 3155 bge_link_upd(sc); 3156 3157 if (ifp->if_flags & IFF_RUNNING) { 3158 /* Check RX return ring producer/consumer */ 3159 bge_rxeof(sc); 3160 3161 /* Check TX ring producer/consumer */ 3162 bge_txeof(sc); 3163 } 3164 3165 if (sc->bge_pending_rxintr_change) { 3166 uint32_t rx_ticks = sc->bge_rx_coal_ticks; 3167 uint32_t rx_bds = sc->bge_rx_max_coal_bds; 3168 uint32_t junk; 3169 3170 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks); 3171 DELAY(10); 3172 junk = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS); 3173 3174 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds); 3175 DELAY(10); 3176 junk = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS); 3177 3178 sc->bge_pending_rxintr_change = 0; 3179 } 3180 bge_handle_events(sc); 3181 3182 /* Re-enable interrupts. */ 3183 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3184 3185 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 3186 bge_start(ifp); 3187 3188 return (1); 3189 } else 3190 return (0); 3191 } 3192 3193 static void 3194 bge_tick(void *xsc) 3195 { 3196 struct bge_softc *sc = xsc; 3197 struct mii_data *mii = &sc->bge_mii; 3198 int s; 3199 3200 s = splnet(); 3201 3202 bge_stats_update(sc); 3203 3204 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3205 /* 3206 * Since in TBI mode auto-polling can't be used we should poll 3207 * link status manually. Here we register pending link event 3208 * and trigger interrupt. 3209 */ 3210 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3211 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3212 } else { 3213 /* 3214 * Do not touch PHY if we have link up. This could break 3215 * IPMI/ASF mode or produce extra input errors. 3216 * (extra input errors was reported for bcm5701 & bcm5704). 3217 */ 3218 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3219 mii_tick(mii); 3220 } 3221 3222 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3223 3224 splx(s); 3225 } 3226 3227 static void 3228 bge_stats_update(struct bge_softc *sc) 3229 { 3230 struct ifnet *ifp = &sc->ethercom.ec_if; 3231 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3232 bus_size_t rstats = BGE_RX_STATS; 3233 3234 #define READ_RSTAT(sc, stats, stat) \ 3235 CSR_READ_4(sc, stats + offsetof(struct bge_mac_stats_regs, stat)) 3236 3237 if (BGE_IS_5705_OR_BEYOND(sc)) { 3238 ifp->if_collisions += 3239 READ_RSTAT(sc, rstats, dot3StatsSingleCollisionFrames) + 3240 READ_RSTAT(sc, rstats, dot3StatsMultipleCollisionFrames) + 3241 READ_RSTAT(sc, rstats, dot3StatsExcessiveCollisions) + 3242 READ_RSTAT(sc, rstats, dot3StatsLateCollisions); 3243 3244 BGE_EVCNT_ADD(sc->bge_ev_tx_xoff, 3245 READ_RSTAT(sc, rstats, outXoffSent)); 3246 BGE_EVCNT_ADD(sc->bge_ev_tx_xon, 3247 READ_RSTAT(sc, rstats, outXonSent)); 3248 BGE_EVCNT_ADD(sc->bge_ev_rx_xoff, 3249 READ_RSTAT(sc, rstats, xoffPauseFramesReceived)); 3250 BGE_EVCNT_ADD(sc->bge_ev_rx_xon, 3251 READ_RSTAT(sc, rstats, xonPauseFramesReceived)); 3252 BGE_EVCNT_ADD(sc->bge_ev_rx_macctl, 3253 READ_RSTAT(sc, rstats, macControlFramesReceived)); 3254 BGE_EVCNT_ADD(sc->bge_ev_xoffentered, 3255 READ_RSTAT(sc, rstats, xoffStateEntered)); 3256 return; 3257 } 3258 3259 #undef READ_RSTAT 3260 #define READ_STAT(sc, stats, stat) \ 3261 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3262 3263 ifp->if_collisions += 3264 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 3265 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 3266 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 3267 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 3268 ifp->if_collisions; 3269 3270 BGE_EVCNT_UPD(sc->bge_ev_tx_xoff, 3271 READ_STAT(sc, stats, outXoffSent.bge_addr_lo)); 3272 BGE_EVCNT_UPD(sc->bge_ev_tx_xon, 3273 READ_STAT(sc, stats, outXonSent.bge_addr_lo)); 3274 BGE_EVCNT_UPD(sc->bge_ev_rx_xoff, 3275 READ_STAT(sc, stats, 3276 xoffPauseFramesReceived.bge_addr_lo)); 3277 BGE_EVCNT_UPD(sc->bge_ev_rx_xon, 3278 READ_STAT(sc, stats, xonPauseFramesReceived.bge_addr_lo)); 3279 BGE_EVCNT_UPD(sc->bge_ev_rx_macctl, 3280 READ_STAT(sc, stats, 3281 macControlFramesReceived.bge_addr_lo)); 3282 BGE_EVCNT_UPD(sc->bge_ev_xoffentered, 3283 READ_STAT(sc, stats, xoffStateEntered.bge_addr_lo)); 3284 3285 #undef READ_STAT 3286 3287 #ifdef notdef 3288 ifp->if_collisions += 3289 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3290 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3291 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3292 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3293 ifp->if_collisions; 3294 #endif 3295 } 3296 3297 /* 3298 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3299 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3300 * but when such padded frames employ the bge IP/TCP checksum offload, 3301 * the hardware checksum assist gives incorrect results (possibly 3302 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3303 * If we pad such runts with zeros, the onboard checksum comes out correct. 3304 */ 3305 static inline int 3306 bge_cksum_pad(struct mbuf *pkt) 3307 { 3308 struct mbuf *last = NULL; 3309 int padlen; 3310 3311 padlen = ETHER_MIN_NOPAD - pkt->m_pkthdr.len; 3312 3313 /* if there's only the packet-header and we can pad there, use it. */ 3314 if (pkt->m_pkthdr.len == pkt->m_len && 3315 M_TRAILINGSPACE(pkt) >= padlen) { 3316 last = pkt; 3317 } else { 3318 /* 3319 * Walk packet chain to find last mbuf. We will either 3320 * pad there, or append a new mbuf and pad it 3321 * (thus perhaps avoiding the bcm5700 dma-min bug). 3322 */ 3323 for (last = pkt; last->m_next != NULL; last = last->m_next) { 3324 continue; /* do nothing */ 3325 } 3326 3327 /* `last' now points to last in chain. */ 3328 if (M_TRAILINGSPACE(last) < padlen) { 3329 /* Allocate new empty mbuf, pad it. Compact later. */ 3330 struct mbuf *n; 3331 MGET(n, M_DONTWAIT, MT_DATA); 3332 if (n == NULL) 3333 return ENOBUFS; 3334 n->m_len = 0; 3335 last->m_next = n; 3336 last = n; 3337 } 3338 } 3339 3340 KDASSERT(!M_READONLY(last)); 3341 KDASSERT(M_TRAILINGSPACE(last) >= padlen); 3342 3343 /* Now zero the pad area, to avoid the bge cksum-assist bug */ 3344 memset(mtod(last, char *) + last->m_len, 0, padlen); 3345 last->m_len += padlen; 3346 pkt->m_pkthdr.len += padlen; 3347 return 0; 3348 } 3349 3350 /* 3351 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3352 */ 3353 static inline int 3354 bge_compact_dma_runt(struct mbuf *pkt) 3355 { 3356 struct mbuf *m, *prev; 3357 int totlen, prevlen; 3358 3359 prev = NULL; 3360 totlen = 0; 3361 prevlen = -1; 3362 3363 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3364 int mlen = m->m_len; 3365 int shortfall = 8 - mlen ; 3366 3367 totlen += mlen; 3368 if (mlen == 0) { 3369 continue; 3370 } 3371 if (mlen >= 8) 3372 continue; 3373 3374 /* If we get here, mbuf data is too small for DMA engine. 3375 * Try to fix by shuffling data to prev or next in chain. 3376 * If that fails, do a compacting deep-copy of the whole chain. 3377 */ 3378 3379 /* Internal frag. If fits in prev, copy it there. */ 3380 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 3381 memcpy(prev->m_data + prev->m_len, m->m_data, mlen); 3382 prev->m_len += mlen; 3383 m->m_len = 0; 3384 /* XXX stitch chain */ 3385 prev->m_next = m_free(m); 3386 m = prev; 3387 continue; 3388 } 3389 else if (m->m_next != NULL && 3390 M_TRAILINGSPACE(m) >= shortfall && 3391 m->m_next->m_len >= (8 + shortfall)) { 3392 /* m is writable and have enough data in next, pull up. */ 3393 3394 memcpy(m->m_data + m->m_len, m->m_next->m_data, 3395 shortfall); 3396 m->m_len += shortfall; 3397 m->m_next->m_len -= shortfall; 3398 m->m_next->m_data += shortfall; 3399 } 3400 else if (m->m_next == NULL || 1) { 3401 /* Got a runt at the very end of the packet. 3402 * borrow data from the tail of the preceding mbuf and 3403 * update its length in-place. (The original data is still 3404 * valid, so we can do this even if prev is not writable.) 3405 */ 3406 3407 /* if we'd make prev a runt, just move all of its data. */ 3408 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3409 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3410 3411 if ((prev->m_len - shortfall) < 8) 3412 shortfall = prev->m_len; 3413 3414 #ifdef notyet /* just do the safe slow thing for now */ 3415 if (!M_READONLY(m)) { 3416 if (M_LEADINGSPACE(m) < shorfall) { 3417 void *m_dat; 3418 m_dat = (m->m_flags & M_PKTHDR) ? 3419 m->m_pktdat : m->dat; 3420 memmove(m_dat, mtod(m, void*), m->m_len); 3421 m->m_data = m_dat; 3422 } 3423 } else 3424 #endif /* just do the safe slow thing */ 3425 { 3426 struct mbuf * n = NULL; 3427 int newprevlen = prev->m_len - shortfall; 3428 3429 MGET(n, M_NOWAIT, MT_DATA); 3430 if (n == NULL) 3431 return ENOBUFS; 3432 KASSERT(m->m_len + shortfall < MLEN 3433 /*, 3434 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3435 3436 /* first copy the data we're stealing from prev */ 3437 memcpy(n->m_data, prev->m_data + newprevlen, 3438 shortfall); 3439 3440 /* update prev->m_len accordingly */ 3441 prev->m_len -= shortfall; 3442 3443 /* copy data from runt m */ 3444 memcpy(n->m_data + shortfall, m->m_data, 3445 m->m_len); 3446 3447 /* n holds what we stole from prev, plus m */ 3448 n->m_len = shortfall + m->m_len; 3449 3450 /* stitch n into chain and free m */ 3451 n->m_next = m->m_next; 3452 prev->m_next = n; 3453 /* KASSERT(m->m_next == NULL); */ 3454 m->m_next = NULL; 3455 m_free(m); 3456 m = n; /* for continuing loop */ 3457 } 3458 } 3459 prevlen = m->m_len; 3460 } 3461 return 0; 3462 } 3463 3464 /* 3465 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3466 * pointers to descriptors. 3467 */ 3468 static int 3469 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3470 { 3471 struct bge_tx_bd *f = NULL; 3472 u_int32_t frag, cur; 3473 u_int16_t csum_flags = 0; 3474 u_int16_t txbd_tso_flags = 0; 3475 struct txdmamap_pool_entry *dma; 3476 bus_dmamap_t dmamap; 3477 int i = 0; 3478 struct m_tag *mtag; 3479 int use_tso, maxsegsize, error; 3480 3481 cur = frag = *txidx; 3482 3483 if (m_head->m_pkthdr.csum_flags) { 3484 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 3485 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3486 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 3487 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3488 } 3489 3490 /* 3491 * If we were asked to do an outboard checksum, and the NIC 3492 * has the bug where it sometimes adds in the Ethernet padding, 3493 * explicitly pad with zeros so the cksum will be correct either way. 3494 * (For now, do this for all chip versions, until newer 3495 * are confirmed to not require the workaround.) 3496 */ 3497 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) == 0 || 3498 #ifdef notyet 3499 (sc->bge_quirks & BGE_QUIRK_SHORT_CKSUM_BUG) == 0 || 3500 #endif 3501 m_head->m_pkthdr.len >= ETHER_MIN_NOPAD) 3502 goto check_dma_bug; 3503 3504 if (bge_cksum_pad(m_head) != 0) { 3505 return ENOBUFS; 3506 } 3507 3508 check_dma_bug: 3509 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3510 goto doit; 3511 3512 /* 3513 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3514 * less than eight bytes. If we encounter a teeny mbuf 3515 * at the end of a chain, we can pad. Otherwise, copy. 3516 */ 3517 if (bge_compact_dma_runt(m_head) != 0) 3518 return ENOBUFS; 3519 3520 doit: 3521 dma = SLIST_FIRST(&sc->txdma_list); 3522 if (dma == NULL) 3523 return ENOBUFS; 3524 dmamap = dma->dmamap; 3525 3526 /* 3527 * Set up any necessary TSO state before we start packing... 3528 */ 3529 use_tso = (m_head->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 3530 if (!use_tso) { 3531 maxsegsize = 0; 3532 } else { /* TSO setup */ 3533 unsigned mss; 3534 struct ether_header *eh; 3535 unsigned ip_tcp_hlen, iptcp_opt_words, tcp_seg_flags, offset; 3536 struct mbuf * m0 = m_head; 3537 struct ip *ip; 3538 struct tcphdr *th; 3539 int iphl, hlen; 3540 3541 /* 3542 * XXX It would be nice if the mbuf pkthdr had offset 3543 * fields for the protocol headers. 3544 */ 3545 3546 eh = mtod(m0, struct ether_header *); 3547 switch (htons(eh->ether_type)) { 3548 case ETHERTYPE_IP: 3549 offset = ETHER_HDR_LEN; 3550 break; 3551 3552 case ETHERTYPE_VLAN: 3553 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3554 break; 3555 3556 default: 3557 /* 3558 * Don't support this protocol or encapsulation. 3559 */ 3560 return (ENOBUFS); 3561 } 3562 3563 /* 3564 * TCP/IP headers are in the first mbuf; we can do 3565 * this the easy way. 3566 */ 3567 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 3568 hlen = iphl + offset; 3569 if (__predict_false(m0->m_len < 3570 (hlen + sizeof(struct tcphdr)))) { 3571 3572 aprint_debug_dev(sc->bge_dev, 3573 "TSO: hard case m0->m_len == %d < ip/tcp hlen %zd," 3574 "not handled yet\n", 3575 m0->m_len, hlen+ sizeof(struct tcphdr)); 3576 #ifdef NOTYET 3577 /* 3578 * XXX jonathan@NetBSD.org: untested. 3579 * how to force this branch to be taken? 3580 */ 3581 BGE_EVCNT_INCR(&sc->sc_ev_txtsopain); 3582 3583 m_copydata(m0, offset, sizeof(ip), &ip); 3584 m_copydata(m0, hlen, sizeof(th), &th); 3585 3586 ip.ip_len = 0; 3587 3588 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 3589 sizeof(ip.ip_len), &ip.ip_len); 3590 3591 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 3592 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 3593 3594 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 3595 sizeof(th.th_sum), &th.th_sum); 3596 3597 hlen += th.th_off << 2; 3598 iptcp_opt_words = hlen; 3599 #else 3600 /* 3601 * if_wm "hard" case not yet supported, can we not 3602 * mandate it out of existence? 3603 */ 3604 (void) ip; (void)th; (void) ip_tcp_hlen; 3605 3606 return ENOBUFS; 3607 #endif 3608 } else { 3609 ip = (struct ip *) (mtod(m0, char *) + offset); 3610 th = (struct tcphdr *) (mtod(m0, char *) + hlen); 3611 ip_tcp_hlen = iphl + (th->th_off << 2); 3612 3613 /* Total IP/TCP options, in 32-bit words */ 3614 iptcp_opt_words = (ip_tcp_hlen 3615 - sizeof(struct tcphdr) 3616 - sizeof(struct ip)) >> 2; 3617 } 3618 if (BGE_IS_5750_OR_BEYOND(sc)) { 3619 th->th_sum = 0; 3620 csum_flags &= ~(BGE_TXBDFLAG_TCP_UDP_CSUM); 3621 } else { 3622 /* 3623 * XXX jonathan@NetBSD.org: 5705 untested. 3624 * Requires TSO firmware patch for 5701/5703/5704. 3625 */ 3626 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 3627 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3628 } 3629 3630 mss = m_head->m_pkthdr.segsz; 3631 txbd_tso_flags |= 3632 BGE_TXBDFLAG_CPU_PRE_DMA | 3633 BGE_TXBDFLAG_CPU_POST_DMA; 3634 3635 /* 3636 * Our NIC TSO-assist assumes TSO has standard, optionless 3637 * IPv4 and TCP headers, which total 40 bytes. By default, 3638 * the NIC copies 40 bytes of IP/TCP header from the 3639 * supplied header into the IP/TCP header portion of 3640 * each post-TSO-segment. If the supplied packet has IP or 3641 * TCP options, we need to tell the NIC to copy those extra 3642 * bytes into each post-TSO header, in addition to the normal 3643 * 40-byte IP/TCP header (and to leave space accordingly). 3644 * Unfortunately, the driver encoding of option length 3645 * varies across different ASIC families. 3646 */ 3647 tcp_seg_flags = 0; 3648 if (iptcp_opt_words) { 3649 if ( BGE_IS_5705_OR_BEYOND(sc)) { 3650 tcp_seg_flags = 3651 iptcp_opt_words << 11; 3652 } else { 3653 txbd_tso_flags |= 3654 iptcp_opt_words << 12; 3655 } 3656 } 3657 maxsegsize = mss | tcp_seg_flags; 3658 ip->ip_len = htons(mss + ip_tcp_hlen); 3659 3660 } /* TSO setup */ 3661 3662 /* 3663 * Start packing the mbufs in this chain into 3664 * the fragment pointers. Stop when we run out 3665 * of fragments or hit the end of the mbuf chain. 3666 */ 3667 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3668 BUS_DMA_NOWAIT); 3669 if (error) { 3670 return (ENOBUFS); 3671 } 3672 /* 3673 * Sanity check: avoid coming within 16 descriptors 3674 * of the end of the ring. 3675 */ 3676 if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3677 BGE_TSO_PRINTF(("%s: " 3678 " dmamap_load_mbuf too close to ring wrap\n", 3679 device_xname(sc->bge_dev))); 3680 goto fail_unload; 3681 } 3682 3683 mtag = sc->ethercom.ec_nvlans ? 3684 m_tag_find(m_head, PACKET_TAG_VLAN, NULL) : NULL; 3685 3686 3687 /* Iterate over dmap-map fragments. */ 3688 for (i = 0; i < dmamap->dm_nsegs; i++) { 3689 f = &sc->bge_rdata->bge_tx_ring[frag]; 3690 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3691 break; 3692 3693 bge_set_hostaddr(&f->bge_addr, dmamap->dm_segs[i].ds_addr); 3694 f->bge_len = dmamap->dm_segs[i].ds_len; 3695 3696 /* 3697 * For 5751 and follow-ons, for TSO we must turn 3698 * off checksum-assist flag in the tx-descr, and 3699 * supply the ASIC-revision-specific encoding 3700 * of TSO flags and segsize. 3701 */ 3702 if (use_tso) { 3703 if (BGE_IS_5750_OR_BEYOND(sc) || i == 0) { 3704 f->bge_rsvd = maxsegsize; 3705 f->bge_flags = csum_flags | txbd_tso_flags; 3706 } else { 3707 f->bge_rsvd = 0; 3708 f->bge_flags = 3709 (csum_flags | txbd_tso_flags) & 0x0fff; 3710 } 3711 } else { 3712 f->bge_rsvd = 0; 3713 f->bge_flags = csum_flags; 3714 } 3715 3716 if (mtag != NULL) { 3717 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3718 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3719 } else { 3720 f->bge_vlan_tag = 0; 3721 } 3722 cur = frag; 3723 BGE_INC(frag, BGE_TX_RING_CNT); 3724 } 3725 3726 if (i < dmamap->dm_nsegs) { 3727 BGE_TSO_PRINTF(("%s: reached %d < dm_nsegs %d\n", 3728 device_xname(sc->bge_dev), i, dmamap->dm_nsegs)); 3729 goto fail_unload; 3730 } 3731 3732 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3733 BUS_DMASYNC_PREWRITE); 3734 3735 if (frag == sc->bge_tx_saved_considx) { 3736 BGE_TSO_PRINTF(("%s: frag %d = wrapped id %d?\n", 3737 device_xname(sc->bge_dev), frag, sc->bge_tx_saved_considx)); 3738 3739 goto fail_unload; 3740 } 3741 3742 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3743 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3744 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3745 sc->txdma[cur] = dma; 3746 sc->bge_txcnt += dmamap->dm_nsegs; 3747 3748 *txidx = frag; 3749 3750 return (0); 3751 3752 fail_unload: 3753 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3754 3755 return ENOBUFS; 3756 } 3757 3758 /* 3759 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3760 * to the mbuf data regions directly in the transmit descriptors. 3761 */ 3762 static void 3763 bge_start(struct ifnet *ifp) 3764 { 3765 struct bge_softc *sc; 3766 struct mbuf *m_head = NULL; 3767 u_int32_t prodidx; 3768 int pkts = 0; 3769 3770 sc = ifp->if_softc; 3771 3772 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 3773 return; 3774 3775 prodidx = sc->bge_tx_prodidx; 3776 3777 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3778 IFQ_POLL(&ifp->if_snd, m_head); 3779 if (m_head == NULL) 3780 break; 3781 3782 #if 0 3783 /* 3784 * XXX 3785 * safety overkill. If this is a fragmented packet chain 3786 * with delayed TCP/UDP checksums, then only encapsulate 3787 * it if we have enough descriptors to handle the entire 3788 * chain at once. 3789 * (paranoia -- may not actually be needed) 3790 */ 3791 if (m_head->m_flags & M_FIRSTFRAG && 3792 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3793 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3794 M_CSUM_DATA_IPv4_OFFSET(m_head->m_pkthdr.csum_data) + 16) { 3795 ifp->if_flags |= IFF_OACTIVE; 3796 break; 3797 } 3798 } 3799 #endif 3800 3801 /* 3802 * Pack the data into the transmit ring. If we 3803 * don't have room, set the OACTIVE flag and wait 3804 * for the NIC to drain the ring. 3805 */ 3806 if (bge_encap(sc, m_head, &prodidx)) { 3807 ifp->if_flags |= IFF_OACTIVE; 3808 break; 3809 } 3810 3811 /* now we are committed to transmit the packet */ 3812 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3813 pkts++; 3814 3815 #if NBPFILTER > 0 3816 /* 3817 * If there's a BPF listener, bounce a copy of this frame 3818 * to him. 3819 */ 3820 if (ifp->if_bpf) 3821 bpf_mtap(ifp->if_bpf, m_head); 3822 #endif 3823 } 3824 if (pkts == 0) 3825 return; 3826 3827 /* Transmit */ 3828 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3829 /* 5700 b2 errata */ 3830 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 3831 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3832 3833 sc->bge_tx_prodidx = prodidx; 3834 3835 /* 3836 * Set a timeout in case the chip goes out to lunch. 3837 */ 3838 ifp->if_timer = 5; 3839 } 3840 3841 static int 3842 bge_init(struct ifnet *ifp) 3843 { 3844 struct bge_softc *sc = ifp->if_softc; 3845 const u_int16_t *m; 3846 int s, error = 0; 3847 3848 s = splnet(); 3849 3850 ifp = &sc->ethercom.ec_if; 3851 3852 /* Cancel pending I/O and flush buffers. */ 3853 bge_stop(ifp, 0); 3854 bge_reset(sc); 3855 bge_chipinit(sc); 3856 3857 /* 3858 * Init the various state machines, ring 3859 * control blocks and firmware. 3860 */ 3861 error = bge_blockinit(sc); 3862 if (error != 0) { 3863 aprint_error_dev(sc->bge_dev, "initialization error %d\n", 3864 error); 3865 splx(s); 3866 return error; 3867 } 3868 3869 ifp = &sc->ethercom.ec_if; 3870 3871 /* Specify MTU. */ 3872 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3873 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3874 3875 /* Load our MAC address. */ 3876 m = (const u_int16_t *)&(CLLADDR(ifp->if_sadl)[0]); 3877 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3878 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3879 3880 /* Enable or disable promiscuous mode as needed. */ 3881 if (ifp->if_flags & IFF_PROMISC) { 3882 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3883 } else { 3884 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3885 } 3886 3887 /* Program multicast filter. */ 3888 bge_setmulti(sc); 3889 3890 /* Init RX ring. */ 3891 bge_init_rx_ring_std(sc); 3892 3893 /* 3894 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3895 * memory to insure that the chip has in fact read the first 3896 * entry of the ring. 3897 */ 3898 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3899 u_int32_t v, i; 3900 for (i = 0; i < 10; i++) { 3901 DELAY(20); 3902 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3903 if (v == (MCLBYTES - ETHER_ALIGN)) 3904 break; 3905 } 3906 if (i == 10) 3907 aprint_error_dev(sc->bge_dev, 3908 "5705 A0 chip failed to load RX ring\n"); 3909 } 3910 3911 /* Init jumbo RX ring. */ 3912 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3913 bge_init_rx_ring_jumbo(sc); 3914 3915 /* Init our RX return ring index */ 3916 sc->bge_rx_saved_considx = 0; 3917 3918 /* Init TX ring. */ 3919 bge_init_tx_ring(sc); 3920 3921 /* Turn on transmitter */ 3922 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3923 3924 /* Turn on receiver */ 3925 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3926 3927 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3928 3929 /* Tell firmware we're alive. */ 3930 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3931 3932 /* Enable host interrupts. */ 3933 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3934 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3935 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3936 3937 if ((error = bge_ifmedia_upd(ifp)) != 0) 3938 goto out; 3939 3940 ifp->if_flags |= IFF_RUNNING; 3941 ifp->if_flags &= ~IFF_OACTIVE; 3942 3943 callout_reset(&sc->bge_timeout, hz, bge_tick, sc); 3944 3945 out: 3946 splx(s); 3947 3948 return error; 3949 } 3950 3951 /* 3952 * Set media options. 3953 */ 3954 static int 3955 bge_ifmedia_upd(struct ifnet *ifp) 3956 { 3957 struct bge_softc *sc = ifp->if_softc; 3958 struct mii_data *mii = &sc->bge_mii; 3959 struct ifmedia *ifm = &sc->bge_ifmedia; 3960 int rc; 3961 3962 /* If this is a 1000baseX NIC, enable the TBI port. */ 3963 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3964 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3965 return (EINVAL); 3966 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3967 case IFM_AUTO: 3968 /* 3969 * The BCM5704 ASIC appears to have a special 3970 * mechanism for programming the autoneg 3971 * advertisement registers in TBI mode. 3972 */ 3973 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3974 u_int32_t sgdig; 3975 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3976 if (sgdig & BGE_SGDIGSTS_DONE) { 3977 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3978 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3979 sgdig |= BGE_SGDIGCFG_AUTO | 3980 BGE_SGDIGCFG_PAUSE_CAP | 3981 BGE_SGDIGCFG_ASYM_PAUSE; 3982 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3983 sgdig | BGE_SGDIGCFG_SEND); 3984 DELAY(5); 3985 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3986 } 3987 } 3988 break; 3989 case IFM_1000_SX: 3990 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3991 BGE_CLRBIT(sc, BGE_MAC_MODE, 3992 BGE_MACMODE_HALF_DUPLEX); 3993 } else { 3994 BGE_SETBIT(sc, BGE_MAC_MODE, 3995 BGE_MACMODE_HALF_DUPLEX); 3996 } 3997 break; 3998 default: 3999 return (EINVAL); 4000 } 4001 /* XXX 802.3x flow control for 1000BASE-SX */ 4002 return (0); 4003 } 4004 4005 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4006 if ((rc = mii_mediachg(mii)) == ENXIO) 4007 return 0; 4008 4009 /* 4010 * Force an interrupt so that we will call bge_link_upd 4011 * if needed and clear any pending link state attention. 4012 * Without this we are not getting any further interrupts 4013 * for link state changes and thus will not UP the link and 4014 * not be able to send in bge_start. The only way to get 4015 * things working was to receive a packet and get a RX intr. 4016 */ 4017 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4018 sc->bge_flags & BGE_IS_5788) 4019 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4020 else 4021 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4022 4023 return rc; 4024 } 4025 4026 /* 4027 * Report current media status. 4028 */ 4029 static void 4030 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4031 { 4032 struct bge_softc *sc = ifp->if_softc; 4033 struct mii_data *mii = &sc->bge_mii; 4034 4035 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4036 ifmr->ifm_status = IFM_AVALID; 4037 ifmr->ifm_active = IFM_ETHER; 4038 if (CSR_READ_4(sc, BGE_MAC_STS) & 4039 BGE_MACSTAT_TBI_PCS_SYNCHED) 4040 ifmr->ifm_status |= IFM_ACTIVE; 4041 ifmr->ifm_active |= IFM_1000_SX; 4042 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4043 ifmr->ifm_active |= IFM_HDX; 4044 else 4045 ifmr->ifm_active |= IFM_FDX; 4046 return; 4047 } 4048 4049 mii_pollstat(mii); 4050 ifmr->ifm_status = mii->mii_media_status; 4051 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4052 sc->bge_flowflags; 4053 } 4054 4055 static int 4056 bge_ioctl(struct ifnet *ifp, u_long command, void *data) 4057 { 4058 struct bge_softc *sc = ifp->if_softc; 4059 struct ifreq *ifr = (struct ifreq *) data; 4060 int s, error = 0; 4061 struct mii_data *mii; 4062 4063 s = splnet(); 4064 4065 switch(command) { 4066 case SIOCSIFFLAGS: 4067 if ((error = ifioctl_common(ifp, command, data)) != 0) 4068 break; 4069 if (ifp->if_flags & IFF_UP) { 4070 /* 4071 * If only the state of the PROMISC flag changed, 4072 * then just use the 'set promisc mode' command 4073 * instead of reinitializing the entire NIC. Doing 4074 * a full re-init means reloading the firmware and 4075 * waiting for it to start up, which may take a 4076 * second or two. 4077 */ 4078 if (ifp->if_flags & IFF_RUNNING && 4079 ifp->if_flags & IFF_PROMISC && 4080 !(sc->bge_if_flags & IFF_PROMISC)) { 4081 BGE_SETBIT(sc, BGE_RX_MODE, 4082 BGE_RXMODE_RX_PROMISC); 4083 } else if (ifp->if_flags & IFF_RUNNING && 4084 !(ifp->if_flags & IFF_PROMISC) && 4085 sc->bge_if_flags & IFF_PROMISC) { 4086 BGE_CLRBIT(sc, BGE_RX_MODE, 4087 BGE_RXMODE_RX_PROMISC); 4088 } else if (!(sc->bge_if_flags & IFF_UP)) 4089 bge_init(ifp); 4090 } else { 4091 if (ifp->if_flags & IFF_RUNNING) 4092 bge_stop(ifp, 1); 4093 } 4094 sc->bge_if_flags = ifp->if_flags; 4095 error = 0; 4096 break; 4097 case SIOCSIFMEDIA: 4098 /* XXX Flow control is not supported for 1000BASE-SX */ 4099 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4100 ifr->ifr_media &= ~IFM_ETH_FMASK; 4101 sc->bge_flowflags = 0; 4102 } 4103 4104 /* Flow control requires full-duplex mode. */ 4105 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4106 (ifr->ifr_media & IFM_FDX) == 0) { 4107 ifr->ifr_media &= ~IFM_ETH_FMASK; 4108 } 4109 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4110 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4111 /* We can do both TXPAUSE and RXPAUSE. */ 4112 ifr->ifr_media |= 4113 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4114 } 4115 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4116 } 4117 /* FALLTHROUGH */ 4118 case SIOCGIFMEDIA: 4119 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4120 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4121 command); 4122 } else { 4123 mii = &sc->bge_mii; 4124 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4125 command); 4126 } 4127 break; 4128 default: 4129 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 4130 break; 4131 4132 error = 0; 4133 4134 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 4135 ; 4136 else if (ifp->if_flags & IFF_RUNNING) 4137 bge_setmulti(sc); 4138 break; 4139 } 4140 4141 splx(s); 4142 4143 return (error); 4144 } 4145 4146 static void 4147 bge_watchdog(struct ifnet *ifp) 4148 { 4149 struct bge_softc *sc; 4150 4151 sc = ifp->if_softc; 4152 4153 aprint_error_dev(sc->bge_dev, "watchdog timeout -- resetting\n"); 4154 4155 ifp->if_flags &= ~IFF_RUNNING; 4156 bge_init(ifp); 4157 4158 ifp->if_oerrors++; 4159 } 4160 4161 static void 4162 bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit) 4163 { 4164 int i; 4165 4166 BGE_CLRBIT(sc, reg, bit); 4167 4168 for (i = 0; i < BGE_TIMEOUT; i++) { 4169 if ((CSR_READ_4(sc, reg) & bit) == 0) 4170 return; 4171 delay(100); 4172 if (sc->bge_flags & BGE_PCIE) 4173 DELAY(1000); 4174 } 4175 4176 /* 4177 * Doesn't print only when the register is BGE_SRS_MODE. It occurs 4178 * on some environment (and once after boot?) 4179 */ 4180 if (reg != BGE_SRS_MODE) 4181 aprint_error_dev(sc->bge_dev, 4182 "block failed to stop: reg 0x%lx, bit 0x%08x\n", 4183 (u_long)reg, bit); 4184 } 4185 4186 /* 4187 * Stop the adapter and free any mbufs allocated to the 4188 * RX and TX lists. 4189 */ 4190 static void 4191 bge_stop(struct ifnet *ifp, int disable) 4192 { 4193 struct bge_softc *sc = ifp->if_softc; 4194 4195 callout_stop(&sc->bge_timeout); 4196 4197 /* 4198 * Disable all of the receiver blocks 4199 */ 4200 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4201 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4202 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4203 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4204 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4205 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4206 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4207 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4208 4209 /* 4210 * Disable all of the transmit blocks 4211 */ 4212 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4213 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4214 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4215 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4216 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4217 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4218 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4219 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4220 4221 /* 4222 * Shut down all of the memory managers and related 4223 * state machines. 4224 */ 4225 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4226 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4227 if (!(BGE_IS_5705_OR_BEYOND(sc))) 4228 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4229 4230 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4231 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4232 4233 if (!(BGE_IS_5705_OR_BEYOND(sc))) { 4234 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4235 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4236 } 4237 4238 /* Disable host interrupts. */ 4239 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4240 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4241 4242 /* 4243 * Tell firmware we're shutting down. 4244 */ 4245 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4246 4247 /* Free the RX lists. */ 4248 bge_free_rx_ring_std(sc); 4249 4250 /* Free jumbo RX list. */ 4251 bge_free_rx_ring_jumbo(sc); 4252 4253 /* Free TX buffers. */ 4254 bge_free_tx_ring(sc); 4255 4256 /* 4257 * Isolate/power down the PHY. 4258 */ 4259 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) 4260 mii_down(&sc->bge_mii); 4261 4262 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4263 4264 /* Clear MAC's link state (PHY may still have link UP). */ 4265 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4266 4267 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4268 } 4269 4270 static void 4271 bge_link_upd(struct bge_softc *sc) 4272 { 4273 struct ifnet *ifp = &sc->ethercom.ec_if; 4274 struct mii_data *mii = &sc->bge_mii; 4275 u_int32_t status; 4276 int link; 4277 4278 /* Clear 'pending link event' flag */ 4279 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4280 4281 /* 4282 * Process link state changes. 4283 * Grrr. The link status word in the status block does 4284 * not work correctly on the BCM5700 rev AX and BX chips, 4285 * according to all available information. Hence, we have 4286 * to enable MII interrupts in order to properly obtain 4287 * async link changes. Unfortunately, this also means that 4288 * we have to read the MAC status register to detect link 4289 * changes, thereby adding an additional register access to 4290 * the interrupt handler. 4291 */ 4292 4293 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4294 status = CSR_READ_4(sc, BGE_MAC_STS); 4295 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4296 mii_pollstat(mii); 4297 4298 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4299 mii->mii_media_status & IFM_ACTIVE && 4300 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4301 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4302 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4303 (!(mii->mii_media_status & IFM_ACTIVE) || 4304 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4305 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4306 4307 /* Clear the interrupt */ 4308 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4309 BGE_EVTENB_MI_INTERRUPT); 4310 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4311 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4312 BRGPHY_INTRS); 4313 } 4314 return; 4315 } 4316 4317 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 4318 status = CSR_READ_4(sc, BGE_MAC_STS); 4319 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4320 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4321 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4322 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4323 BGE_CLRBIT(sc, BGE_MAC_MODE, 4324 BGE_MACMODE_TBI_SEND_CFGS); 4325 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4326 if_link_state_change(ifp, LINK_STATE_UP); 4327 } 4328 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4329 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4330 if_link_state_change(ifp, LINK_STATE_DOWN); 4331 } 4332 /* 4333 * Discard link events for MII/GMII cards if MI auto-polling disabled. 4334 * This should not happen since mii callouts are locked now, but 4335 * we keep this check for debug. 4336 */ 4337 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4338 /* 4339 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED 4340 * bit in status word always set. Workaround this bug by 4341 * reading PHY link status directly. 4342 */ 4343 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4344 BGE_STS_LINK : 0; 4345 4346 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4347 mii_pollstat(mii); 4348 4349 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4350 mii->mii_media_status & IFM_ACTIVE && 4351 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4352 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4353 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4354 (!(mii->mii_media_status & IFM_ACTIVE) || 4355 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4356 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4357 } 4358 } 4359 4360 /* Clear the attention */ 4361 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4362 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4363 BGE_MACSTAT_LINK_CHANGED); 4364 } 4365 4366 static int 4367 sysctl_bge_verify(SYSCTLFN_ARGS) 4368 { 4369 int error, t; 4370 struct sysctlnode node; 4371 4372 node = *rnode; 4373 t = *(int*)rnode->sysctl_data; 4374 node.sysctl_data = &t; 4375 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 4376 if (error || newp == NULL) 4377 return (error); 4378 4379 #if 0 4380 DPRINTF2(("%s: t = %d, nodenum = %d, rnodenum = %d\n", __func__, t, 4381 node.sysctl_num, rnode->sysctl_num)); 4382 #endif 4383 4384 if (node.sysctl_num == bge_rxthresh_nodenum) { 4385 if (t < 0 || t >= NBGE_RX_THRESH) 4386 return (EINVAL); 4387 bge_update_all_threshes(t); 4388 } else 4389 return (EINVAL); 4390 4391 *(int*)rnode->sysctl_data = t; 4392 4393 return (0); 4394 } 4395 4396 /* 4397 * Set up sysctl(3) MIB, hw.bge.*. 4398 * 4399 * TBD condition SYSCTL_PERMANENT on being an LKM or not 4400 */ 4401 SYSCTL_SETUP(sysctl_bge, "sysctl bge subtree setup") 4402 { 4403 int rc, bge_root_num; 4404 const struct sysctlnode *node; 4405 4406 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 4407 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL, 4408 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 4409 goto err; 4410 } 4411 4412 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4413 CTLFLAG_PERMANENT, CTLTYPE_NODE, "bge", 4414 SYSCTL_DESCR("BGE interface controls"), 4415 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 4416 goto err; 4417 } 4418 4419 bge_root_num = node->sysctl_num; 4420 4421 /* BGE Rx interrupt mitigation level */ 4422 if ((rc = sysctl_createv(clog, 0, NULL, &node, 4423 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, 4424 CTLTYPE_INT, "rx_lvl", 4425 SYSCTL_DESCR("BGE receive interrupt mitigation level"), 4426 sysctl_bge_verify, 0, 4427 &bge_rx_thresh_lvl, 4428 0, CTL_HW, bge_root_num, CTL_CREATE, 4429 CTL_EOL)) != 0) { 4430 goto err; 4431 } 4432 4433 bge_rxthresh_nodenum = node->sysctl_num; 4434 4435 return; 4436 4437 err: 4438 aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 4439 } 4440 4441 static int 4442 bge_get_eaddr_mem(struct bge_softc *sc, u_int8_t ether_addr[]) 4443 { 4444 u_int32_t mac_addr; 4445 4446 mac_addr = bge_readmem_ind(sc, 0x0c14); 4447 if ((mac_addr >> 16) == 0x484b) { 4448 ether_addr[0] = (uint8_t)(mac_addr >> 8); 4449 ether_addr[1] = (uint8_t)mac_addr; 4450 mac_addr = bge_readmem_ind(sc, 0x0c18); 4451 ether_addr[2] = (uint8_t)(mac_addr >> 24); 4452 ether_addr[3] = (uint8_t)(mac_addr >> 16); 4453 ether_addr[4] = (uint8_t)(mac_addr >> 8); 4454 ether_addr[5] = (uint8_t)mac_addr; 4455 return (0); 4456 } 4457 return (1); 4458 } 4459 4460 static int 4461 bge_get_eaddr_nvram(struct bge_softc *sc, u_int8_t ether_addr[]) 4462 { 4463 int mac_offset = BGE_EE_MAC_OFFSET; 4464 4465 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4466 mac_offset = BGE_EE_MAC_OFFSET_5906; 4467 } 4468 4469 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 4470 ETHER_ADDR_LEN)); 4471 } 4472 4473 static int 4474 bge_get_eaddr_eeprom(struct bge_softc *sc, u_int8_t ether_addr[]) 4475 { 4476 4477 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 4478 return (1); 4479 } 4480 4481 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 4482 ETHER_ADDR_LEN)); 4483 } 4484 4485 static int 4486 bge_get_eaddr(struct bge_softc *sc, u_int8_t eaddr[]) 4487 { 4488 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 4489 /* NOTE: Order is critical */ 4490 bge_get_eaddr_mem, 4491 bge_get_eaddr_nvram, 4492 bge_get_eaddr_eeprom, 4493 NULL 4494 }; 4495 const bge_eaddr_fcn_t *func; 4496 4497 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 4498 if ((*func)(sc, eaddr) == 0) 4499 break; 4500 } 4501 return (*func == NULL ? ENXIO : 0); 4502 } 4503