1 /* $NetBSD: if_bce.c,v 1.18 2007/12/11 11:25:50 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff@snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.18 2007/12/11 11:25:50 lukem Exp $"); 39 40 #include "bpfilter.h" 41 #include "vlan.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/socket.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #if NRND > 0 63 #include <sys/rnd.h> 64 #endif 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 #include <dev/mii/miidevs.h> 73 #include <dev/mii/brgphyreg.h> 74 75 #include <dev/pci/if_bcereg.h> 76 77 #include <uvm/uvm_extern.h> 78 79 /* transmit buffer max frags allowed */ 80 #define BCE_NTXFRAGS 16 81 82 /* ring descriptor */ 83 struct bce_dma_slot { 84 u_int32_t ctrl; 85 u_int32_t addr; 86 }; 87 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 88 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 89 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 90 #define CTRL_EOF 0x40000000 /* end of frame */ 91 #define CTRL_SOF 0x80000000 /* start of frame */ 92 93 /* Packet status is returned in a pre-packet header */ 94 struct rx_pph { 95 u_int16_t len; 96 u_int16_t flags; 97 u_int16_t pad[12]; 98 }; 99 100 /* packet status flags bits */ 101 #define RXF_NO 0x8 /* odd number of nibbles */ 102 #define RXF_RXER 0x4 /* receive symbol error */ 103 #define RXF_CRC 0x2 /* crc error */ 104 #define RXF_OV 0x1 /* fifo overflow */ 105 106 /* number of descriptors used in a ring */ 107 #define BCE_NRXDESC 128 108 #define BCE_NTXDESC 128 109 110 /* 111 * Mbuf pointers. We need these to keep track of the virtual addresses 112 * of our mbuf chains since we can only convert from physical to virtual, 113 * not the other way around. 114 */ 115 struct bce_chain_data { 116 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 117 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 118 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 119 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 120 }; 121 122 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 123 124 struct bce_softc { 125 struct device bce_dev; 126 bus_space_tag_t bce_btag; 127 bus_space_handle_t bce_bhandle; 128 bus_dma_tag_t bce_dmatag; 129 struct ethercom ethercom; /* interface info */ 130 void *bce_intrhand; 131 struct pci_attach_args bce_pa; 132 struct mii_data bce_mii; 133 u_int32_t bce_phy; /* eeprom indicated phy */ 134 struct ifmedia bce_ifmedia; /* media info *//* Check */ 135 u_int8_t enaddr[ETHER_ADDR_LEN]; 136 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 137 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 138 struct bce_chain_data bce_cdata; /* mbufs */ 139 bus_dmamap_t bce_ring_map; 140 u_int32_t bce_intmask; /* current intr mask */ 141 u_int32_t bce_rxin; /* last rx descriptor seen */ 142 u_int32_t bce_txin; /* last tx descriptor seen */ 143 int bce_txsfree; /* no. tx slots available */ 144 int bce_txsnext; /* next available tx slot */ 145 callout_t bce_timeout; 146 #if NRND > 0 147 rndsource_element_t rnd_source; 148 #endif 149 }; 150 151 /* for ring descriptors */ 152 #define BCE_RXBUF_LEN (MCLBYTES - 4) 153 #define BCE_INIT_RXDESC(sc, x) \ 154 do { \ 155 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 156 \ 157 *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0; \ 158 __bced->addr = \ 159 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 160 + 0x40000000); \ 161 if (x != (BCE_NRXDESC - 1)) \ 162 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 163 else \ 164 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 165 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 166 sizeof(struct bce_dma_slot) * x, \ 167 sizeof(struct bce_dma_slot), \ 168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 169 } while (/* CONSTCOND */ 0) 170 171 static int bce_probe(struct device *, struct cfdata *, void *); 172 static void bce_attach(struct device *, struct device *, void *); 173 static int bce_ioctl(struct ifnet *, u_long, void *); 174 static void bce_start(struct ifnet *); 175 static void bce_watchdog(struct ifnet *); 176 static int bce_intr(void *); 177 static void bce_rxintr(struct bce_softc *); 178 static void bce_txintr(struct bce_softc *); 179 static int bce_init(struct ifnet *); 180 static void bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long); 181 static int bce_add_rxbuf(struct bce_softc *, int); 182 static void bce_rxdrain(struct bce_softc *); 183 static void bce_stop(struct ifnet *, int); 184 static void bce_reset(struct bce_softc *); 185 static void bce_set_filter(struct ifnet *); 186 static int bce_mii_read(struct device *, int, int); 187 static void bce_mii_write(struct device *, int, int, int); 188 static void bce_statchg(struct device *); 189 static int bce_mediachange(struct ifnet *); 190 static void bce_mediastatus(struct ifnet *, struct ifmediareq *); 191 static void bce_tick(void *); 192 193 #define BCE_DEBUG 194 #ifdef BCE_DEBUG 195 #define DPRINTF(x) do { \ 196 if (bcedebug) \ 197 printf x; \ 198 } while (/* CONSTCOND */ 0) 199 #define DPRINTFN(n,x) do { \ 200 if (bcedebug >= (n)) \ 201 printf x; \ 202 } while (/* CONSTCOND */ 0) 203 int bcedebug = 0; 204 #else 205 #define DPRINTF(x) 206 #define DPRINTFN(n,x) 207 #endif 208 209 #if __NetBSD_Version__ >= 106080000 210 CFATTACH_DECL(bce, sizeof(struct bce_softc), 211 bce_probe, bce_attach, NULL, NULL); 212 #else 213 struct cfattach bce_ca = { 214 sizeof(struct bce_softc), bce_probe, bce_attach 215 }; 216 #endif 217 218 #if __NetBSD_Version__ >= 106120000 219 #define APRINT_ERROR aprint_error 220 #define APRINT_NORMAL aprint_normal 221 #else 222 #define APRINT_ERROR printf 223 #define APRINT_NORMAL printf 224 #endif 225 226 227 static const struct bce_product { 228 pci_vendor_id_t bp_vendor; 229 pci_product_id_t bp_product; 230 const char *bp_name; 231 } bce_products[] = { 232 { 233 PCI_VENDOR_BROADCOM, 234 PCI_PRODUCT_BROADCOM_BCM4401, 235 "Broadcom BCM4401 10/100 Ethernet" 236 }, 237 { 238 PCI_VENDOR_BROADCOM, 239 PCI_PRODUCT_BROADCOM_BCM4401_B0, 240 "Broadcom BCM4401-B0 10/100 Ethernet" 241 }, 242 { 243 244 0, 245 0, 246 NULL 247 }, 248 }; 249 250 static const struct bce_product * 251 bce_lookup(const struct pci_attach_args * pa) 252 { 253 const struct bce_product *bp; 254 255 for (bp = bce_products; bp->bp_name != NULL; bp++) { 256 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 257 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 258 return (bp); 259 } 260 261 return (NULL); 262 } 263 264 /* 265 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 266 * against drivers product list, and return its name if a match is found. 267 */ 268 static int 269 bce_probe(struct device *parent, struct cfdata *match, 270 void *aux) 271 { 272 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 273 274 if (bce_lookup(pa) != NULL) 275 return (1); 276 277 return (0); 278 } 279 280 static void 281 bce_attach(struct device *parent, struct device *self, void *aux) 282 { 283 struct bce_softc *sc = (struct bce_softc *) self; 284 struct pci_attach_args *pa = aux; 285 const struct bce_product *bp; 286 pci_chipset_tag_t pc = pa->pa_pc; 287 pci_intr_handle_t ih; 288 const char *intrstr = NULL; 289 void * kva; 290 bus_dma_segment_t seg; 291 int rseg; 292 u_int32_t command; 293 struct ifnet *ifp; 294 pcireg_t memtype; 295 bus_addr_t memaddr; 296 bus_size_t memsize; 297 int pmreg; 298 pcireg_t pmode; 299 int error; 300 int i; 301 302 bp = bce_lookup(pa); 303 KASSERT(bp != NULL); 304 305 sc->bce_pa = *pa; 306 307 /* BCM440x can only address 30 bits (1GB) */ 308 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 309 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) 310 { 311 APRINT_ERROR("WARNING: %s failed to restrict dma range," 312 " falling back to parent bus dma range\n", 313 sc->bce_dev.dv_xname); 314 sc->bce_dmatag = pa->pa_dmat; 315 } 316 317 #if __NetBSD_Version__ >= 106120000 318 aprint_naive(": Ethernet controller\n"); 319 #endif 320 APRINT_NORMAL(": %s\n", bp->bp_name); 321 322 /* 323 * Map control/status registers. 324 */ 325 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 326 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 327 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 328 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 329 330 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 331 APRINT_ERROR("%s: failed to enable memory mapping!\n", 332 sc->bce_dev.dv_xname); 333 return; 334 } 335 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 336 switch (memtype) { 337 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 338 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 339 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 340 &sc->bce_bhandle, &memaddr, &memsize) == 0) 341 break; 342 default: 343 APRINT_ERROR("%s: unable to find mem space\n", 344 sc->bce_dev.dv_xname); 345 return; 346 } 347 348 /* Get it out of power save mode if needed. */ 349 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 350 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 351 if (pmode == 3) { 352 /* 353 * The card has lost all configuration data in 354 * this state, so punt. 355 */ 356 printf("%s: unable to wake up from power state D3\n", 357 sc->bce_dev.dv_xname); 358 return; 359 } 360 if (pmode != 0) { 361 printf("%s: waking up from power state D%d\n", 362 sc->bce_dev.dv_xname, pmode); 363 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 364 } 365 } 366 if (pci_intr_map(pa, &ih)) { 367 APRINT_ERROR("%s: couldn't map interrupt\n", 368 sc->bce_dev.dv_xname); 369 return; 370 } 371 intrstr = pci_intr_string(pc, ih); 372 373 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 374 375 if (sc->bce_intrhand == NULL) { 376 APRINT_ERROR("%s: couldn't establish interrupt", 377 sc->bce_dev.dv_xname); 378 if (intrstr != NULL) 379 APRINT_NORMAL(" at %s", intrstr); 380 APRINT_NORMAL("\n"); 381 return; 382 } 383 APRINT_NORMAL("%s: interrupting at %s\n", 384 sc->bce_dev.dv_xname, intrstr); 385 386 /* reset the chip */ 387 bce_reset(sc); 388 389 /* 390 * Allocate DMA-safe memory for ring descriptors. 391 * The receive, and transmit rings can not share the same 392 * 4k space, however both are allocated at once here. 393 */ 394 /* 395 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 396 * due to the limition above. ?? 397 */ 398 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 399 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 400 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 401 printf("%s: unable to alloc space for ring descriptors, " 402 "error = %d\n", sc->bce_dev.dv_xname, error); 403 return; 404 } 405 /* map ring space to kernel */ 406 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 407 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 408 printf("%s: unable to map DMA buffers, error = %d\n", 409 sc->bce_dev.dv_xname, error); 410 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 411 return; 412 } 413 /* create a dma map for the ring */ 414 if ((error = bus_dmamap_create(sc->bce_dmatag, 415 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 416 &sc->bce_ring_map))) { 417 printf("%s: unable to create ring DMA map, error = %d\n", 418 sc->bce_dev.dv_xname, error); 419 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 420 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 421 return; 422 } 423 /* connect the ring space to the dma map */ 424 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 425 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 426 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 427 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 428 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 429 return; 430 } 431 /* save the ring space in softc */ 432 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 433 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 434 435 /* Create the transmit buffer DMA maps. */ 436 for (i = 0; i < BCE_NTXDESC; i++) { 437 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 438 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 439 printf("%s: unable to create tx DMA map, error = %d\n", 440 sc->bce_dev.dv_xname, error); 441 } 442 sc->bce_cdata.bce_tx_chain[i] = NULL; 443 } 444 445 /* Create the receive buffer DMA maps. */ 446 for (i = 0; i < BCE_NRXDESC; i++) { 447 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 448 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 449 printf("%s: unable to create rx DMA map, error = %d\n", 450 sc->bce_dev.dv_xname, error); 451 } 452 sc->bce_cdata.bce_rx_chain[i] = NULL; 453 } 454 455 /* Set up ifnet structure */ 456 ifp = &sc->ethercom.ec_if; 457 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 458 ifp->if_softc = sc; 459 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 460 ifp->if_ioctl = bce_ioctl; 461 ifp->if_start = bce_start; 462 ifp->if_watchdog = bce_watchdog; 463 ifp->if_init = bce_init; 464 ifp->if_stop = bce_stop; 465 IFQ_SET_READY(&ifp->if_snd); 466 467 /* Initialize our media structures and probe the MII. */ 468 469 sc->bce_mii.mii_ifp = ifp; 470 sc->bce_mii.mii_readreg = bce_mii_read; 471 sc->bce_mii.mii_writereg = bce_mii_write; 472 sc->bce_mii.mii_statchg = bce_statchg; 473 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 474 bce_mediastatus); 475 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 476 MII_OFFSET_ANY, 0); 477 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 478 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 479 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 480 } else 481 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 482 /* get the phy */ 483 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 484 BCE_MAGIC_PHY) & 0x1f; 485 /* 486 * Enable activity led. 487 * XXX This should be in a phy driver, but not currently. 488 */ 489 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 490 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 491 /* enable traffic meter led mode */ 492 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 493 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 494 495 496 /* Attach the interface */ 497 if_attach(ifp); 498 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 499 BCE_MAGIC_ENET0); 500 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 501 BCE_MAGIC_ENET1); 502 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 503 BCE_MAGIC_ENET2); 504 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 505 BCE_MAGIC_ENET3); 506 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 507 BCE_MAGIC_ENET4); 508 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 509 BCE_MAGIC_ENET5); 510 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 511 ether_sprintf(sc->enaddr)); 512 ether_ifattach(ifp, sc->enaddr); 513 #if NRND > 0 514 rnd_attach_source(&sc->rnd_source, sc->bce_dev.dv_xname, 515 RND_TYPE_NET, 0); 516 #endif 517 callout_init(&sc->bce_timeout, 0); 518 } 519 520 /* handle media, and ethernet requests */ 521 static int 522 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 523 { 524 struct bce_softc *sc = ifp->if_softc; 525 struct ifreq *ifr = (struct ifreq *) data; 526 int s, error; 527 528 s = splnet(); 529 switch (cmd) { 530 case SIOCSIFMEDIA: 531 case SIOCGIFMEDIA: 532 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 533 break; 534 default: 535 error = ether_ioctl(ifp, cmd, data); 536 if (error == ENETRESET) { 537 /* change multicast list */ 538 error = 0; 539 } 540 break; 541 } 542 543 /* Try to get more packets going. */ 544 bce_start(ifp); 545 546 splx(s); 547 return error; 548 } 549 550 /* Start packet transmission on the interface. */ 551 static void 552 bce_start(struct ifnet *ifp) 553 { 554 struct bce_softc *sc = ifp->if_softc; 555 struct mbuf *m0; 556 bus_dmamap_t dmamap; 557 int txstart; 558 int txsfree; 559 int newpkts = 0; 560 int error; 561 562 /* 563 * do not start another if currently transmitting, and more 564 * descriptors(tx slots) are needed for next packet. 565 */ 566 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 567 return; 568 569 /* determine number of descriptors available */ 570 if (sc->bce_txsnext >= sc->bce_txin) 571 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 572 else 573 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 574 575 /* 576 * Loop through the send queue, setting up transmit descriptors 577 * until we drain the queue, or use up all available transmit 578 * descriptors. 579 */ 580 while (txsfree > 0) { 581 int seg; 582 583 /* Grab a packet off the queue. */ 584 IFQ_POLL(&ifp->if_snd, m0); 585 if (m0 == NULL) 586 break; 587 588 /* get the transmit slot dma map */ 589 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 590 591 /* 592 * Load the DMA map. If this fails, the packet either 593 * didn't fit in the alloted number of segments, or we 594 * were short on resources. If the packet will not fit, 595 * it will be dropped. If short on resources, it will 596 * be tried again later. 597 */ 598 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 599 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 600 if (error == EFBIG) { 601 printf("%s: Tx packet consumes too many DMA segments, " 602 "dropping...\n", sc->bce_dev.dv_xname); 603 IFQ_DEQUEUE(&ifp->if_snd, m0); 604 m_freem(m0); 605 ifp->if_oerrors++; 606 continue; 607 } else if (error) { 608 /* short on resources, come back later */ 609 printf("%s: unable to load Tx buffer, error = %d\n", 610 sc->bce_dev.dv_xname, error); 611 break; 612 } 613 /* If not enough descriptors available, try again later */ 614 if (dmamap->dm_nsegs > txsfree) { 615 ifp->if_flags |= IFF_OACTIVE; 616 bus_dmamap_unload(sc->bce_dmatag, dmamap); 617 break; 618 } 619 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 620 621 /* So take it off the queue */ 622 IFQ_DEQUEUE(&ifp->if_snd, m0); 623 624 /* save the pointer so it can be freed later */ 625 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 626 627 /* Sync the data DMA map. */ 628 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 629 BUS_DMASYNC_PREWRITE); 630 631 /* Initialize the transmit descriptor(s). */ 632 txstart = sc->bce_txsnext; 633 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 634 u_int32_t ctrl; 635 636 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 637 if (seg == 0) 638 ctrl |= CTRL_SOF; 639 if (seg == dmamap->dm_nsegs - 1) 640 ctrl |= CTRL_EOF; 641 if (sc->bce_txsnext == BCE_NTXDESC - 1) 642 ctrl |= CTRL_EOT; 643 ctrl |= CTRL_IOC; 644 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 645 sc->bce_tx_ring[sc->bce_txsnext].addr = 646 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 647 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 648 sc->bce_txsnext = 0; 649 else 650 sc->bce_txsnext++; 651 txsfree--; 652 } 653 /* sync descriptors being used */ 654 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 655 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 656 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 657 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 658 659 /* Give the packet to the chip. */ 660 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 661 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 662 663 newpkts++; 664 665 #if NBPFILTER > 0 666 /* Pass the packet to any BPF listeners. */ 667 if (ifp->if_bpf) 668 bpf_mtap(ifp->if_bpf, m0); 669 #endif /* NBPFILTER > 0 */ 670 } 671 if (txsfree == 0) { 672 /* No more slots left; notify upper layer. */ 673 ifp->if_flags |= IFF_OACTIVE; 674 } 675 if (newpkts) { 676 /* Set a watchdog timer in case the chip flakes out. */ 677 ifp->if_timer = 5; 678 } 679 } 680 681 /* Watchdog timer handler. */ 682 static void 683 bce_watchdog(struct ifnet *ifp) 684 { 685 struct bce_softc *sc = ifp->if_softc; 686 687 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 688 ifp->if_oerrors++; 689 690 (void) bce_init(ifp); 691 692 /* Try to get more packets going. */ 693 bce_start(ifp); 694 } 695 696 int 697 bce_intr(void *xsc) 698 { 699 struct bce_softc *sc; 700 struct ifnet *ifp; 701 u_int32_t intstatus; 702 int wantinit; 703 int handled = 0; 704 705 sc = xsc; 706 ifp = &sc->ethercom.ec_if; 707 708 709 for (wantinit = 0; wantinit == 0;) { 710 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 711 BCE_INT_STS); 712 713 /* ignore if not ours, or unsolicited interrupts */ 714 intstatus &= sc->bce_intmask; 715 if (intstatus == 0) 716 break; 717 718 handled = 1; 719 720 /* Ack interrupt */ 721 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 722 intstatus); 723 724 /* Receive interrupts. */ 725 if (intstatus & I_RI) 726 bce_rxintr(sc); 727 /* Transmit interrupts. */ 728 if (intstatus & I_XI) 729 bce_txintr(sc); 730 /* Error interrupts */ 731 if (intstatus & ~(I_RI | I_XI)) { 732 if (intstatus & I_XU) 733 printf("%s: transmit fifo underflow\n", 734 sc->bce_dev.dv_xname); 735 if (intstatus & I_RO) { 736 printf("%s: receive fifo overflow\n", 737 sc->bce_dev.dv_xname); 738 ifp->if_ierrors++; 739 } 740 if (intstatus & I_RU) 741 printf("%s: receive descriptor underflow\n", 742 sc->bce_dev.dv_xname); 743 if (intstatus & I_DE) 744 printf("%s: descriptor protocol error\n", 745 sc->bce_dev.dv_xname); 746 if (intstatus & I_PD) 747 printf("%s: data error\n", 748 sc->bce_dev.dv_xname); 749 if (intstatus & I_PC) 750 printf("%s: descriptor error\n", 751 sc->bce_dev.dv_xname); 752 if (intstatus & I_TO) 753 printf("%s: general purpose timeout\n", 754 sc->bce_dev.dv_xname); 755 wantinit = 1; 756 } 757 } 758 759 if (handled) { 760 if (wantinit) 761 bce_init(ifp); 762 #if NRND > 0 763 if (RND_ENABLED(&sc->rnd_source)) 764 rnd_add_uint32(&sc->rnd_source, intstatus); 765 #endif 766 /* Try to get more packets going. */ 767 bce_start(ifp); 768 } 769 return (handled); 770 } 771 772 /* Receive interrupt handler */ 773 void 774 bce_rxintr(struct bce_softc *sc) 775 { 776 struct ifnet *ifp = &sc->ethercom.ec_if; 777 struct rx_pph *pph; 778 struct mbuf *m; 779 int curr; 780 int len; 781 int i; 782 783 /* get pointer to active receive slot */ 784 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 785 & RS_CD_MASK; 786 curr = curr / sizeof(struct bce_dma_slot); 787 if (curr >= BCE_NRXDESC) 788 curr = BCE_NRXDESC - 1; 789 790 /* process packets up to but not current packet being worked on */ 791 for (i = sc->bce_rxin; i != curr; 792 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 793 /* complete any post dma memory ops on packet */ 794 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 795 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 796 BUS_DMASYNC_POSTREAD); 797 798 /* 799 * If the packet had an error, simply recycle the buffer, 800 * resetting the len, and flags. 801 */ 802 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 803 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 804 ifp->if_ierrors++; 805 pph->len = 0; 806 pph->flags = 0; 807 continue; 808 } 809 /* receive the packet */ 810 len = pph->len; 811 if (len == 0) 812 continue; /* no packet if empty */ 813 pph->len = 0; 814 pph->flags = 0; 815 /* bump past pre header to packet */ 816 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 817 818 /* 819 * The chip includes the CRC with every packet. Trim 820 * it off here. 821 */ 822 len -= ETHER_CRC_LEN; 823 824 /* 825 * If the packet is small enough to fit in a 826 * single header mbuf, allocate one and copy 827 * the data into it. This greatly reduces 828 * memory consumption when receiving lots 829 * of small packets. 830 * 831 * Otherwise, add a new buffer to the receive 832 * chain. If this fails, drop the packet and 833 * recycle the old buffer. 834 */ 835 if (len <= (MHLEN - 2)) { 836 MGETHDR(m, M_DONTWAIT, MT_DATA); 837 if (m == NULL) 838 goto dropit; 839 m->m_data += 2; 840 memcpy(mtod(m, void *), 841 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 842 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 843 } else { 844 m = sc->bce_cdata.bce_rx_chain[i]; 845 if (bce_add_rxbuf(sc, i) != 0) { 846 dropit: 847 ifp->if_ierrors++; 848 /* continue to use old buffer */ 849 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 850 bus_dmamap_sync(sc->bce_dmatag, 851 sc->bce_cdata.bce_rx_map[i], 0, 852 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 853 BUS_DMASYNC_PREREAD); 854 continue; 855 } 856 } 857 858 m->m_pkthdr.rcvif = ifp; 859 m->m_pkthdr.len = m->m_len = len; 860 ifp->if_ipackets++; 861 862 #if NBPFILTER > 0 863 /* 864 * Pass this up to any BPF listeners, but only 865 * pass it up the stack if it's for us. 866 */ 867 if (ifp->if_bpf) 868 bpf_mtap(ifp->if_bpf, m); 869 #endif /* NBPFILTER > 0 */ 870 871 /* Pass it on. */ 872 (*ifp->if_input) (ifp, m); 873 874 /* re-check current in case it changed */ 875 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 876 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 877 sizeof(struct bce_dma_slot); 878 if (curr >= BCE_NRXDESC) 879 curr = BCE_NRXDESC - 1; 880 } 881 sc->bce_rxin = curr; 882 } 883 884 /* Transmit interrupt handler */ 885 void 886 bce_txintr(struct bce_softc *sc) 887 { 888 struct ifnet *ifp = &sc->ethercom.ec_if; 889 int curr; 890 int i; 891 892 ifp->if_flags &= ~IFF_OACTIVE; 893 894 /* 895 * Go through the Tx list and free mbufs for those 896 * frames which have been transmitted. 897 */ 898 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 899 RS_CD_MASK; 900 curr = curr / sizeof(struct bce_dma_slot); 901 if (curr >= BCE_NTXDESC) 902 curr = BCE_NTXDESC - 1; 903 for (i = sc->bce_txin; i != curr; 904 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 905 /* do any post dma memory ops on transmit data */ 906 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 907 continue; 908 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 909 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 910 BUS_DMASYNC_POSTWRITE); 911 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 912 m_freem(sc->bce_cdata.bce_tx_chain[i]); 913 sc->bce_cdata.bce_tx_chain[i] = NULL; 914 ifp->if_opackets++; 915 } 916 sc->bce_txin = curr; 917 918 /* 919 * If there are no more pending transmissions, cancel the watchdog 920 * timer 921 */ 922 if (sc->bce_txsnext == sc->bce_txin) 923 ifp->if_timer = 0; 924 } 925 926 /* initialize the interface */ 927 static int 928 bce_init(struct ifnet *ifp) 929 { 930 struct bce_softc *sc = ifp->if_softc; 931 u_int32_t reg_win; 932 int error; 933 int i; 934 935 /* Cancel any pending I/O. */ 936 bce_stop(ifp, 0); 937 938 /* enable pci inerrupts, bursts, and prefetch */ 939 940 /* remap the pci registers to the Sonics config registers */ 941 942 /* save the current map, so it can be restored */ 943 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 944 BCE_REG_WIN); 945 946 /* set register window to Sonics registers */ 947 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 948 BCE_SONICS_WIN); 949 950 /* enable SB to PCI interrupt */ 951 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 952 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 953 SBIV_ENET0); 954 955 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 956 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 957 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 958 SBTOPCI_PREF | SBTOPCI_BURST); 959 960 /* restore to ethernet register space */ 961 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 962 reg_win); 963 964 /* Reset the chip to a known state. */ 965 bce_reset(sc); 966 967 /* Initialize transmit descriptors */ 968 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 969 sc->bce_txsnext = 0; 970 sc->bce_txin = 0; 971 972 /* enable crc32 generation */ 973 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 974 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 975 BCE_EMC_CG); 976 977 /* setup DMA interrupt control */ 978 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 979 980 /* setup packet filter */ 981 bce_set_filter(ifp); 982 983 /* set max frame length, account for possible vlan tag */ 984 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 985 ETHER_MAX_LEN + 32); 986 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 987 ETHER_MAX_LEN + 32); 988 989 /* set tx watermark */ 990 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 991 992 /* enable transmit */ 993 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 994 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 995 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 996 997 /* 998 * Give the receive ring to the chip, and 999 * start the receive DMA engine. 1000 */ 1001 sc->bce_rxin = 0; 1002 1003 /* clear the rx descriptor ring */ 1004 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 1005 /* enable receive */ 1006 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 1007 30 << 1 | 1); /* MAGIC */ 1008 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 1009 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 1010 1011 /* Initalize receive descriptors */ 1012 for (i = 0; i < BCE_NRXDESC; i++) { 1013 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 1014 if ((error = bce_add_rxbuf(sc, i)) != 0) { 1015 printf("%s: unable to allocate or map rx(%d) " 1016 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 1017 i, error); 1018 bce_rxdrain(sc); 1019 return (error); 1020 } 1021 } else 1022 BCE_INIT_RXDESC(sc, i); 1023 } 1024 1025 /* Enable interrupts */ 1026 sc->bce_intmask = 1027 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 1028 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 1029 sc->bce_intmask); 1030 1031 /* start the receive dma */ 1032 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 1033 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 1034 1035 /* set media */ 1036 mii_mediachg(&sc->bce_mii); 1037 1038 /* turn on the ethernet mac */ 1039 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1040 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1041 BCE_ENET_CTL) | EC_EE); 1042 1043 /* start timer */ 1044 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1045 1046 /* mark as running, and no outputs active */ 1047 ifp->if_flags |= IFF_RUNNING; 1048 ifp->if_flags &= ~IFF_OACTIVE; 1049 1050 return 0; 1051 } 1052 1053 /* add a mac address to packet filter */ 1054 void 1055 bce_add_mac(struct bce_softc *sc, u_int8_t *mac, u_long idx) 1056 { 1057 int i; 1058 u_int32_t rval; 1059 1060 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1061 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1062 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1063 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1064 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1065 idx << 16 | 8); /* MAGIC */ 1066 /* wait for write to complete */ 1067 for (i = 0; i < 100; i++) { 1068 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1069 BCE_FILT_CTL); 1070 if (!(rval & 0x80000000)) /* MAGIC */ 1071 break; 1072 delay(10); 1073 } 1074 if (i == 100) { 1075 printf("%s: timed out writing pkt filter ctl\n", 1076 sc->bce_dev.dv_xname); 1077 } 1078 } 1079 1080 /* Add a receive buffer to the indiciated descriptor. */ 1081 static int 1082 bce_add_rxbuf(struct bce_softc *sc, int idx) 1083 { 1084 struct mbuf *m; 1085 int error; 1086 1087 MGETHDR(m, M_DONTWAIT, MT_DATA); 1088 if (m == NULL) 1089 return (ENOBUFS); 1090 1091 MCLGET(m, M_DONTWAIT); 1092 if ((m->m_flags & M_EXT) == 0) { 1093 m_freem(m); 1094 return (ENOBUFS); 1095 } 1096 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1097 bus_dmamap_unload(sc->bce_dmatag, 1098 sc->bce_cdata.bce_rx_map[idx]); 1099 1100 sc->bce_cdata.bce_rx_chain[idx] = m; 1101 1102 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1103 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1104 BUS_DMA_READ | BUS_DMA_NOWAIT); 1105 if (error) 1106 return (error); 1107 1108 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1109 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1110 1111 BCE_INIT_RXDESC(sc, idx); 1112 1113 return (0); 1114 1115 } 1116 1117 /* Drain the receive queue. */ 1118 static void 1119 bce_rxdrain(struct bce_softc *sc) 1120 { 1121 int i; 1122 1123 for (i = 0; i < BCE_NRXDESC; i++) { 1124 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1125 bus_dmamap_unload(sc->bce_dmatag, 1126 sc->bce_cdata.bce_rx_map[i]); 1127 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1128 sc->bce_cdata.bce_rx_chain[i] = NULL; 1129 } 1130 } 1131 } 1132 1133 /* Stop transmission on the interface */ 1134 static void 1135 bce_stop(struct ifnet *ifp, int disable) 1136 { 1137 struct bce_softc *sc = ifp->if_softc; 1138 int i; 1139 u_int32_t val; 1140 1141 /* Stop the 1 second timer */ 1142 callout_stop(&sc->bce_timeout); 1143 1144 /* Down the MII. */ 1145 mii_down(&sc->bce_mii); 1146 1147 /* Disable interrupts. */ 1148 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1149 sc->bce_intmask = 0; 1150 delay(10); 1151 1152 /* Disable emac */ 1153 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1154 for (i = 0; i < 200; i++) { 1155 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1156 BCE_ENET_CTL); 1157 if (!(val & EC_ED)) 1158 break; 1159 delay(10); 1160 } 1161 1162 /* Stop the DMA */ 1163 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1164 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1165 delay(10); 1166 1167 /* Release any queued transmit buffers. */ 1168 for (i = 0; i < BCE_NTXDESC; i++) { 1169 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1170 bus_dmamap_unload(sc->bce_dmatag, 1171 sc->bce_cdata.bce_tx_map[i]); 1172 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1173 sc->bce_cdata.bce_tx_chain[i] = NULL; 1174 } 1175 } 1176 1177 /* drain receive queue */ 1178 if (disable) 1179 bce_rxdrain(sc); 1180 1181 /* Mark the interface down and cancel the watchdog timer. */ 1182 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1183 ifp->if_timer = 0; 1184 } 1185 1186 /* reset the chip */ 1187 static void 1188 bce_reset(struct bce_softc *sc) 1189 { 1190 u_int32_t val; 1191 u_int32_t sbval; 1192 int i; 1193 1194 /* if SB core is up */ 1195 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1196 BCE_SBTMSTATELOW); 1197 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1198 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1199 0); 1200 1201 /* disable emac */ 1202 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1203 EC_ED); 1204 for (i = 0; i < 200; i++) { 1205 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1206 BCE_ENET_CTL); 1207 if (!(val & EC_ED)) 1208 break; 1209 delay(10); 1210 } 1211 if (i == 200) 1212 printf("%s: timed out disabling ethernet mac\n", 1213 sc->bce_dev.dv_xname); 1214 1215 /* reset the dma engines */ 1216 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1217 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1218 /* if error on receive, wait to go idle */ 1219 if (val & RS_ERROR) { 1220 for (i = 0; i < 100; i++) { 1221 val = bus_space_read_4(sc->bce_btag, 1222 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1223 if (val & RS_DMA_IDLE) 1224 break; 1225 delay(10); 1226 } 1227 if (i == 100) 1228 printf("%s: receive dma did not go idle after" 1229 " error\n", sc->bce_dev.dv_xname); 1230 } 1231 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1232 BCE_DMA_RXSTATUS, 0); 1233 1234 /* reset ethernet mac */ 1235 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1236 EC_ES); 1237 for (i = 0; i < 200; i++) { 1238 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1239 BCE_ENET_CTL); 1240 if (!(val & EC_ES)) 1241 break; 1242 delay(10); 1243 } 1244 if (i == 200) 1245 printf("%s: timed out restting ethernet mac\n", 1246 sc->bce_dev.dv_xname); 1247 } else { 1248 u_int32_t reg_win; 1249 1250 /* remap the pci registers to the Sonics config registers */ 1251 1252 /* save the current map, so it can be restored */ 1253 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1254 BCE_REG_WIN); 1255 /* set register window to Sonics registers */ 1256 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1257 BCE_REG_WIN, BCE_SONICS_WIN); 1258 1259 /* enable SB to PCI interrupt */ 1260 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1261 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1262 BCE_SBINTVEC) | 1263 SBIV_ENET0); 1264 1265 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1266 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1267 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1268 BCE_SPCI_TR2) | 1269 SBTOPCI_PREF | SBTOPCI_BURST); 1270 1271 /* restore to ethernet register space */ 1272 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1273 reg_win); 1274 } 1275 1276 /* disable SB core if not in reset */ 1277 if (!(sbval & SBTML_RESET)) { 1278 1279 /* set the reject bit */ 1280 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1281 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1282 for (i = 0; i < 200; i++) { 1283 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1284 BCE_SBTMSTATELOW); 1285 if (val & SBTML_REJ) 1286 break; 1287 delay(1); 1288 } 1289 if (i == 200) 1290 printf("%s: while restting core, reject did not set\n", 1291 sc->bce_dev.dv_xname); 1292 /* wait until busy is clear */ 1293 for (i = 0; i < 200; i++) { 1294 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1295 BCE_SBTMSTATEHI); 1296 if (!(val & 0x4)) 1297 break; 1298 delay(1); 1299 } 1300 if (i == 200) 1301 printf("%s: while restting core, busy did not clear\n", 1302 sc->bce_dev.dv_xname); 1303 /* set reset and reject while enabling the clocks */ 1304 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1305 BCE_SBTMSTATELOW, 1306 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1307 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1308 BCE_SBTMSTATELOW); 1309 delay(10); 1310 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1311 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1312 delay(1); 1313 } 1314 /* enable clock */ 1315 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1316 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1317 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1318 delay(1); 1319 1320 /* clear any error bits that may be on */ 1321 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1322 if (val & 1) 1323 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1324 0); 1325 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1326 if (val & SBIM_MAGIC_ERRORBITS) 1327 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1328 val & ~SBIM_MAGIC_ERRORBITS); 1329 1330 /* clear reset and allow it to propagate throughout the core */ 1331 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1332 SBTML_FGC | SBTML_CLK); 1333 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1334 delay(1); 1335 1336 /* leave clock enabled */ 1337 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1338 SBTML_CLK); 1339 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1340 delay(1); 1341 1342 /* initialize MDC preamble, frequency */ 1343 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1344 1345 /* enable phy, differs for internal, and external */ 1346 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1347 if (!(val & BCE_DC_IP)) { 1348 /* select external phy */ 1349 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1350 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1351 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1352 val & ~BCE_DC_ER); 1353 delay(100); 1354 } 1355 } 1356 1357 /* Set up the receive filter. */ 1358 void 1359 bce_set_filter(struct ifnet *ifp) 1360 { 1361 struct bce_softc *sc = ifp->if_softc; 1362 1363 if (ifp->if_flags & IFF_PROMISC) { 1364 ifp->if_flags |= IFF_ALLMULTI; 1365 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1366 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1367 | ERC_PE); 1368 } else { 1369 ifp->if_flags &= ~IFF_ALLMULTI; 1370 1371 /* turn off promiscuous */ 1372 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1373 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1374 BCE_RX_CTL) & ~ERC_PE); 1375 1376 /* enable/disable broadcast */ 1377 if (ifp->if_flags & IFF_BROADCAST) 1378 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1379 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1380 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1381 else 1382 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1383 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1384 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1385 1386 /* disable the filter */ 1387 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1388 0); 1389 1390 /* add our own address */ 1391 bce_add_mac(sc, sc->enaddr, 0); 1392 1393 /* for now accept all multicast */ 1394 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1395 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1396 ERC_AM); 1397 ifp->if_flags |= IFF_ALLMULTI; 1398 1399 /* enable the filter */ 1400 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1401 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1402 BCE_FILT_CTL) | 1); 1403 } 1404 } 1405 1406 /* Read a PHY register on the MII. */ 1407 int 1408 bce_mii_read(struct device *self, int phy, int reg) 1409 { 1410 struct bce_softc *sc = (struct bce_softc *) self; 1411 int i; 1412 u_int32_t val; 1413 1414 /* clear mii_int */ 1415 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1416 1417 /* Read the PHY register */ 1418 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1419 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1420 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1421 1422 for (i = 0; i < BCE_TIMEOUT; i++) { 1423 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1424 if (val & BCE_MIINTR) 1425 break; 1426 delay(10); 1427 } 1428 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1429 if (i == BCE_TIMEOUT) { 1430 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1431 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1432 return (0); 1433 } 1434 return (val & BCE_MICOMM_DATA); 1435 } 1436 1437 /* Write a PHY register on the MII */ 1438 void 1439 bce_mii_write(struct device *self, int phy, int reg, int val) 1440 { 1441 struct bce_softc *sc = (struct bce_softc *) self; 1442 int i; 1443 u_int32_t rval; 1444 1445 /* clear mii_int */ 1446 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1447 BCE_MIINTR); 1448 1449 /* Write the PHY register */ 1450 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1451 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1452 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1453 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1454 1455 /* wait for write to complete */ 1456 for (i = 0; i < BCE_TIMEOUT; i++) { 1457 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1458 BCE_MI_STS); 1459 if (rval & BCE_MIINTR) 1460 break; 1461 delay(10); 1462 } 1463 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1464 if (i == BCE_TIMEOUT) { 1465 printf("%s: PHY timed out writing phy %d, reg %d, val " 1466 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1467 } 1468 } 1469 1470 /* sync hardware duplex mode to software state */ 1471 void 1472 bce_statchg(struct device *self) 1473 { 1474 struct bce_softc *sc = (struct bce_softc *) self; 1475 u_int32_t reg; 1476 1477 /* if needed, change register to match duplex mode */ 1478 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1479 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1480 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1481 reg | EXC_FD); 1482 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1483 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1484 reg & ~EXC_FD); 1485 1486 /* 1487 * Enable activity led. 1488 * XXX This should be in a phy driver, but not currently. 1489 */ 1490 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1491 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1492 /* enable traffic meter led mode */ 1493 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1494 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1495 } 1496 1497 /* Set hardware to newly-selected media */ 1498 int 1499 bce_mediachange(struct ifnet *ifp) 1500 { 1501 struct bce_softc *sc = ifp->if_softc; 1502 1503 if (ifp->if_flags & IFF_UP) 1504 mii_mediachg(&sc->bce_mii); 1505 return (0); 1506 } 1507 1508 /* Get the current interface media status */ 1509 static void 1510 bce_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1511 { 1512 struct bce_softc *sc = ifp->if_softc; 1513 1514 mii_pollstat(&sc->bce_mii); 1515 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1516 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1517 } 1518 1519 /* One second timer, checks link status */ 1520 static void 1521 bce_tick(void *v) 1522 { 1523 struct bce_softc *sc = v; 1524 1525 /* Tick the MII. */ 1526 mii_tick(&sc->bce_mii); 1527 1528 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1529 } 1530