1 /* $NetBSD: if_bce.c,v 1.21 2008/01/30 12:00:35 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Clifford Wright. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 32 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 33 * 34 * Cliff Wright cliff@snipe444.org 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_bce.c,v 1.21 2008/01/30 12:00:35 simonb Exp $"); 39 40 #include "bpfilter.h" 41 #include "vlan.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/socket.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 #if NRND > 0 63 #include <sys/rnd.h> 64 #endif 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 #include <dev/mii/miidevs.h> 73 #include <dev/mii/brgphyreg.h> 74 75 #include <dev/pci/if_bcereg.h> 76 77 #include <uvm/uvm_extern.h> 78 79 /* transmit buffer max frags allowed */ 80 #define BCE_NTXFRAGS 16 81 82 /* ring descriptor */ 83 struct bce_dma_slot { 84 uint32_t ctrl; 85 uint32_t addr; 86 }; 87 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 88 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 89 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 90 #define CTRL_EOF 0x40000000 /* end of frame */ 91 #define CTRL_SOF 0x80000000 /* start of frame */ 92 93 /* Packet status is returned in a pre-packet header */ 94 struct rx_pph { 95 uint16_t len; 96 uint16_t flags; 97 uint16_t pad[12]; 98 }; 99 100 /* packet status flags bits */ 101 #define RXF_NO 0x8 /* odd number of nibbles */ 102 #define RXF_RXER 0x4 /* receive symbol error */ 103 #define RXF_CRC 0x2 /* crc error */ 104 #define RXF_OV 0x1 /* fifo overflow */ 105 106 /* number of descriptors used in a ring */ 107 #define BCE_NRXDESC 128 108 #define BCE_NTXDESC 128 109 110 /* 111 * Mbuf pointers. We need these to keep track of the virtual addresses 112 * of our mbuf chains since we can only convert from physical to virtual, 113 * not the other way around. 114 */ 115 struct bce_chain_data { 116 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 117 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 118 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 119 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 120 }; 121 122 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 123 124 struct bce_softc { 125 struct device bce_dev; 126 bus_space_tag_t bce_btag; 127 bus_space_handle_t bce_bhandle; 128 bus_dma_tag_t bce_dmatag; 129 struct ethercom ethercom; /* interface info */ 130 void *bce_intrhand; 131 struct pci_attach_args bce_pa; 132 struct mii_data bce_mii; 133 uint32_t bce_phy; /* eeprom indicated phy */ 134 struct ifmedia bce_ifmedia; /* media info *//* Check */ 135 uint8_t enaddr[ETHER_ADDR_LEN]; 136 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 137 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 138 struct bce_chain_data bce_cdata; /* mbufs */ 139 bus_dmamap_t bce_ring_map; 140 uint32_t bce_intmask; /* current intr mask */ 141 uint32_t bce_rxin; /* last rx descriptor seen */ 142 uint32_t bce_txin; /* last tx descriptor seen */ 143 int bce_txsfree; /* no. tx slots available */ 144 int bce_txsnext; /* next available tx slot */ 145 callout_t bce_timeout; 146 #if NRND > 0 147 rndsource_element_t rnd_source; 148 #endif 149 }; 150 151 /* for ring descriptors */ 152 #define BCE_RXBUF_LEN (MCLBYTES - 4) 153 #define BCE_INIT_RXDESC(sc, x) \ 154 do { \ 155 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 156 \ 157 *mtod(sc->bce_cdata.bce_rx_chain[x], uint32_t *) = 0; \ 158 __bced->addr = \ 159 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 160 + 0x40000000); \ 161 if (x != (BCE_NRXDESC - 1)) \ 162 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 163 else \ 164 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 165 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 166 sizeof(struct bce_dma_slot) * x, \ 167 sizeof(struct bce_dma_slot), \ 168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 169 } while (/* CONSTCOND */ 0) 170 171 static int bce_probe(struct device *, struct cfdata *, void *); 172 static void bce_attach(struct device *, struct device *, void *); 173 static int bce_ioctl(struct ifnet *, u_long, void *); 174 static void bce_start(struct ifnet *); 175 static void bce_watchdog(struct ifnet *); 176 static int bce_intr(void *); 177 static void bce_rxintr(struct bce_softc *); 178 static void bce_txintr(struct bce_softc *); 179 static int bce_init(struct ifnet *); 180 static void bce_add_mac(struct bce_softc *, uint8_t *, unsigned long); 181 static int bce_add_rxbuf(struct bce_softc *, int); 182 static void bce_rxdrain(struct bce_softc *); 183 static void bce_stop(struct ifnet *, int); 184 static void bce_reset(struct bce_softc *); 185 static bool bce_resume(device_t); 186 static void bce_set_filter(struct ifnet *); 187 static int bce_mii_read(struct device *, int, int); 188 static void bce_mii_write(struct device *, int, int, int); 189 static void bce_statchg(struct device *); 190 static void bce_tick(void *); 191 192 CFATTACH_DECL(bce, sizeof(struct bce_softc), bce_probe, bce_attach, NULL, NULL); 193 194 static const struct bce_product { 195 pci_vendor_id_t bp_vendor; 196 pci_product_id_t bp_product; 197 const char *bp_name; 198 } bce_products[] = { 199 { 200 PCI_VENDOR_BROADCOM, 201 PCI_PRODUCT_BROADCOM_BCM4401, 202 "Broadcom BCM4401 10/100 Ethernet" 203 }, 204 { 205 PCI_VENDOR_BROADCOM, 206 PCI_PRODUCT_BROADCOM_BCM4401_B0, 207 "Broadcom BCM4401-B0 10/100 Ethernet" 208 }, 209 { 210 211 0, 212 0, 213 NULL 214 }, 215 }; 216 217 static const struct bce_product * 218 bce_lookup(const struct pci_attach_args * pa) 219 { 220 const struct bce_product *bp; 221 222 for (bp = bce_products; bp->bp_name != NULL; bp++) { 223 if (PCI_VENDOR(pa->pa_id) == bp->bp_vendor && 224 PCI_PRODUCT(pa->pa_id) == bp->bp_product) 225 return (bp); 226 } 227 228 return (NULL); 229 } 230 231 /* 232 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 233 * against drivers product list, and return its name if a match is found. 234 */ 235 static int 236 bce_probe(struct device *parent, struct cfdata *match, 237 void *aux) 238 { 239 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 240 241 if (bce_lookup(pa) != NULL) 242 return (1); 243 244 return (0); 245 } 246 247 static void 248 bce_attach(struct device *parent, struct device *self, void *aux) 249 { 250 struct bce_softc *sc = (struct bce_softc *) self; 251 struct pci_attach_args *pa = aux; 252 const struct bce_product *bp; 253 pci_chipset_tag_t pc = pa->pa_pc; 254 pci_intr_handle_t ih; 255 const char *intrstr = NULL; 256 void *kva; 257 bus_dma_segment_t seg; 258 int rseg; 259 uint32_t command; 260 struct ifnet *ifp; 261 pcireg_t memtype; 262 bus_addr_t memaddr; 263 bus_size_t memsize; 264 int pmreg; 265 pcireg_t pmode; 266 int error; 267 int i; 268 269 bp = bce_lookup(pa); 270 KASSERT(bp != NULL); 271 272 sc->bce_pa = *pa; 273 274 /* BCM440x can only address 30 bits (1GB) */ 275 if (bus_dmatag_subregion(pa->pa_dmat, 0, (1 << 30), 276 &(sc->bce_dmatag), BUS_DMA_NOWAIT) != 0) { 277 aprint_error("WARNING: %s failed to restrict dma range," 278 " falling back to parent bus dma range\n", 279 sc->bce_dev.dv_xname); 280 sc->bce_dmatag = pa->pa_dmat; 281 } 282 283 aprint_naive(": Ethernet controller\n"); 284 aprint_normal(": %s\n", bp->bp_name); 285 286 /* 287 * Map control/status registers. 288 */ 289 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 290 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 291 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 292 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 293 294 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 295 aprint_error("%s: failed to enable memory mapping!\n", 296 sc->bce_dev.dv_xname); 297 return; 298 } 299 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 300 switch (memtype) { 301 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 302 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 303 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 304 &sc->bce_bhandle, &memaddr, &memsize) == 0) 305 break; 306 default: 307 aprint_error("%s: unable to find mem space\n", 308 sc->bce_dev.dv_xname); 309 return; 310 } 311 312 /* Get it out of power save mode if needed. */ 313 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 314 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 315 if (pmode == 3) { 316 /* 317 * The card has lost all configuration data in 318 * this state, so punt. 319 */ 320 printf("%s: unable to wake up from power state D3\n", 321 sc->bce_dev.dv_xname); 322 return; 323 } 324 if (pmode != 0) { 325 printf("%s: waking up from power state D%d\n", 326 sc->bce_dev.dv_xname, pmode); 327 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 328 } 329 } 330 if (pci_intr_map(pa, &ih)) { 331 aprint_error("%s: couldn't map interrupt\n", 332 sc->bce_dev.dv_xname); 333 return; 334 } 335 intrstr = pci_intr_string(pc, ih); 336 337 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc); 338 339 if (sc->bce_intrhand == NULL) { 340 aprint_error("%s: couldn't establish interrupt", 341 sc->bce_dev.dv_xname); 342 if (intrstr != NULL) 343 aprint_normal(" at %s", intrstr); 344 aprint_normal("\n"); 345 return; 346 } 347 aprint_normal("%s: interrupting at %s\n", 348 sc->bce_dev.dv_xname, intrstr); 349 350 /* reset the chip */ 351 bce_reset(sc); 352 353 /* 354 * Allocate DMA-safe memory for ring descriptors. 355 * The receive, and transmit rings can not share the same 356 * 4k space, however both are allocated at once here. 357 */ 358 /* 359 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 360 * due to the limition above. ?? 361 */ 362 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 363 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 364 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 365 printf("%s: unable to alloc space for ring descriptors, " 366 "error = %d\n", sc->bce_dev.dv_xname, error); 367 return; 368 } 369 /* map ring space to kernel */ 370 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 371 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 372 printf("%s: unable to map DMA buffers, error = %d\n", 373 sc->bce_dev.dv_xname, error); 374 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 375 return; 376 } 377 /* create a dma map for the ring */ 378 if ((error = bus_dmamap_create(sc->bce_dmatag, 379 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 380 &sc->bce_ring_map))) { 381 printf("%s: unable to create ring DMA map, error = %d\n", 382 sc->bce_dev.dv_xname, error); 383 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 384 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 385 return; 386 } 387 /* connect the ring space to the dma map */ 388 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 389 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 390 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 391 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 392 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 393 return; 394 } 395 /* save the ring space in softc */ 396 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 397 sc->bce_tx_ring = (struct bce_dma_slot *) ((char *)kva + PAGE_SIZE); 398 399 /* Create the transmit buffer DMA maps. */ 400 for (i = 0; i < BCE_NTXDESC; i++) { 401 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 402 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 403 printf("%s: unable to create tx DMA map, error = %d\n", 404 sc->bce_dev.dv_xname, error); 405 } 406 sc->bce_cdata.bce_tx_chain[i] = NULL; 407 } 408 409 /* Create the receive buffer DMA maps. */ 410 for (i = 0; i < BCE_NRXDESC; i++) { 411 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 412 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 413 printf("%s: unable to create rx DMA map, error = %d\n", 414 sc->bce_dev.dv_xname, error); 415 } 416 sc->bce_cdata.bce_rx_chain[i] = NULL; 417 } 418 419 /* Set up ifnet structure */ 420 ifp = &sc->ethercom.ec_if; 421 strcpy(ifp->if_xname, sc->bce_dev.dv_xname); 422 ifp->if_softc = sc; 423 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 424 ifp->if_ioctl = bce_ioctl; 425 ifp->if_start = bce_start; 426 ifp->if_watchdog = bce_watchdog; 427 ifp->if_init = bce_init; 428 ifp->if_stop = bce_stop; 429 IFQ_SET_READY(&ifp->if_snd); 430 431 /* Initialize our media structures and probe the MII. */ 432 433 sc->bce_mii.mii_ifp = ifp; 434 sc->bce_mii.mii_readreg = bce_mii_read; 435 sc->bce_mii.mii_writereg = bce_mii_write; 436 sc->bce_mii.mii_statchg = bce_statchg; 437 438 sc->ethercom.ec_mii = &sc->bce_mii; 439 ifmedia_init(&sc->bce_mii.mii_media, 0, ether_mediachange, 440 ether_mediastatus); 441 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 442 MII_OFFSET_ANY, 0); 443 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 444 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 445 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 446 } else 447 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 448 /* get the phy */ 449 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 450 BCE_MAGIC_PHY) & 0x1f; 451 /* 452 * Enable activity led. 453 * XXX This should be in a phy driver, but not currently. 454 */ 455 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 456 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 457 /* enable traffic meter led mode */ 458 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 459 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 460 461 462 /* Attach the interface */ 463 if_attach(ifp); 464 sc->enaddr[0] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 465 BCE_MAGIC_ENET0); 466 sc->enaddr[1] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 467 BCE_MAGIC_ENET1); 468 sc->enaddr[2] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 469 BCE_MAGIC_ENET2); 470 sc->enaddr[3] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 471 BCE_MAGIC_ENET3); 472 sc->enaddr[4] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 473 BCE_MAGIC_ENET4); 474 sc->enaddr[5] = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 475 BCE_MAGIC_ENET5); 476 printf("%s: Ethernet address %s\n", sc->bce_dev.dv_xname, 477 ether_sprintf(sc->enaddr)); 478 ether_ifattach(ifp, sc->enaddr); 479 #if NRND > 0 480 rnd_attach_source(&sc->rnd_source, sc->bce_dev.dv_xname, 481 RND_TYPE_NET, 0); 482 #endif 483 callout_init(&sc->bce_timeout, 0); 484 485 if (!pmf_device_register(self, NULL, bce_resume)) 486 aprint_error_dev(self, "couldn't establish power handler\n"); 487 else 488 pmf_class_network_register(self, ifp); 489 } 490 491 /* handle media, and ethernet requests */ 492 static int 493 bce_ioctl(struct ifnet *ifp, u_long cmd, void *data) 494 { 495 int s, error; 496 497 s = splnet(); 498 error = ether_ioctl(ifp, cmd, data); 499 if (error == ENETRESET) { 500 /* change multicast list */ 501 error = 0; 502 } 503 504 /* Try to get more packets going. */ 505 bce_start(ifp); 506 507 splx(s); 508 return error; 509 } 510 511 /* Start packet transmission on the interface. */ 512 static void 513 bce_start(struct ifnet *ifp) 514 { 515 struct bce_softc *sc = ifp->if_softc; 516 struct mbuf *m0; 517 bus_dmamap_t dmamap; 518 int txstart; 519 int txsfree; 520 int newpkts = 0; 521 int error; 522 523 /* 524 * do not start another if currently transmitting, and more 525 * descriptors(tx slots) are needed for next packet. 526 */ 527 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 528 return; 529 530 /* determine number of descriptors available */ 531 if (sc->bce_txsnext >= sc->bce_txin) 532 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 533 else 534 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 535 536 /* 537 * Loop through the send queue, setting up transmit descriptors 538 * until we drain the queue, or use up all available transmit 539 * descriptors. 540 */ 541 while (txsfree > 0) { 542 int seg; 543 544 /* Grab a packet off the queue. */ 545 IFQ_POLL(&ifp->if_snd, m0); 546 if (m0 == NULL) 547 break; 548 549 /* get the transmit slot dma map */ 550 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 551 552 /* 553 * Load the DMA map. If this fails, the packet either 554 * didn't fit in the alloted number of segments, or we 555 * were short on resources. If the packet will not fit, 556 * it will be dropped. If short on resources, it will 557 * be tried again later. 558 */ 559 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 560 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 561 if (error == EFBIG) { 562 printf("%s: Tx packet consumes too many DMA segments, " 563 "dropping...\n", sc->bce_dev.dv_xname); 564 IFQ_DEQUEUE(&ifp->if_snd, m0); 565 m_freem(m0); 566 ifp->if_oerrors++; 567 continue; 568 } else if (error) { 569 /* short on resources, come back later */ 570 printf("%s: unable to load Tx buffer, error = %d\n", 571 sc->bce_dev.dv_xname, error); 572 break; 573 } 574 /* If not enough descriptors available, try again later */ 575 if (dmamap->dm_nsegs > txsfree) { 576 ifp->if_flags |= IFF_OACTIVE; 577 bus_dmamap_unload(sc->bce_dmatag, dmamap); 578 break; 579 } 580 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 581 582 /* So take it off the queue */ 583 IFQ_DEQUEUE(&ifp->if_snd, m0); 584 585 /* save the pointer so it can be freed later */ 586 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 587 588 /* Sync the data DMA map. */ 589 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 590 BUS_DMASYNC_PREWRITE); 591 592 /* Initialize the transmit descriptor(s). */ 593 txstart = sc->bce_txsnext; 594 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 595 uint32_t ctrl; 596 597 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 598 if (seg == 0) 599 ctrl |= CTRL_SOF; 600 if (seg == dmamap->dm_nsegs - 1) 601 ctrl |= CTRL_EOF; 602 if (sc->bce_txsnext == BCE_NTXDESC - 1) 603 ctrl |= CTRL_EOT; 604 ctrl |= CTRL_IOC; 605 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 606 sc->bce_tx_ring[sc->bce_txsnext].addr = 607 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 608 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 609 sc->bce_txsnext = 0; 610 else 611 sc->bce_txsnext++; 612 txsfree--; 613 } 614 /* sync descriptors being used */ 615 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 616 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 617 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 618 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 619 620 /* Give the packet to the chip. */ 621 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 622 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 623 624 newpkts++; 625 626 #if NBPFILTER > 0 627 /* Pass the packet to any BPF listeners. */ 628 if (ifp->if_bpf) 629 bpf_mtap(ifp->if_bpf, m0); 630 #endif /* NBPFILTER > 0 */ 631 } 632 if (txsfree == 0) { 633 /* No more slots left; notify upper layer. */ 634 ifp->if_flags |= IFF_OACTIVE; 635 } 636 if (newpkts) { 637 /* Set a watchdog timer in case the chip flakes out. */ 638 ifp->if_timer = 5; 639 } 640 } 641 642 /* Watchdog timer handler. */ 643 static void 644 bce_watchdog(struct ifnet *ifp) 645 { 646 struct bce_softc *sc = ifp->if_softc; 647 648 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 649 ifp->if_oerrors++; 650 651 (void) bce_init(ifp); 652 653 /* Try to get more packets going. */ 654 bce_start(ifp); 655 } 656 657 int 658 bce_intr(void *xsc) 659 { 660 struct bce_softc *sc; 661 struct ifnet *ifp; 662 uint32_t intstatus; 663 int wantinit; 664 int handled = 0; 665 666 sc = xsc; 667 ifp = &sc->ethercom.ec_if; 668 669 for (wantinit = 0; wantinit == 0;) { 670 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 671 BCE_INT_STS); 672 673 /* ignore if not ours, or unsolicited interrupts */ 674 intstatus &= sc->bce_intmask; 675 if (intstatus == 0) 676 break; 677 678 handled = 1; 679 680 /* Ack interrupt */ 681 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 682 intstatus); 683 684 /* Receive interrupts. */ 685 if (intstatus & I_RI) 686 bce_rxintr(sc); 687 /* Transmit interrupts. */ 688 if (intstatus & I_XI) 689 bce_txintr(sc); 690 /* Error interrupts */ 691 if (intstatus & ~(I_RI | I_XI)) { 692 if (intstatus & I_XU) 693 printf("%s: transmit fifo underflow\n", 694 sc->bce_dev.dv_xname); 695 if (intstatus & I_RO) { 696 printf("%s: receive fifo overflow\n", 697 sc->bce_dev.dv_xname); 698 ifp->if_ierrors++; 699 } 700 if (intstatus & I_RU) 701 printf("%s: receive descriptor underflow\n", 702 sc->bce_dev.dv_xname); 703 if (intstatus & I_DE) 704 printf("%s: descriptor protocol error\n", 705 sc->bce_dev.dv_xname); 706 if (intstatus & I_PD) 707 printf("%s: data error\n", 708 sc->bce_dev.dv_xname); 709 if (intstatus & I_PC) 710 printf("%s: descriptor error\n", 711 sc->bce_dev.dv_xname); 712 if (intstatus & I_TO) 713 printf("%s: general purpose timeout\n", 714 sc->bce_dev.dv_xname); 715 wantinit = 1; 716 } 717 } 718 719 if (handled) { 720 if (wantinit) 721 bce_init(ifp); 722 #if NRND > 0 723 if (RND_ENABLED(&sc->rnd_source)) 724 rnd_add_uint32(&sc->rnd_source, intstatus); 725 #endif 726 /* Try to get more packets going. */ 727 bce_start(ifp); 728 } 729 return (handled); 730 } 731 732 /* Receive interrupt handler */ 733 void 734 bce_rxintr(struct bce_softc *sc) 735 { 736 struct ifnet *ifp = &sc->ethercom.ec_if; 737 struct rx_pph *pph; 738 struct mbuf *m; 739 int curr; 740 int len; 741 int i; 742 743 /* get pointer to active receive slot */ 744 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 745 & RS_CD_MASK; 746 curr = curr / sizeof(struct bce_dma_slot); 747 if (curr >= BCE_NRXDESC) 748 curr = BCE_NRXDESC - 1; 749 750 /* process packets up to but not current packet being worked on */ 751 for (i = sc->bce_rxin; i != curr; 752 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 753 /* complete any post dma memory ops on packet */ 754 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 755 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 756 BUS_DMASYNC_POSTREAD); 757 758 /* 759 * If the packet had an error, simply recycle the buffer, 760 * resetting the len, and flags. 761 */ 762 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 763 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 764 ifp->if_ierrors++; 765 pph->len = 0; 766 pph->flags = 0; 767 continue; 768 } 769 /* receive the packet */ 770 len = pph->len; 771 if (len == 0) 772 continue; /* no packet if empty */ 773 pph->len = 0; 774 pph->flags = 0; 775 /* bump past pre header to packet */ 776 sc->bce_cdata.bce_rx_chain[i]->m_data += 30; /* MAGIC */ 777 778 /* 779 * The chip includes the CRC with every packet. Trim 780 * it off here. 781 */ 782 len -= ETHER_CRC_LEN; 783 784 /* 785 * If the packet is small enough to fit in a 786 * single header mbuf, allocate one and copy 787 * the data into it. This greatly reduces 788 * memory consumption when receiving lots 789 * of small packets. 790 * 791 * Otherwise, add a new buffer to the receive 792 * chain. If this fails, drop the packet and 793 * recycle the old buffer. 794 */ 795 if (len <= (MHLEN - 2)) { 796 MGETHDR(m, M_DONTWAIT, MT_DATA); 797 if (m == NULL) 798 goto dropit; 799 m->m_data += 2; 800 memcpy(mtod(m, void *), 801 mtod(sc->bce_cdata.bce_rx_chain[i], void *), len); 802 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; /* MAGIC */ 803 } else { 804 m = sc->bce_cdata.bce_rx_chain[i]; 805 if (bce_add_rxbuf(sc, i) != 0) { 806 dropit: 807 ifp->if_ierrors++; 808 /* continue to use old buffer */ 809 sc->bce_cdata.bce_rx_chain[i]->m_data -= 30; 810 bus_dmamap_sync(sc->bce_dmatag, 811 sc->bce_cdata.bce_rx_map[i], 0, 812 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 813 BUS_DMASYNC_PREREAD); 814 continue; 815 } 816 } 817 818 m->m_pkthdr.rcvif = ifp; 819 m->m_pkthdr.len = m->m_len = len; 820 ifp->if_ipackets++; 821 822 #if NBPFILTER > 0 823 /* 824 * Pass this up to any BPF listeners, but only 825 * pass it up the stack if it's for us. 826 */ 827 if (ifp->if_bpf) 828 bpf_mtap(ifp->if_bpf, m); 829 #endif /* NBPFILTER > 0 */ 830 831 /* Pass it on. */ 832 (*ifp->if_input) (ifp, m); 833 834 /* re-check current in case it changed */ 835 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 836 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 837 sizeof(struct bce_dma_slot); 838 if (curr >= BCE_NRXDESC) 839 curr = BCE_NRXDESC - 1; 840 } 841 sc->bce_rxin = curr; 842 } 843 844 /* Transmit interrupt handler */ 845 void 846 bce_txintr(struct bce_softc *sc) 847 { 848 struct ifnet *ifp = &sc->ethercom.ec_if; 849 int curr; 850 int i; 851 852 ifp->if_flags &= ~IFF_OACTIVE; 853 854 /* 855 * Go through the Tx list and free mbufs for those 856 * frames which have been transmitted. 857 */ 858 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 859 RS_CD_MASK; 860 curr = curr / sizeof(struct bce_dma_slot); 861 if (curr >= BCE_NTXDESC) 862 curr = BCE_NTXDESC - 1; 863 for (i = sc->bce_txin; i != curr; 864 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 865 /* do any post dma memory ops on transmit data */ 866 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 867 continue; 868 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 869 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 870 BUS_DMASYNC_POSTWRITE); 871 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 872 m_freem(sc->bce_cdata.bce_tx_chain[i]); 873 sc->bce_cdata.bce_tx_chain[i] = NULL; 874 ifp->if_opackets++; 875 } 876 sc->bce_txin = curr; 877 878 /* 879 * If there are no more pending transmissions, cancel the watchdog 880 * timer 881 */ 882 if (sc->bce_txsnext == sc->bce_txin) 883 ifp->if_timer = 0; 884 } 885 886 /* initialize the interface */ 887 static int 888 bce_init(struct ifnet *ifp) 889 { 890 struct bce_softc *sc = ifp->if_softc; 891 uint32_t reg_win; 892 int error; 893 int i; 894 895 /* Cancel any pending I/O. */ 896 bce_stop(ifp, 0); 897 898 /* enable pci inerrupts, bursts, and prefetch */ 899 900 /* remap the pci registers to the Sonics config registers */ 901 902 /* save the current map, so it can be restored */ 903 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 904 BCE_REG_WIN); 905 906 /* set register window to Sonics registers */ 907 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 908 BCE_SONICS_WIN); 909 910 /* enable SB to PCI interrupt */ 911 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 912 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 913 SBIV_ENET0); 914 915 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 916 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 917 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 918 SBTOPCI_PREF | SBTOPCI_BURST); 919 920 /* restore to ethernet register space */ 921 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 922 reg_win); 923 924 /* Reset the chip to a known state. */ 925 bce_reset(sc); 926 927 /* Initialize transmit descriptors */ 928 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 929 sc->bce_txsnext = 0; 930 sc->bce_txin = 0; 931 932 /* enable crc32 generation */ 933 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 934 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 935 BCE_EMC_CG); 936 937 /* setup DMA interrupt control */ 938 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 939 940 /* setup packet filter */ 941 bce_set_filter(ifp); 942 943 /* set max frame length, account for possible vlan tag */ 944 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 945 ETHER_MAX_LEN + 32); 946 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 947 ETHER_MAX_LEN + 32); 948 949 /* set tx watermark */ 950 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 951 952 /* enable transmit */ 953 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 954 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 955 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 956 957 /* 958 * Give the receive ring to the chip, and 959 * start the receive DMA engine. 960 */ 961 sc->bce_rxin = 0; 962 963 /* clear the rx descriptor ring */ 964 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 965 /* enable receive */ 966 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 967 30 << 1 | 1); /* MAGIC */ 968 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 969 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 970 971 /* Initalize receive descriptors */ 972 for (i = 0; i < BCE_NRXDESC; i++) { 973 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 974 if ((error = bce_add_rxbuf(sc, i)) != 0) { 975 printf("%s: unable to allocate or map rx(%d) " 976 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 977 i, error); 978 bce_rxdrain(sc); 979 return (error); 980 } 981 } else 982 BCE_INIT_RXDESC(sc, i); 983 } 984 985 /* Enable interrupts */ 986 sc->bce_intmask = 987 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 988 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 989 sc->bce_intmask); 990 991 /* start the receive dma */ 992 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 993 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 994 995 /* set media */ 996 if ((error = ether_mediachange(ifp)) != 0) 997 return error; 998 999 /* turn on the ethernet mac */ 1000 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1001 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1002 BCE_ENET_CTL) | EC_EE); 1003 1004 /* start timer */ 1005 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1006 1007 /* mark as running, and no outputs active */ 1008 ifp->if_flags |= IFF_RUNNING; 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 1011 return 0; 1012 } 1013 1014 /* add a mac address to packet filter */ 1015 void 1016 bce_add_mac(struct bce_softc *sc, uint8_t *mac, u_long idx) 1017 { 1018 int i; 1019 uint32_t rval; 1020 1021 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1022 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1023 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1024 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1025 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1026 idx << 16 | 8); /* MAGIC */ 1027 /* wait for write to complete */ 1028 for (i = 0; i < 100; i++) { 1029 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1030 BCE_FILT_CTL); 1031 if (!(rval & 0x80000000)) /* MAGIC */ 1032 break; 1033 delay(10); 1034 } 1035 if (i == 100) { 1036 printf("%s: timed out writing pkt filter ctl\n", 1037 sc->bce_dev.dv_xname); 1038 } 1039 } 1040 1041 /* Add a receive buffer to the indiciated descriptor. */ 1042 static int 1043 bce_add_rxbuf(struct bce_softc *sc, int idx) 1044 { 1045 struct mbuf *m; 1046 int error; 1047 1048 MGETHDR(m, M_DONTWAIT, MT_DATA); 1049 if (m == NULL) 1050 return (ENOBUFS); 1051 1052 MCLGET(m, M_DONTWAIT); 1053 if ((m->m_flags & M_EXT) == 0) { 1054 m_freem(m); 1055 return (ENOBUFS); 1056 } 1057 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1058 bus_dmamap_unload(sc->bce_dmatag, 1059 sc->bce_cdata.bce_rx_map[idx]); 1060 1061 sc->bce_cdata.bce_rx_chain[idx] = m; 1062 1063 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1064 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1065 BUS_DMA_READ | BUS_DMA_NOWAIT); 1066 if (error) 1067 return (error); 1068 1069 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1070 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1071 1072 BCE_INIT_RXDESC(sc, idx); 1073 1074 return (0); 1075 1076 } 1077 1078 /* Drain the receive queue. */ 1079 static void 1080 bce_rxdrain(struct bce_softc *sc) 1081 { 1082 int i; 1083 1084 for (i = 0; i < BCE_NRXDESC; i++) { 1085 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1086 bus_dmamap_unload(sc->bce_dmatag, 1087 sc->bce_cdata.bce_rx_map[i]); 1088 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1089 sc->bce_cdata.bce_rx_chain[i] = NULL; 1090 } 1091 } 1092 } 1093 1094 /* Stop transmission on the interface */ 1095 static void 1096 bce_stop(struct ifnet *ifp, int disable) 1097 { 1098 struct bce_softc *sc = ifp->if_softc; 1099 int i; 1100 uint32_t val; 1101 1102 /* Stop the 1 second timer */ 1103 callout_stop(&sc->bce_timeout); 1104 1105 /* Down the MII. */ 1106 mii_down(&sc->bce_mii); 1107 1108 /* Disable interrupts. */ 1109 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1110 sc->bce_intmask = 0; 1111 delay(10); 1112 1113 /* Disable emac */ 1114 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1115 for (i = 0; i < 200; i++) { 1116 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1117 BCE_ENET_CTL); 1118 if (!(val & EC_ED)) 1119 break; 1120 delay(10); 1121 } 1122 1123 /* Stop the DMA */ 1124 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1125 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1126 delay(10); 1127 1128 /* Release any queued transmit buffers. */ 1129 for (i = 0; i < BCE_NTXDESC; i++) { 1130 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1131 bus_dmamap_unload(sc->bce_dmatag, 1132 sc->bce_cdata.bce_tx_map[i]); 1133 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1134 sc->bce_cdata.bce_tx_chain[i] = NULL; 1135 } 1136 } 1137 1138 /* drain receive queue */ 1139 if (disable) 1140 bce_rxdrain(sc); 1141 1142 /* Mark the interface down and cancel the watchdog timer. */ 1143 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1144 ifp->if_timer = 0; 1145 } 1146 1147 /* reset the chip */ 1148 static void 1149 bce_reset(struct bce_softc *sc) 1150 { 1151 uint32_t val; 1152 uint32_t sbval; 1153 int i; 1154 1155 /* if SB core is up */ 1156 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1157 BCE_SBTMSTATELOW); 1158 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1159 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1160 0); 1161 1162 /* disable emac */ 1163 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1164 EC_ED); 1165 for (i = 0; i < 200; i++) { 1166 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1167 BCE_ENET_CTL); 1168 if (!(val & EC_ED)) 1169 break; 1170 delay(10); 1171 } 1172 if (i == 200) 1173 printf("%s: timed out disabling ethernet mac\n", 1174 sc->bce_dev.dv_xname); 1175 1176 /* reset the dma engines */ 1177 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1178 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1179 /* if error on receive, wait to go idle */ 1180 if (val & RS_ERROR) { 1181 for (i = 0; i < 100; i++) { 1182 val = bus_space_read_4(sc->bce_btag, 1183 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1184 if (val & RS_DMA_IDLE) 1185 break; 1186 delay(10); 1187 } 1188 if (i == 100) 1189 printf("%s: receive dma did not go idle after" 1190 " error\n", sc->bce_dev.dv_xname); 1191 } 1192 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1193 BCE_DMA_RXSTATUS, 0); 1194 1195 /* reset ethernet mac */ 1196 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1197 EC_ES); 1198 for (i = 0; i < 200; i++) { 1199 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1200 BCE_ENET_CTL); 1201 if (!(val & EC_ES)) 1202 break; 1203 delay(10); 1204 } 1205 if (i == 200) 1206 printf("%s: timed out restting ethernet mac\n", 1207 sc->bce_dev.dv_xname); 1208 } else { 1209 uint32_t reg_win; 1210 1211 /* remap the pci registers to the Sonics config registers */ 1212 1213 /* save the current map, so it can be restored */ 1214 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1215 BCE_REG_WIN); 1216 /* set register window to Sonics registers */ 1217 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1218 BCE_REG_WIN, BCE_SONICS_WIN); 1219 1220 /* enable SB to PCI interrupt */ 1221 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1222 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1223 BCE_SBINTVEC) | 1224 SBIV_ENET0); 1225 1226 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1227 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1228 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1229 BCE_SPCI_TR2) | 1230 SBTOPCI_PREF | SBTOPCI_BURST); 1231 1232 /* restore to ethernet register space */ 1233 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1234 reg_win); 1235 } 1236 1237 /* disable SB core if not in reset */ 1238 if (!(sbval & SBTML_RESET)) { 1239 1240 /* set the reject bit */ 1241 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1242 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1243 for (i = 0; i < 200; i++) { 1244 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1245 BCE_SBTMSTATELOW); 1246 if (val & SBTML_REJ) 1247 break; 1248 delay(1); 1249 } 1250 if (i == 200) 1251 printf("%s: while restting core, reject did not set\n", 1252 sc->bce_dev.dv_xname); 1253 /* wait until busy is clear */ 1254 for (i = 0; i < 200; i++) { 1255 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1256 BCE_SBTMSTATEHI); 1257 if (!(val & 0x4)) 1258 break; 1259 delay(1); 1260 } 1261 if (i == 200) 1262 printf("%s: while restting core, busy did not clear\n", 1263 sc->bce_dev.dv_xname); 1264 /* set reset and reject while enabling the clocks */ 1265 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1266 BCE_SBTMSTATELOW, 1267 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1268 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1269 BCE_SBTMSTATELOW); 1270 delay(10); 1271 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1272 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1273 delay(1); 1274 } 1275 /* enable clock */ 1276 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1277 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1278 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1279 delay(1); 1280 1281 /* clear any error bits that may be on */ 1282 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1283 if (val & 1) 1284 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1285 0); 1286 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1287 if (val & SBIM_MAGIC_ERRORBITS) 1288 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1289 val & ~SBIM_MAGIC_ERRORBITS); 1290 1291 /* clear reset and allow it to propagate throughout the core */ 1292 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1293 SBTML_FGC | SBTML_CLK); 1294 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1295 delay(1); 1296 1297 /* leave clock enabled */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1299 SBTML_CLK); 1300 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1301 delay(1); 1302 1303 /* initialize MDC preamble, frequency */ 1304 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1305 1306 /* enable phy, differs for internal, and external */ 1307 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1308 if (!(val & BCE_DC_IP)) { 1309 /* select external phy */ 1310 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1311 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1312 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1313 val & ~BCE_DC_ER); 1314 delay(100); 1315 } 1316 } 1317 1318 /* Set up the receive filter. */ 1319 void 1320 bce_set_filter(struct ifnet *ifp) 1321 { 1322 struct bce_softc *sc = ifp->if_softc; 1323 1324 if (ifp->if_flags & IFF_PROMISC) { 1325 ifp->if_flags |= IFF_ALLMULTI; 1326 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1327 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1328 | ERC_PE); 1329 } else { 1330 ifp->if_flags &= ~IFF_ALLMULTI; 1331 1332 /* turn off promiscuous */ 1333 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1334 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1335 BCE_RX_CTL) & ~ERC_PE); 1336 1337 /* enable/disable broadcast */ 1338 if (ifp->if_flags & IFF_BROADCAST) 1339 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1340 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1341 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1342 else 1343 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1344 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1345 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1346 1347 /* disable the filter */ 1348 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1349 0); 1350 1351 /* add our own address */ 1352 bce_add_mac(sc, sc->enaddr, 0); 1353 1354 /* for now accept all multicast */ 1355 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1356 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1357 ERC_AM); 1358 ifp->if_flags |= IFF_ALLMULTI; 1359 1360 /* enable the filter */ 1361 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1362 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1363 BCE_FILT_CTL) | 1); 1364 } 1365 } 1366 1367 static bool 1368 bce_resume(device_t dv) 1369 { 1370 struct bce_softc *sc = device_private(dv); 1371 1372 bce_reset(sc); 1373 1374 return true; 1375 } 1376 1377 /* Read a PHY register on the MII. */ 1378 int 1379 bce_mii_read(struct device *self, int phy, int reg) 1380 { 1381 struct bce_softc *sc = (struct bce_softc *) self; 1382 int i; 1383 uint32_t val; 1384 1385 /* clear mii_int */ 1386 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1387 1388 /* Read the PHY register */ 1389 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1390 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1391 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1392 1393 for (i = 0; i < BCE_TIMEOUT; i++) { 1394 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1395 if (val & BCE_MIINTR) 1396 break; 1397 delay(10); 1398 } 1399 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1400 if (i == BCE_TIMEOUT) { 1401 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1402 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1403 return (0); 1404 } 1405 return (val & BCE_MICOMM_DATA); 1406 } 1407 1408 /* Write a PHY register on the MII */ 1409 void 1410 bce_mii_write(struct device *self, int phy, int reg, int val) 1411 { 1412 struct bce_softc *sc = (struct bce_softc *) self; 1413 int i; 1414 uint32_t rval; 1415 1416 /* clear mii_int */ 1417 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1418 BCE_MIINTR); 1419 1420 /* Write the PHY register */ 1421 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1422 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1423 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1424 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1425 1426 /* wait for write to complete */ 1427 for (i = 0; i < BCE_TIMEOUT; i++) { 1428 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1429 BCE_MI_STS); 1430 if (rval & BCE_MIINTR) 1431 break; 1432 delay(10); 1433 } 1434 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1435 if (i == BCE_TIMEOUT) { 1436 printf("%s: PHY timed out writing phy %d, reg %d, val " 1437 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1438 } 1439 } 1440 1441 /* sync hardware duplex mode to software state */ 1442 void 1443 bce_statchg(struct device *self) 1444 { 1445 struct bce_softc *sc = (struct bce_softc *) self; 1446 uint32_t reg; 1447 1448 /* if needed, change register to match duplex mode */ 1449 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1450 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1451 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1452 reg | EXC_FD); 1453 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1454 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1455 reg & ~EXC_FD); 1456 1457 /* 1458 * Enable activity led. 1459 * XXX This should be in a phy driver, but not currently. 1460 */ 1461 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1462 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1463 /* enable traffic meter led mode */ 1464 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1465 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1466 } 1467 1468 /* One second timer, checks link status */ 1469 static void 1470 bce_tick(void *v) 1471 { 1472 struct bce_softc *sc = v; 1473 1474 /* Tick the MII. */ 1475 mii_tick(&sc->bce_mii); 1476 1477 callout_reset(&sc->bce_timeout, hz, bce_tick, sc); 1478 } 1479