1 /* $NetBSD: if_ath_pci.c,v 1.38 2010/04/28 22:00:39 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: if_ath_pci.c,v 1.38 2010/04/28 22:00:39 dyoung Exp $"); 41 42 /* 43 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 52 #include <external/isc/atheros_hal/dist/ah.h> 53 54 #include <dev/ic/ath_netbsd.h> 55 #include <dev/ic/athvar.h> 56 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcidevs.h> 60 61 /* 62 * PCI configuration space registers 63 */ 64 #define ATH_PCI_MMBA 0x10 /* memory mapped base */ 65 66 struct ath_pci_softc { 67 struct ath_softc sc_sc; 68 pci_chipset_tag_t sc_pc; 69 pcitag_t sc_tag; 70 pci_intr_handle_t sc_pih; 71 void *sc_ih; 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 bus_size_t sc_mapsz; 75 }; 76 77 static void ath_pci_attach(device_t, device_t, void *); 78 static int ath_pci_detach(device_t, int); 79 static int ath_pci_match(device_t, cfdata_t, void *); 80 static bool ath_pci_setup(struct ath_pci_softc *); 81 82 CFATTACH_DECL_NEW(ath_pci, sizeof(struct ath_pci_softc), 83 ath_pci_match, ath_pci_attach, ath_pci_detach, NULL); 84 85 static int 86 ath_pci_match(device_t parent, cfdata_t match, void *aux) 87 { 88 const char *devname; 89 struct pci_attach_args *pa = aux; 90 91 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 92 return (devname != NULL) ? 1 : 0; 93 } 94 95 static bool 96 ath_pci_suspend(device_t self, const pmf_qual_t *qual) 97 { 98 struct ath_pci_softc *sc = device_private(self); 99 100 ath_suspend(&sc->sc_sc); 101 if (sc->sc_ih != NULL) { 102 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 103 sc->sc_ih = NULL; 104 } 105 return true; 106 } 107 108 static bool 109 ath_pci_resume(device_t self, const pmf_qual_t *qual) 110 { 111 struct ath_pci_softc *sc = device_private(self); 112 113 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pih, IPL_NET, ath_intr, 114 &sc->sc_sc); 115 if (sc->sc_ih == NULL) { 116 aprint_error_dev(self, "couldn't map interrupt\n"); 117 return false; 118 } 119 return ath_resume(&sc->sc_sc); 120 } 121 122 static void 123 ath_pci_attach(device_t parent, device_t self, void *aux) 124 { 125 struct ath_pci_softc *psc = device_private(self); 126 struct ath_softc *sc = &psc->sc_sc; 127 struct pci_attach_args *pa = aux; 128 pci_chipset_tag_t pc = pa->pa_pc; 129 const char *intrstr = NULL; 130 pcireg_t mem_type; 131 132 sc->sc_dev = self; 133 sc->sc_dmat = pa->pa_dmat; 134 psc->sc_pc = pc; 135 psc->sc_tag = pa->pa_tag; 136 137 aprint_normal("\n"); 138 139 if (!ath_pci_setup(psc)) 140 goto bad; 141 142 /* 143 * Setup memory-mapping of PCI registers. 144 */ 145 mem_type = pci_mapreg_type(pc, pa->pa_tag, ATH_PCI_MMBA); 146 if (mem_type != PCI_MAPREG_TYPE_MEM && 147 mem_type != PCI_MAPREG_MEM_TYPE_64BIT) { 148 aprint_error("bad pci register type %d\n", (int)mem_type); 149 goto bad; 150 } 151 if (pci_mapreg_map(pa, ATH_PCI_MMBA, mem_type, 0, &psc->sc_iot, 152 &psc->sc_ioh, NULL, &psc->sc_mapsz) != 0) { 153 aprint_error("cannot map register space\n"); 154 goto bad; 155 } 156 157 sc->sc_st = HALTAG(psc->sc_iot); 158 sc->sc_sh = HALHANDLE(psc->sc_ioh); 159 160 /* 161 * Arrange interrupt line. 162 */ 163 if (pci_intr_map(pa, &psc->sc_pih)) { 164 aprint_error("couldn't map interrupt\n"); 165 goto bad1; 166 } 167 168 intrstr = pci_intr_string(pc, psc->sc_pih); 169 psc->sc_ih = pci_intr_establish(pc, psc->sc_pih, IPL_NET, ath_intr, sc); 170 if (psc->sc_ih == NULL) { 171 aprint_error("couldn't map interrupt\n"); 172 goto bad1; 173 } 174 175 aprint_verbose_dev(self, "interrupting at %s\n", intrstr); 176 177 ATH_LOCK_INIT(sc); 178 179 if (ath_attach(PCI_PRODUCT(pa->pa_id), sc) != 0) 180 goto bad3; 181 182 if (pmf_device_register(self, ath_pci_suspend, ath_pci_resume)) { 183 pmf_class_network_register(self, &sc->sc_if); 184 pmf_device_suspend(self, &sc->sc_qual); 185 } else 186 aprint_error_dev(self, "couldn't establish power handler\n"); 187 return; 188 bad3: 189 ATH_LOCK_DESTROY(sc); 190 191 pci_intr_disestablish(pc, psc->sc_ih); 192 bad1: 193 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 194 bad: 195 return; 196 } 197 198 static int 199 ath_pci_detach(device_t self, int flags) 200 { 201 struct ath_pci_softc *psc = device_private(self); 202 int rv; 203 204 if ((rv = ath_detach(&psc->sc_sc)) != 0) 205 return rv; 206 207 pmf_device_deregister(self); 208 209 if (psc->sc_ih != NULL) 210 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 211 212 ATH_LOCK_DESTROY(&psc->sc_sc); 213 214 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 215 return 0; 216 } 217 218 static bool 219 ath_pci_setup(struct ath_pci_softc *sc) 220 { 221 int rc; 222 pcireg_t bhlc, csr, icr, lattimer; 223 224 if ((rc = pci_set_powerstate(sc->sc_pc, sc->sc_tag, PCI_PWR_D0)) != 0) 225 aprint_debug("%s: pci_set_powerstate %d\n", __func__, rc); 226 /* 227 * Enable memory mapping and bus mastering. 228 */ 229 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 230 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 231 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 232 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 233 234 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 235 aprint_error_dev(sc->sc_sc.sc_dev, 236 "couldn't enable memory mapping\n"); 237 return false; 238 } 239 if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { 240 aprint_error_dev(sc->sc_sc.sc_dev, 241 "couldn't enable bus mastering\n"); 242 return false; 243 } 244 245 /* 246 * XXX Both this comment and code are replicated in 247 * XXX cardbus_rescan(). 248 * 249 * Make sure the latency timer is set to some reasonable 250 * value. 251 * 252 * I will set the initial value of the Latency Timer here. 253 * 254 * While a PCI device owns the bus, its Latency Timer counts 255 * down bus cycles from its initial value to 0. Minimum 256 * Grant tells for how long the device wants to own the 257 * bus once it gets access, in units of 250ns. 258 * 259 * On a 33 MHz bus, there are 8 cycles per 250ns. So I 260 * multiply the Minimum Grant by 8 to find out the initial 261 * value of the Latency Timer. 262 * 263 * I never set a Latency Timer less than 0x10, since that 264 * is what the old code did. 265 */ 266 bhlc = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG); 267 icr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_INTERRUPT_REG); 268 lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr))); 269 if (PCI_LATTIMER(bhlc) < lattimer) { 270 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 271 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 272 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG, bhlc); 273 } 274 return true; 275 } 276