1 /* $NetBSD: if_ath_pci.c,v 1.25 2007/12/14 03:18:46 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath_pci.c,v 1.11 2005/01/18 18:08:16 sam Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: if_ath_pci.c,v 1.25 2007/12/14 03:18:46 dyoung Exp $"); 45 #endif 46 47 /* 48 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 49 */ 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #include <net/if.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <net80211/ieee80211_netbsd.h> 65 #include <net80211/ieee80211_var.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #endif 70 71 #include <dev/ic/ath_netbsd.h> 72 #include <dev/ic/athvar.h> 73 #include <contrib/dev/ath/ah.h> 74 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcidevs.h> 78 79 /* 80 * PCI glue. 81 */ 82 83 struct ath_pci_softc { 84 struct ath_softc sc_sc; 85 pci_chipset_tag_t sc_pc; 86 pcitag_t sc_pcitag; 87 void *sc_ih; /* interrupt handler */ 88 bus_space_tag_t sc_iot; 89 bus_space_handle_t sc_ioh; 90 }; 91 92 #define BS_BAR 0x10 93 94 static void ath_pci_attach(struct device *, struct device *, void *); 95 static int ath_pci_detach(struct device *, int); 96 static int ath_pci_match(struct device *, struct cfdata *, void *); 97 static int ath_pci_detach(struct device *, int); 98 99 CFATTACH_DECL(ath_pci, 100 sizeof(struct ath_pci_softc), 101 ath_pci_match, 102 ath_pci_attach, 103 ath_pci_detach, 104 NULL); 105 106 static int 107 ath_pci_match(struct device *parent, struct cfdata *match, void *aux) 108 { 109 const char* devname; 110 struct pci_attach_args *pa = aux; 111 112 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 113 if (devname != NULL) 114 return 1; 115 return 0; 116 } 117 118 static bool 119 ath_pci_resume(device_t dv) 120 { 121 struct ath_pci_softc *sc = device_private(dv); 122 123 /* Insofar as I understand what the PCI retry timeout is 124 * (it does not appear to be documented in any PCI standard, 125 * and we don't have any Atheros documentation), disabling 126 * it on resume does not seem to be justified. 127 * 128 * Taking a guess, the DMA engine counts down from the 129 * retry timeout to 0 while it retries a delayed PCI 130 * transaction. When it reaches 0, it ceases retrying. 131 * A PCI master is *never* supposed to stop retrying a 132 * delayed transaction, though. 133 * 134 * Incidentally, while I am hopeful that pci_disable_retry() 135 * does disable retries, because that would help to explain 136 * some ath(4) lossage, I suspect that writing 0 to the 137 * register does not disable *retries*, but it disables 138 * the timeout. That is, the device will *never* timeout. 139 */ 140 #if 0 141 pci_disable_retry(sc->sc_pc, sc->sc_pcitag); 142 #endif 143 ath_resume(&sc->sc_sc); 144 145 return true; 146 } 147 148 static int 149 ath_pci_setup(struct ath_pci_softc *sc) 150 { 151 pcireg_t bhlc, csr, icr, lattimer; 152 /* 153 * Enable memory mapping and bus mastering. 154 */ 155 csr = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 156 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 157 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, csr); 158 csr = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 159 160 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 161 aprint_error("couldn't enable memory mapping\n"); 162 return 0; 163 } 164 if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { 165 aprint_error("couldn't enable bus mastering\n"); 166 return 0; 167 } 168 169 #if 0 170 pci_disable_retry(sc->sc_pc, sc->sc_pcitag); 171 #endif 172 173 /* 174 * XXX Both this comment and code are replicated in 175 * XXX cardbus_rescan(). 176 * 177 * Make sure the latency timer is set to some reasonable 178 * value. 179 * 180 * I will set the initial value of the Latency Timer here. 181 * 182 * While a PCI device owns the bus, its Latency Timer counts 183 * down bus cycles from its initial value to 0. Minimum 184 * Grant tells for how long the device wants to own the 185 * bus once it gets access, in units of 250ns. 186 * 187 * On a 33 MHz bus, there are 8 cycles per 250ns. So I 188 * multiply the Minimum Grant by 8 to find out the initial 189 * value of the Latency Timer. 190 * 191 * I never set a Latency Timer less than 0x10, since that 192 * is what the old code did. 193 */ 194 bhlc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_BHLC_REG); 195 icr = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_INTERRUPT_REG); 196 lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr))); 197 if (PCI_LATTIMER(bhlc) < lattimer) { 198 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 199 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 200 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_BHLC_REG, bhlc); 201 } 202 return 1; 203 } 204 205 static void 206 ath_pci_attach(struct device *parent, struct device *self, void *aux) 207 { 208 struct ath_pci_softc *psc = (struct ath_pci_softc *)self; 209 struct ath_softc *sc = &psc->sc_sc; 210 struct pci_attach_args *pa = aux; 211 pci_chipset_tag_t pc = pa->pa_pc; 212 pci_intr_handle_t ih; 213 pcireg_t mem_type; 214 const char *intrstr = NULL; 215 216 psc->sc_pc = pc; 217 218 psc->sc_pcitag = pa->pa_tag; 219 220 if (!ath_pci_setup(psc)) 221 goto bad; 222 223 /* 224 * Setup memory-mapping of PCI registers. 225 */ 226 mem_type = pci_mapreg_type(pc, pa->pa_tag, BS_BAR); 227 if (mem_type != PCI_MAPREG_TYPE_MEM && 228 mem_type != PCI_MAPREG_MEM_TYPE_64BIT) { 229 aprint_error("bad pci register type %d\n", (int)mem_type); 230 goto bad; 231 } 232 if (pci_mapreg_map(pa, BS_BAR, mem_type, 0, &psc->sc_iot, 233 &psc->sc_ioh, NULL, NULL)) { 234 aprint_error("cannot map register space\n"); 235 goto bad; 236 } 237 238 sc->sc_st = HALTAG(psc->sc_iot); 239 sc->sc_sh = HALHANDLE(psc->sc_ioh); 240 241 sc->sc_invalid = 1; 242 243 /* 244 * Arrange interrupt line. 245 */ 246 if (pci_intr_map(pa, &ih)) { 247 aprint_error("couldn't map interrupt\n"); 248 goto bad1; 249 } 250 251 intrstr = pci_intr_string(pc, ih); 252 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ath_intr, sc); 253 if (psc->sc_ih == NULL) { 254 aprint_error("couldn't map interrupt\n"); 255 goto bad2; 256 } 257 258 printf("\n"); 259 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 260 261 sc->sc_dmat = pa->pa_dmat; 262 263 if (!pmf_device_register(self, NULL, ath_pci_resume)) 264 aprint_error_dev(self, "couldn't establish power handler\n"); 265 266 if (ath_attach(PCI_PRODUCT(pa->pa_id), sc) == 0) { 267 pmf_class_network_register(self, &sc->sc_if); 268 return; 269 } 270 271 pci_intr_disestablish(pc, psc->sc_ih); 272 bad2: /* XXX */ 273 bad1: /* XXX */ 274 bad: 275 return; 276 } 277 278 static int 279 ath_pci_detach(struct device *self, int flags) 280 { 281 struct ath_pci_softc *psc = (struct ath_pci_softc *)self; 282 283 ath_detach(&psc->sc_sc); 284 pmf_device_deregister(self); 285 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 286 287 return (0); 288 } 289