1 /* $NetBSD: if_ath_pci.c,v 1.41 2011/02/21 14:43:58 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: if_ath_pci.c,v 1.41 2011/02/21 14:43:58 jmcneill Exp $"); 41 42 /* 43 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/module.h> 52 53 #include <external/isc/atheros_hal/dist/ah.h> 54 55 #include <dev/ic/ath_netbsd.h> 56 #include <dev/ic/athvar.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcidevs.h> 61 62 /* 63 * PCI configuration space registers 64 */ 65 #define ATH_PCI_MMBA 0x10 /* memory mapped base */ 66 67 struct ath_pci_softc { 68 struct ath_softc sc_sc; 69 pci_chipset_tag_t sc_pc; 70 pcitag_t sc_tag; 71 pci_intr_handle_t sc_pih; 72 void *sc_ih; 73 bus_space_tag_t sc_iot; 74 bus_space_handle_t sc_ioh; 75 bus_size_t sc_mapsz; 76 }; 77 78 static void ath_pci_attach(device_t, device_t, void *); 79 static int ath_pci_detach(device_t, int); 80 static int ath_pci_match(device_t, cfdata_t, void *); 81 static bool ath_pci_setup(struct ath_pci_softc *); 82 83 CFATTACH_DECL_NEW(ath_pci, sizeof(struct ath_pci_softc), 84 ath_pci_match, ath_pci_attach, ath_pci_detach, NULL); 85 86 static int 87 ath_pci_match(device_t parent, cfdata_t match, void *aux) 88 { 89 const char *devname; 90 struct pci_attach_args *pa = aux; 91 92 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 93 return (devname != NULL) ? 1 : 0; 94 } 95 96 static bool 97 ath_pci_suspend(device_t self, const pmf_qual_t *qual) 98 { 99 struct ath_pci_softc *sc = device_private(self); 100 101 ath_suspend(&sc->sc_sc); 102 if (sc->sc_ih != NULL) { 103 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 104 sc->sc_ih = NULL; 105 } 106 return true; 107 } 108 109 static bool 110 ath_pci_resume(device_t self, const pmf_qual_t *qual) 111 { 112 struct ath_pci_softc *sc = device_private(self); 113 114 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pih, IPL_NET, ath_intr, 115 &sc->sc_sc); 116 if (sc->sc_ih == NULL) { 117 aprint_error_dev(self, "couldn't map interrupt\n"); 118 return false; 119 } 120 return ath_resume(&sc->sc_sc); 121 } 122 123 static void 124 ath_pci_attach(device_t parent, device_t self, void *aux) 125 { 126 struct ath_pci_softc *psc = device_private(self); 127 struct ath_softc *sc = &psc->sc_sc; 128 struct pci_attach_args *pa = aux; 129 pci_chipset_tag_t pc = pa->pa_pc; 130 const char *intrstr = NULL; 131 const char *devname; 132 pcireg_t mem_type; 133 134 sc->sc_dev = self; 135 sc->sc_dmat = pa->pa_dmat; 136 psc->sc_pc = pc; 137 psc->sc_tag = pa->pa_tag; 138 139 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 140 aprint_normal(": %s\n", devname); 141 142 if (!ath_pci_setup(psc)) 143 goto bad; 144 145 /* 146 * Setup memory-mapping of PCI registers. 147 */ 148 mem_type = pci_mapreg_type(pc, pa->pa_tag, ATH_PCI_MMBA); 149 if (mem_type != PCI_MAPREG_TYPE_MEM && 150 mem_type != PCI_MAPREG_MEM_TYPE_64BIT) { 151 aprint_error_dev(self, "bad pci register type %d\n", 152 (int)mem_type); 153 goto bad; 154 } 155 if (pci_mapreg_map(pa, ATH_PCI_MMBA, mem_type, 0, &psc->sc_iot, 156 &psc->sc_ioh, NULL, &psc->sc_mapsz) != 0) { 157 aprint_error_dev(self, "cannot map register space\n"); 158 goto bad; 159 } 160 161 sc->sc_st = HALTAG(psc->sc_iot); 162 sc->sc_sh = HALHANDLE(psc->sc_ioh); 163 164 /* 165 * Arrange interrupt line. 166 */ 167 if (pci_intr_map(pa, &psc->sc_pih)) { 168 aprint_error("couldn't map interrupt\n"); 169 goto bad1; 170 } 171 172 intrstr = pci_intr_string(pc, psc->sc_pih); 173 psc->sc_ih = pci_intr_establish(pc, psc->sc_pih, IPL_NET, ath_intr, sc); 174 if (psc->sc_ih == NULL) { 175 aprint_error("couldn't map interrupt\n"); 176 goto bad1; 177 } 178 179 aprint_verbose_dev(self, "interrupting at %s\n", intrstr); 180 181 ATH_LOCK_INIT(sc); 182 183 if (ath_attach(PCI_PRODUCT(pa->pa_id), sc) != 0) 184 goto bad3; 185 186 if (pmf_device_register(self, ath_pci_suspend, ath_pci_resume)) { 187 pmf_class_network_register(self, &sc->sc_if); 188 pmf_device_suspend(self, &sc->sc_qual); 189 } else 190 aprint_error_dev(self, "couldn't establish power handler\n"); 191 return; 192 bad3: 193 ATH_LOCK_DESTROY(sc); 194 195 pci_intr_disestablish(pc, psc->sc_ih); 196 bad1: 197 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 198 bad: 199 return; 200 } 201 202 static int 203 ath_pci_detach(device_t self, int flags) 204 { 205 struct ath_pci_softc *psc = device_private(self); 206 int rv; 207 208 if ((rv = ath_detach(&psc->sc_sc)) != 0) 209 return rv; 210 211 pmf_device_deregister(self); 212 213 if (psc->sc_ih != NULL) 214 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 215 216 ATH_LOCK_DESTROY(&psc->sc_sc); 217 218 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 219 return 0; 220 } 221 222 static bool 223 ath_pci_setup(struct ath_pci_softc *sc) 224 { 225 int rc; 226 pcireg_t bhlc, csr, icr, lattimer; 227 228 if ((rc = pci_set_powerstate(sc->sc_pc, sc->sc_tag, PCI_PWR_D0)) != 0) 229 aprint_debug("%s: pci_set_powerstate %d\n", __func__, rc); 230 /* 231 * Enable memory mapping and bus mastering. 232 */ 233 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 234 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 235 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr); 236 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 237 238 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 239 aprint_error_dev(sc->sc_sc.sc_dev, 240 "couldn't enable memory mapping\n"); 241 return false; 242 } 243 if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { 244 aprint_error_dev(sc->sc_sc.sc_dev, 245 "couldn't enable bus mastering\n"); 246 return false; 247 } 248 249 /* 250 * XXX Both this comment and code are replicated in 251 * XXX cardbus_rescan(). 252 * 253 * Make sure the latency timer is set to some reasonable 254 * value. 255 * 256 * I will set the initial value of the Latency Timer here. 257 * 258 * While a PCI device owns the bus, its Latency Timer counts 259 * down bus cycles from its initial value to 0. Minimum 260 * Grant tells for how long the device wants to own the 261 * bus once it gets access, in units of 250ns. 262 * 263 * On a 33 MHz bus, there are 8 cycles per 250ns. So I 264 * multiply the Minimum Grant by 8 to find out the initial 265 * value of the Latency Timer. 266 * 267 * I never set a Latency Timer less than 0x10, since that 268 * is what the old code did. 269 */ 270 bhlc = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG); 271 icr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_INTERRUPT_REG); 272 lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr))); 273 if (PCI_LATTIMER(bhlc) < lattimer) { 274 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 275 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 276 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BHLC_REG, bhlc); 277 } 278 return true; 279 } 280 281 MODULE(MODULE_CLASS_DRIVER, if_ath_pci, "ath"); 282 283 #ifdef _MODULE 284 #include "ioconf.c" 285 #endif 286 287 static int 288 if_ath_pci_modcmd(modcmd_t cmd, void *opaque) 289 { 290 int error = 0; 291 292 switch (cmd) { 293 case MODULE_CMD_INIT: 294 #ifdef _MODULE 295 error = config_init_component(cfdriver_ioconf_if_ath_pci, 296 cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); 297 #endif 298 return error; 299 case MODULE_CMD_FINI: 300 #ifdef _MODULE 301 error = config_fini_component(cfdriver_ioconf_if_ath_pci, 302 cfattach_ioconf_if_ath_pci, cfdata_ioconf_if_ath_pci); 303 #endif 304 return error; 305 default: 306 return ENOTTY; 307 } 308 } 309